WO2016125363A1 - Module semi-conducteur de puissance - Google Patents

Module semi-conducteur de puissance Download PDF

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Publication number
WO2016125363A1
WO2016125363A1 PCT/JP2015/081916 JP2015081916W WO2016125363A1 WO 2016125363 A1 WO2016125363 A1 WO 2016125363A1 JP 2015081916 W JP2015081916 W JP 2015081916W WO 2016125363 A1 WO2016125363 A1 WO 2016125363A1
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WO
WIPO (PCT)
Prior art keywords
power semiconductor
semiconductor module
electrode pad
substrate
area
Prior art date
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PCT/JP2015/081916
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English (en)
Japanese (ja)
Inventor
勝美 工藤
佐藤　朝彦
雅明 山田
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株式会社 村田製作所
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Application filed by 株式会社 村田製作所 filed Critical 株式会社 村田製作所
Priority to JP2016573185A priority Critical patent/JP6330924B2/ja
Publication of WO2016125363A1 publication Critical patent/WO2016125363A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a power semiconductor module, and in particular, a substrate having an upper surface provided with a plurality of electrode pads, a plurality of leads respectively connected to the plurality of electrode pads, and one or more leads of the plurality of electrode pads.
  • the present invention relates to a power semiconductor module including a power semiconductor element mounted on one.
  • the tip of the lead is soldered to the electrode on the substrate, and the area of the tip of the lead is made smaller than the area of the electrode.
  • the power semiconductor module 1 to which such a structure is applied is configured, for example, as shown in FIGS. 15 (A) to 15 (B) and FIGS. 16 (A) to 16 (C).
  • FIG. 15A shows the upper surface of the power semiconductor module 1
  • FIG. 15B shows the lower surface of the power semiconductor module 1.
  • 16A shows a side view of the power semiconductor module 1
  • FIG. 16B shows a vertical section of the power semiconductor module 1
  • FIG. 16C shows a horizontal section of the power semiconductor module 1. .
  • the area of the tip of the lead 2 is smaller than the area of the electrode pad 4 provided on the substrate 3.
  • the solder 5 forms a fillet.
  • the connection strength between the lead 2 and the electrode pad 4 and thus the connection reliability are ensured.
  • solder 5 is sucked up to the upper surface of the lead 2 as shown in FIGS. 19A and 19B, or flies to the upper surface of the lead 2 as shown in FIGS. 20A and 20B. There is a risk of dripping. On the upper surface of the lead 2, the flux residue 7 may be sucked up or flew.
  • the power semiconductor element 6 when the power semiconductor element 6 is mounted or mounted on the upper surface of the lead 2, the power semiconductor element 6 may be inclined due to the influence of the solder 5, or a gap may be formed on the lower surface of the power semiconductor element 6. That is, when the structure depicted in FIG. 2 of Patent Document 1 is applied to the power semiconductor module 1, there is a concern that the quality of the power semiconductor module 1 may deteriorate.
  • a main object of the present invention is to provide a power semiconductor module capable of suppressing deterioration in quality due to the magnitude relationship between the area of the tip of the lead and the area of the electrode on the substrate.
  • the power semiconductor module according to the present invention includes a substrate having an upper surface provided with a plurality of electrode pads, a plurality of leads connected to the plurality of electrode pads and separated from the frame, and one of the plurality of electrode pads or A power semiconductor module including a power semiconductor element mounted on one of a plurality of leads, wherein the plurality of leads are members respectively connected to the plurality of electrode pads in a state of being integrated with the frame.
  • Each of the tips has a bonding surface that has an area larger than the area of the upper surface of the target electrode pad and is bonded to the upper surface of the target electrode pad.
  • the bonding surface is bonded to the upper surface of the target electrode pad while allowing misalignment in a range below a predetermined value, and from the outer edge of the bonding surface when the center of the bonding surface is aligned with the center of the upper surface of the target electrode pad.
  • the distance to the outer edge of the upper surface of the target electrode pad is a value greater than or equal to a predetermined value.
  • the distance from the outer edge of the bonding surface to the outer edge of the upper surface of the target electrode pad when the center of the bonding surface is aligned with the center of the upper surface of the target electrode pad is a value of 0.1 mm or more.
  • the area of the upper surface of the target electrode pad is 40% or more of the area of the bonding surface, more preferably 70% or more.
  • the substrate is a metal substrate having an insulating film or an insulating substrate formed on the upper surface.
  • the insulating substrate is made of resin or ceramic.
  • the plurality of leads are integrated by being connected to the frame, and the distance between the leads is fixed. Further, the bonding surface formed at the tip of each of the plurality of leads is bonded to the upper surface of the target electrode pad. Based on this, the area of the bonding surface is made larger than the area of the upper surface of the target electrode pad. As a result, when the frame is misaligned, the possibility that the electrode pad protrudes outside the outer edge of the joint surface in a plan view is reduced, thereby reducing the possibility of an insulation failure between the leads.
  • the area of the joint surface formed at the tip of the lead is made larger than the area of the upper surface of the target electrode pad, the possibility of solder or flux residue being sucked up or flying to the upper surface of the lead is reduced. The concern that a mounting failure of the power semiconductor element on the upper surface may be reduced.
  • FIG. 1 is a top view showing the top surface of the power semiconductor module of this embodiment, and (B) is a bottom view showing the bottom surface of the power semiconductor module of this embodiment.
  • (A) is a side view showing the side of the power semiconductor module of this embodiment,
  • (B) is a cross-sectional view showing a certain vertical cross section of the power semiconductor module of this embodiment, and (C) is this embodiment. It is sectional drawing which shows a certain horizontal cross section of this power semiconductor module.
  • (A) is an expanded sectional view showing the principal part of a certain horizontal section of the power semiconductor module of this embodiment,
  • (B) is an enlarged section showing the principal part of a certain vertical section of the power semiconductor module of this embodiment.
  • FIG. (A) is an expanded sectional view showing the principal part of a certain horizontal section of the power semiconductor module of this embodiment
  • (B) is an enlarged section showing the principal part of a certain vertical section of the power semiconductor module of this embodiment.
  • FIG. (A) is an expanded sectional view showing the principal part of a certain horizontal section of the power semiconductor module of this embodiment
  • (B) is an enlarged section showing the principal part of a certain vertical section of the power semiconductor module of this embodiment.
  • FIG. (A) is an expanded sectional view showing the principal part of a certain horizontal section of the power semiconductor module of this embodiment
  • (B) is an enlarged section showing the principal part of a certain vertical section of the power semiconductor module of this embodiment.
  • FIG. 1 is an expanded sectional view showing the principal part of a certain horizontal section of the power semiconductor module of this embodiment
  • (B) is an enlarged section showing the principal part of a certain vertical section of the power semiconductor module of this embodiment.
  • FIG. It is an illustration figure which shows a part of process of connecting a lead
  • (A) is an illustrative view showing a state where there is no misalignment between the lead and the substrate
  • (A) is a graph which shows the relationship between the area ratio of the upper surface of an electrode pad with respect to the joint surface of a lead
  • (B) is an illustration figure for demonstrating thermal resistance.
  • (A) is sectional drawing which shows the vertical cross section of the power semiconductor module of another Example
  • (B) is a top view which shows the lower surface of the power semiconductor module of another Example.
  • (A) is sectional drawing which shows a certain perpendicular
  • (A) is sectional drawing which shows a certain perpendicular
  • (B) is a bottom view which shows the lower surface of the power semiconductor module of still another Example.
  • (A) is sectional drawing which shows a certain perpendicular
  • (B) is a bottom view which shows the lower surface of the power semiconductor module of another Example.
  • (A) is a top view showing the upper surface of the power semiconductor module to which the structure of Patent Document 1 is applied
  • (B) is a bottom view showing the lower surface of the power semiconductor module to which the structure of Patent Document 1 is applied.
  • FIG. 1 is a side view showing a side surface of a power semiconductor module to which the structure of Patent Document 1 is applied, and (B) is a sectional view showing a certain vertical section of the power semiconductor module to which the structure of Patent Document 1 is applied.
  • C is sectional drawing which shows a certain horizontal cross section of the power semiconductor module to which the structure of patent document 1 is applied.
  • A) is the illustration which looked at the principal part structure of the power semiconductor module which applied the structure of patent document 1 from the side
  • (B) is the illustration which looked at the principal part structure of the power semiconductor module of this Example from the top.
  • (A) is an illustrative view showing a state in which there is no misalignment between the lead and the substrate
  • (B) is an illustrative view showing a state in which there is no misalignment between the lead and the substrate.
  • (A) is an illustrative view of the state in which solder and flux residue are sucked up on the upper surface of the lead
  • (B) is an illustration in which the state of solder and flux residue sucked up on the upper surface of the lead is viewed from above.
  • (A) is an illustrative view of a state in which solder and flux residue are blown on the upper surface of the lead
  • (B) is an illustrative view in which the state of solder and flux residue is flying on the upper surface of the lead. is there.
  • a power semiconductor module 10 of this embodiment includes power semiconductor elements (FETs) 18a to 18b, for control.
  • FETs power semiconductor elements
  • 1 is a power semiconductor module for power supply that is integrated into one package by incorporating the integrated circuit 20 and the like, and includes a substrate 12 whose upper surface and lower surface are rectangular.
  • FIG. 2B and FIG. 2C chip parts and the like are not drawn, but various parts are actually mounted.
  • the substrate 12 is a metal substrate having an insulating film formed on the upper surface thereof. Strictly speaking, the substrate 12 is formed by a thin-film insulating layer 121 and a plate-like conductive layer 122 that supports the insulating layer 121. A circuit pattern (not shown) is provided on the surface of the insulating layer 121, and the power semiconductor elements 18a to 18b, the integrated circuit 20, and the like are electrically connected to the circuit pattern. Further, the side surface and the upper surface of the substrate 12 are sealed with the sealing resin 26, while the lower surface of the substrate 12 (strictly, the lower surface of the conductive layer 122) is exposed to the outside. The heat generated in the power semiconductor module 10 is released to the outside through such a substrate 12.
  • the X axis and the Y axis are respectively assigned along the long and short sides of the rectangle drawn by the upper surface or the lower surface of the substrate 12, and the Z axis is assigned in the direction orthogonal to the upper surface or the lower surface of the substrate 12. It is done. Although not shown, the origins of the X, Y, and Z axes are assigned to the center of the substrate 12.
  • electrode pads 14a to 14h made of copper are provided on the upper surface of the substrate 12.
  • the upper or lower surface of each of the electrode pads 14a to 14h has a rectangular shape.
  • the upper surface faces the positive side in the Z axis direction
  • the long side of the rectangle extends along the X axis
  • the short side of the rectangle extends along the Y axis.
  • the electrode pads 14a to 14c are arranged in the Y axis direction at positions on the negative side of the origin in the X axis direction
  • the electrode pads 14d to 14h are arranged at positions on the positive side from the origin in the X axis direction in the Y axis direction.
  • the area of the upper surface of the electrode pad 14b matches the area of the upper surface of the electrode pad 14a, while the area of the upper surface of the electrode pad 14c is smaller than the area of the upper surface of the electrode pad 14b.
  • the area of the upper surface of each of the electrode pads 14d to 14h is smaller than the area of the upper surface of the electrode pad 14c and coincides with each other.
  • the distance between the electrode pads 14a and 14b is equal to the distance between the electrode pads 14b and 14c
  • the distance between the electrode pads 14d and 14e is equal to the distance between the electrode pads 14f and 14g
  • the distance between the electrode pads 14f and 14g is the electrode pad. It corresponds to the interval of 14g and 14h. However, the interval between the electrode pads 14e and 14f is made wider than the interval between the electrode pads 14d and 14e.
  • each of the leads 16a to 16h mainly made of copper are electrically connected to the electrode pads 14a to 14h, respectively. More specifically, each of the leads 16a to 16h has one end connected to the target electrode pad and the other end protruding outside the sealing resin 26, and extends in the X-axis direction. 3 (A) to 3 (B), 4 (A) to 4 (B), 5 (A) to 5 (B), 6 (A) to 6 (B), As shown in an enlarged view in FIGS. 7A to 7B, each of the leads 16a to 16h bends in the Z-axis direction in the vicinity of one end and then extends in the X-axis direction. The portions are joined portions 161a to 161h. The lower surface of each of the bonding portions 161a to 161h serves as a bonding surface for bonding to the upper surface of the target electrode pad, and is bonded to the upper surface of the target electrode pad by the solder 24.
  • the area of the bonding surface exceeds the area of the upper surface of the target electrode pad. Therefore, when the center of the bonding surface is aligned with the center of the upper surface of the target electrode pad, the upper surface of the target electrode pad is covered with the bonding surface in plan view. In other words, the bonding surface is within the outline or outer edge drawn by the upper surface of the target electrode pad.
  • the width of joint portion 161a is made wider than the width of the other portion of lead 16a, and the width of joint portion 161b is set to lead 16b. It is made wider than the width of other parts.
  • the power semiconductor element 18a is mounted or mounted on the upper surface of the joint portion 161a, and the power semiconductor element 18b is mounted or mounted on the upper surface of the joint portion 161b.
  • the width of the joint portion 161c matches the width of the other portion of the lead 16c. Further, no element is mounted or mounted on the upper surface of the joint 161c.
  • the power semiconductor element 18a is connected to the joint 161b of the lead 16b by the bonding wire W1
  • the power semiconductor element 18b is connected to the joint 161c of the lead 16c by the bonding wire W2.
  • the bonding wires W1 and W2 are mainly made of aluminum.
  • bonding portion 161d is connected to the circuit pattern on substrate 12 by bonding wire W3, and bonding portion 161e is connected to the substrate by bonding wire W4.
  • 12 is connected to the circuit pattern on the substrate 12, and the joint 161f is connected to the circuit pattern on the substrate 12 by the bonding wire W5.
  • the bonding wires W3 to W5 are mainly made of gold.
  • the joints 161g and 161h remain connected to the electrode pads 14g and 14h for the leads 16g and 16h, respectively.
  • the integrated circuit 20 is mounted on the upper surface of the substrate 12 again. At this time, the legs of the integrated circuit 20 are bonded to the electrode pads 22 provided on the upper surface of the substrate 12.
  • the solder 24 is used for joining to the electrode pad 22 as described above.
  • the area of the bonding surface exceeds the area of the upper surface of the target electrode pad, and the relationship between the areas is as follows.
  • the leads 16a to 16h are integrated with the frame FR1 and the tie bars TB1 and TB2 as shown in FIG.
  • the distance between the leads is fixed.
  • the misalignment of the frame FR1 and the tie bars TB1 and TB2 within a range below a predetermined value is allowed in each of the X-axis direction and the Y-axis direction.
  • the frame FR1 and the tie bars TB1 and TB2 are cut after the leads 16a to 16h are connected to the electrode pads 14a to 14h and sealed with the sealing resin 26.
  • the predetermined value is about 0.1 mm from a commonly used manufacturing facility.
  • the area of the bonding surface and the area of the upper surface of the target electrode pad are such that the distance from the outer edge of the bonding surface to the outer edge of the upper surface of the target electrode pad is equal to or greater than a predetermined value when the centers of the surfaces are aligned. To be adjusted.
  • the area of the bonding surface larger than the area of the upper surface of the target electrode pad, the possibility that the solder 24 or the flux residue sucks up or flies to the upper surface of the bonding portions 161a to 161h is reduced. As a result, the concern that mounting defects such as mounting of the power semiconductor element 18a or 18b at an incline or a gap on the lower surface of the power semiconductor element 18a or 18b may be reduced.
  • the adhesion of the flux residue to the upper surfaces of the joints 161a to 161h causes poor connection of the bonding wires W1 to W5, and further causes the intrusion of moisture due to peeling between the joints 161a to 161h and the sealing resin 26. Therefore, such a concern is reduced by making the area of the bonding surface larger than the area of the upper surface of the target electrode pad.
  • the distance from the outer edge of the bonding surface to the outer edge of the upper surface of the target electrode pad is a predetermined value or more defines the upper limit of the area of the upper surface of the target electrode pad.
  • the lower limit of the area of the upper surface of the electrode pads 14a and 14b to be bonded will be described.
  • heat generated in power semiconductor element 18a is transmitted to substrate 12 through joint 161a, solder 24, and electrode pad 14a.
  • heat generated in the power semiconductor element 18b is transmitted to the substrate 12 through the joint portion 161b, the solder 24, and the electrode pad 14b.
  • the horizontal axis represents the area ratio obtained by dividing the area of the upper surface of the electrode pad 14a or 14b by the area of the bonding surface of the bonding portion 161a or 161b, and the thermal resistance when the above-described area ratio is 1 is shown.
  • the vertical axis represents the ratio to the time when the value is 1, and the thermal resistance increases as the area of the upper surface of the electrode pad 14a or 14b decreases. Since the thermal resistance ratio greatly increases when the area ratio of the horizontal axis is 40% or less, the area of the upper surface of the electrode pad 14a or 14b is preferably 40% with respect to the area of the bonding surface of the bonding portion 161a or 161b. It adjusts so that the above magnitude
  • the size of the area of the upper surface of the electrode pad 14a or 14b is adjusted such that the area ratio becomes 70% or more at which the thermal resistance ratio is about 1.5 times or less.
  • the lower surface of the substrate 12 is exposed to the outside (see FIGS. 1B and 2B).
  • the entire surface of the substrate 12 may be sealed with a sealing resin 26.
  • the substrate 12 is formed of a thin insulating layer 121 and a plate-like conductive layer 122 that supports the insulating layer 121.
  • a resin or ceramic substrate 12 ′ may be employed instead of the substrate 12, and further, FIG. 13 (A) and FIG. As shown in FIG. 13B, the entire surface of the substrate 12 ′ may be sealed with a sealing resin 26.
  • a thicker resin or ceramic insulating substrate (not shown) may be used instead of the insulating layer 121.
  • a power semiconductor module having a more complicated circuit configuration can be realized by multilayering the substrate 12 'or a thick insulating substrate.
  • the power semiconductor module 30 of another embodiment is also a power semiconductor module for power supply in which power semiconductor elements 38a to 38b are incorporated into one package, It includes a substrate 32 whose upper and lower surfaces are rectangular.
  • FIG. 14A and FIG. 14B chip parts and the like are not drawn, but various parts are actually mounted.
  • the substrate 32 is formed of a thin insulating layer 321 and a plate-like conductive layer 322 that supports the insulating layer 321.
  • a circuit pattern (not shown) is provided on the surface of the insulating layer 321, and the power semiconductor elements 38a to 38b are electrically connected to the circuit pattern.
  • the side surface and the upper surface of the substrate 32 are sealed with the sealing resin 40, while the lower surface of the substrate 32 is exposed to the outside. The heat generated in the power semiconductor module 30 is released to the outside through such a substrate 32.
  • the X axis and the Y axis are respectively assigned along the long side and the short side of the rectangle drawn by the upper surface or the lower surface of the substrate 32, and the Z axis is assigned in the direction orthogonal to the upper surface or the lower surface of the substrate 32.
  • electrode pads 34a to 34h made of copper are provided on the upper surface of the substrate 32.
  • the upper or lower surface of each of the electrode pads 34a to 34h has a rectangular shape.
  • the upper surface faces the positive side in the Z-axis direction, the long side of the rectangle extends along the X axis, and the short side of the rectangle extends along the Y axis.
  • the electrode pads 34a to 34d are arranged in the Y axis direction at positions on the negative side of the origin in the X axis direction, and the electrode pads 34e to 34h are arranged in the Y axis direction on the positive side from the origin in the X axis direction.
  • the area of the upper surface is coincident between the electrode pads 34b and 34c, coincident between the electrode pads 34g and 34h, coincident between the electrode pads 34a and 34d, and coincident between the electrode pads 34e and 34f. To do. However, the area of the upper surface of the electrode pad 34e is smaller than the area of the upper surface of the electrode pad 34b, and the area of the upper surface of the electrode pad 34a is smaller than the area of the upper surface of the electrode pad 34e.
  • the distance between the electrode pads 34a and 34b is equal to the distance between the electrode pads 34b and 34c and the distance between the electrode pads 34c and 34d. Further, the distance between the electrode pads 34e and 34g matches the distance between the electrode pads 34h and 34f. However, the interval between the electrode pads 34e and 34g is made smaller than the interval between the electrode pads 34a and 34b.
  • each of the leads 36a to 36f made mainly of copper are electrically connected to the electrode pads 34a to 34f, respectively. More specifically, each of the leads 36a to 36f has one end connected to the target electrode pad and the other end protruding outside the sealing resin 40, and extends in the X-axis direction. Further, each of the leads 36a to 36f is bent in the Z-axis direction in the vicinity of one end and then extends in the X-axis direction, and the portions ahead of the bent position are the joint portions 361a to 361f.
  • the lower surface of each of the bonding portions 361a to 361f serves as a bonding surface for bonding to the upper surface of the target electrode pad, and is bonded to the upper surface of the target electrode pad by the solder 24.
  • the area of the bonding surface exceeds the area of the upper surface of the target electrode pad. Therefore, when the center of the bonding surface is aligned with the center of the upper surface of the target electrode pad, the upper surface of the target electrode pad is covered with the bonding surface in plan view. In other words, the bonding surface is within the outline or outer edge drawn by the upper surface of the target electrode pad.
  • the width of the joint portion 361b is wider than the width of the other portion of the lead 36b, and the width of the joint portion 361c is wider than the width of the other portion of the lead 36c.
  • the width of the joints 361a, 361d, 361e, and 361f matches the width of the other portions of the leads 36a, 36d, 36e, and 36f.
  • the joint portion 361a of the lead 36a is connected to the circuit pattern on the substrate 12 by the bonding wire W6, and the joint portion 361d of the lead 36d is connected to the circuit pattern on the substrate 12 by the bonding wire W7.
  • the joint portion 361b of the lead 36b is connected to the electrode pad 34g by the bonding wire W8, and the joint portion 361c of the lead 36c is connected to the electrode pad 34h by the bonding wire W9.
  • the power semiconductor element 38a is mounted on the electrode pad 34g and connected to the joint 361e of the lead 36e by the bonding wire W10.
  • the power semiconductor element 38b is mounted on the electrode pad 34h and connected to the joint portion 361f of the lead 36f by the bonding wire W11.
  • the bonding wires W6 to W7 are mainly made of gold, and the bonding wires W8 to W11 are mainly made of aluminum.
  • the area of the bonding surface and the area of the upper surface of the target electrode pad are such that the distance from the outer edge of the bonding surface to the outer edge of the upper surface of the target electrode pad is equal to or greater than a predetermined value when the centers of the surfaces are aligned. To be adjusted. As a result, the quality of the power semiconductor module 30 or the reliability of the electrical connection is maintained as in the above-described embodiment.
  • the power semiconductor elements 38a and 38b are mounted on the electrode pads 34g and 34h. Therefore, most of the heat generated in the power semiconductor elements 38a and 38b is released to the outside through the wires W8 and W10, not from the leads 36b and 36c but from the conductive layer 322 forming the substrate 32.
  • part of the configuration of the power semiconductor module 30 illustrated in FIGS. 14A and 14B can be changed to the configuration of the power semiconductor module 10 illustrated in FIG. 13B within a consistent range. it can.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

Selon la présente invention, des broches (16a-16h) sont respectivement connectées à des plots d'électrode (14a-14h) disposés sur la surface supérieure d'un substrat (12). Des éléments à semi-conducteur de puissance (18a, 18b) sont respectivement montés sur les plots d'électrode (14a, 14b). Les broches (16a-16h), intégrées conjointement avec un cadre, sont respectivement connectées aux plots d'électrode (14a-14h). Au niveau de l'extrémité distale de chacune des broches (16a-16h) est formée une surface d'assemblage qui présente une superficie supérieure à la superficie de la surface supérieure d'un plot d'électrode cible et qui est assemblée à la surface supérieure du plot d'électrode cible.
PCT/JP2015/081916 2015-02-06 2015-11-13 Module semi-conducteur de puissance WO2016125363A1 (fr)

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JP2015-022076 2015-02-06
JP2015022076 2015-02-06

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019244372A1 (fr) * 2018-06-20 2019-12-26 ローム株式会社 Dispositif à semi-conducteurs
WO2021200337A1 (fr) * 2020-04-01 2021-10-07 ローム株式会社 Dispositif électronique

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Publication number Priority date Publication date Assignee Title
JPH0878619A (ja) * 1994-09-07 1996-03-22 Hitachi Ltd 電力用半導体装置
JP2008135735A (ja) * 2006-10-31 2008-06-12 Sanyo Electric Co Ltd 回路装置
WO2012114857A1 (fr) * 2011-02-24 2012-08-30 株式会社村田製作所 Structure de montage de composant électronique

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JP2003007765A (ja) * 2001-06-22 2003-01-10 Canon Inc Ｔａｂテープ及びボンディング方法

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Publication number Priority date Publication date Assignee Title
JPH0878619A (ja) * 1994-09-07 1996-03-22 Hitachi Ltd 電力用半導体装置
JP2008135735A (ja) * 2006-10-31 2008-06-12 Sanyo Electric Co Ltd 回路装置
WO2012114857A1 (fr) * 2011-02-24 2012-08-30 株式会社村田製作所 Structure de montage de composant électronique

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019244372A1 (fr) * 2018-06-20 2019-12-26 ローム株式会社 Dispositif à semi-conducteurs
JPWO2019244372A1 (ja) * 2018-06-20 2021-03-25 ローム株式会社 半導体装置
JP7071499B2 (ja) 2018-06-20 2022-05-19 ローム株式会社 半導体装置
JP2022105164A (ja) * 2018-06-20 2022-07-12 ローム株式会社 半導体装置
US11437354B2 (en) 2018-06-20 2022-09-06 Rohm Co, Ltd. Semiconductor device
JP7357719B2 (ja) 2018-06-20 2023-10-06 ローム株式会社 半導体装置
US11804478B2 (en) 2018-06-20 2023-10-31 Rohm Co., Ltd. Semiconductor device
WO2021200337A1 (fr) * 2020-04-01 2021-10-07 ローム株式会社 Dispositif électronique

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