WO2016123800A1 - 一种阵列基板及液晶显示面板 - Google Patents

一种阵列基板及液晶显示面板 Download PDF

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WO2016123800A1
WO2016123800A1 PCT/CN2015/072427 CN2015072427W WO2016123800A1 WO 2016123800 A1 WO2016123800 A1 WO 2016123800A1 CN 2015072427 W CN2015072427 W CN 2015072427W WO 2016123800 A1 WO2016123800 A1 WO 2016123800A1
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metal layer
layer
pixel electrode
disposed
insulating layer
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French (fr)
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高冬子
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13392—Gaskets; Spacers; Sealing of cells spacers dispersed on the cell substrate, e.g. spherical particles, microfibres
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a liquid crystal display panel.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display, ultra-thin film transistor liquid crystal display
  • pixels use a capacitor formed between different metals to maintain pixel display and prevent color shift.
  • the same layer of metal is used to make the capacitor, the same layer of metal is on the same layer. No, therefore, it is easily affected by particles and causes a short circuit.
  • FIG. 1 is a structural schematic diagram of an array substrate provided by the prior art.
  • the array substrate includes a substrate 10, and a first metal layer 20, a first insulating layer 30, a second metal layer 40, a second insulating layer 50, and a pixel electrode layer 60, which are sequentially disposed on the surface of the substrate 10.
  • a pixel electrode in the pixel electrode layer 60 and a common electrode on the opposite substrate as a pixel capacitance, a common electrode in the pixel electrode layer 60 and a common line on the first metal layer 20 or the second metal layer 40 Storage capacitor.
  • the pixel electrode layer 60 is made of ITO (Indium Tin Oxide, tin-doped indium oxide).
  • ITO has the function of pixel capacitance and storage capacitor, and the purpose of forming the capacitor is to display the main pixel (main). Pixel) and subpixel (sub Pixel) has an inconsistent charge distribution and thus has a low color shift.
  • this design has a gap between the pixel electrode and the common electrode in the pixel electrode layer 60 because the ITO is located in the same layer, so that the particles easily fall into the gap, thereby causing the capacitance ITO and the pixel ITO. Short-circuiting together causes the capacitor to lose its effectiveness, eventually causing an abnormality in the display and degrading the quality of the product.
  • An object of the present invention is to provide an array substrate and a liquid crystal display panel, which can effectively avoid the problem of short circuit caused by the influence of particles and improve the quality of the product.
  • An array substrate wherein the array substrate comprises:
  • the first metal layer is disposed on the surface of the substrate;
  • the first metal layer includes a gate of the thin film transistor and a scan line;
  • the first insulating layer is disposed on the first metal layer for isolating the first metal layer and the second metal layer;
  • the second metal layer is disposed on the first insulating layer;
  • the second metal layer includes a source of the thin film transistor, a drain of the thin film transistor, and a data line;
  • a second insulating layer disposed on the second metal layer for isolating the second metal layer and the pixel electrode layer;
  • the protrusion is disposed on the second insulation layer
  • the pixel electrode layer is disposed on the second insulating layer;
  • the pixel electrode layer includes a pixel electrode and a common electrode;
  • the protrusion is located between the pixel electrode and the common electrode, and the protrusion is used for isolating the pixel electrode and the common electrode;
  • the thickness of the second insulating layer corresponding to the convex position is greater than the thickness of the second insulating layer at the non-convex position; the thickness of the second metal layer corresponding to the convex position Greater than the thickness of the second metal layer at the non-protruding location.
  • the first metal layer further comprises a common line; the common electrode on the pixel electrode and the opposite substrate is used as a pixel capacitor, and the common electrode and the first metal layer are The common line acts as a storage capacitor.
  • the second metal layer further comprises a common line; the common electrode on the pixel electrode and the opposite substrate is used as a pixel capacitor, and the common electrode and the second metal layer are The common line acts as a storage capacitor.
  • the pixel electrode layer is made of tin-doped indium oxide ITO material.
  • the first insulating layer is made of a G-Sinx material.
  • the second insulating layer is made of a P-Sinx material.
  • the first metal layer is disposed on the surface of the substrate;
  • the first metal layer includes a gate of the thin film transistor and a scan line;
  • the first insulating layer is disposed on the first metal layer for isolating the first metal layer and the second metal layer;
  • the second metal layer is disposed on the first insulating layer;
  • the second metal layer includes a source of the thin film transistor, a drain of the thin film transistor, and a data line;
  • a second insulating layer disposed on the second metal layer for isolating the second metal layer and the pixel electrode layer;
  • the protrusion is disposed on the second insulation layer
  • the pixel electrode layer is disposed on the second insulating layer;
  • the pixel electrode layer includes a pixel electrode and a common electrode;
  • the protrusion is located between the pixel electrode and the common electrode, and the protrusion is used to isolate the pixel electrode and the common electrode.
  • a thickness of the second insulating layer corresponding to the convex position is greater than a thickness of the second insulating layer at a non-bumping position.
  • a thickness of the second metal layer corresponding to the convex position is greater than a thickness of the second metal layer at a non-bumping position.
  • the first metal layer further includes a common line; the common electrode on the pixel electrode and the opposite substrate serves as a pixel capacitance, and the common electrode and the first metal layer
  • the common line acts as a storage capacitor.
  • the second metal layer further includes a common line; the common electrode on the pixel electrode and the opposite substrate serves as a pixel capacitor, and the common electrode and the second metal layer
  • the common line acts as a storage capacitor.
  • a liquid crystal display panel comprising an array substrate, a color filter substrate, and a liquid crystal cell disposed between the array substrate and the color filter substrate;
  • the array substrate includes:
  • the first metal layer is disposed on the surface of the substrate;
  • the first metal layer includes a gate of the thin film transistor and a scan line;
  • the first insulating layer is disposed on the first metal layer for isolating the first metal layer and the second metal layer;
  • the second metal layer is disposed on the first insulating layer;
  • the second metal layer includes a source of the thin film transistor, a drain of the thin film transistor, and a data line;
  • a second insulating layer disposed on the second metal layer for isolating the second metal layer and the pixel electrode layer;
  • the protrusion is disposed on the second insulation layer
  • the pixel electrode layer is disposed on the second insulating layer;
  • the pixel electrode layer includes a pixel electrode and a common electrode;
  • the protrusion is located between the pixel electrode and the common electrode, and the protrusion is used to isolate the pixel electrode and the common electrode.
  • a thickness of the second insulating layer corresponding to the convex position is greater than a thickness of the second insulating layer at a non-bumping position.
  • a thickness of the second metal layer corresponding to the convex position is greater than a thickness of the second metal layer at a non-bumping position.
  • the first metal layer further includes a common line; the common electrode on the pixel electrode and the opposite substrate serves as a pixel capacitor, and the common electrode and the first metal layer
  • the common line acts as a storage capacitor.
  • the second metal layer further includes a common line; the common electrode on the pixel electrode and the opposite substrate serves as a pixel capacitor, and the common electrode and the second metal layer
  • the common line acts as a storage capacitor.
  • the present invention is provided with a protrusion on the second insulating layer, the protrusion being located between the pixel electrode and the common electrode in the pixel electrode layer, the protrusion for isolating the pixel electrode and the common electrode . Therefore, even if the capacitor ITO and the pixel ITO are in the same layer, it is not affected by the Particle, and the short circuit between the capacitor ITO and the pixel ITO is avoided, thereby improving the quality of the product. Similar to a wall block between the capacitor ITO and the pixel ITO, it can effectively prevent the ITO short circuit from occurring and avoid the short circuit caused by the influence of the Particle.
  • the design of the protrusions makes it difficult for the Particle to stay at a higher position; even if a Particle falls in the raised position, the position of the protrusion is easily developed or etched during development and etching. The liquid is etched away, thus greatly reducing the short circuit caused by the Particle.
  • FIG. 1 is a schematic structural view of an array substrate provided by the prior art
  • FIG. 2 is a schematic structural diagram of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 3 is a schematic structural diagram of an array substrate according to Embodiment 3 of the present invention.
  • the bump is located between the pixel electrode and the common electrode in the pixel electrode layer, and the bump is used to isolate the pixel electrode and the common electrode . Therefore, even if the capacitor ITO and the pixel ITO are in the same layer, it is not affected by the Particle, and the short circuit between the capacitor ITO and the pixel ITO is avoided, thereby improving the quality of the product.
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. For the convenience of description, only parts related to the embodiment of the present invention are shown.
  • the array substrate includes a substrate 100, a first metal layer 101, a first insulating layer 102, a second metal layer 103, a second insulating layer 104, and a pixel electrode layer 105.
  • the first metal layer 101 is disposed on the surface of the substrate 100; the first insulating layer 102 is disposed on the first metal layer 101; the second metal layer 103 is disposed on the first insulating layer
  • the first insulating layer 102 is used to isolate the first metal layer 101 and the second metal layer 103; the second insulating layer 104 is disposed on the second metal layer 103; the pixel electrode
  • the layer 105 is disposed on the second insulating layer 104; the second insulating layer 104 is used to isolate the second metal layer 103 and the pixel electrode layer 105.
  • the first metal layer 101 is deposited on the surface of the substrate 100, and then the pattern of the first metal layer 101 is formed by using a yellow light and an etching process, wherein the pattern of the first metal layer 101 includes the gate of the thin film transistor. Pole and scan lines.
  • the pattern of the first metal layer 101 further includes a common line that forms a storage capacitor with the common electrode.
  • the pattern of the second metal layer 103 is formed by using a yellow light and an etching process, wherein the pattern of the second metal layer 103 includes the source of the thin film transistor.
  • the pattern of the second metal layer 103 further includes a common line, which forms a storage capacitor with the common electrode.
  • the pattern of the pixel electrode layer 105 is formed by using a yellow light and an etching process, wherein the pattern of the pixel electrode layer 105 includes a pixel electrode. And a common electrode.
  • the pixel electrode layer 105 is made of ITO (Indium Tin). Oxide, tin-doped indium oxide) or indium zinc oxide IZO or the like; the first insulating layer 102 may be made of G-Sinx material; the second insulating layer 104 may be made of P-Sinx material .
  • ITO Indium Tin
  • the first insulating layer 102 may be made of G-Sinx material
  • the second insulating layer 104 may be made of P-Sinx material .
  • a protrusion 106 is disposed on the second insulating layer 104, and the protrusion 106 is located between the pixel electrode and the common electrode in the pixel electrode layer 105, and the protrusion 106 is used to isolate the a pixel electrode and a common electrode.
  • the pixel electrode in the pixel electrode layer 105 and the common electrode on the opposite substrate serve as a pixel capacitor, and the common electrode and the first metal layer 101 or the second metal layer
  • the common line on 103 serves as a storage capacitor; since the protrusion 106 is provided between the pixel electrode and the common electrode in the pixel electrode layer 105, the pixel electrode can be isolated from the common electrode.
  • the protrusions 106 are located between the pixel electrode layer 105 (ie, between the same layer of ITO), and are similar to a wall block between the capacitor ITO and the pixel ITO, which can effectively prevent the ITO short circuit from occurring and avoid A short circuit caused by the influence of Particle occurs.
  • the design of the protrusions makes it difficult for the Particle to stay at a higher position; even if a Particle falls in the raised position, the position of the protrusion is easily developed or etched during development and etching. The liquid is etched away, thus greatly reducing the short circuit caused by the Particle.
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. For the convenience of description, only parts related to the embodiment of the present invention are shown.
  • the array substrate includes a substrate 100, and a first metal layer 101, a first insulating layer 102, a second metal layer 103, a second insulating layer 104, and a pixel electrode layer 105, which are sequentially disposed on the surface of the substrate 100.
  • the first metal layer 101 includes a gate of a thin film transistor and a scan line;
  • the second metal layer 103 includes a source of the thin film transistor, a drain of the thin film transistor, and a data line;
  • the pixel electrode layer 105 includes a pixel Electrode and common electrode.
  • the first insulating layer 102 is used to isolate the first metal layer 101 and the second metal layer 103;
  • the second insulating layer 104 is used to isolate the second metal layer 103 and the pixel electrode layer 105.
  • the pixel electrode in the pixel electrode layer 105 and the common electrode on the opposite substrate serve as a pixel capacitor, and the common electrode and the first metal layer 101 or the second metal layer
  • the common line on 103 acts as a storage capacitor.
  • a bump 106 is disposed on the second insulating layer 104, and the bump 106 is located between the pixel electrode and the common electrode in the pixel electrode layer 105, and the bump 106 is used to isolate the pixel electrode and the common electrode.
  • the protrusions 106 are formed by thickening the second metal layer 103. That is, the thickness of the second metal layer 103 corresponding to the position of the protrusion 106 is greater than the thickness of the second metal layer 103 at the non-bumping position. That is, in the second metal layer 103 corresponding to the portion of the gap between the pixel electrode and the common electrode, the second metal layer 103 of this portion is coated with photoresist, exposed, developed, During the etching operation, the thickness of the position is made thicker than the thickness of the other locations, so that the second metal layer 103 at the position raises the second insulating layer 104 at the position, so that the height of the position is higher than the gap height.
  • the gap is presented as a protrusion, similar to a wall block between the capacitor ITO and the pixel ITO, and the capacitor ITO and the pixel ITO are isolated, which can effectively prevent the ITO short circuit from occurring and avoid the short circuit caused by the influence of the Particle.
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. For the convenience of description, only parts related to the embodiment of the present invention are shown.
  • the array substrate includes a substrate 100, a first metal layer 101, a first insulating layer 102, a second metal layer 103, a second insulating layer 104, and a pixel electrode layer 105.
  • the first metal layer 101 is disposed on the surface of the substrate 100; the first insulating layer 102 is disposed on the first metal layer 101; the second metal layer 103 is disposed on the first insulating layer
  • the first insulating layer 102 is used to isolate the first metal layer 101 and the second metal layer 103; the second insulating layer 104 is disposed on the second metal layer 103; the pixel electrode
  • the layer 105 is disposed on the second insulating layer 104; the second insulating layer 104 is used to isolate the second metal layer 103 and the pixel electrode layer 105.
  • the first metal layer 101 includes a gate of a thin film transistor and a scan line; the second metal layer 103 includes a source of the thin film transistor, a drain of the thin film transistor, and a data line; the pixel electrode layer 105 includes a pixel Electrode and common electrode.
  • the pattern of the first metal layer 101 further includes a common line that forms a storage capacitor with the common electrode.
  • the pattern of the second metal layer 103 further includes a common line, which forms a storage capacitor with the common electrode.
  • the pixel electrode in the pixel electrode layer 105 and the common electrode on the opposite substrate serve as a pixel capacitor, and the common electrode and the first metal layer 101 or the second metal layer
  • the common line on 103 acts as a storage capacitor.
  • a bump 106 is disposed on the second insulating layer 104, and the bump 106 is located between the pixel electrode and the common electrode in the pixel electrode layer 105, and the bump 106 is used to isolate the pixel electrode and the common electrode.
  • the protrusions 106 are formed by thickening the second insulating layer 104. That is, the thickness of the second insulating layer 104 corresponding to the convex position is greater than the thickness of the second insulating layer 104 at the non-bumping position. That is, in the second insulating layer 104 corresponding to the portion of the gap between the pixel electrode and the common electrode, the second insulating layer 104 of this portion is coated with photoresist, exposed, developed, During the etching operation, the thickness of the position is made thicker than the thickness of the other positions, so that the height of the second insulating layer 104 at the position is higher than the gap height, so that the gap exhibits a protrusion, similar to a wall block.
  • the capacitor ITO and the pixel ITO are isolated, which can effectively prevent the ITO short circuit from occurring and avoid the short circuit caused by the influence of the Particle.
  • the design of the protrusions makes it difficult for the Particle to stay at a higher position; even if a Particle falls in the raised position, the position of the protrusion is easily developed or etched during development and etching. The liquid is etched away, thus greatly reducing the short circuit caused by the Particle.
  • the embodiment of the invention further provides a liquid crystal display panel.
  • the liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal cell disposed between the array substrate and the color filter substrate.
  • the array substrate includes a substrate 100, a first metal layer 101, a first insulating layer 102, a second metal layer 103, a second insulating layer 104, and a pixel electrode layer 105.
  • the first metal layer 101 is disposed on the surface of the substrate 100; the first insulating layer 102 is disposed on the first metal layer 101; the second metal layer 103 is disposed on the first insulating layer
  • the first insulating layer 102 is used to isolate the first metal layer 101 and the second metal layer 103; the second insulating layer 104 is disposed on the second metal layer 103; the pixel electrode
  • the layer 105 is disposed on the second insulating layer 104; the second insulating layer 104 is used to isolate the second metal layer 103 and the pixel electrode layer 105.
  • the first metal layer 101 includes a gate of a thin film transistor and a scan line; the second metal layer 103 includes a source of the thin film transistor, a drain of the thin film transistor, and a data line; the pixel electrode layer 105 includes a pixel Electrode and common electrode.
  • the pattern of the first metal layer 101 further includes a common line that forms a storage capacitor with the common electrode.
  • the pattern of the second metal layer 103 further includes a common line, which forms a storage capacitor with the common electrode.
  • the pixel electrode in the pixel electrode layer 105 and the common electrode on the opposite substrate serve as a pixel capacitor, and the common electrode and the first metal layer 101 or the second metal layer
  • the common line on 103 acts as a storage capacitor.
  • a bump 106 is disposed on the second insulating layer 104, and the bump 106 is located between the pixel electrode and the common electrode in the pixel electrode layer 105, and the bump 106 is used to isolate the pixel electrode and the common electrode.
  • the protrusion may be formed by thickening the second insulating layer; that is, the thickness of the second insulating layer 104 corresponding to the convex position is greater than the non-protruding position.
  • the thickness of the second insulating layer 104 may be formed by thickening the second metal layer; that is, the thickness of the second metal layer 103 corresponding to the position of the protrusion 106 is greater than that at the non-bumping position The thickness of the second metal layer 103.
  • the protrusion may be formed by thickening the second insulating layer; or, the protrusion may be by the second The metal layer is formed by thickening; the protrusion is located between the pixel electrode and the common electrode in the pixel electrode layer, and the protrusion is used to isolate the pixel electrode and the common electrode. Therefore, even if the capacitor ITO and the pixel ITO are in the same layer, it is not affected by the Particle, and the short circuit between the capacitor ITO and the pixel ITO is avoided, thereby improving the quality of the product.

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Abstract

一种阵列基板包括基板(100)，以及依次设置于基板(100)表面上的第一金属层(101)、第一绝缘层(102)、第二金属层(103)、第二绝缘层(104)以及像素电极层(105)，像素电极层(105)包括像素电极和公共电极；在第二绝缘层(104)上设置有凸起(106)，凸起(106)位于像素电极与公共电极之间，凸起(106)用于隔离像素电极和公共电极。该阵列基板有效避免由于粒子的影响而导致发生短路的问题。

Description

一种阵列基板及液晶显示面板 技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板及液晶显示面板。
 背景技术
在TFT-LCD（Thin Film Transistor Liquid Crystal Display，超薄膜晶体管液晶显示器）行业中，像素会用到不同金属之间形成的电容来维持像素显示及防止色偏，当用到同一层金属来制作电容的时候，因为同一层金属在同一层别上，因此，很容易受到粒子（particle）的影响而导致短路的发生。
请参阅图1，为现有技术提供的阵列基板的结构示意图。所述阵列基板包括一基板10，以及依次设置于所述基板10表面上的第一金属层20、第一绝缘层30、第二金属层40、第二绝缘层50以及像素电极层60，其中，像素电极层60中的像素电极与相对的基板上的共通电极作为像素电容，像素电极层60中的公共电极与所述第一金属层20或所述第二金属层40上的公共线作为存储电容。像素电极层60由ITO（Indium Tin Oxide，掺锡氧化铟）制成。可知，ITO具有像素电容和存储电容的作用，形成电容的目的是为了显示的时候，将主像素（main pixel）和子像素（sub pixel）的电荷分配的不一致，从而起到低色偏的作用。但这种设计因为ITO位于同一层，在所述像素电极层60中的所述像素电极与所述公共电极之间具有间隙，因此粒子很容易落到间隙中，从而导致电容ITO和像素ITO 短路在一起，从而造成电容失去功效，最终导致显示器出现异常，降低了产品的品质。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种阵列基板及液晶显示面板，其能有效避免由于粒子的影响而导致发生短路的问题，提高了产品的品质。
 技术解决方案
一种阵列基板，其中所述阵列基板包括：
一基板；
一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层包括薄膜晶体管的栅极和扫描线；
一第一绝缘层，所述第一绝缘层设置于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
一所述第二金属层，所述第二金属层设置于所述第一绝缘层上；所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极以及数据线；
一第二绝缘层，所述第二绝缘层设置于所述第二金属层上，用于隔离所述第二金属层和像素电极层；
一凸起，所述凸起设置于所述第二绝缘层上；
一所述像素电极层，所述像素电极层设置于所述第二绝缘层上；所述像素电极层包括像素电极和公共电极；
其中，所述凸起位于所述像素电极与所述公共电极之间，所述凸起用于隔离所述像素电极和公共电极；
其中，对应所述凸起位置处的所述第二绝缘层的厚度大于非凸起位置处的所述第二绝缘层的厚度；对应所述凸起位置处的所述第二金属层的厚度大于非凸起位置处的所述第二金属层的厚度。
优选的，在所述阵列基板中，其中所述第一金属层还包括公共线；所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第一金属层上的所述公共线作为存储电容。
优选的，在所述阵列基板中，其中所述第二金属层还包括公共线；所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第二金属层上的所述公共线作为存储电容。
优选的，在所述阵列基板中，其中所述像素电极层采用掺锡氧化铟ITO材料制成。
优选的，在所述阵列基板中，其中所述第一绝缘层采用G-Sinx材料制成。
优选的，在所述阵列基板中，其中所述第二绝缘层采用P-Sinx材料制成。
一种阵列基板，所述阵列基板包括：
一基板；
一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层包括薄膜晶体管的栅极和扫描线；
一第一绝缘层，所述第一绝缘层设置于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
一所述第二金属层，所述第二金属层设置于所述第一绝缘层上；所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极以及数据线；
一第二绝缘层，所述第二绝缘层设置于所述第二金属层上，用于隔离所述第二金属层和像素电极层；
一凸起，所述凸起设置于所述第二绝缘层上；
一所述像素电极层，所述像素电极层设置于所述第二绝缘层上；所述像素电极层包括像素电极和公共电极；
其中，所述凸起位于所述像素电极与所述公共电极之间，所述凸起用于隔离所述像素电极和公共电极。
优选的，在所述阵列基板中，对应所述凸起位置处的所述第二绝缘层的厚度大于非凸起位置处的所述第二绝缘层的厚度。
优选的，在所述阵列基板中，对应所述凸起位置处的所述第二金属层的厚度大于非凸起位置处的所述第二金属层的厚度。
优选的，在所述阵列基板中，所述第一金属层还包括公共线；所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第一金属层上的所述公共线作为存储电容。
优选的，在所述阵列基板中，所述第二金属层还包括公共线；所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第二金属层上的所述公共线作为存储电容。
一种液晶显示面板，包括阵列基板、彩膜基板、以及设置于所述阵列基板与彩膜基板之间的液晶盒；其中，
所述阵列基板包括：
一基板；
一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层包括薄膜晶体管的栅极和扫描线；
一第一绝缘层，所述第一绝缘层设置于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
一所述第二金属层，所述第二金属层设置于所述第一绝缘层上；所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极以及数据线；
一第二绝缘层，所述第二绝缘层设置于所述第二金属层上，用于隔离所述第二金属层和像素电极层；
一凸起，所述凸起设置于所述第二绝缘层上；
一所述像素电极层，所述像素电极层设置于所述第二绝缘层上；所述像素电极层包括像素电极和公共电极；
其中，所述凸起位于所述像素电极与所述公共电极之间，所述凸起用于隔离所述像素电极和公共电极。
优选的，在所述液晶显示面板中，对应所述凸起位置处的所述第二绝缘层的厚度大于非凸起位置处的所述第二绝缘层的厚度。
优选的，在所述液晶显示面板中，对应所述凸起位置处的所述第二金属层的厚度大于非凸起位置处的所述第二金属层的厚度。
优选的，在所述液晶显示面板中，所述第一金属层还包括公共线；所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第一金属层上的所述公共线作为存储电容。
优选的，在所述液晶显示面板中，所述第二金属层还包括公共线；所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第二金属层上的所述公共线作为存储电容。
 有益效果
相对现有技术，本发明通过在第二绝缘层上设置有凸起，所述凸起位于像素电极层中的像素电极与公共电极之间，所述凸起用于隔离所述像素电极和公共电极。从而使得即使电容ITO与像素ITO位于同一层，也不会受到Particle的影响，避免了电容ITO和像素ITO发生短路，提高了产品的品质。类似于一堵墙挡在电容ITO和像素ITO之间，可以有效的防止ITO短路发生，避免由于Particle的影响导致的短路发生。所述凸起的设计使得Particle不易停留在地势较高的位置；即使有Particle落在所述凸起的位置，但在经过显影和蚀刻的过程中，因突起的位置很容易被显影液或者蚀刻液蚀刻掉，因此将大大降低因为Particle造成的短路。
 附图说明
图1为现有技术提供的阵列基板的结构示意图；
图2为本发明实施例二提供的阵列基板的结构示意图；
图3为本发明实施例三提供的阵列基板的结构示意图。
 本发明的最佳实施方式
本说明书所使用的词语“实施例”意指用作实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为意指“一个或多个”，除非另外指定或从上下文清楚导向单数形式。
在本发明实施例中，通过在第二绝缘层上设置有凸起，所述凸起位于像素电极层中的像素电极与公共电极之间，所述凸起用于隔离所述像素电极和公共电极。从而使得即使电容ITO与像素ITO位于同一层，也不会受到Particle的影响，避免了电容ITO和像素ITO发生短路，提高了产品的品质。
实施例一
请参阅图2，为本发明实施例提供的阵列基板的结构示意图。为了便于说明，仅示出了与本发明实施例相关的部分。
所述阵列基板包括：一基板100，一第一金属层101、一第一绝缘层102、一第二金属层103、一第二绝缘层104、以及一像素电极层105。其中，所述第一金属层101设置于所述基板100表面上；所述第一绝缘层102设置于所述第一金属层101上；所述第二金属层103设置于所述第一绝缘层102上；所述第一绝缘层102用于隔离所述第一金属层101和第二金属层103；所述第二绝缘层104设置于所述第二金属层103上；所述像素电极层105设置于所述第二绝缘层104上；所述第二绝缘层104用于隔离所述第二金属层103和像素电极层105。
在本发明实施例中，在基板100表面上沉积第一金属层101，并接着利用黄光及蚀刻工艺形成第一金属层101的图样，其中该第一金属层101的图样包括薄膜晶体管的栅极和扫描线。当所述像素电极层105中的公共电极与所述第一金属层101作为存储电容时，那么该第一金属层101的图样还包括公共线，该公共线与公共电极形成存储电容。
在本发明实施例中，溅射沉积第二金属层103后，并接着利用黄光及蚀刻工艺形成第二金属层103的图样，其中，所述第二金属层103的图样包括薄膜晶体管的源极、薄膜晶体管的漏极以及数据线。当所述像素电极层105中的公共电极与所述第二金属层103作为存储电容时，那么该第二金属层103的图样还包括公共线，该公共线与公共电极形成存储电容。
在本发明实施例中，溅射沉积一像素电极层105后，并接着利用黄光及蚀刻工艺形成所述像素电极层105的图样，其中，所述所述像素电极层105的图样包括像素电极和公共电极。
在本发明实施例中，所述像素电极层105采用ITO（Indium Tin Oxide，掺锡氧化铟）或铟锌氧化物IZO等等材料制成；所述第一绝缘层102可采用G-Sinx材料制成；所述第二绝缘层104可采用P-Sinx材料制成。然而，可以理解的是，并不限于上述材料，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
在本发明实施例中，在第二绝缘层104上设置有凸起106，所述凸起106位于像素电极层105中的像素电极与公共电极之间，所述凸起106用于隔离所述像素电极和公共电极。
在本发明实施例中，所述像素电极层105中的所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第一金属层101或所述第二金属层103上的公共线作为存储电容；由于所述像素电极层105中的所述像素电极与所述公共电极之间具有所述凸起106，因此能够将所述像素电极与所述公共电极隔离。
由上可知，所述凸起106位于所述像素电极层105（即同层ITO之间），类似于一堵墙挡在电容ITO和像素ITO之间，可以有效的防止ITO短路发生，避免由于Particle的影响导致的短路发生。所述凸起的设计使得Particle不易停留在地势较高的位置；即使有Particle落在所述凸起的位置，但在经过显影和蚀刻的过程中，因突起的位置很容易被显影液或者蚀刻液蚀刻掉，因此将大大降低因为Particle造成的短路。
实施例二
请参阅图2，为本发明实施例提供的阵列基板的结构示意图。为了便于说明，仅示出了与本发明实施例相关的部分。
所述阵列基板包括一基板100，以及依次设置于所述基板100表面上的第一金属层101、第一绝缘层102、第二金属层103、第二绝缘层104以及像素电极层105。其中，所述第一金属层101包括薄膜晶体管的栅极和扫描线；所述第二金属层103包括薄膜晶体管的源极、薄膜晶体管的漏极以及数据线；所述像素电极层105包括像素电极和公共电极。所述第一绝缘层102用于隔离所述第一金属层101和第二金属层103；所述第二绝缘层104用于隔离所述第二金属层103和像素电极层105。
在本发明实施例中，所述像素电极层105中的所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第一金属层101或所述第二金属层103上的公共线作为存储电容。在第二绝缘层104上设置有凸起106，所述凸起106位于像素电极层105中的像素电极与公共电极之间，所述凸起106用于隔离所述像素电极和公共电极。
本实施例二中，所述凸起106是由所述第二金属层103增厚而形成的。即对应所述凸起106位置处的所述第二金属层103的厚度大于非凸起位置处的所述第二金属层103的厚度。即在对应所述像素电极与所述公共电极之间的间隙位置的这一部分的所述第二金属层103，在对这一部分的所述第二金属层103进行涂抹光阻、曝光、显影、蚀刻操作时，使得该位置的厚度要比其他位置的厚度厚一些，这样便使得该位置的第二金属层103垫高该位置的第二绝缘层104，从而该位置的高度高出间隙高度，使得该间隙呈现出突起，类似于一堵墙挡在电容ITO和像素ITO之间，将电容ITO和像素ITO隔离，可以有效的防止ITO短路发生，避免由于Particle的影响导致的短路发生。
实施例三
请参阅图3，为本发明实施例提供的阵列基板的结构示意图。为了便于说明，仅示出了与本发明实施例相关的部分。
所述阵列基板包括：一基板100，一第一金属层101、一第一绝缘层102、一第二金属层103、一第二绝缘层104、以及一像素电极层105。其中，所述第一金属层101设置于所述基板100表面上；所述第一绝缘层102设置于所述第一金属层101上；所述第二金属层103设置于所述第一绝缘层102上；所述第一绝缘层102用于隔离所述第一金属层101和第二金属层103；所述第二绝缘层104设置于所述第二金属层103上；所述像素电极层105设置于所述第二绝缘层104上；所述第二绝缘层104用于隔离所述第二金属层103和像素电极层105。
其中，所述第一金属层101包括薄膜晶体管的栅极和扫描线；所述第二金属层103包括薄膜晶体管的源极、薄膜晶体管的漏极以及数据线；所述像素电极层105包括像素电极和公共电极。当所述像素电极层105中的公共电极与所述第一金属层101作为存储电容时，那么该第一金属层101的图样还包括公共线，该公共线与公共电极形成存储电容。当所述像素电极层105中的公共电极与所述第二金属层103作为存储电容时，那么该第二金属层103的图样还包括公共线，该公共线与公共电极形成存储电容。
在本发明实施例中，所述像素电极层105中的所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第一金属层101或所述第二金属层103上的公共线作为存储电容。在第二绝缘层104上设置有凸起106，所述凸起106位于像素电极层105中的像素电极与公共电极之间，所述凸起106用于隔离所述像素电极和公共电极。
在本实施例三中，所述凸起106是由所述第二绝缘层104增厚而形成的。即对应所述凸起位置处的所述第二绝缘层104的厚度大于非凸起位置处的所述第二绝缘层104的厚度。即在对应所述像素电极与所述公共电极之间的间隙位置的这一部分的所述第二绝缘层104，在对这一部分的所述第二绝缘层104进行涂抹光阻、曝光、显影、蚀刻操作时，使得该位置的厚度要比其他位置的厚度厚一些，这样便使得该位置的第二绝缘层104的高度高出间隙高度，使得该间隙呈现出突起，类似于一堵墙挡在电容ITO和像素ITO之间，将电容ITO和像素ITO隔离，可以有效的防止ITO短路发生，避免由于Particle的影响导致的短路发生。所述凸起的设计使得Particle不易停留在地势较高的位置；即使有Particle落在所述凸起的位置，但在经过显影和蚀刻的过程中，因突起的位置很容易被显影液或者蚀刻液蚀刻掉，因此将大大降低因为Particle造成的短路。
实施例四
本发明实施例还提供了一种液晶显示面板。为了便于说明，仅示出了与本发明实施例相关的部分。所述液晶显示面板包括阵列基板、彩膜基板、以及设置于所述阵列基板与彩膜基板之间的液晶盒。
所述阵列基板包括：一基板100，一第一金属层101、一第一绝缘层102、一第二金属层103、一第二绝缘层104、以及一像素电极层105。其中，所述第一金属层101设置于所述基板100表面上；所述第一绝缘层102设置于所述第一金属层101上；所述第二金属层103设置于所述第一绝缘层102上；所述第一绝缘层102用于隔离所述第一金属层101和第二金属层103；所述第二绝缘层104设置于所述第二金属层103上；所述像素电极层105设置于所述第二绝缘层104上；所述第二绝缘层104用于隔离所述第二金属层103和像素电极层105。
其中，所述第一金属层101包括薄膜晶体管的栅极和扫描线；所述第二金属层103包括薄膜晶体管的源极、薄膜晶体管的漏极以及数据线；所述像素电极层105包括像素电极和公共电极。当所述像素电极层105中的公共电极与所述第一金属层101作为存储电容时，那么该第一金属层101的图样还包括公共线，该公共线与公共电极形成存储电容。当所述像素电极层105中的公共电极与所述第二金属层103作为存储电容时，那么该第二金属层103的图样还包括公共线，该公共线与公共电极形成存储电容。
在本发明实施例中，所述像素电极层105中的所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第一金属层101或所述第二金属层103上的公共线作为存储电容。在第二绝缘层104上设置有凸起106，所述凸起106位于像素电极层105中的像素电极与公共电极之间，所述凸起106用于隔离所述像素电极和公共电极。
然而，可以理解的是，所述凸起可以是由所述第二绝缘层增厚而形成的；即对应所述凸起位置处的所述第二绝缘层104的厚度大于非凸起位置处的所述第二绝缘层104的厚度。或者是，所述凸起可以是由所述第二金属层增厚而形成的；即对应所述凸起106位置处的所述第二金属层103的厚度大于非凸起位置处的所述第二金属层103的厚度。
综上所述，通过在第二绝缘层上设置有凸起，所述凸起可以是由所述第二绝缘层增厚而形成的；或者是，所述凸起可以是由所述第二金属层增厚而形成的；所述凸起位于像素电极层中的像素电极与公共电极之间，所述凸起用于隔离所述像素电极和公共电极。从而使得即使电容ITO与像素ITO位于同一层，也不会受到Particle的影响，避免了电容ITO和像素ITO发生短路，提高了产品的品质。类似于一堵墙挡在电容ITO和像素ITO之间，可以有效的防止ITO短路发生，避免由于Particle的影响导致的短路发生。所述凸起的设计使得Particle不易停留在地势较高的位置；即使有Particle落在所述凸起的位置，但在经过显影和蚀刻的过程中，因突起的位置很容易被显影液或者蚀刻液蚀刻掉，因此将大大降低因为Particle造成的短路。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种阵列基板，其中所述阵列基板包括：
    一基板；
    一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层包括薄膜晶体管的栅极和扫描线；
    一第一绝缘层，所述第一绝缘层设置于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
    一所述第二金属层，所述第二金属层设置于所述第一绝缘层上；所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极以及数据线；
    一第二绝缘层，所述第二绝缘层设置于所述第二金属层上，用于隔离所述第二金属层和像素电极层；
    一凸起，所述凸起设置于所述第二绝缘层上；
    一所述像素电极层，所述像素电极层设置于所述第二绝缘层上；所述像素电极层包括像素电极和公共电极；
    其中，所述凸起位于所述像素电极与所述公共电极之间，所述凸起用于隔离所述像素电极和公共电极；
    其中，对应所述凸起位置处的所述第二绝缘层的厚度大于非凸起位置处的所述第二绝缘层的厚度；对应所述凸起位置处的所述第二金属层的厚度大于非凸起位置处的所述第二金属层的厚度。
  2. 根据权利要求1所述的阵列基板，其中所述第一金属层还包括公共线；所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第一金属层上的所述公共线作为存储电容。
  3. 根据权利要求1所述的阵列基板，其中所述第二金属层还包括公共线；所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第二金属层上的所述公共线作为存储电容。
  4. 根据权利要求1所述的阵列基板，其中所述像素电极层采用掺锡氧化铟ITO材料制成。
  5. 根据权利要求1所述的阵列基板，其中所述第一绝缘层采用G-Sinx材料制成。
  6. 根据权利要求1所述的阵列基板，其中所述第二绝缘层采用P-Sinx材料制成。
  7. 一种阵列基板，其中所述阵列基板包括：
    一基板；
    一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层包括薄膜晶体管的栅极和扫描线；
    一第一绝缘层，所述第一绝缘层设置于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
    一所述第二金属层，所述第二金属层设置于所述第一绝缘层上；所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极以及数据线；
    一第二绝缘层，所述第二绝缘层设置于所述第二金属层上，用于隔离所述第二金属层和像素电极层；
    一凸起，所述凸起设置于所述第二绝缘层上；
    一所述像素电极层，所述像素电极层设置于所述第二绝缘层上；所述像素电极层包括像素电极和公共电极；
    其中，所述凸起位于所述像素电极与所述公共电极之间，所述凸起用于隔离所述像素电极和公共电极。
  8. 根据权利要求7所述的阵列基板，其中对应所述凸起位置处的所述第二绝缘层的厚度大于非凸起位置处的所述第二绝缘层的厚度。
  9. 根据权利要求7所述的阵列基板，其中对应所述凸起位置处的所述第二金属层的厚度大于非凸起位置处的所述第二金属层的厚度。
  10. 根据权利要求7所述的阵列基板，其中所述第一金属层还包括公共线；所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第一金属层上的所述公共线作为存储电容。
  11. 根据权利要求7所述的阵列基板，其中所述第二金属层还包括公共线；所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第二金属层上的所述公共线作为存储电容。
  12. 一种液晶显示面板，包括阵列基板、彩膜基板、以及设置于所述阵列基板与彩膜基板之间的液晶盒；其中
    所述阵列基板包括：
    一基板；
    一第一金属层，所述第一金属层设置于所述基板表面上；所述第一金属层包括薄膜晶体管的栅极和扫描线；
    一第一绝缘层，所述第一绝缘层设置于所述第一金属层上，用于隔离所述第一金属层和第二金属层；
    一所述第二金属层，所述第二金属层设置于所述第一绝缘层上；所述第二金属层包括薄膜晶体管的源极、薄膜晶体管的漏极以及数据线；
    一第二绝缘层，所述第二绝缘层设置于所述第二金属层上，用于隔离所述第二金属层和像素电极层；
    一凸起，所述凸起设置于所述第二绝缘层上；
    一所述像素电极层，所述像素电极层设置于所述第二绝缘层上；所述像素电极层包括像素电极和公共电极；
    其中，所述凸起位于所述像素电极与所述公共电极之间，所述凸起用于隔离所述像素电极和公共电极。
  13. 根据权利要求12所述的液晶显示面板，其中对应所述凸起位置处的所述第二绝缘层的厚度大于非凸起位置处的所述第二绝缘层的厚度。
  14. 根据权利要求12所述的液晶显示面板，其中对应所述凸起位置处的所述第二金属层的厚度大于非凸起位置处的所述第二金属层的厚度。
  15. 根据权利要求12所述的液晶显示面板，其中所述第一金属层还包括公共线；所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第一金属层上的所述公共线作为存储电容。
  16. 根据权利要求12所述的液晶显示面板，其中所述第二金属层还包括公共线；所述像素电极与相对的基板上的共通电极作为像素电容，所述公共电极与所述第二金属层上的所述公共线作为存储电容。
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