WO2016113032A1 - Optoelektronisches halbleiterbauelement und dessen herstellungsverfahren - Google Patents
Optoelektronisches halbleiterbauelement und dessen herstellungsverfahren Download PDFInfo
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- WO2016113032A1 WO2016113032A1 PCT/EP2015/078225 EP2015078225W WO2016113032A1 WO 2016113032 A1 WO2016113032 A1 WO 2016113032A1 EP 2015078225 W EP2015078225 W EP 2015078225W WO 2016113032 A1 WO2016113032 A1 WO 2016113032A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
Definitions
- a component and a method for producing a component are specified.
- the latter has a semiconductor body with an active layer.
- the active layer is a p-n transition zone.
- the active layer may be formed as a layer or as a layer sequence of several layers. in the
- an electromagnetic radiation such as in the visible, ultraviolet or infrared spectral range.
- the active layer may absorb electromagnetic radiation and convert it into electrical signals or electrical energy.
- the semiconductor body may have a first
- the semiconductor body has exclusively semiconductor layers.
- the layers of the semiconductor body can be applied in layers to a growth substrate by means of an epitaxial process. The Growth substrate may then be removed or thinned from the semiconductor body, so that the device for
- Example is free from a growth substrate.
- the semiconductor body has a first main surface which preferably serves as a radiation passage area of the
- the radiation passage area can be structured, as a result of which a radiation coupling-out or radiation coupling-in efficiency is increased.
- the first main surface of the semiconductor body is formed by a surface of the first semiconductor layer.
- the semiconductor body has a second main surface facing away from the first main surface, which is formed, for example, by a surface of the second semiconductor layer.
- the first main surface and the second main surface define the semiconductor body in the vertical direction.
- Main extension plane of the active layer is directed.
- the vertical direction is perpendicular to the first and / or the second main surface of the semiconductor body.
- a lateral direction is understood to mean a direction which runs along, in particular parallel to, the
- Main extension plane of the active layer extends.
- the vertical direction and the lateral direction are
- the semiconductor body has at least one recess.
- Recess Main surface through the second semiconductor layer and the active layer into the first semiconductor layer.
- Recess is understood to mean an opening of the semiconductor body, which is in particular not continuously formed by the semiconductor body. In other words, the recess becomes a blind hole in the semiconductor body
- the semiconductor body may have a plurality of such recesses.
- the recess may be filled with an electrically conductive material.
- the device may have a plurality of such
- this has a first metal layer.
- the first metal layer is, for example, on one of the second main surface
- the first metal layer may have one or a plurality of openings.
- the through-hole extends in the vertical direction through the opening of the first
- Semiconductor bodies are the first metal layer and the
- the first metal layer covers the semiconductor body or the active layer
- the first metal layer is an electrodeposited one
- this has a second metal layer.
- the first metal layer is at least partially between the semiconductor body and arranged the second metal layer.
- the second metal layer has a first portion and a second laterally spaced from the first portion second
- the first subregion is in particular electrically connected to the via contact for the electrical contacting of the first semiconductor layer.
- the first subregion is electrically insulated from the first metal layer.
- the first portion of the second metal layer is associated with a first electrical polarity of the device.
- the first metal layer is associated with a different from the first electrical polarity second electrical polarity of the device.
- the first metal layer and the first portion of the second metal layer thus have different polarities.
- the first metal layer for a p-side contacting and the first portion of the second metal layer for n-side contacting of the device is provided.
- the second subregion of the second metal layer may be electrically connected to the first metal layer and is therefore in particular the second one
- the second subregion adjoins the first metal layer in certain regions.
- the second partial region may be electrically connected to the second semiconductor layer via the first metal layer.
- the first Metal layer and the second metal layer together can completely cover the entire active layer.
- this has in the lateral direction between the first
- the gap of the first metal layer is at least
- the second metal layer may over the first
- Protrude metal layer For example, the active layer or the entire semiconductor body has no location that is not mechanically supported by the first metal layer or by the second metal layer.
- the latter has a semiconductor body, a first metal layer and a second metal layer, wherein the first metal layer is arranged between the semiconductor body and the second metal layer.
- the semiconductor body has a first one
- Component has a via, which in particular in the vertical direction through the second
- the second metal layer has a first one
- the first metal layer completely bridges the gap laterally.
- Metal layer assigned to a different from the first electrical polarity second electrical polarity of the device.
- a laterally complete bridging of the intermediate space means, in particular, that the first partial area and the second partial area are completely bridged at locations of the intermediate space, at least along a lateral direction, of the first metal layer.
- the first metal layer in plan view covers at least 60%, at least 80% or at least 90%, about 95% of the total
- the entire gap is free of a location that is not covered by the first metal layer and / or by the second metal layer.
- Interspace through the first metal layer has a mechanically stabilizing effect on the component, so that possible
- the first metal layer may be formed as a mechanically stabilizing, preferably as a self-supporting layer of the device. In other words, the first metal layer may act as a self-contained layer
- the first metal layer can be coherent
- the first metal layer in the vertical direction a thickness between 5 ym and 50 ym inclusive.
- the thickness of the first metal layer is between 5 ym and 30 ym inclusive, approximately between 5 ym and 15 ym inclusive.
- the second metal layer may be considered a mechanical one
- the second metal layer has a greater thickness compared to the first metal layer.
- the thickness of the second metal layer is between
- the thickness of the second metal layer including 10 ym and 200 ym, approximately between 10 ym and 100 ym, in particular between 50 ym and 100 ym inclusive.
- the thickness of the second metal layer including 10 ym and 200 ym, approximately between 10 ym and 100 ym, in particular between 50 ym and 100 ym inclusive.
- the thickness of the first metal layer at least 2 times, about 4 times or 10 times the thickness of the first metal layer.
- Ratio of the thickness of the second metal layer to the thickness of the first metal layer between 2 and 10 inclusive, approximately between 5 and 10 inclusive.
- Overlapping of the active layer does not leave a region of the active layer of the device without a mechanical
- Growth substrate in particular by an etching or a Laser lifting method, significantly more resistant to soldering, structuring, transporting or placing.
- the second metal layer is bounded laterally by a shaped body, for example by an electrically insulating casting compound.
- the first partial area and the second partial area are preferably embedded in the shaped body.
- the first partial area and the second partial area respectively adjoin the molded body on all sides in the lateral direction.
- Shaped body can be integrally, so coherently formed.
- the gap is at least partially, in particular completely, filled by a material of the shaped body.
- the laterally spaced partial regions of the second metal layer can thus be held together by the shaped body and thus together with the shaped body form a mechanically particularly stable carrier of the component.
- the first metal layer and / or the second metal layer are an electrodeposited metal layer.
- the metal layers comprise a metal such as nickel, copper or other metals.
- the first metal layer and the second metal layer may each comprise a first metal and at least one other
- the proportion of the first metal is in particular at least 90 atomic percent, about at least 95 or 98 atomic percent of the first and / or the second
- the metal layers are formed in terms of their materials so that the first metal layer has a higher modulus of elasticity than the second metal layer and / or the second metal layer has a higher thermal conductivity than the first Metal layer.
- the first metal layer comprises nickel and the second metal layer comprises copper.
- this has an electrically conductive layer, which is arranged between the first metal layer and the second metal layer.
- the electrically conductive layer is formed as a mirror layer and may have a metal.
- the electrically conductive layer covers the active layer in plan view at least partially. Along the vertical direction, the electrically conductive layer can laterally of the second
- Electromagnetic radiations which emerge laterally or backwards out of the semiconductor body, can thus be returned to
- the electrically conductive layer may in particular as a
- Mirror layer may be formed.
- the electrically conductive layer may include a first sub-layer and a second sub-layer laterally rejected by the first sub-layer, wherein the first sub-layer is electrically connected, for example, to the first sub-region of the second metal layer and the second sub-layer is electrically connected to the second sub-region of the second metal layer.
- the sub-layers of the electrically conductive layer are also laterally spaced from each other by the gap between the sub-regions of the second metal layer. For example, a trench is the electrically conductive
- the electrically conductive layer serves as a galvanic coating method
- Metal layer may adjoin the first sub-layer of the electrically conductive layer and the second sub-region to the second sub-layer.
- the first subsection is the second
- the first subarea may be at the first
- Adjacent sub-layer wherein the first sub-layer can also adjoin the via.
- the plated through-hole overlaps in particular with the first partial region of the second metal layer.
- the via can be in the vertical direction of the first
- Partial layer of the electrically conductive layer through the first metal layer, the second semiconductor layer and the active layer extend into the first semiconductor layer, whereby in the electrical contacting of the first semiconductor layer to a complex
- this has an insulation layer, at least
- Isolation is the insulation layer, for example
- Insulating layer may include a first opening or a plurality of first openings, wherein the
- the insulation layer can completely cover inner walls of the recess.
- the insulating layer may extend in regions through the first metal layer.
- the insulating layer and the first metal layer have, in particular in the region of the recess, a common opening, wherein the
- conductive layer extends through the common opening to the first semiconductor layer.
- the insulating layer may also have a second opening or a plurality of second openings, wherein the second portion of the second metal layer for electrically contacting the first metal layer through the second
- the second subregion may adjoin the first metal layer in the second opening. It is also possible that the electric
- a conductive layer such as a radiation-reflecting metal-containing layer is disposed in the second opening between the first metal layer and the second portion of the second metal layer.
- a current distribution layer is arranged between the semiconductor body and the first metal layer.
- Current distribution layer is formed electrically conductive and adjacent, for example, partially to the first
- an electrically conductive connection layer is arranged between the semiconductor body and the first metal layer.
- the connection layer is designed to be radiation-reflecting.
- the connection layer is in particular adjacent to the semiconductor body, for example to the second semiconductor layer. In this case, the connection layer via the first metal layer with the second portion of the second metal layer
- the second semiconductor layer is thus in particular via the connection layer, the
- the latter has a diffusion barrier layer, which is arranged, for example, between the connection layer and the current distribution layer.
- a diffusion barrier layer By means of the diffusion barrier layer, it is possible to prevent metal atoms or metal ions from the current distribution layer or the metal layers from entering the
- Substrate layer migrate into the semiconductor body and thus in the active layer and damage them.
- this has a passivation layer, which is arranged between the first metal layer and the semiconductor body.
- the passivation layer may be one or a plurality of
- Terminal layer extends. In plan view, the
- the passivation layer encloses the
- Terminal layer Terminal layer, the diffusion barrier layer and the
- Passivation layer extends in the vertical direction, for example, from the first metal layer to the semiconductor body and in particular adjacent to the
- the first metal layer is arranged approximately between the passivation layer and the insulating layer.
- the passivation layer partially as a
- the passivation layer may be formed as part of the insulating layer or may be optional.
- this is the first subregion and the second
- the Radiation passage area is thus in particular free of electrical contacts or printed conductors.
- a semiconductor body is provided, for example, grown epitaxially.
- a first metal layer is formed on the semiconductor body, for instance by means of a galvanic deposition method. In this case, the first
- Metal layer on an electrically conductive starting layer which is formed in particular on a side facing away from the semiconductor body of a passivation layer, be electrodeposited. Furthermore, an electric
- conductive layer in particular a metal-containing
- an insulating layer may be formed at least for partial electrical insulation between the electrically conductive layer and the first metal layer.
- the electrically conductive layer may be electrically connected in regions with the via.
- the conductive layer has a first one
- the second sub-layer may be electrically connected to the first metal layer.
- a first subregion and a second region laterally spaced from the first subregion by a gap can be used
- Gap bridged in particular by the first metal layer and thus at least along a lateral
- the first metal layer may completely cover the gap in plan view.
- the first subarea is electrically connected, in particular via the first sublayer, to the plated through hole.
- the second partial region can be approximately directly or via the second partial layer with the first metal layer
- the second metal layer is provided with an electrically insulating
- the first subregion and the second subregion are preferably embedded in the potting compound, so that they are enclosed on all sides by the potting compound at least in the lateral direction.
- Interspace between the first and the second portion is at least partially, preferably completely, filled by a material of the potting compound.
- the method is particularly suitable for the production of a device as described above.
- Figure 1 is a schematic representation of a
- Figure 2 is a schematic representation of a lateral
- FIG. 3 is a schematic representation of another
- Embodiment of a component Embodiment of a component.
- FIG. 100 A first exemplary embodiment of a component is shown schematically in FIG.
- the component 100 has a carrier 1 and one arranged on the carrier
- the semiconductor body 2 has a first semiconductor layer 21, a second semiconductor layer 22 and one between the first and the second
- the first semiconductor layer 21, the second semiconductor layer 22 and the active layer 23 may each have one or a
- the active layer 23 is in particular a p-n junction zone of the semiconductor body.
- the active layer 23 is in particular a p-n junction zone of the semiconductor body.
- the first semiconductor layer and / or the second semiconductor layer have a GaN, GaP or GaAs layer. These layers can additionally comprise aluminum and / or indium and are formed approximately as an AlGaN, InAlGaN or InAlGaP layer.
- Semiconductor layer 22 may be n-type, for example
- second semiconductor layer 22 is p-type.
- the device 100 is in particular free of a growth substrate.
- the component has a radiation passage area 101 and a rear side 102 facing away from the radiation passage area.
- the radiation passage area 101 is structured.
- the radiation passage area 101 is formed by a first main area 201 of the semiconductor body 2, for instance by a surface of the first semiconductor layer 21. It is also possible that the
- the device 100 is external via the rear side 102
- the device 100 may be formed as a surface mountable device.
- connection layer 8 In the figure 1 are a connection layer 8, a
- Diffusion barrier layer 7 a current distribution layer 5, a passivation layer 90, a first metal layer 3, an insulating layer 9 and an electrically conductive
- the carrier 1 has a second metal layer 4.
- the second metal layer includes a first portion 41 and one of the first portion 41 laterally spatially
- a gap 40 is between the first portion 41 and the second
- Partial region 42 is formed so that the first portion 41 is electrically isolated from the second portion 42.
- the carrier 1 also has a shaped body 10.
- the molded body 10 is in particular electrically insulating
- the molded body 10 is formed as a potting compound.
- the second metal layer 4 with the first partial region 41 and the second partial region 42 is in particular laterally full of the molded body 10
- Subarea 42 border here in particular in lateral
- the intermediate space 40 is completely filled, for example, with an electrically insulating material of the shaped body.
- the portions 41 and 42 of the second metal layer 4 are in particular by the
- Shaped body 10 held together mechanically stable. In the lateral direction, the second extends
- Metal layer 4 for example, not to the edge of
- Component 100 and is embedded in lateral directions, in particular completely in the molded body 10.
- the first metal layer 3 is arranged between the semiconductor body 2 and the second metal layer 4. In plan view the first metal layer 3 completely bridges the gap 40 at least along a lateral direction.
- the first metal layer 3 covers at least 60%, approximately at least 80% or at least 90%, approximately approximately 95% of the total gap 40.
- the first metal layer 3 is formed as a mechanically stabilizing layer of the device.
- the first metal layer 3 has a vertical thickness of at least 5 ⁇ m, in particular at least 10 ⁇ m.
- the thickness of the first metal layer 3 is between 5 ym and 50 ym inclusive, approximately between 5 ym and 30 ym, or between 10 ym and 20 ym. Due to the at least laterally complete
- Metal layer 3 is the device in the areas of
- the first metal layer 3 is in particular formed coherently. In plan view, the semiconductor body 2 covers the first metal layer 3 in particular completely. In lateral directions, the first metal layer 3 of the
- Insulation layer 9 surrounded.
- the second metal layer 4 may be considered a mechanical one
- the second metal layer 4 for example in the overlapping regions with the first metal layer 3, has a vertical thickness that is, for example, at least as great, preferably at least 2 times, approximately 4 times or 10 times as large as a thickness of the first one Metal layer 3 is.
- Metal layer 4 together the active layer 23 in plan view completely. With a complete overlap of the active layer 23, in particular no region of the active remains
- the first metal layer 3 and the second metal layer 4 may each be an electrodeposited metal layer. You can use the same metal, such as nickel or
- the first metal layer 3 has a higher modulus of elasticity than the second metal layer 4.
- the second metal layer 4 has, for example, a higher thermal conductivity than the first metal layer 3.
- the first metal layer 3 has a higher modulus of elasticity than the second metal layer 4.
- the second metal layer 4 has, for example, a higher thermal conductivity than the first metal layer 3.
- Metal layer 3 nickel and the second metal layer 4 copper.
- the insulating layer 9 is arranged.
- the first metal layer 3 is electrically insulated from the first partial region 41 of the second metal layer 4.
- the insulation layer 9 may be formed contiguous. It is possible that an adhesive layer (not shown) between the first
- This adhesive layer can be applied to the first metal layer 3 by means of a coating method, for example by means of vapor deposition.
- the adhesive layer comprises titanium or chromium.
- Isolation layer 9 can be achieved.
- the insulating layer 9 and the first metal layer 3 have a common opening 91, through which the Through hole 24 extends therethrough. Furthermore, the insulation layer 9 has at least one second opening 92, through which the second portion 42 of the second
- the second metal layer 4 is a metal layer which is galvanically deposited on the insulation layer 9.
- an electrically conductive layer 6 may be applied to the insulating layer 9.
- This electrically conductive layer 6 can then be patterned so that the gap 40
- the electrically conductive layer 6 serves in particular as a seed layer for the second metal layer 4 with the subregions 41 and 42, for example in a galvanic coating process.
- the electrically conductive layer 6 is preferably formed as a mirror layer.
- it has a metal such as aluminum, rhodium, palladium, silver or gold.
- a metal such as aluminum, rhodium, palladium, silver or gold.
- the electrically conductive layer 6 reflects at least 60%, preferably at least 80%, especially
- the electrically conductive layer 6 extends in the lateral direction Direction beyond the second semiconductor layer 22 and the active layer 23 addition. It is in the lateral direction
- Shaped body 10 limited and in particular fully surrounded.
- the electrically conductive layer 6 can be protected from environmental influences such as moisture or oxygen.
- the diffusion barrier layer 7 is arranged. This layer prevents in particular the
- connection layer 8 is arranged between the semiconductor body 2 and the diffusion barrier layer 7, wherein the connection layer 8 is electrically conductive and preferred
- Radiation reflective is formed, e.g. from Ag, Al, Pd, Rh, Au, ITO, ZnO.
- Radiation reflective is formed, e.g. from Ag, Al, Pd, Rh, Au, ITO, ZnO.
- Terminal layer 8 together the active layer 23rd
- the device has a passivation layer 90 which includes the connection layer 8, the diffusion barrier layer 7 and the current distribution layer 5 in lateral directions
- the electric The conductive layer 6 and the insulating layer 9 have a step at the edge of the device and are formed such that the second semiconductor layer 22 and the active layer 23 are partially surrounded by the insulating layer 9 or the electrically conductive layer 6. Radiation exiting to the rear side 102 of the component 100 can thus be reflected back from the electrically conductive layer 6 in the direction of the radiation passage area 101.
- the insulation layer 9 is permeable to the radiation generated during operation of the device 100.
- the semiconductor body 2 has a recess 25.
- the recess 25 extends from the second main surface 202 of the semiconductor body 2 through the second semiconductor layer 22 and the active layer 23 into the first one
- the plated-through hole 24 is surrounded in the lateral direction, in particular completely, by the insulating layer 9.
- the via 24 comprises an electrically conductive material, such as a metal.
- about the electrically conductive layer 6 is the
- Through-hole 24 and the electrically conductive layer 6 may comprise a same electrically conductive material or different materials.
- Through-hole 24 is in particular in the direct
- the device 100 has a plurality of plated-through holes 24 for electrically contacting the first semiconductor layer 21, whereby a particularly uniform current distribution within the first semiconductor layer 21 is achieved.
- the component 100 is formed on the rear side 102, that is, on the rear side, electrically contacted.
- Component 100 can thus be electrically connected via the first subregion 41 and the second subregion 42 to an external voltage source.
- the semiconductor body 2 covers the first and second sub-regions 41 and 42 of the second metal layer 4 completely, in particular.
- the contact layers 410 and 420 cover the first portion 41 and the second, respectively
- Subarea 42 for example, completely or in each case in particular beyond these subregions 41 and 42 addition.
- the first contact layer 410 is particularly useful as an
- Contact layer and the second contact layer 420 is formed approximately as a p-contact layer.
- FIG. 2 shows a lateral section of the component 100 along a line AA 'marked in FIG.
- the component 100 has common openings 91 of the first metal layer 3 and of the insulation layer 9, through which the plated-through hole 24 extends for electrical contacting of the first semiconductor layer 21.
- FIG. 2 shows two such common openings. Deviating from this, the component 100 can only one or have more than two such openings 91.
- the metal layer 3 has an opening 30 in which the
- Insulation layer 9 for electrical insulation between the via 24 and the first metal layer 3rd
- the via 24 extends from the electrically conductive layer 6, which is formed in particular as a mirror layer, through the opening of the first metal layer 3, in particular through the common opening 91 to the first semiconductor layer 21.
- the electrically conductive layer 6 has a first sub-layer 61 and one laterally from the first sub-layer 61
- the partial layers 61 and 62 are spatially separated from one another by a trench 60 in the region of the intermediate space 40.
- the trench 60 may be made of an electrically insulating material, such as a material of the
- Shaped body 10 be filled.
- the first portion 41 of the second metal layer 4 is electrically connected directly to the via 24 via the first sub-layer 61.
- the first sub-region 41, the first sub-layer 61 and the plated-through hole 24 are thus assigned to a first, approximately n-side polarity of the device 100.
- the passivation layer 90 has a
- Metal layer 3 therethrough for electrically contacting the second semiconductor layer 22 extends.
- Metal layer 3 is in particular with the second portion 42 of the second metal layer 4 is electrically connected.
- Metal layer 3 and the second portion 42 is arranged.
- the second subregion 42, the second sublayer 62 and the first metal layer 3 are thus assigned to a second, approximately p-side, polarity of the device 100, which is different from the first polarity.
- the first metal layer 3 is in the lateral direction of the electrically conductive layer 6 and of the second
- Metal layer 4 is laterally fully enclosed by the molding 10 laterally.
- Component 100 shown schematically. This
- Embodiment corresponds essentially to the embodiment shown in the figure 1.
- the entire semiconductor body 2 including the first semiconductor layer 21 is bounded laterally by the insulating layer 9. It is the whole
- the insulating layer 9 closes in particular with the
- the first metal layer 3 and the second metal layer 4 may together comprise the entire
- Partial areas are contacted externally electrically.
- the device can be free of
- German Patent Application 10 2015 100 578.6 is claimed, the disclosure of which is hereby incorporated by reference.
- the invention is not limited by the description of the invention based on the embodiments of these. Rather, the invention encompasses any novel feature as well as any combination of features, which in particular includes any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments.
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201580073667.7A CN107112392B (zh) | 2015-01-15 | 2015-12-01 | 光电子半导体器件及其制造方法 |
US15/542,935 US10312413B2 (en) | 2015-01-15 | 2015-12-01 | Optoelectronic semiconductor component and method for producing the same |
KR1020177019740A KR102391398B1 (ko) | 2015-01-15 | 2015-12-01 | 광전자 반도체 디바이스 및 이를 제조하기 위한 방법 |
JP2017537369A JP6732759B2 (ja) | 2015-01-15 | 2015-12-01 | オプトエレクトロニクス半導体素子およびオプトエレクトロニクス半導体素子の製造方法 |
DE112015005964.4T DE112015005964A5 (de) | 2015-01-15 | 2015-12-01 | Bauelement und Verfahren zur Herstellung eines Bauelements |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102015100578.6A DE102015100578A1 (de) | 2015-01-15 | 2015-01-15 | Bauelement und Verfahren zur Herstellung eines Bauelements |
DE102015100578.6 | 2015-01-15 |
Publications (1)
Publication Number | Publication Date |
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WO2016113032A1 true WO2016113032A1 (de) | 2016-07-21 |
Family
ID=54780282
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/EP2015/078225 WO2016113032A1 (de) | 2015-01-15 | 2015-12-01 | Optoelektronisches halbleiterbauelement und dessen herstellungsverfahren |
Country Status (6)
Country | Link |
---|---|
US (1) | US10312413B2 (de) |
JP (1) | JP6732759B2 (de) |
KR (1) | KR102391398B1 (de) |
CN (1) | CN107112392B (de) |
DE (2) | DE102015100578A1 (de) |
WO (1) | WO2016113032A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102017106508A1 (de) | 2017-03-27 | 2018-09-27 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauteil und Herstellungsverfahren |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102015105509A1 (de) | 2015-04-10 | 2016-10-13 | Osram Opto Semiconductors Gmbh | Bauelement und Verfahren zur Herstellung eines Bauelements |
DE102015117198A1 (de) | 2015-10-08 | 2017-04-13 | Osram Opto Semiconductors Gmbh | Bauelement und Verfahren zur Herstellung eines Bauelements |
KR20170111974A (ko) * | 2016-03-30 | 2017-10-12 | 엘지이노텍 주식회사 | 발광소자, 백라이트 유닛 및 조명장치 |
WO2018059697A1 (en) * | 2016-09-29 | 2018-04-05 | Osram Opto Semiconductors Gmbh | Optoelectronic semiconductor chip package and manufacturing method thereof |
DE102016124380A1 (de) * | 2016-12-14 | 2018-06-14 | Osram Opto Semiconductors Gmbh | Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements |
DE102017111278A1 (de) * | 2017-05-23 | 2018-11-29 | Osram Opto Semiconductors Gmbh | Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements |
DE102017111277A1 (de) * | 2017-05-23 | 2018-11-29 | Osram Opto Semiconductors Gmbh | Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements |
DE102017111279A1 (de) * | 2017-05-23 | 2018-11-29 | Osram Opto Semiconductors Gmbh | Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements |
US20210167252A1 (en) * | 2018-07-04 | 2021-06-03 | Lg Innotek Co., Ltd. | Semiconductor device and manufacturing method therefor |
DE102018122492A1 (de) * | 2018-09-14 | 2020-03-19 | Osram Opto Semiconductors Gmbh | Optoelektronisches halbleiterbauelement mit einer ersten und zweiten metallschicht sowie verfahren zur herstellung des optoelektronischen halbleiterbauelements |
DE102018122568A1 (de) * | 2018-09-14 | 2020-03-19 | Osram Opto Semiconductors Gmbh | Optoelektronisches halbleiterbauelement mit erstem und zweitem kontaktelement und verfahren zur herstellung des optoelektronischen halbleiterbauelements |
DE102018128692A1 (de) * | 2018-11-15 | 2020-05-20 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauelement mit ersten Verbindungsbereichen und optoelektronische Vorrichtung |
FR3091411B1 (fr) * | 2018-12-28 | 2021-01-29 | Commissariat Energie Atomique | Procédés de fabrication optimisés d’une structure destinée à être assemblée par hybridation et d’un dispositif comprenant une telle structure |
DE102019106938A1 (de) * | 2019-03-19 | 2020-09-24 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronisches Halbleiterbauelement mit isolierender Schicht und Verfahren zur Herstellung des optoelektronischen Halbleiterbauelements |
DE102021209250A1 (de) * | 2021-08-24 | 2023-03-02 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Schichtenstapel für einen Halbleiterchip, Halbleiterchip und Verfahren zur Herstellung eines Schichtenstapels für einen Halbleiterchip |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2365542A1 (de) * | 2010-03-09 | 2011-09-14 | Kabushiki Kaisha Toshiba | Lichtemittierendes Halbleiterbauelement und Herstellungsverfahren |
DE102010025320A1 (de) * | 2010-06-28 | 2011-12-29 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement und Verfahren zu dessen Herstellung |
US20120074441A1 (en) * | 2010-09-24 | 2012-03-29 | Seoul Semiconductor Co., Ltd. | Wafer-level light emitting diode package and method of fabricating the same |
EP2680326A2 (de) * | 2012-06-28 | 2014-01-01 | Kabushiki Kaisha Toshiba | Lichtemittierendes Halbleiterbauelement |
WO2014128574A1 (en) * | 2013-02-19 | 2014-08-28 | Koninklijke Philips N.V. | A light emitting die component formed by multilayer structures |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4012833A (en) * | 1973-12-28 | 1977-03-22 | Sony Corporation | Method of making display structure having light emitting diodes |
JPS57193084A (en) * | 1981-05-22 | 1982-11-27 | Toshiba Corp | Light emitting device |
CN100365834C (zh) * | 2004-08-02 | 2008-01-30 | 晶元光电股份有限公司 | 具有热通道黏结层的发光二极管及发光二极管阵列 |
DE102007022947B4 (de) | 2007-04-26 | 2022-05-05 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronischer Halbleiterkörper und Verfahren zur Herstellung eines solchen |
US8368100B2 (en) * | 2007-11-14 | 2013-02-05 | Cree, Inc. | Semiconductor light emitting diodes having reflective structures and methods of fabricating same |
JP4875185B2 (ja) | 2010-06-07 | 2012-02-15 | 株式会社東芝 | 光半導体装置 |
US8558409B2 (en) * | 2010-07-09 | 2013-10-15 | Vestas Wind Systems A/S | High voltage switchgear power supply arrangement for a wind turbine facility |
DE102010027679A1 (de) | 2010-07-20 | 2012-01-26 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement |
KR101142965B1 (ko) * | 2010-09-24 | 2012-05-08 | 서울반도체 주식회사 | 웨이퍼 레벨 발광 다이오드 패키지 및 그것을 제조하는 방법 |
KR101293637B1 (ko) * | 2011-01-14 | 2013-08-13 | 서울대학교병원 | 줄기세포의 부유배양용 조성물 |
DE102012106953A1 (de) | 2012-07-30 | 2014-01-30 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung einer Mehrzahl von optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip |
DE102012217533A1 (de) * | 2012-09-27 | 2014-03-27 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines optoelektronischen Bauelements |
JP6308025B2 (ja) | 2014-05-30 | 2018-04-11 | 日亜化学工業株式会社 | 発光装置及び発光装置の製造方法 |
-
2015
- 2015-01-15 DE DE102015100578.6A patent/DE102015100578A1/de not_active Withdrawn
- 2015-12-01 WO PCT/EP2015/078225 patent/WO2016113032A1/de active Application Filing
- 2015-12-01 KR KR1020177019740A patent/KR102391398B1/ko active IP Right Grant
- 2015-12-01 DE DE112015005964.4T patent/DE112015005964A5/de active Pending
- 2015-12-01 JP JP2017537369A patent/JP6732759B2/ja active Active
- 2015-12-01 US US15/542,935 patent/US10312413B2/en active Active
- 2015-12-01 CN CN201580073667.7A patent/CN107112392B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2365542A1 (de) * | 2010-03-09 | 2011-09-14 | Kabushiki Kaisha Toshiba | Lichtemittierendes Halbleiterbauelement und Herstellungsverfahren |
DE102010025320A1 (de) * | 2010-06-28 | 2011-12-29 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement und Verfahren zu dessen Herstellung |
US20120074441A1 (en) * | 2010-09-24 | 2012-03-29 | Seoul Semiconductor Co., Ltd. | Wafer-level light emitting diode package and method of fabricating the same |
EP2680326A2 (de) * | 2012-06-28 | 2014-01-01 | Kabushiki Kaisha Toshiba | Lichtemittierendes Halbleiterbauelement |
WO2014128574A1 (en) * | 2013-02-19 | 2014-08-28 | Koninklijke Philips N.V. | A light emitting die component formed by multilayer structures |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102017106508A1 (de) | 2017-03-27 | 2018-09-27 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauteil und Herstellungsverfahren |
WO2018177807A1 (de) | 2017-03-27 | 2018-10-04 | Osram Opto Semiconductors Gmbh | Optoelektronisches halbleiterbauteil und herstellungsverfahren |
Also Published As
Publication number | Publication date |
---|---|
KR102391398B1 (ko) | 2022-04-26 |
DE102015100578A1 (de) | 2016-07-21 |
US10312413B2 (en) | 2019-06-04 |
DE112015005964A5 (de) | 2017-10-12 |
US20180358512A1 (en) | 2018-12-13 |
CN107112392B (zh) | 2019-08-13 |
KR20170104484A (ko) | 2017-09-15 |
JP2018502461A (ja) | 2018-01-25 |
JP6732759B2 (ja) | 2020-07-29 |
CN107112392A (zh) | 2017-08-29 |
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