WO2016112572A1 - 一种阵列基板的制作方法、阵列基板及显示面板 - Google Patents

一种阵列基板的制作方法、阵列基板及显示面板 Download PDF

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Publication number
WO2016112572A1
WO2016112572A1 PCT/CN2015/072643 CN2015072643W WO2016112572A1 WO 2016112572 A1 WO2016112572 A1 WO 2016112572A1 CN 2015072643 W CN2015072643 W CN 2015072643W WO 2016112572 A1 WO2016112572 A1 WO 2016112572A1
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Prior art keywords
electrode
layer
substrate
array substrate
semiconductor layer
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English (en)
French (fr)
Inventor
胡宇彤
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/438,225 priority Critical patent/US9798207B2/en
Publication of WO2016112572A1 publication Critical patent/WO2016112572A1/zh
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Definitions

  • the present invention relates to the field of display, and in particular to a method for fabricating an array substrate, an array substrate, and a display panel.
  • Low temperature polysilicon (Low Temperature Poly-silicon (LTPS) thin-film transistor liquid crystal display uses excimer laser as a heat source in the packaging process. After the laser light passes through the projection system, it generates a laser beam with uniform energy distribution and is projected onto the glass substrate of the amorphous silicon structure. When the amorphous silicon structured glass substrate absorbs the energy of the excimer laser, it is converted into a polycrystalline silicon structure. Since the entire process is completed below 600 ° C, a general glass substrate can be applied.
  • the traditional bottom-gate type LTPS pixel layer has many structures, and the fabrication is relatively complicated, and a larger number of photomasks are needed for production, which greatly increases the production cost. In the case of a conventional PMOS process, it is often necessary to use at least nine masks.
  • a conventional bottom-gate LTPS pixel often uses an organic layer for isolating the metal electrode and the transparent electrode, reducing the parasitic capacitance between them, and the organic layer tends to have a large thickness, but this will put forward the uniformity of the process. Higher requirements, and often lead to problems with uneven display brightness, reducing the yield of the process.
  • the technical problem to be solved by the present invention is to provide a method for fabricating an array substrate, an array substrate and a display panel, which can reduce the number of use of the mask in the process of fabricating the array substrate, reduce the process flow, and reduce the cost.
  • a technical solution adopted by the present invention is to provide a method for fabricating an array substrate, which comprises: sequentially forming a transparent first electrode and a gate electrode on a substrate, wherein between the gate electrode and the substrate a transparent conductive film, the transparent conductive film and the first electrode are formed in the same process; forming an insulating layer on the substrate, the insulating layer covers the gate electrode and the first electrode; forming a semiconductor layer on the insulating layer; Forming a dielectric layer thereon, and opening a first via hole and a second via hole in the region corresponding to the semiconductor layer, exposing the semiconductor layer at the first via hole and the second via hole, and opening the third via hole in the region corresponding to the first electrode a first electrode is exposed at the third via hole; a source electrode, a drain electrode, and a second electrode are formed on the dielectric layer, and the source electrode and the drain electrode are respectively connected to the semiconductor layer through the first via hole and the second via hole, The two electrodes are connected to
  • a transparent first electrode layer and a gate electrode layer are sequentially formed on the substrate, and the first electrode and the gate electrode are formed after patterning, specifically: forming a transparent first electrode layer on the substrate; and forming a transparent first electrode layer on the substrate Forming a gate electrode layer; patterning the first electrode layer and the gate electrode layer to form a first island and a second island, wherein each island includes a first electrode layer and a gate electrode layer; An island and a second island are etched to form a gate electrode and a first electrode, respectively.
  • the step of forming a semiconductor layer on the insulating layer is specifically: depositing a layer of amorphous silicon on the insulating layer and obtaining polysilicon; covering a layer of photoresist on the polysilicon; and performing illumination from the substrate so that the photoresist is not Partially exposing the gate electrode; etching the exposed portion on the photoresist and the polysilicon; doping the polysilicon to form a first doped region corresponding to the first via and a second doped region corresponding to the second via, To connect the source and drain electrodes, respectively.
  • an array substrate including a substrate and a first electrode layer, an insulating layer, a semiconductor layer, a dielectric layer, and a second layer sequentially disposed on the substrate.
  • the first electrode layer comprises a gate electrode and a transparent first electrode, wherein a transparent conductive film is formed between the gate electrode and the substrate, and the transparent conductive film and the first electrode are formed in the same process;
  • the second electrode layer includes a source electrode, a drain electrode, a second electrode, and a transparent third electrode; a first via hole and a second via hole are disposed on the dielectric layer in a region corresponding to the semiconductor layer to respectively make the semiconductor layer and the source electrode and the drain electrode a pole connection; a third via hole is disposed in the dielectric layer and the insulating layer corresponding to the first electrode to connect the first electrode and the second electrode to form a storage capacitor; and the third electrode is connected to the drain electrode to form the pixel electrode.
  • the semiconductor layer is formed by doping polysilicon and forming a first doped region and a second doped region; the first doped region and the second doped region respectively correspond to the first via hole and the second via hole Connect the source and drain electrodes.
  • the gate electrode, the source electrode, the drain electrode, and the second electrode are metal electrodes.
  • the first electrode and the third electrode are indium tin oxide ITO.
  • a display panel which includes a color filter substrate, an array substrate, and a liquid crystal layer between the color filter substrate and the array substrate, wherein the array substrate
  • the substrate includes a first electrode layer, an insulating layer, a semiconductor layer, a dielectric layer, and a second electrode layer disposed on the substrate; wherein the first electrode layer includes a gate electrode and a transparent first electrode, wherein the gate electrode and the substrate There is a transparent conductive film between the transparent conductive film and the first electrode formed in the same process; the second electrode layer comprises a source electrode, a drain electrode, a second electrode and a transparent third electrode; corresponding to the dielectric layer a region of the semiconductor layer is provided with a first via hole and a second via hole for respectively connecting the semiconductor layer to the source electrode and the drain electrode; and a third via hole is provided in the region corresponding to the first electrode on the dielectric layer and the insulating layer to enable One electrode is connected to the second electrode to form
  • the semiconductor layer is formed by doping polysilicon and forming a first doped region and a second doped region; the first doped region and the second doped region respectively correspond to the first via hole and the second via hole Connect the source and drain electrodes.
  • the gate electrode, the source electrode, the drain electrode, and the second electrode are metal electrodes.
  • the first electrode and the third electrode are indium tin oxide ITO.
  • the invention has the beneficial effects that, in the prior art, the first electrode is disposed on the substrate, which avoids the need for a thick isolation layer when the first electrode is disposed on the semiconductor layer.
  • the thickness of the isolation layer causes uneven display brightness, and the display effect is improved.
  • the gate electrode and the first electrode use a single mask at the same time, and only six masks are needed in the manufacturing process, which is three times less than the nine masks in the conventional technology, which simplifies the manufacturing process and reduces the cost.
  • FIG. 1 is a flow chart showing a first embodiment of a method for fabricating an array substrate of the present invention
  • step 101 is a schematic structural view of step 101 in the first embodiment of the method for fabricating the array substrate of the present invention
  • step 102 is a schematic structural view of step 102 in the first embodiment of the method for fabricating the array substrate of the present invention
  • step 103 is a schematic structural view of step 103 in the first embodiment of the method for fabricating the array substrate of the present invention
  • step 104 is a schematic structural view of step 104 in the first embodiment of the method for fabricating the array substrate of the present invention
  • step 105 is a schematic structural view of step 105 in the first embodiment of the method for fabricating the array substrate of the present invention
  • step 106 is a schematic structural view of step 106 in the first embodiment of the method for fabricating the array substrate of the present invention.
  • FIG. 8 is a flow chart showing a second embodiment of a method for fabricating an array substrate of the present invention.
  • step 801 is a schematic structural view of step 801 in the second embodiment of the method for fabricating the array substrate of the present invention.
  • step 802 is a schematic structural diagram of step 802 in the second embodiment of the method for fabricating the array substrate of the present invention.
  • FIG. 11 is a schematic structural view of a step 803 in the second embodiment of the method for fabricating the array substrate of the present invention.
  • step 804 is a schematic structural view of step 804 in the second embodiment of the method for fabricating the array substrate of the present invention.
  • FIG. 13 is a flow chart showing a third embodiment of a method for fabricating an array substrate of the present invention.
  • step 1301 is a schematic structural view of step 1301 in the third embodiment of the method for fabricating the array substrate of the present invention.
  • step 15 is a schematic structural view of step 1302 in the third embodiment of the method for fabricating the array substrate of the present invention.
  • 16 is a schematic structural view of steps 1303 and 804 in the third embodiment of the method for fabricating the array substrate of the present invention.
  • 17 is a schematic structural view of a step 1305 in a third embodiment of the method for fabricating the array substrate of the present invention.
  • FIG. 18 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • 19 is a schematic structural view of an embodiment of a display panel of the present invention.
  • a flowchart of a first embodiment of a method for fabricating an array substrate of the present invention includes:
  • Step 101 First, a first electrode 203 and a gate electrode 202 are formed on the substrate 201.
  • a transparent conductive film 2021 is disposed between the gate electrode 202 and the substrate 201.
  • the transparent conductive film 2021 and the first electrode 203 are in the same process. Forming;
  • the substrate 201 is generally made of glass. After the glass substrate 201 is cleaned and dried, a transparent conductive film and a metal layer are sequentially formed on the glass substrate 201, and the transparent conductive layer is formed into the first electrode 203 through a patterning process.
  • the metal layer forms the gate electrode 202; the gate material may be one or more alloys of Pt, Ru, Au, Ag, Mo, Cr, Al, Ta, Ti or W, and the gate electrode 202 is used to connect the gate lines
  • a transparent conductive film such as ITO (tin-doped indium trioxide), AZO (aluminum-doped zinc oxide), or the like.
  • the first photomask is used when patterning the gate electrode 202 and the first electrode 203 colleague.
  • Step 102 forming an insulating layer 204 on the substrate 201, the insulating layer 204 covers the gate electrode 202 and the first electrode 203;
  • the insulating layer 204 may be a silicon oxide layer (SiOx) or a silicon nitride layer (SiNx), or may be formed of a silicon oxide layer and a silicon nitride stacked layer, which is mainly formed by chemical vapor deposition.
  • the method is formed on the substrate 201 and covers the gate electrode 202 and the first electrode 203 to function as an insulation.
  • the second mask is used when patterning the insulating layer 204.
  • Step 103 forming a semiconductor layer 205 on the insulating layer 204;
  • the semiconductor layer 205 may be a P-MOS, N-MOS or C-MOS structure in which amorphous silicon or polycrystalline silicon is doped.
  • a third mask is used.
  • Step 104 forming a dielectric layer 206 on the semiconductor layer 205, and opening a first via hole 2061 and a second via hole 2062 in a region corresponding to the semiconductor layer 205, and exposing the semiconductor layer at the first via hole 2061 and the second via hole 2062.
  • a third through hole 2063 is opened in a region corresponding to the first electrode 202 to expose the first electrode 202 at the third through hole 2063;
  • the dielectric layer 206 is an ILD interlayer dielectric spacer to isolate the semiconductor layer 206 and subsequent electrode layers.
  • a fourth mask is used.
  • Step 105 forming a source electrode 2071, a drain electrode 2072 and a second electrode 2073 on the dielectric layer 206.
  • the source electrode 2071 and the drain electrode 2072 are connected to the semiconductor layer 205 through the first via 2061 and the second via 2062, respectively.
  • the electrode 2073 is connected to the first electrode 202 through the third through hole 2063 to form a storage capacitor;
  • the source electrode 2071, the drain electrode 2072, and the second electrode 2073 are also formed by plating or the like using one or more alloys of Pt, Ru, Au, Ag, Mo, Cr, Al, Ta, Ti, or W.
  • the fifth mask is used when patterning the source electrode 2071, the drain electrode 2072, and the second electrode 2073.
  • Step 106 A transparent third electrode 208 is formed on the dielectric layer 206, and the third electrode 208 is connected to the drain electrode 2072 to form a pixel electrode.
  • the third electrode 208 is made of the same material as the first electrode 202, and a transparent conductive film such as ITO (tin-doped indium trioxide) or AZO (aluminum-doped zinc oxide) may be used.
  • a transparent conductive film such as ITO (tin-doped indium trioxide) or AZO (aluminum-doped zinc oxide) may be used.
  • the sixth mask is used when patterning the third electrode 208.
  • the first electrode by disposing the first electrode on the substrate, in the conventional technology, when the first electrode is disposed on the semiconductor layer, a thick isolation layer is needed to make the first electrode and the source, The drain electrodes are spaced apart, and the third electrode is disposed on the first electrode and also requires a layer of isolation layer to separate the thicker isolation layer to cause uneven display brightness, and the display effect is improved, and the gate electrode and the first electrode are simultaneously used.
  • a reticle requires only six masks in the manufacturing process, which is three less than the nine masks in the conventional technology, which simplifies the manufacturing process and reduces the cost.
  • a flowchart of a second embodiment of a method for fabricating an array substrate of the present invention includes:
  • Step 801 forming a transparent first electrode layer 203 on the substrate 201;
  • the first electrode layer is a transparent conductive film such as ITO (tin-doped indium trioxide), AZO (aluminum-doped zinc oxide), or the like.
  • Step 802 forming a gate electrode layer 202 on the first electrode layer 203;
  • the gate electrode layer 202 is one or more alloys of Pt, Ru, Au, Ag, Mo, Cr, Al, Ta, Ti or W.
  • Step 803 The first electrode layer 203 and the gate electrode layer 202 are patterned to form a first island and a second island, wherein each island includes a first electrode layer 203 and a gate electrode layer 202;
  • Step 804 etching the first island and the second island to form the gate electrode 202 and the first electrode 203, respectively.
  • the first electrode by disposing the first electrode on the substrate, in the conventional technology, when the first electrode is disposed on the semiconductor layer, a thick isolation layer is needed to make the first electrode and the source, The drain electrodes are spaced apart, and the third electrode is disposed on the first electrode and also requires a layer of isolation layer to separate the thicker isolation layer to cause uneven display brightness, and the display effect is improved, and the gate electrode and the first electrode are simultaneously used.
  • a reticle requires only six masks in the manufacturing process, which is three less than the nine masks in the conventional technology, which simplifies the manufacturing process and reduces the cost.
  • a flowchart of a second embodiment of a method for fabricating an array substrate of the present invention includes:
  • Step 1301 depositing a layer of amorphous silicon on the insulating layer 204 and obtaining polysilicon 211;
  • an amorphous silicon (a-Si) layer is deposited on the insulating layer 204, and an excimer laser is used as a heat source. After the laser light passes through the projection system, a laser beam with uniform energy distribution is generated and projected on the laser beam. On the amorphous silicon layer, when the amorphous silicon layer absorbs the energy of the excimer laser, it will be transformed into the polysilicon 211 structure, and the entire process is completed below 600 °C.
  • Step 1302 covering a polysilicon 211 with a layer of photoresist 212;
  • the photoresist 212 is a negative photoresist.
  • Step 1303 Perform illumination from the substrate to expose a portion of the photoresist 212 that is not blocked by the gate electrode 202;
  • Step 1304 etching the exposed portions on the photoresist 212 and the polysilicon 211;
  • the photoresist 212 corresponding to the gate electrode 202 cannot be exposed, and then the polysilicon and the photoresist of the exposed portion are etched.
  • Step 1305 doping the polysilicon 211 to form a first doping region 212 corresponding to the first via hole and a second doping region 213 corresponding to the second via hole to respectively connect the source electrode and the drain electrode.
  • the doping is P+ doped or N+ doped to form the semiconductor layer into a P-MOS, N-MOS or C-MOS structure.
  • This embodiment is only a detailed step of the step 103 in the first embodiment, and is not a method of completely fabricating the array substrate.
  • the steps include the other steps as in the first embodiment.
  • the first electrode by disposing the first electrode on the substrate, in the conventional technology, when the first electrode is disposed on the semiconductor layer, a thick isolation layer is needed to make the first electrode and the source, The drain electrodes are spaced apart, and the third electrode is disposed on the first electrode and also requires a layer of isolation layer to separate the thicker isolation layer to cause uneven display brightness, and the display effect is improved.
  • the gate electrode and the first electrode are manufactured. Sharing a mask, only six masks are needed in the whole process, which is three times less than the nine masks in the traditional technology, which simplifies the production process and reduces the cost.
  • the array substrate includes a substrate 201 and a first electrode layer, an insulating layer 204, a semiconductor layer, a dielectric layer 206, and a second electrode layer disposed on the substrate 201 in sequence;
  • the first electrode layer includes a gate electrode 202 and a transparent first electrode 203; the second electrode layer includes a source electrode 2071, a drain electrode 2072, a second electrode 2073, and a transparent third electrode 208; and a corresponding semiconductor on the dielectric layer 206 a first via hole and a second via hole are disposed in the layer region to connect the semiconductor layer to the source electrode 2071 and the drain electrode 2072, respectively; and a third pass is disposed on the dielectric layer 206 and the insulating layer 204 corresponding to the first electrode 203.
  • the holes are such that the first electrode 203 and the second electrode 2073 are connected to form a storage capacitor; the third electrode 208 is connected to the drain electrode 2072 to form a pixel electrode.
  • the semiconductor layer is formed by doping polysilicon, and forms a first doping region 2051 and a second doping region 2052; the first doping region 2051 and the second doping region 2052 respectively correspond to the first via hole and the first The two through holes are connected to the source electrode 2071 and the drain electrode 2072.
  • the gate electrode 202 is connected to the gate line.
  • the gate electrode 202, the source electrode 2071, the drain electrode 2072, and the second electrode 2073 are metal electrodes.
  • the first electrode 203 and the third electrode 208 are indium tin oxide ITO.
  • the present embodiment is a product based on the method for fabricating the above array substrate, and the embodiments thereof are similar, and are not described herein again.
  • the first electrode by disposing the first electrode on the substrate, in the conventional technology, when the first electrode is disposed on the semiconductor layer, a thick isolation layer is needed to make the first electrode and the source, The drain electrodes are spaced apart, and the third electrode is disposed on the first electrode and also requires a layer of isolation layer to separate the thicker isolation layer to cause uneven display brightness, and the display effect is improved.
  • the gate electrode and the first electrode are manufactured. The process shares a mask, and the entire process requires only six masks, which is three fewer than the nine masks in the conventional technology, which simplifies the manufacturing process and reduces the cost.
  • the display panel includes a color filter substrate 1091, an array substrate 1092, and a liquid crystal layer 1093 between the color filter substrate 1091 and the array substrate 1092.
  • the array substrate 1091 is characterized by It is an array substrate as in the above embodiment, and details are not described herein again.
  • the array substrate in the display panel of the present embodiment has the first electrode disposed on the substrate, which avoids the need for a thick isolation layer when the first electrode is disposed on the semiconductor layer in the conventional technology.
  • the first electrode is separated from the source and the drain electrode, and the third electrode is disposed on the first electrode and the isolation layer is separated by a spacer layer, and the display brightness is uneven due to the thick isolation layer, and the display effect is improved.
  • the first electrode is shared with the first electrode in the manufacturing process, and only six masks are needed in the whole process, which is three times less than the nine masks in the conventional technology, which simplifies the manufacturing process and reduces the cost.

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Abstract

一种阵列基板的制作方法、阵列基板及显示面板，该方法包括：在基板上先后形成第一电极及栅电极；在基板上形成绝缘层，绝缘层覆盖栅电极及第一电极；在绝缘层上形成半导体层；在半导体层上形成介质层，并开设第一通孔、第二通孔及第三通孔；在介质层上形成源电极、漏电极和第二电极，源电极及漏电极分别通过第一通孔及第二通孔与半导体层连接，第二电极通过第三通孔与第一电极连接以形成存储电容；在介质层上形成透明的第三电极，第三电极与漏电极连接以形成像素电极。通过上述方式，能够在阵列基板的制作过程中减少光罩的使用数量，减少工艺流程，降低成本。

Description

一种阵列基板的制作方法、阵列基板及显示面板
【技术领域】
本发明涉及显示领域，特别是涉及一种阵列基板的制作方法、阵列基板及显示面板。
【背景技术】
低温多晶硅(Low Temperature Poly-silicon；简称LTPS)薄膜晶体管液晶显示器是在封装过程中，利用准分子镭射作为热源，镭射光经过投射系统后，会产生能量均匀分布的镭射光束，投射于非晶硅结构的玻璃基板上，当非晶硅结构玻璃基板吸收准分子镭射的能量后，会转变成为多晶硅结构，因整个处理过程都是在600℃以下完成，故一般玻璃基板皆可适用。
传统的底栅型LTPS像素层别结构很多，制作相对复杂，制作时需要使用更多数量的光罩，这极大的增加了生产成本。以传统的PMOS制程为例，往往至少需要使用9张光罩。
另外，传统的底栅LTPS像素中经常会使用一有机层，用于隔绝金属电极和透明电极，降低它们之间的寄生电容，有机层往往厚度较大，但这样会对制程的均一性提出了更高的要求，而且经常导致显示亮度不均匀的问题，降低了制程的良率。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板的制作方法、阵列基板及显示面板，能够在阵列基板的制作过程中减少光罩的使用数量，减少工艺流程，降低成本。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板的制作方法，该方法包括：在基板上先后形成透明的第一电极及栅电极，其中，栅电极与基板之间有一层透明导电薄膜，透明导电薄膜与第一电极是在同一道工序中形成的；在基板上形成绝缘层，绝缘层覆盖栅电极及第一电极；在绝缘层上形成半导体层；在半导体层上形成介质层，并在对应半导体层的区域开设第一通孔、第二通孔，在第一通孔、第二通孔位置露出半导体层，在对应第一电极的区域开设第三通孔，以在第三通孔处露出第一电极；在介质层上形成源电极、漏电极和第二电极，源电极及漏电极分别通过第一通孔及第二通孔与半导体层连接，第二电极通过第三通孔与第一电极连接以形成存储电容；在介质层上形成透明的第三电极，第三电极与漏电极连接以形成像素电极，其中，栅电极、源电极、漏电极及第二电极为金属电极，第一电极及第三电极为氧化铟锡ITO。
其中，在基板上先后形成透明的第一电极层及栅电极层，图形化后以形成第一电极及栅电极步骤，具体为：在基板上形成透明的第一电极层；在第一电极层上形成栅电极层；对第一电极层及栅电极层进行图形化，以形成第一小岛及第二小岛，其中，每个小岛均包括第一电极层及栅电极层；对第一小岛及第二小岛进行蚀刻以分别形成栅电极及第一电极。
其中，在绝缘层上形成半导体层步骤，具体为：在绝缘层上沉积一层非晶硅并得到多晶硅；在多晶硅上覆盖一层光阻；从基板上进行光照，以使光阻中没有被栅电极遮挡的部分曝光；对光阻及多晶硅上的曝光部分进行蚀刻；对多晶硅进行掺杂以形成对应第一通孔的第一掺杂区及对应第二通孔的第二掺杂区，以分别连接源电极及漏电极。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，该阵列基板包括基板和依次设置于基板上的第一电极层、绝缘层、半导体层、介质层及第二电极层；其中，第一电极层包括栅电极及透明的第一电极，其中，栅电极与基板之间有一层透明导电薄膜，透明导电薄膜与第一电极是在同一道工序中形成的；第二电极层包括源电极、漏电极、第二电极及透明的第三电极；在介质层上对应半导体层的区域设置有第一通孔及第二通孔以使半导体层分别与源电极及漏电极连接；在介质层及绝缘层上对应第一电极的区域设置有第三通孔以使第一电极与第二电极连接形成存储电容；第三电极与漏电极连接以形成像素电极。
其中，半导体层是通过对多晶硅掺杂制成，并形成第一掺杂区及第二掺杂区；第一掺杂区及第二掺杂区分别对应第一通孔及第二通孔以连接源电极及漏电极。
其中，栅电极、源电极、漏电极及第二电极为金属电极。
其中，第一电极及第三电极为氧化铟锡ITO。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示面板，该显示面板包括彩膜基板、阵列基板以及彩膜基板、阵列基板之间的液晶层，其中，该阵列基板包括基板和依次设置于基板上的第一电极层、绝缘层、半导体层、介质层及第二电极层；其中，第一电极层包括栅电极及透明的第一电极，其中，栅电极与基板之间有一层透明导电薄膜，透明导电薄膜与第一电极是在同一道工序中形成的；第二电极层包括源电极、漏电极、第二电极及透明的第三电极；在介质层上对应半导体层的区域设置有第一通孔及第二通孔以使半导体层分别与源电极及漏电极连接；在介质层及绝缘层上对应第一电极的区域设置有第三通孔以使第一电极与第二电极连接形成存储电容；第三电极与漏电极连接以形成像素电极。
其中，半导体层是通过对多晶硅掺杂制成，并形成第一掺杂区及第二掺杂区；第一掺杂区及第二掺杂区分别对应第一通孔及第二通孔以连接源电极及漏电极。
其中，栅电极、源电极、漏电极及第二电极为金属电极。
其中，第一电极及第三电极为氧化铟锡ITO。
本发明的有益效果是：区别于现有技术的情况，本发明通过将第一电极设置于基板上，避免了传统技术中，将第一电极设置于半导体层上时需要采用很厚的隔离层以使第一电极与源、漏电极隔开，而第三电极设置于第一电极也需要一层隔离层隔开时厚厚的隔离层造成的显示亮度不均匀的问题，显示效果提高，另外栅电极和第一电极同时使用一张光罩，在制造过程中只需要六道光罩，比传统的技术中九道光罩减少了三道，使制作工艺简化，成本降低。
【附图说明】
图1是本发明阵列基板的制作方法第一实施方式的流程图；
图2是本发明阵列基板的制作方法第一实施方式中步骤101的结构示意图；
图3是本发明阵列基板的制作方法第一实施方式中步骤102的结构示意图；
图4是本发明阵列基板的制作方法第一实施方式中步骤103的结构示意图；
图5是本发明阵列基板的制作方法第一实施方式中步骤104的结构示意图；
图6是本发明阵列基板的制作方法第一实施方式中步骤105的结构示意图；
图7是本发明阵列基板的制作方法第一实施方式中步骤106的结构示意图；
图8是本发明阵列基板的制作方法第二实施方式的流程图；
图9是本发明阵列基板的制作方法第二实施方式中步骤801的结构示意图；
图10是本发明阵列基板的制作方法第二实施方式中步骤802的结构示意图；
图11是本发明阵列基板的制作方法第二实施方式中步骤803的结构示意图；
图12是本发明阵列基板的制作方法第二实施方式中步骤804的结构示意图；
图13是本发明阵列基板的制作方法第三实施方式的流程图；
图14是本发明阵列基板的制作方法第三实施方式中步骤1301的结构示意图；
图15是本发明阵列基板的制作方法第三实施方式中步骤1302的结构示意图；
图16是本发明阵列基板的制作方法第三实施方式中步骤1303及步骤804的结构示意图；
图17是本发明阵列基板的制作方法第三实施方式中步骤1305的结构示意图；
图18是本发明阵列基板实施方式的结构示意图；
图19是本发明显示面板实施方式的结构示意图。
【具体实施方式】
参阅图1，本发明阵列基板的制作方法第一实施方式的流程图，该方法包括：
步骤101：在基板201上先后形成第一电极203及栅电极202，其中，栅电极202与基板201之间有一层透明导电薄膜2021，透明导电薄膜2021与第一电极203是在同一道工序中形成的；
如图2所示，基板201一般采用玻璃，在玻璃基板201清洗干燥后，在玻璃基板201上先后形成透明导电薄膜及金属层，经过一次图形化处理以使该透明导电层形成第一电极203，金属层形成栅极202；栅极材料可以是Pt、Ru、Au、Ag、Mo、Cr、Al、Ta、Ti或W中的一种或多种合金，栅电极202用于连接栅极线；透明导电薄膜例如ITO（锡掺杂三氧化铟）、AZO(铝掺杂氧化锌)等。
此时，对栅电极202及第一电极203同事进行图形化时使用第一道光罩。
步骤102：在基板201上形成绝缘层204，绝缘层204覆盖栅电极202及第一电极203；
如图3所示，该绝缘层204可以是氧化硅层（SiOx）或氮化硅层（SiNx），也可以是由氧化硅层与氮化硅层叠层形成，其主要是通过化学气相沉积的方式形成于基板201上并且覆盖栅电极202及第一电极203以起到绝缘作用。
此时，对绝缘层204进行图形化时使用第二道光罩。
步骤103：在绝缘层204上形成半导体层205；
如图4所示，半导体层205可以是非晶硅或多晶硅进行掺杂形成的P-MOS、N-MOS或者C-MOS结构。
此时，对半导体层205进行图形化时，使用第三道光罩。
步骤104：在半导体层205上形成介质层206，并在对应半导体层205的区域开设第一通孔2061、第二通孔2062，在第一通孔2061、第二通孔2062位置露出半导体层205，在对应第一电极202的区域开设第三通孔2063，以在第三通孔2063处露出第一电极202；
如图5所示，该介质层206是采用ILD层间介质隔离材料，以对半导体层206及后续的电极层进行隔离。
此时，在对该介质层206进行开孔的过程中，使用第四道光罩。
步骤105：在介质层206上形成源电极2071、漏电极2072和第二电极2073，源电极2071及漏电极2072分别通过第一通孔2061及第二通孔2062与半导体层205连接，第二电极2073通过第三通孔2063与第一电极202连接以形成存储电容；
源电极2071、漏电极2072和第二电极2073同样采用Pt、Ru、Au、Ag、Mo、Cr、Al、Ta、Ti或W中的一种或多种合金通过镀膜等方式形成。
此时，在对源电极2071、漏电极2072及第二电极2073图形化时使用第五道光罩。
步骤106：在介质层206上形成透明的第三电极208，第三电极208与漏电极2072连接以形成像素电极。
该第三电极208与第一电极202材料相同，也可以采用ITO（锡掺杂三氧化铟）、AZO(铝掺杂氧化锌)等透明导电薄膜。
此时，在对该第三电极208进行图形化时使用第六道光罩。
区别于现有技术，本实施方式通过将第一电极设置于基板上，避免了传统技术中，将第一电极设置于半导体层上时需要采用很厚的隔离层以使第一电极与源、漏电极隔开，而第三电极设置于第一电极也需要一层隔离层隔开时厚厚的隔离层造成的显示亮度不均匀的问题，显示效果提高，另外栅电极和第一电极同时使用一张光罩，在制造过程中只需要六道光罩，比传统的技术中九道光罩减少了三道，使制作工艺简化，成本降低。
参阅图8，本发明阵列基板的制作方法第二实施方式的流程图，该方法包括：
步骤801：在基板201上形成透明的第一电极层203；
如图9所示，第一电极层是透明导电薄膜，例如ITO（锡掺杂三氧化铟）、AZO(铝掺杂氧化锌)等。
步骤802：在第一电极层203上形成栅电极层202；
如果10所示，栅电极层202是Pt、Ru、Au、Ag、Mo、Cr、Al、Ta、Ti或W中的一种或多种合金。
步骤803：对第一电极层203及栅电极层202进行图形化，以形成第一小岛及第二小岛，其中，每个小岛均包括第一电极层203及栅电极层202；
如图11所示，在图形化时，仅使用一张光罩。
步骤804：对第一小岛及第二小岛进行蚀刻以分别形成栅电极202及第一电极203。
如图12所示，蚀刻后的栅电极202与基板201之间仍有一层透明导电薄膜，而第一电极203上面的金属层则被蚀刻掉了。
区别于现有技术，本实施方式通过将第一电极设置于基板上，避免了传统技术中，将第一电极设置于半导体层上时需要采用很厚的隔离层以使第一电极与源、漏电极隔开，而第三电极设置于第一电极也需要一层隔离层隔开时厚厚的隔离层造成的显示亮度不均匀的问题，显示效果提高，另外栅电极和第一电极同时使用一张光罩，在制造过程中只需要六道光罩，比传统的技术中九道光罩减少了三道，使制作工艺简化，成本降低。
参阅图13，本发明阵列基板的制作方法第二实施方式的流程图，该方法包括：
步骤1301：在绝缘层204上沉积一层非晶硅并得到多晶硅211；
如图14所示，在绝缘层204上沉积一层非晶硅（a-Si）层，并利用准分子镭射作为热源，镭射光经过投射系统后，会产生能量均匀分布的镭射光束，投射于非晶硅层上，当非晶硅层吸收准分子镭射的能量后，会转变成为多晶硅211结构，整个处理过程都是在600℃以下完成。
步骤1302：在多晶硅211上覆盖一层光阻212；
如图15所示，该光阻212为负性光阻。
步骤1303：从基板上进行光照，以使光阻212中没有被栅电极202遮挡的部分曝光；
步骤1304：对光阻212及多晶硅211上的曝光部分进行蚀刻；
如图16所示，由于栅电极202的遮挡，对应栅电极202上方的光阻212不能被曝光，然后对曝光部分的多晶硅及光阻进行蚀刻。
步骤1305：对多晶硅211进行掺杂以形成对应第一通孔的第一掺杂区212及对应第二通孔的第二掺杂区213，以分别连接源电极及漏电极。
如图17所示，该掺杂为P+掺杂或N+掺杂，以使该半导体层形成P-MOS、N-MOS或者C-MOS结构。
该实施方式仅是第一实施方式中步骤103的详细步骤，并不是完整制作阵列基板的方法，步骤前后还包括如第一实施方式中的其他步骤。
区别于现有技术，本实施方式通过将第一电极设置于基板上，避免了传统技术中，将第一电极设置于半导体层上时需要采用很厚的隔离层以使第一电极与源、漏电极隔开，而第三电极设置于第一电极也需要一层隔离层隔开时厚厚的隔离层造成的显示亮度不均匀的问题，显示效果提高，另外栅电极和第一电极在制造共用一道光罩，整个过程中只需要六道光罩，比传统的技术中九道光罩减少了三道，使制作工艺简化，成本降低。
参阅图18，本发明阵列基板实施方式的结构示意图，该阵列基板包括基板201和依次设置于基板201上的第一电极层、绝缘层204、半导体层、介质层206及第二电极层；
其中，第一电极层包括栅电极202及透明的第一电极203；第二电极层包括源电极2071、漏电极2072、第二电极2073及透明的第三电极208；在介质层206上对应半导体层的区域设置有第一通孔及第二通孔以使半导体层分别与源电极2071及漏电极2072连接；在介质层206及绝缘层204上对应第一电极203的区域设置有第三通孔以使第一电极203与第二电极2073连接形成存储电容；第三电极208与漏电极2072连接以形成像素电极。
其中，半导体层是通过对多晶硅掺杂制成，并形成第一掺杂区2051及第二掺杂区2052；第一掺杂区2051及第二掺杂区2052分别对应第一通孔及第二通孔以连接源电极2071及漏电极2072。
其中，栅电极202连接栅极线。
其中，栅电极202、源电极2071、漏电极2072及第二电极2073为金属电极。
其中，第一电极203及第三电极208为氧化铟锡ITO。
本实施方式是基于上述阵列基板的制作方法的产品，其实施方式类似，这里不再赘述。
区别于现有技术，本实施方式通过将第一电极设置于基板上，避免了传统技术中，将第一电极设置于半导体层上时需要采用很厚的隔离层以使第一电极与源、漏电极隔开，而第三电极设置于第一电极也需要一层隔离层隔开时厚厚的隔离层造成的显示亮度不均匀的问题，显示效果提高，另外栅电极和第一电极在制造过程共用一道光罩，整个过程只需要六道光罩，比传统的技术中九道光罩减少了三道，使制作工艺简化，成本降低。
参阅图19，本发明显示面板实施方式的结构示意图，该显示面板包括彩膜基板1091、阵列基板1092以及彩膜基板1091、阵列基板1092之间的液晶层1093，其特征在于，该阵列基板1091是如上述实施方式中的阵列基板，这里不再赘述。
区别于现有技术，本实施方式中显示面板中的阵列基板将第一电极设置于基板上，避免了传统技术中，将第一电极设置于半导体层上时需要采用很厚的隔离层以使第一电极与源、漏电极隔开，而第三电极设置于第一电极也需要一层隔离层隔开时厚厚的隔离层造成的显示亮度不均匀的问题，显示效果提高，另外栅电极和第一电极在制造过程共用一道光罩，整个过程只需要六道光罩，比传统的技术中九道光罩减少了三道，使制作工艺简化，成本降低。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (11)

  1. 一种阵列基板的制作方法，其中，所述方法包括：
    在基板上先后形成透明的第一电极及栅电极，其中，所述栅电极与所述基板之间有一层透明导电薄膜，所述透明导电薄膜与所述第一电极是在同一道工序中形成的；
    在所述基板上形成绝缘层，所述绝缘层覆盖所述栅电极及第一电极；
    在所述绝缘层上形成半导体层；
    在所述半导体层上形成介质层，并在对应所述半导体层的区域开设第一通孔、第二通孔，在所述第一通孔、第二通孔位置露出所述半导体层，在对应所述第一电极的区域开设第三通孔，以在所述第三通孔处露出所述第一电极；
    在所述介质层上形成源电极、漏电极和第二电极，所述源电极及漏电极分别通过所述第一通孔及第二通孔与所述半导体层连接，所述第二电极通过所述第三通孔与所述第一电极连接以形成存储电容；
    在所述介质层上形成透明的第三电极，所述第三电极与所述漏电极连接以形成像素电极；
    其中，所述栅电极、源电极、漏电极及第二电极为金属电极；
    所述第一电极及第三电极为氧化铟锡ITO。
  2. 根据权利要求1所述的方法，其中，所述在基板上先后形成第一电极及栅电极步骤，具体为：
    在基板上形成透明的第一电极层；
    在所述第一电极层上形成栅电极层；
    对所述第一电极层及栅电极层进行图形化，以形成第一小岛及第二小岛，其中，每个小岛均包括所述第一电极层及栅电极层；
    对所述第一小岛及第二小岛进行蚀刻以分别形成所述栅电极及第一电极。
  3. 根据权利要求1所述的方法，其中，所述在所述绝缘层上形成半导体层步骤，具体为：
    在所述绝缘层上沉积一层非晶硅并得到多晶硅；
    在所述多晶硅上覆盖一层光阻；
    从所述基板上进行光照，以使所述光阻中没有被所述栅电极遮挡的部分曝光；
    对所述光阻及所述多晶硅上的曝光部分进行蚀刻；
    对所述多晶硅进行掺杂以形成对应所述第一通孔的第一掺杂区及对应所述第二通孔的第二掺杂区，以分别连接所述源电极及漏电极。
  4. 一种阵列基板，其中，所述阵列基板包括基板和依次设置于所述基板上的第一电极层、绝缘层、半导体层、介质层及第二电极层；
    所述第一电极层包括栅电极及透明的第一电极，其中，所述栅电极与所述基板之间有一层透明导电薄膜，所述透明导电薄膜与所述第一电极是在同一道工序中形成的；
    所述第二电极层包括源电极、漏电极、第二电极及透明的第三电极；
    在所述介质层上对应所述半导体层的区域设置有第一通孔及第二通孔以使所述半导体层分别与所述源电极及漏电极连接；
    在所述介质层及绝缘层上对应所述第一电极的区域设置有第三通孔以使所述第一电极与所述第二电极连接形成存储电容；
    所述第三电极与所述漏电极连接以形成像素电极。
  5. 根据权利要求4所述的阵列基板，其中，所述半导体层是通过对多晶硅掺杂制成，并形成第一掺杂区及第二掺杂区；
    所述第一掺杂区及第二掺杂区分别对应所述第一通孔及第二通孔以连接所述源电极及漏电极。
  6. 根据权利要求4所述的阵列基板，其中，所述栅电极、源电极、漏电极及第二电极为金属电极。
  7. 根据权利要求4所述的阵列基板，其中，所述第一电极及第三电极为氧化铟锡ITO。
  8. 一种显示面板，包括彩膜基板、阵列基板以及所述彩膜基板、阵列基板之间的液晶层，其中，所述阵列基板包括基板和依次设置于所述基板上的第一电极层、绝缘层、半导体层、介质层及第二电极层；
    所述第一电极层包括栅电极及透明的第一电极，其中，所述栅电极与所述基板之间有一层透明导电薄膜，所述透明导电薄膜与所述第一电极是在同一道工序中形成的；
    所述第二电极层包括源电极、漏电极、第二电极及透明的第三电极；
    在所述介质层上对应所述半导体层的区域设置有第一通孔及第二通孔以使所述半导体层分别与所述源电极及漏电极连接；
    在所述介质层及绝缘层上对应所述第一电极的区域设置有第三通孔以使所述第一电极与所述第二电极连接形成存储电容；
    所述第三电极与所述漏电极连接以形成像素电极。
  9. 根据权利要求8所述的显示面板，其中，所述半导体层是通过对多晶硅掺杂制成，并形成第一掺杂区及第二掺杂区；
    所述第一掺杂区及第二掺杂区分别对应所述第一通孔及第二通孔以连接所述源电极及漏电极。
  10. 根据权利要求8所述的显示面板，其中，所述栅电极、源电极、漏电极及第二电极为金属电极。
  11. 根据权利要求8所述的显示面板，其中，所述第一电极及第三电极为氧化铟锡ITO。
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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
CN108064418A (zh) * 2016-12-27 2018-05-22 深圳市柔宇科技有限公司 阵列基板及阵列基板的制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1702531A (zh) * 2004-05-27 2005-11-30 Lg.菲利浦Lcd株式会社 液晶显示器件及其制造方法
CN102306650A (zh) * 2011-07-13 2012-01-04 友达光电股份有限公司 像素结构及其制作方法
CN102468324A (zh) * 2010-10-28 2012-05-23 三星移动显示器株式会社 有机发光显示设备及其制造方法
CN103094304A (zh) * 2011-11-07 2013-05-08 三星显示有限公司 薄膜晶体管阵列基板及其制造方法和有机发光显示装置
US8742425B2 (en) * 2012-05-23 2014-06-03 Samsung Display Co., Ltd. Thin film transistor array substrate, organic light-emitting display device comprising the same, and method of manufacturing the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7973871B2 (en) * 2004-05-27 2011-07-05 Sharp Kabushiki Kaisha Active matrix substrate, method for correcting a pixel deffect therein and manufacturing method thereof
KR101735568B1 (ko) 2010-03-30 2017-05-15 엘지디스플레이 주식회사 컬러필터 어레이 기판과 이를 포함하는 액정 표시 장치, 및 그의 제조 방법
KR101783352B1 (ko) * 2010-06-17 2017-10-10 삼성디스플레이 주식회사 평판 표시 장치 및 그 제조 방법
CN102403311B (zh) * 2010-09-16 2015-07-15 北京京东方光电科技有限公司 阵列基板及其制造方法和液晶显示器
TWI459253B (zh) 2011-01-25 2014-11-01 Chunghwa Picture Tubes Ltd 觸控面板
TWI483370B (zh) 2012-05-25 2015-05-01 Chunghwa Picture Tubes Ltd 觸控面板之電極陣列
CN103018990B (zh) * 2012-12-14 2015-12-02 京东方科技集团股份有限公司 一种阵列基板和其制备方法、及液晶显示装置
CN103700663B (zh) * 2013-12-12 2016-09-07 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN104037090B (zh) * 2014-06-19 2016-10-19 深圳市华星光电技术有限公司 氧化物薄膜晶体管结构制作方法及氧化物薄膜晶体管结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1702531A (zh) * 2004-05-27 2005-11-30 Lg.菲利浦Lcd株式会社 液晶显示器件及其制造方法
CN102468324A (zh) * 2010-10-28 2012-05-23 三星移动显示器株式会社 有机发光显示设备及其制造方法
CN102306650A (zh) * 2011-07-13 2012-01-04 友达光电股份有限公司 像素结构及其制作方法
CN103094304A (zh) * 2011-11-07 2013-05-08 三星显示有限公司 薄膜晶体管阵列基板及其制造方法和有机发光显示装置
US8742425B2 (en) * 2012-05-23 2014-06-03 Samsung Display Co., Ltd. Thin film transistor array substrate, organic light-emitting display device comprising the same, and method of manufacturing the same

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