WO2016107018A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2016107018A1
WO2016107018A1 PCT/CN2015/076960 CN2015076960W WO2016107018A1 WO 2016107018 A1 WO2016107018 A1 WO 2016107018A1 CN 2015076960 W CN2015076960 W CN 2015076960W WO 2016107018 A1 WO2016107018 A1 WO 2016107018A1
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Prior art keywords
line
insulating layer
sub
display substrate
layer
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PCT/CN2015/076960
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English (en)
French (fr)
Inventor
李卿硕
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/892,809 priority Critical patent/US10401695B2/en
Publication of WO2016107018A1 publication Critical patent/WO2016107018A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/13378—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
    • G02F1/133784—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation by rubbing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device

Definitions

  • Embodiments of the present invention relate to a display substrate and a display device.
  • a known display substrate 10 includes a substrate substrate 11 and is disposed on the substrate.
  • such a display substrate 10 is known to have a defect in that the insulating lines formed on the base substrate 11 and the respective signal lines 12 are caused since the respective signal lines 12 are disposed on the upper surface of the base substrate 11.
  • the layer 13 has protrusions; and when an external force acts on the insulating layer 13, the insulating layer 13 is liable to be damaged, so that the signal line 12 is easily corroded by the electrolyte or water vapor, resulting in poor signal lines.
  • the position of the alignment film on the display substrate and the protrusion corresponding to the protrusion of the insulating layer 13 form a certain slope, resulting in a friction dead zone at the position during the rubbing orientation, which causes an abnormal arrangement of the liquid crystal molecules to cause a light leakage phenomenon of the liquid crystal panel.
  • Embodiments of the present invention provide a display substrate and a display device to reduce the probability of occurrence of a signal line defect problem.
  • a first insulating layer disposed on the base substrate, the first insulating layer is provided with at least one line groove;
  • At least one signal line at least one of the signal lines being disposed in the line slot, and one of the line slots for accommodating one of the signal lines;
  • a second insulating layer covering the first insulating layer and the signal line.
  • the display substrate includes a peripheral routing area and a display area.
  • the line slot is located in the peripheral routing area, and the signal line includes Grid or data line.
  • the line slot is located in the peripheral routing area
  • the signal line includes a data line and a gate line
  • the data line and the gate line are disposed in the same layer.
  • the line slot is located in the peripheral trace area
  • the signal line includes a data line and a gate line
  • the data line and the gate line are disposed in different layers.
  • the data lines and the gate lines are arranged in different layers as follows:
  • the first insulating layer includes a first sub-insulating layer and a second sub-insulating layer respectively provided with at least one receiving line groove, and the second sub-insulating layer is located above the first sub-insulating layer, wherein
  • the data line is located in a capacitance groove of the first sub-insulation layer, and the gate line is located in a capacitance groove of the second sub-insulation layer;
  • the data line is located in a capacitance groove of the second sub-insulation layer
  • the gate line is located in a capacitance groove of the first sub-insulation layer.
  • the line slot is located in the display area, and the signal line includes a data line or a gate line.
  • the line slot is located in the display area, and the signal line includes a data line and a gate line.
  • the line slot is located in the display area
  • the signal line includes a data line and a gate line
  • the data line and the gate line are disposed in different layers.
  • the data lines and gate lines are arranged in different layers as follows:
  • the first insulating layer includes a first sub-insulating layer and a second sub-insulating layer respectively provided with at least one receiving line groove, and the second sub-insulating layer is located above the first sub-insulating layer, wherein
  • the data line is located in a capacitance groove of the first sub-insulation layer, and the gate line is located in a capacitance groove of the second sub-insulation layer;
  • the data line is located in a capacitance groove of the second sub-insulation layer
  • the gate line is located in a capacitance groove of the first sub-insulation layer.
  • the first insulating layer is a silicon nitride layer or a silicon dioxide layer, or the first insulating layer is a combined layer including a silicon nitride layer and a silicon dioxide layer.
  • an upper surface of the signal line is flush with an upper surface of the first insulating layer.
  • At least one embodiment of the present invention also provides a display device including any of the above display substrates.
  • 1 is a schematic structural view of a known display substrate
  • FIG. 2 is a schematic structural view 1 of a display substrate according to an embodiment of the present invention.
  • FIG. 3 is a second schematic structural view of a display substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural view 3 of a display substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural view 4 of a display substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural view 5 of a display substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural view 6 of a display substrate according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram showing the arrangement of signal lines of a display area of a display substrate according to an embodiment of the present invention.
  • FIG. 9 is a flowchart of a method of manufacturing a display substrate according to an embodiment of the present invention.
  • 10a, 10b, 10c, 10d, and 10e are schematic views showing a manufacturing process of a display substrate according to an embodiment of the present invention.
  • FIG. 11 is a flow chart of a method for manufacturing a display substrate according to another embodiment of the present invention.
  • the display substrate 10 of the embodiment of the present invention includes: a substrate substrate 11 , a first insulating layer 131 disposed on the substrate substrate 11 , and a first insulating layer 131 disposed on the first insulating layer 131 . And at least one signal line 12 covering the second insulating layer 132 on the first insulating layer 131 and the signal line 12; wherein at least one of the signal lines 12 is disposed in the receiving line slot 14, and one of the receiving line slots 14 A signal line 12 is accommodated.
  • the base substrate 11 may be a glass substrate or a plastic substrate; the first insulating layer 131 may be an insulating light transmissive material layer; the second insulating layer 132 may be a single layer structure or a double layer structure, such as: As shown in FIG. 3, the second insulating layer 132 has a two-layer structure, including a gate insulating layer 1321 located in the lower layer, and a protective layer (PVX layer) 1322 located in the upper layer; wherein the gate insulating layer 1321 can be, for example, silicon nitride. Floor.
  • the number of the signal lines 12 is determined by the function and structure of the display substrate.
  • the number of the signal lines 12 is plural, and the plurality of signal lines 12 may all be disposed in the respective line slots 14 or only a part of the signal lines. 12 is disposed in each of the line grooves 14, but it should be noted that in any case, one of the line grooves 14 is provided with only one signal line 12.
  • the upper surface of the second insulating layer 132 formed on the first insulating layer 131 and the signal lines 12 tends to The flat surface is such that the upper surface of the display substrate 10 tends to be flat, reducing the probability of breakage of the second insulating layer 132 above the signal line 12, thereby reducing the probability of occurrence of a problem of the signal line 12.
  • the alignment film of the display substrate 10 is rubbed, the friction dead zone caused by the convexity having the slope of the upper surface of the display substrate 10 is reduced, and the rubbing cloth and the alignment film can be more sufficiently contacted, so that the alignment film can be made normal. Orientation, the alignment of the liquid crystal molecules is normal, and the probability of light leakage of the display device is reduced.
  • the display substrate may be divided into a peripheral routing area and a display area according to a display function, and the receiving line slot 14 is located in a peripheral routing area and/or a display area, and the signal line may specifically be Grid lines and/or data lines.
  • the first insulating layer 131 is a buffer layer
  • the position of the capacitance groove 14 corresponds to the peripheral wiring region on the base substrate 11
  • the signal line 12 is the gate line and And/or a data line;
  • a plurality of spaced-apart line slots 14 are disposed on the buffer layer, and each of the capacitor slots 14 is provided with a signal line, which may be a gate line or a data line.
  • the buffer layer is made of an insulating light-transmitting material, the buffer layer can be used to isolate the respective signal lines from mutual signal interference.
  • the first insulating layer may specifically be selected from a silicon nitride layer or a silicon dioxide layer, or a combined layer including a silicon nitride layer and a silicon dioxide layer.
  • the upper surface of the signal line 12 may be flush with the upper surface of the first insulating layer 131, that is, the gate
  • the upper surface of the wire or the upper surface of the data line is flush with the upper surface of the first insulating layer.
  • the signal line 12 is a gate line
  • the first insulating layer 131 is a buffer layer
  • the upper surface of the gate line is flush with the upper surface of the buffer layer.
  • the first insulating layer 131 may be a gate insulating layer, and the upper surface of the data line is flush with the upper surface of the gate insulating layer. Therefore, the upper surface of the second insulating layer 132 formed over the gate line or the data line and the first insulating layer 131 is flat, so that the upper surface of the display substrate 10 is also flat, avoiding being located above the gate line or the data line.
  • the second insulating layer 132 is damaged, thereby reducing the probability of occurrence of defective gate lines or data lines; and the friction dead zone on the upper surface of the display substrate 10 can be reduced, thereby reducing the probability of light leakage of the display device.
  • the signal line 12 provided in the peripheral wiring region is a gate line or a data line.
  • the present invention is not limited thereto, and the signal line 12 disposed in the peripheral routing area may also be the gate line 15 and the data line 16, wherein the gate line 15 and the data line 16 may be disposed in the same layer as shown in FIG. It can be set as a different layer as shown in Fig. 6 or Fig. 7.
  • the first insulating layer 131 includes a first sub-insulating layer 1311 and a second sub-insulating layer 1312 respectively provided with at least one line groove 14, and the second sub-insulating layer 1312 is located Above the first sub-insulating layer 1311, for example, referring to FIG. 6, the data line 16 is located in the receiving line groove 14 of the first sub-insulating layer 1311, and the gate line 15 is located in the receiving line groove 14 of the second sub-insulating layer 1312.
  • the second insulating layer 132 covers the second sub-insulating layer 1312 and the gate line 15; or, referring to FIG.
  • the data line 16 is located in the receiving line slot 14 of the second sub-insulating layer 1312, and the gate line 15 is located in the first sub-portion In the capacitor groove 14 of the insulating layer 1311, the second insulating layer 132 covers the second sub-insulating layer 1312 and the data line 16.
  • the gate line 15 and the data line 16 are located in the line groove 14 of the corresponding sub-insulating layer, so that the second line is formed in the second
  • the sub-insulating layer and the second insulating layer 132 on the signal line 12 tend to be flat, so that the upper surface of the display substrate 10 is relatively flat, and the second insulating layer 132 located above the gate line 15 and the data line 16 is prevented from being damaged, thereby reducing The probability of undesirable problems with gate lines 15 and data lines 16 occurs.
  • the upper surface of the gate line 15 and the first sub-insulating layer The upper surface of the 1311 is flush, and the upper surface of the data line 16 is flush with the upper surface of the second sub-insulating layer 1312. Therefore, the upper surface of the second insulating layer 132 formed over the signal line 12 and the first insulating layer is flat, so that the upper surface of the display substrate 10 is also flat, avoiding the first portion above the gate line 15 and the data line 16.
  • the two insulating layers 132 are damaged, thereby reducing the probability of occurrence of defective problems of the gate lines 15 and the data lines 16.
  • the line slot 14 in the display substrate 10 provided by the above embodiment may also be located in the display area, and the signal line 12 includes the data line 16 or the gate line 15; or, as shown in FIG. 8, the signal line 12 includes data disposed in different layers.
  • the line 16 and the gate line 15, the gate line 15 and the data line 16 are criss-crossed, and the angle between the gate line 15 and the projection of the data line 16 is 90°, and the first insulating layer 131 includes the first portion provided with at least one line groove 14 respectively.
  • the gate line 15 is located in the capacitance groove 14 of the second sub-insulating layer 1312; or the data line 16 is located in the capacitance line 14 of the second sub-insulating layer 1312, and the gate line 15 is located in the capacitance line of the first sub-insulating layer 1311. In the slot 14.
  • the display panel 10 in the above embodiment may be a substrate provided with signal lines such as an array substrate, a color filter substrate, and a touch substrate.
  • the signal line may be a data line and/or a gate line as described above, and may also be a signal that can transmit signals such as a power line, a common electrode line, a touch scan line, or a touch sensing line.
  • an embodiment of the present invention provides a manufacturing method for manufacturing the above display substrate 10 , including:
  • Step 201 forming a first insulating layer 131 on the base substrate 11, and forming a pattern including at least one of the toner grooves 14 on the first insulating layer 131 by one patterning process.
  • Step 201 For an exemplary fabrication process, please refer to FIG. 10a and FIG. 10b; as shown in FIG. 10a, a first insulating layer 131 is formed on the substrate substrate 11; then, as shown in FIG. 10b, a patterning process by development, etching, etc. A pattern including at least one of the toner grooves 14 is formed in the first insulating layer 131.
  • the depth of the line groove may be the same as the thickness of the first insulating layer, or may be smaller than the thickness of the first insulating layer.
  • the first insulating layer 131 may be selected from a silicon nitride layer or a silicon dioxide layer, or a combined layer composed of a silicon nitride layer and a silicon dioxide layer.
  • Step 202 forming a conductive layer 17 on the first insulating layer 131 and each of the line grooves 14, and forming a pattern of signal lines 12 in each of the line grooves 14 by one patterning process.
  • a conductive layer 17 is formed on the first insulating layer 131 and the capacitor line groove 14 remaining after the etching in step 201, wherein the conductive layer It may be a metal layer or a conductive glass layer or the like; then, as shown in FIG.
  • a signal line 12 is formed in each of the capacitance grooves 14 by a patterning process such as development, etching, etc., and the signal line 12 is a conductive layer 17 The remaining part after etching.
  • the upper surface of the signal line may be flush with the upper surface of the first insulating layer to further reduce the probability of breakage of the second insulating layer above the signal line, thereby reducing the probability of occurrence of signal line defects.
  • Step 203 forming a second insulating layer 132 on the first insulating layer 131 and the plurality of signal lines 12.
  • the capacitance groove 14 is disposed on the first insulating layer 131 corresponding to the signal line 12, at least one of the signal lines 12 is located in the capacitance groove 14.
  • a capacitor line 14 accommodates a signal line 12 such that the upper surface of the second insulating layer 132 formed on the first insulating layer 131 and each of the signal lines 12 tends to be flat, so that the upper surface of the display substrate 10 tends to be flat.
  • the second insulating layer 132 located above the signal line 12 is prevented from being damaged, thereby reducing the frequency of occurrence of the problem of the signal line 12.
  • the display substrate 10 may be divided into a peripheral routing area and a display area according to a display function, wherein the manufacturing method of the peripheral routing area is similar to the manufacturing method of the display area, and the data line is used as the gate line and the data below.
  • the line, the first insulating layer includes a first sub-insulating layer and a second sub-insulating layer, and the gate lines and the data lines are disposed on different layers, and the data lines are located above the gate lines.
  • the example of the method of fabricating the substrate includes:
  • Step 301 forming a first sub-insulating layer 1311 on the base substrate 11, and passing a patterning work Forming a pattern including at least one toner groove 14 on the first sub-insulating layer 1311;
  • Step 302 forming a conductive layer 17 on the first sub-insulating layer 1311 and each of the capacitor lines 14 to form a pattern of gate lines 15 in each of the capacitor lines 14 by a patterning process;
  • Step 303 forming a second sub-insulating layer 1312 on the first sub-insulating layer 1311 and each gate line 15 to form a pattern including at least one of the line grooves 14 on the second sub-insulating layer 1312 by one patterning process.
  • Step 304 forming a conductive layer 17 on the second sub-insulating layer 1312 and each of the capacitor lines 14 to form a pattern of data lines 16 in each of the capacitor lines 14 by a patterning process;
  • Step 305 forming a second insulating layer 132 on the second sub-insulating layer 1312 and the data line 16.
  • a capacitance groove 14 is disposed on the first sub-insulating layer 1311 corresponding to the gate line 15, and one gate line 15 is located in one of the capacitance grooves 14.
  • a capacitance groove 14 is disposed on the second sub-insulating layer 1312 corresponding to the data line 16, and one data line 16 is disposed in one of the capacitance grooves 14 so as to be formed on the first sub-insulating layer 1311, the gate line 15, and the second
  • the sub-insulating layer 1312 and the second insulating layer 132 over the data line 16 tend to be flat, so that the upper surface of the display substrate 10 is relatively flat, and the second insulating layer 132 located above the gate line 15 and the data line 16 is prevented from being damaged, thereby reducing
  • the probability of occurrence of defective problems of the gate lines 15 and the data lines 16 is reduced; at the same time, the probability of light leakage in the display area of the liquid crystal screen is also reduced because the friction dead zone caused by the bumps having the slope is reduced.
  • the embodiment of the invention further provides a display device, which comprises the display substrate provided by any of the above embodiments.
  • the display device may be any product or component having a display function such as a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a liquid crystal display device, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种显示基板(10)及显示装置，所述显示基板(10)包括：衬底基板(11)；设置在衬底基板(11)上的第一绝缘层(131)，第一绝缘层(131)上设有至少一个容线槽(14)；以及至少一条信号线(12)，信号线(12)中的至少一条设置在容线槽(14)中，且一个容线槽(14)配置以容纳一条信号线(12)；以及覆盖在第一绝缘层(131)和信号线(12)上的第二绝缘层(132)。所述显示装置包括上述技术方案所提供的显示基板(10)。

Description

显示基板及显示装置 技术领域
本发明的实施例涉及一种显示基板及显示装置。
背景技术
随着显示技术的不断发展，薄膜晶体管(Thin Film Transistor，以下简称TFT)液晶显示器在当前的显示器中占据了主导地位。显示基板在TFT液晶显示器的高响应度、高亮度、高对比度等方面起到了重要的作用，如图1所示，一种已知的显示基板10包括衬底基板11、设置在衬底基板上的信号线12以及在信号线上形成的绝缘层13。
然而，本申请发明人发现已知的这种显示基板10存在如下缺陷：由于各信号线12设置在衬底基板11的上表面上，导致形成在衬底基板11和各信号线12上的绝缘层13存在凸起；而当有外力作用在该绝缘层13上时，导致绝缘层13易出现破损，使得信号线12易被电解液或水汽腐蚀，导致信号线出现不良。显示基板上的取向膜与绝缘层13凸起所对应的位置形成一定坡度，导致摩擦取向时所述位置存在摩擦盲区，所述盲区导致液晶分子排列异常从而引起液晶屏漏光现象。
发明内容
本发明的实施例提供一种显示基板及显示装置以减少信号线不良问题出现的机率。
本发明的至少一个实施例提供了一种显示基板，包括：
衬底基板；
设置在所述衬底基板上的第一绝缘层，所述第一绝缘层上设有至少一个容线槽；
至少一条信号线，所述信号线中的至少一条设置在所述容线槽中，且一个所述容线槽用于容纳一条所述信号线；以及
第二绝缘层，覆盖在所述第一绝缘层和所述信号线上。
在一个示例中，所述显示基板包括外围走线区域和显示区域。
在一个示例中，所述容线槽位于所述外围走线区域，所述信号线包括 栅线或数据线。
在一个示例中，所述容线槽位于所述外围走线区域，所述信号线包括数据线和栅线，且所述数据线和所述栅线设置在同层。
在一个示例中，所述容线槽位于所述外围走线区域，所述信号线包括数据线和栅线，且所述数据线和所述栅线设置在不同层。
在一个示例中，所述数据线和所述栅线以如下方式设置在不同层：
所述第一绝缘层包括分别设有至少一个容线槽的第一子绝缘层和第二子绝缘层，且所述第二子绝缘层位于所述第一子绝缘层的上方，其中，
所述数据线位于所述第一子绝缘层的容线槽中，所述栅线位于所述第二子绝缘层的容线槽中；
或者，所述数据线位于所述第二子绝缘层的容线槽中，所述栅线位于所述第一子绝缘层的容线槽中。
在一个示例中，所述容线槽位于所述显示区域，所述信号线包括数据线或栅线。
在一个示例中，所述容线槽位于所述显示区域，所述信号线包括数据线和栅线。
在一个示例中，所述容线槽位于所述显示区域，所述信号线包括数据线和栅线，且所述数据线和栅线设置在不同层。
在一个示例中，所述数据线和栅线以如下方式设置在不同层：
所述第一绝缘层包括分别设有至少一个容线槽的第一子绝缘层和第二子绝缘层，且所述第二子绝缘层位于所述第一子绝缘层的上方，其中，
所述数据线位于所述第一子绝缘层的容线槽中，所述栅线位于所述第二子绝缘层的容线槽中；
或者，所述数据线位于所述第二子绝缘层的容线槽中，所述栅线位于所述第一子绝缘层的容线槽中。
在一个示例中，所述第一绝缘层为氮化硅层或二氧化硅层，或所述第一绝缘层为包括氮化硅层和二氧化硅层的组合层。
在一个示例中，所述信号线的上表面与所述第一绝缘层的上表面平齐。
本发明的至少一个实施例还提供了一种显示装置，包括上述任一显示基板。
附图说明
以下将结合附图对本发明的实施例进行更详细的说明，以使本领域普通技术人员更加清楚地理解本发明，其中：
图1为一种已知的显示基板的结构示意图；
图2为本发明实施例中显示基板的结构示意图一；
图3为本发明实施例中显示基板的结构示意图二；
图4为本发明实施例中显示基板的结构示意图三；
图5为本发明实施例中显示基板的结构示意图四；
图6为本发明实施例中显示基板的结构示意图五；
图7为本发明实施例中显示基板的结构示意图六；
图8为本发明实施例中显示基板的显示区域的信号线的排布示意图；
图9为本发明实施例中显示基板的制造方法的方法流程图；
图10a、图10b、图10c、图10d、图10e为本发明实施例中显示基板的制造过程示意图；
图11为本发明实施例中显示基板的又一制造方法的方法流程图。
附图标记：
10-显示基板，                11-衬底基板，
12-信号线，                  13-绝缘层，
14-容线槽，                  15-栅线，
16-数据线，                  17-导电层，
131-第一绝缘层，             132-第二绝缘层，
1311-第一子绝缘层，          1312-第二子绝缘层，
1321-栅极绝缘层，            1322-保护层。
具体实施方式
为使本发明的实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图对本发明的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例仅是本发明的一部分示例性实施例，而不是全部的实施例。基于所描述的本发明的示例性实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例都属于本发明的保护范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“上”、“下”、等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
请参阅图2，本发明实施例提供的显示基板10包括：衬底基板11，设置在衬底基板11上的第一绝缘层131，第一绝缘层131上设有至少一个容线槽14，以及至少一条信号线12，覆盖在第一绝缘层131和信号线12上的第二绝缘层132；其中，信号线12中的至少一条设置在容线槽14中，且一个容线槽14用于容纳一条信号线12。
在一个示例中，衬底基板11可以为玻璃基板或塑料基板；第一绝缘层131可以为绝缘透光材料层；第二绝缘层132可以为单层结构，也可以为双层结构，比如：如图3所示，第二绝缘层132为两层结构，包括位于下层的栅极绝缘层1321，位于上层的保护层(PVX层)1322；其中，栅极绝缘层1321可为例如氮化硅层。信号线12的条数由显示基板的功能和结构决定，在本实施中信号线12数量为多条，多条信号线12可以全部设置在各容线槽14内，也可以仅有一部分信号线12设置在各容线槽14内，但需要注意的是，在任何情况下，一个容线槽14仅设置有一条信号线12。
在上述实施例提供的显示基板中，由于信号线12部分或全部设置在对应的容线槽14内，使得形成在第一绝缘层131和信号线12上的第二绝缘层132上表面趋于平整，从而使得显示基板10的上表面趋于平整，减少位于信号线12上方的第二绝缘层132发生破损的机率，进而减少信号线12不良问题出现的机率。而且，当对显示基板10的取向膜进行摩擦时，减少了显示基板10的上表面由具有坡度的凸起造成的摩擦盲区，摩擦布和取向膜能够较为充分地接触，从而使得取向膜能够正常取向，液晶分子排列正常，减少了显示装置出现漏光现象的机率。
在一个示例中，上述显示基板可按照显示功能划分为外围走线区域和显示区域，容线槽14位于外围走线区域和/或显示区域，信号线具体可以为 栅线和/或数据线。例如，在衬底基板11上的外围走线区域中，第一绝缘层131为缓冲层，容线槽14的位置与衬底基板11上的外围走线区域对应，信号线12为栅线和/或数据线；例如，在该缓冲层上设有多个间隔排列的容线槽14，在每个容线槽14设置有一条信号线，该信号线可以为栅线或数据线。由于缓冲层是由绝缘透光材料制成的，因此利用该缓冲层可以隔离各个信号线以防止其相互间的信号干扰。需要说明的是，第一绝缘层具体可以选自氮化硅层或二氧化硅层，或为包括氮化硅层和二氧化硅层的组合层。
在一个示例中，为了防止在显示基板10的上表面与各信号线12对应的区域出现凸起，例如，信号线12的上表面可与第一绝缘层131的上表面平齐，即，栅线的上表面或数据线的上表面与第一绝缘层的上表面平齐。请参阅图2，信号线12为栅线时，第一绝缘层131为缓冲层，栅线的上表面与缓冲层的上表面平齐。或者，请参阅图4，信号线12为数据线时，第一绝缘层131可以为栅绝缘层，数据线的上表面与栅绝缘层的上表面平齐。因此，形成在栅线或数据线以及第一绝缘层131上方的第二绝缘层132的上表面是平整的，从而使得显示基板10的上表面也是平整的，避免位于栅线或数据线上方的第二绝缘层132发生破损，进而减少栅线或数据线不良问题出现的机率；并可减少在显示基板10的上表面的摩擦盲区，所以也减少了显示装置出现漏光现象的几率。
上述实施例提供的显示基板10中，设于外围走线区域中的信号线12为栅线或数据线。但本发明不限于此，设于外围走线区域中的信号线12还可以同时为栅线15和数据线16，其中，栅线15和数据线16可以如图5所示同层设置，也可以如图6或图7所示异层设置。当栅线15和数据线16异层设置时，第一绝缘层131包括分别设有至少一个容线槽14的第一子绝缘层1311和第二子绝缘层1312，第二子绝缘层1312位于第一子绝缘层1311的上方，比如：请参阅图6，数据线16位于第一子绝缘层1311的容线槽14中，栅线15位于第二子绝缘层1312的容线槽14中，第二绝缘层132覆盖于第二子绝缘层1312和栅线15上；或者，请参阅图7，数据线16位于第二子绝缘层1312的容线槽14中，栅线15位于第一子绝缘层1311的容线槽14中，第二绝缘层132覆盖于第二子绝缘层1312和数据线16上。
由于在第一子绝缘层1311和第二子绝缘层1312上设置有容线槽14，栅线15和数据线16位于对应的子绝缘层的容线槽14中，使得形成在第二 子绝缘层和信号线12上的第二绝缘层132趋于平整，从而使得显示基板10的上表面较平整，避免位于栅线15和数据线16上方的第二绝缘层132破损，进而减少了栅线15和数据线16不良问题出现的机率。
在一个示例中，为了防止在显示基板10的上表面与各数据线16对应的区域出现凸起，例如，当数据线16位于第一子绝缘层1311的容线槽14中并且栅线15位于第二子绝缘层1312的容线槽14中时，数据线16的上表面与第一子绝缘层1311的上表面平齐，栅线15的上表面与第二子绝缘层1312的上表面平齐；当数据线16位于第二子绝缘层1312的容线槽14中并且栅线15位于第一子绝缘层1311的容线槽14中时，栅线15的上表面与第一子绝缘层1311的上表面平齐，数据线16的上表面与第二子绝缘层1312的上表面平齐。因此，形成在信号线12和第一绝缘层上方的第二绝缘层132的上表面是平整的，从而使得显示基板10的上表面也是平整的，避免位于栅线15和数据线16上方的第二绝缘层132发生破损，进而减少栅线15和数据线16不良问题出现的机率。
上述实施例提供的显示基板10中的容线槽14还可以位于显示区域，信号线12包括数据线16或栅线15；或者，如图8所示，信号线12包括设置在不同层的数据线16和栅线15，栅线15和数据线16纵横交错，栅线15与数据线16的投影的夹角为90°，第一绝缘层131包括分别设有至少一个容线槽14的第一子绝缘层1311和第二子绝缘层1312，且第二子绝缘层1312位于所述第一子绝缘层1311的上方，其中，数据线16位于第一子绝缘层1311的容线槽14中，栅线15位于第二子绝缘层1312的容线槽14中；或者，数据线16位于第二子绝缘层1312的容线槽14中，栅线15位于第一子绝缘层1311的容线槽14中。
需要说明的是，上述实施例中的显示面板10可以为阵列基板、彩膜基板、触控基板等设有信号线的基板。信号线除如上所述可以为数据线和/或栅线外，还可以为电源线、公共电极线、触控扫描线或触控感应线等可传递信号的导线。
请参考图9，本发明实施例提供了一种制造上述显示基板10的制作方法，包括：
步骤201，在衬底基板11上形成第一绝缘层131，通过一次构图工艺在所述第一绝缘层131上形成包括至少一个容线槽14的图形。步骤201的 一个示例性制作过程请参考图10a和图10b；如图10a所示，在衬底基板11上形成一层第一绝缘层131；之后，如图10b所示，通过显影、刻蚀等构图工艺，在第一绝缘层131形成包括至少一个容线槽14的图形。其中，容线槽的深度可以和第一绝缘层的厚度相同，也可以小于第一绝缘层的厚度。需要说明的是，第一绝缘层131可以选自氮化硅层或二氧化硅层，或为由氮化硅层和二氧化硅层构成的组合层。
步骤202，在所述第一绝缘层131和各所述容线槽14上形成导电层17，通过一次构图工艺在每个所述容线槽14中形成一条信号线12的图形。步骤202的一个示例性制作过程请参考图10c和图10d；如图10c所示，在经过步骤201刻蚀后剩余的第一绝缘层131和容线槽14上形成导电层17，其中导电层可以是金属层或导电玻璃层等等；之后，如图10d所示，经过显影、刻蚀等构图工艺，在每个容线槽14中形成一条信号线12，信号线12是导电层17经过刻蚀后剩余的部分。例如，信号线的上表面可与第一绝缘层的上表面平齐，以进一步减少位于信号线上方的第二绝缘层发生破损的机率，进而减轻信号线不良问题出现的机率。
步骤203，在所述第一绝缘层131和多条所述信号线12上形成第二绝缘层132。步骤203的一个示例性制作过程请参考图10e，在第一绝缘层131和多条信号线12上形成第二绝缘层132。
在本发明实施例提供的制造显示基板10的制造方法中，由于在与信号线12对应的第一绝缘层131上设置有容线槽14，信号线12中的至少一条位于容线槽14中，且一个容线槽14容纳一条信号线12，使得形成在第一绝缘层131和各信号线12上的第二绝缘层132上表面趋于平整，从而使得显示基板10的上表面趋于平整，避免位于信号线12上方的第二绝缘层132发生破损，进而减少信号线12不良问题出现的频率。
而且，在一个示例中，显示基板10可按照显示功能划分为外围走线区域和显示区域，其中，外围走线区域的制造方法与显示区域的制造方法类似，下面以数据线为栅线和数据线、第一绝缘层包括第一子绝缘层和第二子绝缘层并且栅线和数据线设置于不同层、数据线位于栅线的上方为例，进行显示基板10的制作方法的说明，请参考图11，显示基板的制作方法的该示例包括：
步骤301，在衬底基板11上形成第一子绝缘层1311，通过一次构图工 艺在所述第一子绝缘层1311上形成包括至少一个容线槽14的图形；
步骤302，在所述第一子绝缘层1311和各所述容线槽14上形成导电层17，通过一次构图工艺在每个所述容线槽14中形成一条栅线15的图形；
步骤303，在所述第一子绝缘层1311和各栅线15上形成第二子绝缘层1312，通过一次构图工艺在所述第二子绝缘层1312上形成包括至少一个容线槽14的图形；
步骤304，在所述第二子绝缘层1312和各所述容线槽14上形成导电层17，通过一次构图工艺在每个所述容线槽14中形成一条数据线16的图形；
步骤305，在所述第二子绝缘层1312和所述数据线16上形成第二绝缘层132。
其中步骤301-步骤305中的构图工艺等具体方式可以参考步骤201-步骤203的具体内容，在此不再赘述。
在本示例中，由于信号线12为栅线15和数据线16，在与栅线15对应的第一子绝缘层1311上设置有容线槽14，一条栅线15位于一个容线槽14中，在与数据线16对应的第二子绝缘层1312上设置有容线槽14，一条数据线16位于一个容线槽14中，使得形成在第一子绝缘层1311、栅线15、第二子绝缘层1312和数据线16上方的第二绝缘层132趋于平整，从而使得显示基板10的上表面较平整，避免位于栅线15和数据线16上方的第二绝缘层132破损，进而减少了栅线15和数据线16不良问题出现的机率；同时，由于减少了由具有坡度的凸起造成的摩擦盲区，也减少了液晶屏幕的显示区域出现漏光现象的机率。
本发明实施例还提供了一种显示装置，包括上述任一实施例提供的显示基板。该显示装置可以为：液晶显示面板、电子纸、手机、平板电脑、电视机、液晶显示装置、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。
本申请要求于2014年12月31日提交的名称为“一种显示基板及显示装置”的中国专利申请No.201410853852.5的优先权，该申请全文以引用方式合并于本文。

Claims (14)

  1. 一种显示基板，包括：
    衬底基板；
    设置在所述衬底基板上的第一绝缘层，所述第一绝缘层上设有至少一个容线槽；以及
    至少一条信号线，所述信号线中的至少一条设置在所述容线槽中，且一个所述容线槽配置以容纳一条所述信号线；以及
    第二绝缘层，覆盖在所述第一绝缘层和所述信号线上。
  2. 根据权利要求1所述的显示基板，其中，所述显示基板包括外围走线区域和显示区域。
  3. 根据权利要求2所述的显示基板，其中，所述容线槽位于所述外围走线区域，所述信号线包括栅线和数据线。
  4. 根据权利要求2所述的显示基板，其中，所述容线槽位于所述外围走线区域，所述信号线包括数据线或栅线。
  5. 根据权利要求3所述的显示基板，其中，所述数据线和所述栅线设置在同层。
  6. 根据权利要求3所述的显示基板，其中，所述数据线和所述栅线设置在不同层。
  7. 根据权利要求6所述的显示基板，其中，所述第一绝缘层包括分别设有至少一个容线槽的第一子绝缘层和第二子绝缘层，且所述第二子绝缘层位于所述第一子绝缘层的上方，其中，
    所述数据线位于所述第一子绝缘层的容线槽中，所述栅线位于所述第二子绝缘层的容线槽中；
    或者，所述数据线位于所述第二子绝缘层的容线槽中，所述栅线位于所述第一子绝缘层的容线槽中。
  8. 根据权利要求2所述的显示基板，其中，所述容线槽位于所述显示区域，所述信号线包括数据线或栅线。
  9. 根据权利要求2所述的显示基板，其中，所述容线槽位于所述显示区域，所述信号线包括数据线和栅线。
  10. 根据权利要求9所述的显示基板，其中，所述数据线和栅线设置 在不同层。
  11. 根据权利要求10所述的显示基板，其中，所述第一绝缘层包括分别设有至少一个容线槽的第一子绝缘层和第二子绝缘层，且所述第二子绝缘层位于所述第一子绝缘层的上方，其中，
    所述数据线位于所述第一子绝缘层的容线槽中，所述栅线位于所述第二子绝缘层的容线槽中；
    或者，所述数据线位于所述第二子绝缘层的容线槽中，所述栅线位于所述第一子绝缘层的容线槽中。
  12. 根据权利要求1-11中任一所述的显示基板，其中，所述第一绝缘层为氮化硅层或二氧化硅层，或为包括氮化硅层和二氧化硅层的组合层。
  13. 根据权利要求1-11中任一所述的显示基板，其中，所述信号线的上表面与所述第一绝缘层的上表面平齐。
  14. 一种显示装置，包括如权利要求1-13中任一所述的显示基板。
PCT/CN2015/076960 2014-12-31 2015-04-20 显示基板及显示装置 WO2016107018A1 (zh)

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