WO2016106843A1 - 显示面板及其驱动电路 - Google Patents

显示面板及其驱动电路 Download PDF

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Publication number
WO2016106843A1
WO2016106843A1 PCT/CN2015/070620 CN2015070620W WO2016106843A1 WO 2016106843 A1 WO2016106843 A1 WO 2016106843A1 CN 2015070620 W CN2015070620 W CN 2015070620W WO 2016106843 A1 WO2016106843 A1 WO 2016106843A1
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WO
WIPO (PCT)
Prior art keywords
selection signal
switch
electrically connected
current channel
turned
Prior art date
Application number
PCT/CN2015/070620
Other languages
English (en)
French (fr)
Inventor
左清成
曹昌
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to KR1020177019953A priority Critical patent/KR101977710B1/ko
Priority to EA201791486A priority patent/EA033985B1/ru
Priority to JP2017535692A priority patent/JP6650459B2/ja
Priority to US14/418,081 priority patent/US9607539B2/en
Priority to GB1712019.7A priority patent/GB2550728B/en
Publication of WO2016106843A1 publication Critical patent/WO2016106843A1/zh

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Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003Display of colours
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3648Control of matrices with row and column drivers using an active matrix
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3685Details of drivers for data electrodes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00Details of flat display driving waveforms
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0297Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/06Details of flat display driving waveforms
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/08Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display panel and a driving circuit thereof.
  • a conventional display panel generally includes a driving circuit for controlling a pixel unit in the display panel to display a corresponding image.
  • the driving circuit generates a scan signal, a data signal and a selection signal, the scan signal is sent to the pixel unit through a scan line, the data signal is sent to the pixel unit through a data line, and the selection signal is used for selection
  • the output of the data signal to the pixel unit is controlled.
  • the selection signal In the process of scanning the pixel unit of the display panel by the scan signal, the selection signal needs to perform level conversion when the scanning object switches from one row of pixels to another row of pixels, and therefore, the selection signal
  • the level shifting frequency is high.
  • a driving circuit for controlling a pixel array display image in a corresponding display panel comprising: a data signal providing module for generating a data signal, wherein the data signal is used for providing a pixel array; a first selection signal generating module for providing a first selection signal; a second selection signal generating module for providing a second selection signal; and a selection module, the selection module comprising: at least two options a switch combination, the selection switch combination being electrically connected to the first selection signal generation module, the second selection signal generation module, the data signal providing module, and the pixel array, wherein the selection switch is combined for receiving The first selection signal, the second selection signal, and the data signal, and configured to output the data signal to the pixel array according to the first selection signal and the second selection signal;
  • the switch combination includes: a first switch, the first switch and the first selection signal generating module, and the data signal providing mode Electrically connecting with the first pixel column in the pixel array; a second switch, the second switch and the second selection signal generating module, the data signal providing
  • the first switch includes: a first control end, the first control end is electrically connected to the first selection signal generating module; a first input end, the first input end Electrically connecting with the data signal providing module; and a first output end, the first output end is electrically connected to the first pixel column; wherein the first control end is configured to receive the first Selecting a signal, and for controlling opening and closing of the first current channel between the first input end and the first output end according to the first selection signal; the second switch comprises: a second control end The second control end is electrically connected to the second selection signal generating module; a second input end is electrically connected to the data signal providing module; and a second output end is The second output end is electrically connected to the second pixel column; wherein the second control end is configured to receive the second selection signal, and is configured to control the second input according to the second selection signal Between the end and the second output Opening and closing of the second current channel; the third switch includes: a third control end, the third control end is electrically connected to the first selection
  • the first current channel is used to be turned off when the third current channel is turned on, and is turned on when the third current channel is turned off;
  • the second current channel is used in the The fourth current channel is turned off when turned on, and is turned on when the fourth current channel is turned off;
  • the third current channel is used to be turned off when the first current channel is turned on, and used for the first current The channel is turned on when the channel is closed;
  • the fourth current channel is used to be turned off when the second current channel is turned on, and is turned on when the second current channel is turned off.
  • the duration of the high level of the first selection signal is the same as the duration of the high level of the second selection signal, and the duration of the low level of the first selection signal
  • the duration of the low level of the second selection signal is the same; the duration of the high level of the first selection signal and the high level duration of the second selection signal are both 2K clock unit periods, The duration of the low level of the first selection signal and the low level duration of the second selection signal are both 4K clock unit periods, wherein the K is a positive integer;
  • the scan signal of the pixel array is high
  • the start time of the rising edge of the level is located for the duration of the high level of the first selection signal or for the duration of the high level of the second selection signal.
  • a driving circuit for controlling a pixel array display image in a corresponding display panel comprising: a data signal providing module for generating a data signal, wherein the data signal is used for providing a pixel array; a first selection signal generating module for providing a first selection signal; a second selection signal generating module for providing a second selection signal; and a selection module, the selection module comprising: at least two options a switch combination, the selection switch combination being electrically connected to the first selection signal generation module, the second selection signal generation module, the data signal providing module, and the pixel array, wherein the selection switch is combined for receiving The first selection signal, the second selection signal, and the data signal are used to output the data signal to the pixel array according to the first selection signal and the second selection signal.
  • the selection switch combination includes: a first switch, the first switch and the first selection signal generating module, the data signal providing module, and a first pixel column in the pixel array Electrically connecting; a second switch, the second switch is electrically connected to the second selection signal generating module, the data signal providing module, and the second pixel column in the pixel array; a third switch, The third switch is electrically connected to the first selection signal generating module and the data signal providing module; and a fourth switch, the fourth switch and the second selection signal generating module, the third The switch and the third pixel column in the pixel array are electrically connected.
  • the first switch includes: a first control end, the first control end is electrically connected to the first selection signal generating module; a first input end, the first input end Electrically connecting with the data signal providing module; and a first output end, the first output end is electrically connected to the first pixel column; wherein the first control end is configured to receive the first Selecting a signal, and for controlling opening and closing of the first current channel between the first input end and the first output end according to the first selection signal; the second switch comprises: a second control end The second control end is electrically connected to the second selection signal generating module; a second input end is electrically connected to the data signal providing module; and a second output end is The second output end is electrically connected to the second pixel column; wherein the second control end is configured to receive the second selection signal, and is configured to control the second input according to the second selection signal Between the end and the second output Opening and closing of the second current channel; the third switch includes: a third control end, the third control end is electrically connected to the first selection
  • the first control terminal is electrically connected to the first selection signal generating module through a first signal line; the second control terminal passes through the second signal line and the second selection signal generating module Electrically connecting; the third control end is electrically connected to the first selection signal generating module through the first signal line; the fourth control end passes the second signal line and the second selection signal Generate module electrical connections.
  • the first current channel is used to be turned off when the third current channel is turned on, and is turned on when the third current channel is turned off;
  • the second current channel is used in the The fourth current channel is turned off when turned on, and is turned on when the fourth current channel is turned off;
  • the third current channel is used to be turned off when the first current channel is turned on, and used for the first current The channel is turned on when the channel is closed;
  • the fourth current channel is used to be turned off when the second current channel is turned on, and is turned on when the second current channel is turned off.
  • the first switch and the second switch are both N-channel MOS transistors, and the third switch and the fourth switch are both P-channel MOS transistors; Or the first switch and the second switch are both P-channel MOS transistors, and the third switch and the fourth switch are both N-channel MOS transistors.
  • the duration of the high level of the first selection signal is the same as the duration of the high level of the second selection signal, and the duration of the low level of the first selection signal
  • the duration of the low level of the second selection signal is the same; the duration of the high level of the first selection signal and the high level duration of the second selection signal are both 2K clock unit periods, The duration of the low level of the first selection signal and the low level duration of the second selection signal are both 4K clock unit periods, wherein the K is a positive integer;
  • the scan signal of the pixel array is high
  • the start time of the rising edge of the level is located for the duration of the high level of the first selection signal or for the duration of the high level of the second selection signal.
  • the duration of the high level of the scan signal is 3K clock unit periods, and the duration of the low level of the scan signal is also 3K clock unit periods.
  • a display panel comprising: a pixel array; and a driving circuit, the driving circuit is configured to control the pixel array to display an image
  • the driving circuit comprises: a data signal providing module, configured to generate data a signal, the data signal is provided to the pixel array; a first selection signal generating module for providing a first selection signal; a second selection signal generating module for providing a second selection signal; and a selection a module, the selection module comprising: at least two selection switch combinations, the selection switch combination and the first selection signal generation module, the second selection signal generation module, the data signal providing module, and the pixel array a selective connection, the selection switch combination for receiving the first selection signal, the second selection signal, and the data signal, and for using the data according to the first selection signal and the second selection signal A signal is output to the array of pixels.
  • the selection switch combination includes: a first switch, the first switch and the first selection signal generating module, the data signal providing module, and a first pixel column in the pixel array Electrically connecting; a second switch, the second switch is electrically connected to the second selection signal generating module, the data signal providing module, and the second pixel column in the pixel array; a third switch, The third switch is electrically connected to the first selection signal generating module and the data signal providing module; and a fourth switch, the fourth switch and the second selection signal generating module, the third The switch and the third pixel column in the pixel array are electrically connected.
  • the first switch includes: a first control end, the first control end is electrically connected to the first selection signal generating module; a first input end, the first input end Electrically connecting with the data signal providing module; and a first output end, the first output end is electrically connected to the first pixel column; wherein the first control end is configured to receive the first Selecting a signal, and for controlling opening and closing of the first current channel between the first input end and the first output end according to the first selection signal; the second switch comprises: a second control end The second control end is electrically connected to the second selection signal generating module; a second input end is electrically connected to the data signal providing module; and a second output end is The second output end is electrically connected to the second pixel column; wherein the second control end is configured to receive the second selection signal, and is configured to control the second input according to the second selection signal Between the end and the second output Opening and closing of the second current channel; the third switch includes: a third control end, the third control end is electrically connected to the first selection
  • the first control terminal is electrically connected to the first selection signal generating module through a first signal line; and the second control terminal passes through the second signal line and the second selection signal generating module Electrically connecting; the third control end is electrically connected to the first selection signal generating module through the first signal line; the fourth control end passes the second signal line and the second selection signal Generate module electrical connections.
  • the first current channel is used to be turned off when the third current channel is turned on, and is turned on when the third current channel is turned off;
  • the second current channel is used in the The fourth current channel is turned off when turned on, and is turned on when the fourth current channel is turned off;
  • the third current channel is used to be turned off when the first current channel is turned on, and used for the first current The channel is turned on when the channel is closed;
  • the fourth current channel is used to be turned off when the second current channel is turned on, and is turned on when the second current channel is turned off.
  • the first switch and the second switch are both N-channel MOS transistors, and the third switch and the fourth switch are both P-channel MOS transistors; Or the first switch and the second switch are both P-channel MOS transistors, and the third switch and the fourth switch are both N-channel MOS transistors.
  • the duration of the high level of the first selection signal is the same as the duration of the high level of the second selection signal, and the duration of the low level of the first selection signal
  • the duration of the low level of the second selection signal is the same; the duration of the high level of the first selection signal and the high level duration of the second selection signal are both 2K clock unit periods, The duration of the low level of the first selection signal and the low level duration of the second selection signal are both 4K clock unit periods, wherein the K is a positive integer;
  • the scan signal of the pixel array is high
  • the start time of the rising edge of the level is located for the duration of the high level of the first selection signal or for the duration of the high level of the second selection signal.
  • the duration of the high level of the scan signal is 3K clock unit periods, and the duration of the low level of the scan signal is also 3K clock unit periods.
  • the present invention can effectively reduce the level shifting frequency of the selection signal of the driving circuit.
  • Figure 1 is a block diagram of a display panel of the present invention
  • FIG. 2 is a circuit diagram of a first embodiment of the display panel shown in FIG. 1;
  • FIG. 3 is a waveform diagram of a driving signal of the display panel shown in FIG. 2.
  • Figure 1 is a block diagram of a display panel of the present invention.
  • the display panel of the present invention may be a TFT-LCD (Thin Film Transistor Liquid) Crystal Display, thin film transistor liquid crystal display panel), OLED (Organic Light Emitting) Diode, organic light emitting diode display panel) and so on.
  • TFT-LCD Thin Film Transistor Liquid
  • OLED Organic Light Emitting
  • OLED Organic Light Emitting Diode
  • the display panel of the present invention includes a pixel array 10 and a drive circuit 20.
  • the driving circuit 20 is electrically connected to the pixel array 10 in the display panel, the driving circuit 20 is configured to control the pixel array 10 to display an image, and the driving circuit 20 includes a data signal providing module 201, A selection signal generation module 202, a second selection signal generation module 203, and a selection module 204.
  • the data signal providing module 201 is configured to generate a data signal for providing to the pixel array 10.
  • the first selection signal generating module 202 is configured to provide a first selection signal MUX1.
  • the second selection signal generating module 203 is configured to provide a second selection signal MUX2.
  • the selection module 204 includes at least two selection switch combinations, the selection switch combination and the first selection signal generation module 202, the second selection signal generation module 203, the data signal providing module 201, and the pixel array 10 electrically connected, the selection switch is configured to receive the first selection signal MUX1, the second selection signal MUX2 and the data signal, and to be used according to the first selection signal MUX1 and the second selection Signal MUX2 outputs the data signal to the pixel array 10.
  • the driving circuit 20 further includes a scan signal providing module, the scan signal providing module is electrically connected to the pixel array 10, the scan signal providing module is configured to generate a scan signal (gate signal), and is used to A scan signal is sent to the pixel array 10.
  • a scan signal providing module is electrically connected to the pixel array 10
  • the scan signal providing module is configured to generate a scan signal (gate signal), and is used to A scan signal is sent to the pixel array 10.
  • FIG. 2 is a circuit diagram of a first embodiment of the display panel shown in FIG. 1.
  • the pixel array 10 includes at least one first pixel row 101 and at least one second pixel row 102, and the first pixel row 101 and the second pixel row 102 are arrayed along the first direction 30.
  • (1D array) in the form of an array.
  • the first pixel row 101 includes at least one first pixel R1, at least one second pixel G1, and at least one third pixel B1, and the first pixel R1, the second pixel G1, and the third pixel B1 along
  • the second direction 40 is arranged in an array (one-dimensional array).
  • the second pixel row 102 includes at least a fourth pixel R2, at least a fifth pixel G2, and at least a sixth pixel B2, the fourth pixel R2, the fifth pixel G2, and the sixth pixel B2 along The second directions 40 are arranged in an array (one-dimensional array).
  • the pixel array 10 further includes at least a first pixel column 103, at least a second pixel column 104, and at least a third pixel column 105, wherein the first pixel column 103 includes the first pixel R1 and the The fourth pixel R2 includes the second pixel G1 and the fifth pixel G2, and the third pixel column 105 includes the third pixel B1 and the sixth pixel B2.
  • the first direction 30 is perpendicular to the second direction 40.
  • the selection switch combination includes a first switch 2041, a second switch 2042, a third switch 2043, and a fourth switch 2044.
  • the first switch 2041 is electrically connected to the first selection signal generating module 202, the data signal providing module 201, and the first pixel column 103 in the pixel array 10.
  • the second switch 2042 is electrically connected to the second selection signal generating module 203, the data signal providing module 201, and the second pixel column 104 in the pixel array 10.
  • the third switch 2043 is electrically connected to the first selection signal generating module 202, the data signal providing module 201, and the fourth switch 2044.
  • the fourth switch 2044 is electrically connected to the second selection signal generating module 203, the third switch 2043, and the third pixel column 105 of the pixel array 10.
  • the first switch 2041, the second switch 2042, the third switch 2043, and the fourth switch 2044 may each be a triode.
  • the first switch 2041 includes a first control terminal 20411, a first input terminal 20412, and a first output terminal 20413.
  • the first control terminal 20411 is electrically connected to the first selection signal generating module 202. Specifically, the first control terminal 20411 is electrically connected to the first selection signal generating module 202 through the first signal line 2021. .
  • the first input end 20412 is electrically connected to the data signal providing module 201.
  • the first output end 20413 is electrically connected to the first pixel column 103.
  • the first control terminal 20411 is configured to receive the first selection signal MUX1, and is configured to control, between the first input end 20412 and the first output end 20413, according to the first selection signal MUX1.
  • a current channel is turned on and off.
  • the second switch 2042 includes a second control end 20421, a second input end 20422, and a second output end 20423.
  • the second control terminal 20421 is electrically connected to the second selection signal generating module 203. Specifically, the second control terminal 20421 is electrically connected to the second selection signal generating module 203 through the second signal line 2031. .
  • the second input end 20422 is electrically connected to the data signal providing module 201.
  • the second output end 20423 is electrically connected to the second pixel column 104.
  • the second control terminal 20421 is configured to receive the second selection signal MUX2, and is configured to control a second between the second input terminal 20422 and the second output terminal 20423 according to the second selection signal MUX2. The opening and closing of the two current channels.
  • the third switch 2043 includes a third control terminal 20431, a third input terminal 20432, and a third output terminal 20433.
  • the third control terminal 20431 is electrically connected to the first selection signal generating module 202. Specifically, the third control terminal 20431 is electrically connected to the first selection signal generating module 202 by the first signal line 2021. Sexual connection.
  • the third input terminal 20432 is electrically connected to the data signal providing module 201.
  • the third output end 20433 is electrically connected to the fourth switch 2044.
  • the third control terminal 20431 is configured to receive the first selection signal MUX1, and is configured to control a third between the third input terminal 20432 and the third output terminal 20433 according to the first selection signal MUX1. Three current channels are turned on and off.
  • the fourth switch 2044 includes a fourth control terminal 20441, a fourth input terminal 20442, and a fourth output terminal 20443.
  • the fourth control terminal 20441 is electrically connected to the second selection signal generating module 203. Specifically, the fourth control terminal 20441 is electrically connected to the second selection signal generating module 203 by the second signal line 2031. Sexual connection.
  • the fourth input end 20442 is electrically connected to the third output end 20433.
  • the fourth output end 20443 is electrically connected to the third pixel column 105.
  • the fourth control terminal 20441 is configured to receive the second selection signal MUX2, and is configured to control a second between the fourth input terminal 20442 and the fourth output terminal 20443 according to the second selection signal MUX2.
  • Four current channels are turned on and off.
  • the first switch 2041 and the second switch 2042 are both NMOS (Negative channel) Metal Oxide Semiconductor (N-channel metal oxide semiconductor) transistor
  • the third switch 2043 and the fourth switch 2044 are both PMOS (Positive Channel Metal Oxide Semiconductor, P-channel metal oxide semiconductor) transistor.
  • the first current channel is for closing when the third current channel is turned on, and for turning on when the third current channel is turned off.
  • the second current channel is for closing when the fourth current channel is turned on, and for turning on when the fourth current channel is turned off.
  • the third current channel is for closing when the first current channel is turned on, and for turning on when the first current channel is turned off.
  • the fourth current channel is for closing when the second current channel is turned on, and for turning on when the second current channel is turned off.
  • the duration of the high level of the first selection signal MUX1 is the same as the duration of the high level of the second selection signal MUX2, and the low level of the first selection signal MUX1 continues.
  • the time is the same as the duration of the low level of the second selection signal MUX2.
  • the duration of the high level of the first selection signal MUX1 and the high level duration of the second selection signal MUX2 are both 2K clock unit periods, and the duration of the low level of the first selection signal MUX1
  • the low level duration of the second selection signal MUX2 is 4K clock unit periods
  • the scan signal includes the first scan signal Gate1 and the second pixel row corresponding to the first pixel row 101.
  • the duration of the high level of the second scan signal Gate2) corresponding to 102 is 3K clock unit periods, and the duration of the low level of the scan signal is also 3K clock unit periods.
  • a start time of a rising edge of a high level of the scan signal of the pixel array 10 is located for a duration of a high level of the first selection signal MUX1 or a duration of a high level of the second selection signal MUX2 .
  • FIG. 3 is a waveform diagram of a driving signal of the display panel shown in FIG. 2.
  • the first scan signal Gate1 corresponding to the first pixel row 101 and the second scan signal Gate2 corresponding to the second pixel row 102 turn on the switch of the pixel in the pixel array 10 at a high level.
  • the switch that turns off the pixel at a low level is taken as an example. vice versa.
  • the first scan signal Gate1 generated by the scan signal providing module is at a high level, and the second scan signal Gate2 is at a low level.
  • the switches of the first pixel R1, the second pixel G1, and the third pixel B1 are all turned on, and the switches of the fourth pixel R2, the fifth pixel G2, and the sixth pixel B2 are turned on. Both are closed.
  • the first selection signal MUX1 is at a high level
  • the second selection signal MUX2 is at a low level.
  • the first current channel of the first switch 2041 is turned on
  • the second current channel of the second switch 2042 is turned off
  • the third current channel of the third switch 2043 is turned off.
  • the fourth current path of the fourth switch 2044 is turned on.
  • the data signal is input to the first pixel R1 of the first pixel column 103 through the first current channel to charge the first pixel R1.
  • the first scan signal Gate1 is still at a high level, and the second scan signal Gate2 is still at a low level. At this time, the switches of the first pixel R1, the second pixel G1, and the third pixel B1 are all turned on, and the switches of the fourth pixel R2, the fifth pixel G2, and the sixth pixel B2 are turned on. Both are closed.
  • the first selection signal MUX1 is at a low level, and the second selection signal MUX2 is at a low level. At this time, the first current channel is turned off, the second current channel is turned off, the third current channel is turned on, and the fourth current channel is turned on.
  • the data signal is input to the third pixel B1 of the third pixel column 105 through the third current channel and the fourth current channel to charge the third pixel B1.
  • the first scan signal Gate1 is still at a high level, and the second scan signal Gate2 is still at a low level. At this time, the switches of the first pixel R1, the second pixel G1, and the third pixel B1 are all turned on, and the switches of the fourth pixel R2, the fifth pixel G2, and the sixth pixel B2 are turned on. Both are closed.
  • the first selection signal MUX1 is at a low level, and the second selection signal MUX2 is at a high level. At this time, the first current channel is turned off, the second current channel is turned on, the third current channel is turned on, and the fourth current channel is turned off.
  • the data signal is input to the second pixel G1 of the second pixel column 104 through the second current channel to charge the second pixel G1.
  • the first scan signal Gate1 is at a low level, and the second scan signal Gate2 is at a high level. At this time, the switches of the first pixel R1, the second pixel G1, and the third pixel B1 are all turned off, and the switches of the fourth pixel R2, the fifth pixel G2, and the sixth pixel B2 are turned off. Both are turned on.
  • the first selection signal MUX1 is held at a low level, and the second selection signal MUX2 is maintained at a high level. At this time, the first current channel is turned off, the second current channel is turned on, the third current channel is turned on, and the fourth current channel is turned off.
  • the data signal is input to the fifth pixel G2 of the second pixel column 104 through the second current channel to charge the fifth pixel G2.
  • the first scan signal Gate1 is still at a low level, and the second scan signal Gate2 is still at a high level. At this time, the switches of the first pixel R1, the second pixel G1, and the third pixel B1 are all turned off, and the switches of the fourth pixel R2, the fifth pixel G2, and the sixth pixel B2 are turned off. Both are turned on.
  • the first selection signal MUX1 is maintained at a low level, and the second selection signal MUX2 is at a low level. At this time, the first current channel is turned off, the second current channel is turned off, the third current channel is turned on, and the fourth current channel is turned on.
  • the data signal is input to the sixth pixel B2 of the third pixel column 105 through the third current channel and the fourth current channel to charge the sixth pixel B2.
  • the first scan signal Gate1 is still at a low level, and the second scan signal Gate2 is still at a high level. At this time, the switches of the first pixel R1, the second pixel G1, and the third pixel B1 are all turned off, and the switches of the fourth pixel R2, the fifth pixel G2, and the sixth pixel B2 are turned off. Both are turned on.
  • the first selection signal MUX1 is at a high level, and the second selection signal MUX2 is still at a low level. At this time, the first current channel is turned on, the second current channel is turned off, the third current channel is turned off, and the fourth current channel is turned on.
  • the data signal is input to the fourth pixel R2 of the first pixel column 103 through the first current channel to charge the fourth pixel R2.
  • the level switching frequency of the selection signal can be effectively reduced, that is, the level conversion frequency of the selection signal is reduced from N times/frame to (N/2) times/frame, wherein the N The number of pixel rows for the pixel array.
  • the above technical solution is also advantageous in reducing the number of wirings of the display panel such that the improvement in resolution of the display panel is not limited by the number of the wirings.
  • the second embodiment of the display panel of the present invention is similar to the first embodiment described above, except that:
  • the first switch 2041 and the second switch 2042 are both PMOS (Positive channel Metal) Oxide Semiconductor (P-channel metal oxide semiconductor) transistor
  • the third switch 2043 and the fourth switch 2044 are both NMOS (Negative Channel Metal Oxide Semiconductor (N-channel metal oxide semiconductor) transistor.

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Abstract

一种显示面板及其驱动电路(20)。驱动电路(20)包括:数据信号提供模块(201),用于生成数据信号;第一选择信号生成模块(202),用于提供第一选择信号(MUX1);第二选择信号生成模块(203),用于提供第二选择信号(MUX2);选择模块(204),包括选择开关组合,用于接收第一选择信号(MUX1)和第二选择信号(MUX2),并将数据信号输出至像素阵列(10)。显示面板及其驱动电路(20)能降低选择信号的电平转换频率。

Description

显示面板及其驱动电路 技术领域
本发明涉及显示技术领域,特别涉及一种显示面板及其驱动电路。
背景技术
传统的显示面板一般都包括有驱动电路,传统的驱动电路用于控制所述显示面板中的像素单元显示相应的图像。
传统的驱动电路对所述显示面板进行驱动的技术方案一般为:
所述驱动电路生成扫描信号、数据信号和选择信号,所述扫描信号通过扫描线发送给所述像素单元,所述数据信号通过数据线发送给所述像素单元,所述选择信号用于有选择性地控制所述数据信号向所述像素单元的输出。
在实践中,发明人发现现有技术至少存在以下问题:
在通过所述扫描信号对所述显示面板的像素单元进行扫描的过程中,所述选择信号在扫描对象从一行像素切换至另一行像素时均需要进行电平转换,因此,所述选择信号的电平转换频率较高。
故,有必要提出一种新的技术方案,以解决上述技术问题。
技术问题
本发明的目的在于提供一种显示面板及其驱动电路,其能降低驱动电路的选择信号的电平转换频率。
技术解决方案
一种驱动电路,所述驱动电路用于控制相应的显示面板中的像素阵列显示图像,所述驱动电路包括:一数据信号提供模块,用于生成数据信号,所述数据信号用于提供给所述像素阵列;一第一选择信号生成模块,用于提供第一选择信号;一第二选择信号生成模块,用于提供第二选择信号;以及一选择模块,所述选择模块包括:至少两选择开关组合,所述选择开关组合与所述第一选择信号生成模块、所述第二选择信号生成模块、所述数据信号提供模块和所述像素阵列电性连接,所述选择开关组合用于接收所述第一选择信号、所述第二选择信号和所述数据信号,并用于根据所述第一选择信号和所述第二选择信号将所述数据信号输出至所述像素阵列;所述选择开关组合包括:一第一开关,所述第一开关与所述第一选择信号生成模块、所述数据信号提供模块和所述像素阵列中的第一像素列电性连接;一第二开关,所述第二开关与所述第二选择信号生成模块、所述数据信号提供模块和所述像素阵列中的第二像素列电性连接;一第三开关,所述第三开关与所述第一选择信号生成模块和所述数据信号提供模块电性连接;以及一第四开关,所述第四开关与所述第二选择信号生成模块、所述第三开关和所述像素阵列中的第三像素列电性连接;所述驱动电路还包括扫描信号提供模块,所述扫描信号提供模块与所述像素阵列电性连接,所述扫描信号提供模块用于生成扫描信号,并用于将所述扫描信号发送至所述像素阵列。
在上述驱动电路中,所述第一开关包括:一第一控制端,所述第一控制端与所述第一选择信号生成模块电性连接;一第一输入端,所述第一输入端与所述数据信号提供模块电性连接;以及一第一输出端,所述第一输出端与所述第一像素列电性连接;其中,所述第一控制端用于接收所述第一选择信号,并用于根据所述第一选择信号控制所述第一输入端和所述第一输出端之间的第一电流通道的开启和关闭;所述第二开关包括:一第二控制端,所述第二控制端与所述第二选择信号生成模块电性连接;一第二输入端,所述第二输入端与所述数据信号提供模块电性连接;以及一第二输出端,所述第二输出端与所述第二像素列电性连接;其中,所述第二控制端用于接收所述第二选择信号,并用于根据所述第二选择信号控制所述第二输入端和所述第二输出端之间的第二电流通道的开启和关闭;所述第三开关包括:一第三控制端,所述第三控制端与所述第一选择信号生成模块电性连接;一第三输入端,所述第三输入端与所述数据信号提供模块电性连接;以及一第三输出端,所述第三输出端与所述第四开关电性连接;其中,所述第三控制端用于接收所述第一选择信号,并用于根据所述第一选择信号控制所述第三输入端和所述第三输出端之间的第三电流通道的开启和关闭;所述第四开关包括:一第四控制端,所述第四控制端与所述第二选择信号生成模块电性连接;一第四输入端,所述第四输入端与所述第三输出端电性连接;以及一第四输出端,所述第四输出端与所述第三像素列电性连接;其中,所述第四控制端用于接收所述第二选择信号,并用于根据所述第二选择信号控制所述第四输入端和所述第四输出端之间的第四电流通道的开启和关闭。
在上述驱动电路中,所述第一电流通道用于在所述第三电流通道开启时关闭,以及用于在所述第三电流通道关闭时开启;所述第二电流通道用于在所述第四电流通道开启时关闭,以及用于在所述第四电流通道关闭时开启;所述第三电流通道用于在所述第一电流通道开启时关闭,以及用于在所述第一电流通道关闭时开启;所述第四电流通道用于在所述第二电流通道开启时关闭,以及用于在所述第二电流通道关闭时开启。
在上述驱动电路中,所述第一选择信号的高电平的持续时间和所述第二选择信号的高电平的持续时间相同,所述第一选择信号的低电平的持续时间和所述第二选择信号的低电平的持续时间相同;所述第一选择信号的高电平的持续时间和所述第二选择信号的高电平持续时间均为2K个时钟单元周期,所述第一选择信号的低电平的持续时间和所述第二选择信号的低电平持续时间均为4K个时钟单元周期,其中,所述K为正整数;所述像素阵列的扫描信号的高电平的上升沿的开始时间位于所述第一选择信号的高电平的持续时间内或者所述第二选择信号的高电平的持续时间内。
一种驱动电路,所述驱动电路用于控制相应的显示面板中的像素阵列显示图像,所述驱动电路包括:一数据信号提供模块,用于生成数据信号,所述数据信号用于提供给所述像素阵列;一第一选择信号生成模块,用于提供第一选择信号;一第二选择信号生成模块,用于提供第二选择信号;以及一选择模块,所述选择模块包括:至少两选择开关组合,所述选择开关组合与所述第一选择信号生成模块、所述第二选择信号生成模块、所述数据信号提供模块和所述像素阵列电性连接,所述选择开关组合用于接收所述第一选择信号、所述第二选择信号和所述数据信号,并用于根据所述第一选择信号和所述第二选择信号将所述数据信号输出至所述像素阵列。
在上述驱动电路中,所述选择开关组合包括:一第一开关,所述第一开关与所述第一选择信号生成模块、所述数据信号提供模块和所述像素阵列中的第一像素列电性连接;一第二开关,所述第二开关与所述第二选择信号生成模块、所述数据信号提供模块和所述像素阵列中的第二像素列电性连接;一第三开关,所述第三开关与所述第一选择信号生成模块和所述数据信号提供模块电性连接;以及一第四开关,所述第四开关与所述第二选择信号生成模块、所述第三开关和所述像素阵列中的第三像素列电性连接。
在上述驱动电路中,所述第一开关包括:一第一控制端,所述第一控制端与所述第一选择信号生成模块电性连接;一第一输入端,所述第一输入端与所述数据信号提供模块电性连接;以及一第一输出端,所述第一输出端与所述第一像素列电性连接;其中,所述第一控制端用于接收所述第一选择信号,并用于根据所述第一选择信号控制所述第一输入端和所述第一输出端之间的第一电流通道的开启和关闭;所述第二开关包括:一第二控制端,所述第二控制端与所述第二选择信号生成模块电性连接;一第二输入端,所述第二输入端与所述数据信号提供模块电性连接;以及一第二输出端,所述第二输出端与所述第二像素列电性连接;其中,所述第二控制端用于接收所述第二选择信号,并用于根据所述第二选择信号控制所述第二输入端和所述第二输出端之间的第二电流通道的开启和关闭;所述第三开关包括:一第三控制端,所述第三控制端与所述第一选择信号生成模块电性连接;一第三输入端,所述第三输入端与所述数据信号提供模块电性连接;以及一第三输出端,所述第三输出端与所述第四开关电性连接;其中,所述第三控制端用于接收所述第一选择信号,并用于根据所述第一选择信号控制所述第三输入端和所述第三输出端之间的第三电流通道的开启和关闭;所述第四开关包括:一第四控制端,所述第四控制端与所述第二选择信号生成模块电性连接;一第四输入端,所述第四输入端与所述第三输出端电性连接;以及一第四输出端,所述第四输出端与所述第三像素列电性连接;其中,所述第四控制端用于接收所述第二选择信号,并用于根据所述第二选择信号控制所述第四输入端和所述第四输出端之间的第四电流通道的开启和关闭。
在上述驱动电路中,所述第一控制端通过第一信号线与所述第一选择信号生成模块电性连接;所述第二控制端通过第二信号线与所述第二选择信号生成模块电性连接;所述第三控制端通过所述第一信号线与所述第一选择信号生成模块电性连接;所述第四控制端通过所述第二信号线与所述第二选择信号生成模块电性连接。
在上述驱动电路中,所述第一电流通道用于在所述第三电流通道开启时关闭,以及用于在所述第三电流通道关闭时开启;所述第二电流通道用于在所述第四电流通道开启时关闭,以及用于在所述第四电流通道关闭时开启;所述第三电流通道用于在所述第一电流通道开启时关闭,以及用于在所述第一电流通道关闭时开启;所述第四电流通道用于在所述第二电流通道开启时关闭,以及用于在所述第二电流通道关闭时开启。
在上述驱动电路中,所述第一开关和所述第二开关均是N沟道金属氧化物半导体晶体管,所述第三开关和所述第四开关均是P沟道金属氧化物半导体晶体管;或者所述第一开关和所述第二开关均是P沟道金属氧化物半导体晶体管,所述第三开关和所述第四开关均是N沟道金属氧化物半导体晶体管。
在上述驱动电路中,所述第一选择信号的高电平的持续时间和所述第二选择信号的高电平的持续时间相同,所述第一选择信号的低电平的持续时间和所述第二选择信号的低电平的持续时间相同;所述第一选择信号的高电平的持续时间和所述第二选择信号的高电平持续时间均为2K个时钟单元周期,所述第一选择信号的低电平的持续时间和所述第二选择信号的低电平持续时间均为4K个时钟单元周期,其中,所述K为正整数;所述像素阵列的扫描信号的高电平的上升沿的开始时间位于所述第一选择信号的高电平的持续时间内或者所述第二选择信号的高电平的持续时间内。
在上述驱动电路中,所述扫描信号的高电平的持续时间为3K个时钟单元周期,所述扫描信号的低电平的持续时间也为3K个时钟单元周期。
一种显示面板,所述显示面板包括:一像素阵列;以及一驱动电路,所述驱动电路用于控制所述像素阵列显示图像,所述驱动电路包括:一数据信号提供模块,用于生成数据信号,所述数据信号用于提供给所述像素阵列;一第一选择信号生成模块,用于提供第一选择信号;一第二选择信号生成模块,用于提供第二选择信号;以及一选择模块,所述选择模块包括:至少两选择开关组合,所述选择开关组合与所述第一选择信号生成模块、所述第二选择信号生成模块、所述数据信号提供模块和所述像素阵列电性连接,所述选择开关组合用于接收所述第一选择信号、所述第二选择信号和所述数据信号,并用于根据所述第一选择信号和所述第二选择信号将所述数据信号输出至所述像素阵列。
在上述显示面板中,所述选择开关组合包括:一第一开关,所述第一开关与所述第一选择信号生成模块、所述数据信号提供模块和所述像素阵列中的第一像素列电性连接;一第二开关,所述第二开关与所述第二选择信号生成模块、所述数据信号提供模块和所述像素阵列中的第二像素列电性连接;一第三开关,所述第三开关与所述第一选择信号生成模块和所述数据信号提供模块电性连接;以及一第四开关,所述第四开关与所述第二选择信号生成模块、所述第三开关和所述像素阵列中的第三像素列电性连接。
在上述显示面板中,所述第一开关包括:一第一控制端,所述第一控制端与所述第一选择信号生成模块电性连接;一第一输入端,所述第一输入端与所述数据信号提供模块电性连接;以及一第一输出端,所述第一输出端与所述第一像素列电性连接;其中,所述第一控制端用于接收所述第一选择信号,并用于根据所述第一选择信号控制所述第一输入端和所述第一输出端之间的第一电流通道的开启和关闭;所述第二开关包括:一第二控制端,所述第二控制端与所述第二选择信号生成模块电性连接;一第二输入端,所述第二输入端与所述数据信号提供模块电性连接;以及一第二输出端,所述第二输出端与所述第二像素列电性连接;其中,所述第二控制端用于接收所述第二选择信号,并用于根据所述第二选择信号控制所述第二输入端和所述第二输出端之间的第二电流通道的开启和关闭;所述第三开关包括:一第三控制端,所述第三控制端与所述第一选择信号生成模块电性连接;一第三输入端,所述第三输入端与所述数据信号提供模块电性连接;以及一第三输出端,所述第三输出端与所述第四开关电性连接;其中,所述第三控制端用于接收所述第一选择信号,并用于根据所述第一选择信号控制所述第三输入端和所述第三输出端之间的第三电流通道的开启和关闭;所述第四开关包括:一第四控制端,所述第四控制端与所述第二选择信号生成模块电性连接;一第四输入端,所述第四输入端与所述第三输出端电性连接;以及一第四输出端,所述第四输出端与所述第三像素列电性连接;其中,所述第四控制端用于接收所述第二选择信号,并用于根据所述第二选择信号控制所述第四输入端和所述第四输出端之间的第四电流通道的开启和关闭。
在上述显示面板中,所述第一控制端通过第一信号线与所述第一选择信号生成模块电性连接;所述第二控制端通过第二信号线与所述第二选择信号生成模块电性连接;所述第三控制端通过所述第一信号线与所述第一选择信号生成模块电性连接;所述第四控制端通过所述第二信号线与所述第二选择信号生成模块电性连接。
在上述显示面板中,所述第一电流通道用于在所述第三电流通道开启时关闭,以及用于在所述第三电流通道关闭时开启;所述第二电流通道用于在所述第四电流通道开启时关闭,以及用于在所述第四电流通道关闭时开启;所述第三电流通道用于在所述第一电流通道开启时关闭,以及用于在所述第一电流通道关闭时开启;所述第四电流通道用于在所述第二电流通道开启时关闭,以及用于在所述第二电流通道关闭时开启。
在上述显示面板中,所述第一开关和所述第二开关均是N沟道金属氧化物半导体晶体管,所述第三开关和所述第四开关均是P沟道金属氧化物半导体晶体管;或者所述第一开关和所述第二开关均是P沟道金属氧化物半导体晶体管,所述第三开关和所述第四开关均是N沟道金属氧化物半导体晶体管。
在上述显示面板中,所述第一选择信号的高电平的持续时间和所述第二选择信号的高电平的持续时间相同,所述第一选择信号的低电平的持续时间和所述第二选择信号的低电平的持续时间相同;所述第一选择信号的高电平的持续时间和所述第二选择信号的高电平持续时间均为2K个时钟单元周期,所述第一选择信号的低电平的持续时间和所述第二选择信号的低电平持续时间均为4K个时钟单元周期,其中,所述K为正整数;所述像素阵列的扫描信号的高电平的上升沿的开始时间位于所述第一选择信号的高电平的持续时间内或者所述第二选择信号的高电平的持续时间内。
在上述显示面板中,所述扫描信号的高电平的持续时间为3K个时钟单元周期,所述扫描信号的低电平的持续时间也为3K个时钟单元周期。
有益效果
相对现有技术,本发明可以有效降低所述驱动电路的选择信号的电平转换频率。
附图说明
图1为本发明的显示面板的框图;
图2为图1所示的显示面板的第一实施例的电路图;
图3为图2所示的显示面板的驱动信号的波形图。
本发明的最佳实施方式
本说明书所使用的词语“实施例”意指用作实例、示例或例证。此外,本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为意指“一个或多个”,除非另外指定或从上下文可以清楚确定单数形式。
参考图1,图1为本发明的显示面板的框图。
本发明的显示面板可以是TFT-LCD(Thin Film Transistor Liquid Crystal Display,薄膜晶体管液晶显示面板)、OLED(Organic Light Emitting Diode,有机发光二极管显示面板)等。
本发明的显示面板包括像素阵列10和驱动电路20。
所述驱动电路20与所述显示面板中的所述像素阵列10电性连接,所述驱动电路20用于控制所述像素阵列10显示图像,所述驱动电路20包括数据信号提供模块201、第一选择信号生成模块202、第二选择信号生成模块203和选择模块204。
所述数据信号提供模块201用于生成数据信号,所述数据信号用于提供给所述像素阵列10。所述第一选择信号生成模块202,用于提供第一选择信号MUX1。所述第二选择信号生成模块203,用于提供第二选择信号MUX2。所述选择模块204包括至少两选择开关组合,所述选择开关组合与所述第一选择信号生成模块202、所述第二选择信号生成模块203、所述数据信号提供模块201和所述像素阵列10电性连接,所述选择开关组合用于接收所述第一选择信号MUX1、所述第二选择信号MUX2和所述数据信号,并用于根据所述第一选择信号MUX1和所述第二选择信号MUX2将所述数据信号输出至所述像素阵列10。
所述驱动电路20还包括扫描信号提供模块,所述扫描信号提供模块与所述像素阵列10电性连接,所述扫描信号提供模块用于生成扫描信号(栅极信号),并用于将所述扫描信号发送至所述像素阵列10。
参考图2,图2为图1所示的显示面板的第一实施例的电路图。
在本实施例中,所述像素阵列10包括至少一第一像素行101和至少一第二像素行102,所述第一像素行101和所述第二像素行102沿第一方向30以阵列(一维阵列)的形式排列。所述第一像素行101包括至少一第一像素R1、至少一第二像素G1和至少一第三像素B1,所述第一像素R1、所述第二像素G1和所述第三像素B1沿第二方向40以阵列(一维阵列)的形式排列。所述第二像素行102包括至少一第四像素R2、至少一第五像素G2和至少一第六像素B2,所述第四像素R2、所述第五像素G2和所述第六像素B2沿所述第二方向40以阵列(一维阵列)的形式排列。所述像素阵列10还包括至少一第一像素列103、至少一第二像素列104以及至少一第三像素列105,其中,所述第一像素列103包括所述第一像素R1和所述第四像素R2,所述第二像素列104包括所述第二像素G1和所述第五像素G2,所述第三像素列105包括所述第三像素B1和所述第六像素B2。其中,所述第一方向30与所述第二方向40垂直。
在本实施例中,所述选择开关组合包括第一开关2041、第二开关2042、第三开关2043和第四开关2044。所述第一开关2041与所述第一选择信号生成模块202、所述数据信号提供模块201和所述像素阵列10中的第一像素列103电性连接。所述第二开关2042与所述第二选择信号生成模块203、所述数据信号提供模块201和所述像素阵列10中的第二像素列104电性连接。所述第三开关2043与所述第一选择信号生成模块202、所述数据信号提供模块201和所述第四开关2044电性连接。所述第四开关2044与所述第二选择信号生成模块203、所述第三开关2043和所述像素阵列10中的第三像素列105电性连接。
在本实施例中,所述第一开关2041、所述第二开关2042、所述第三开关2043和所述第四开关2044均可以是三极管。所述第一开关2041包括第一控制端20411、第一输入端20412和第一输出端20413。所述第一控制端20411与所述第一选择信号生成模块202电性连接,具体地,所述第一控制端20411通过第一信号线2021与所述第一选择信号生成模块202电性连接。所述第一输入端20412与所述数据信号提供模块201电性连接。所述第一输出端20413与所述第一像素列103电性连接。其中,所述第一控制端20411用于接收所述第一选择信号MUX1,并用于根据所述第一选择信号MUX1控制所述第一输入端20412和所述第一输出端20413之间的第一电流通道的开启和关闭。
所述第二开关2042包括第二控制端20421、第二输入端20422和第二输出端20423。所述第二控制端20421与所述第二选择信号生成模块203电性连接,具体地,所述第二控制端20421通过第二信号线2031与所述第二选择信号生成模块203电性连接。所述第二输入端20422与所述数据信号提供模块201电性连接。所述第二输出端20423与所述第二像素列104电性连接。其中,所述第二控制端20421用于接收所述第二选择信号MUX2,并用于根据所述第二选择信号MUX2控制所述第二输入端20422和所述第二输出端20423之间的第二电流通道的开启和关闭。
所述第三开关2043包括第三控制端20431、第三输入端20432和第三输出端20433。所述第三控制端20431与所述第一选择信号生成模块202电性连接,具体地,所述第三控制端20431通过所述第一信号线2021与所述第一选择信号生成模块202电性连接。所述第三输入端20432与所述数据信号提供模块201电性连接。所述第三输出端20433与所述第四开关2044电性连接。其中,所述第三控制端20431用于接收所述第一选择信号MUX1,并用于根据所述第一选择信号MUX1控制所述第三输入端20432和所述第三输出端20433之间的第三电流通道的开启和关闭。
所述第四开关2044包括第四控制端20441、第四输入端20442和第四输出端20443。所述第四控制端20441与所述第二选择信号生成模块203电性连接,具体地,所述第四控制端20441通过所述第二信号线2031与所述第二选择信号生成模块203电性连接。所述第四输入端20442与所述第三输出端20433电性连接。所述第四输出端20443与所述第三像素列105电性连接。其中,所述第四控制端20441用于接收所述第二选择信号MUX2,并用于根据所述第二选择信号MUX2控制所述第四输入端20442和所述第四输出端20443之间的第四电流通道的开启和关闭。
在本实施例中,所述第一开关2041和所述第二开关2042均是NMOS(Negative channel Metal Oxide Semiconductor,N沟道金属氧化物半导体)晶体管,所述第三开关2043和所述第四开关2044均是PMOS(Positive channel Metal Oxide Semiconductor,P沟道金属氧化物半导体)晶体管。
所述第一电流通道用于在所述第三电流通道开启时关闭,以及用于在所述第三电流通道关闭时开启。
所述第二电流通道用于在所述第四电流通道开启时关闭,以及用于在所述第四电流通道关闭时开启。
所述第三电流通道用于在所述第一电流通道开启时关闭,以及用于在所述第一电流通道关闭时开启。
所述第四电流通道用于在所述第二电流通道开启时关闭,以及用于在所述第二电流通道关闭时开启。
在本实施例中,所述第一选择信号MUX1的高电平的持续时间和所述第二选择信号MUX2的高电平的持续时间相同,所述第一选择信号MUX1的低电平的持续时间和所述第二选择信号MUX2的低电平的持续时间相同。
所述第一选择信号MUX1的高电平的持续时间和所述第二选择信号MUX2的高电平持续时间均为2K个时钟单元周期,所述第一选择信号MUX1的低电平的持续时间和所述第二选择信号MUX2的低电平持续时间均为4K个时钟单元周期,所述扫描信号(包括所述第一像素行101所对应的第一扫描信号Gate1、所述第二像素行102所对应的第二扫描信号Gate2)的高电平的持续时间为3K个时钟单元周期,所述扫描信号的低电平的持续时间也为3K个时钟单元周期。其中,所述K为正整数。例如,所述K=1。
所述像素阵列10的扫描信号的高电平的上升沿的开始时间位于所述第一选择信号MUX1的高电平的持续时间内或者所述第二选择信号MUX2的高电平的持续时间内。
参考图3,图3为图2所示的显示面板的驱动信号的波形图。
下面以所述第一像素行101所对应的第一扫描信号Gate1、所述第二像素行102所对应的第二扫描信号Gate2在高电平时开启所述像素阵列10中的像素的开关,在低电平时关闭所述像素的开关为例来说明。反之亦然。
在第一个时钟单元周期301:
所述扫描信号提供模块所生成的所述第一扫描信号Gate1为高电平,所述第二扫描信号Gate2为低电平。此时,所述第一像素R1、所述第二像素G1和所述第三像素B1的开关均开启,所述第四像素R2、所述第五像素G2和所述第六像素B2的开关均关闭。
所述第一选择信号MUX1为高电平,所述第二选择信号MUX2为低电平。此时,所述第一开关2041的所述第一电流通道开启,所述第二开关2042的所述第二电流通道关闭,所述第三开关2043的所述第三电流通道关闭,所述第四开关2044的所述第四电流通道开启。所述数据信号通过所述第一电流通道输入到所述第一像素列103的所述第一像素R1中,以对所述第一像素R1充电。
在第二个时钟单元周期302:
所述第一扫描信号Gate1仍为高电平,所述第二扫描信号Gate2仍为低电平。此时,所述第一像素R1、所述第二像素G1和所述第三像素B1的开关均开启,所述第四像素R2、所述第五像素G2和所述第六像素B2的开关均关闭。
所述第一选择信号MUX1为低电平,所述第二选择信号MUX2为低电平。此时,所述第一电流通道关闭,所述第二电流通道关闭,所述第三电流通道开启,所述第四电流通道开启。所述数据信号通过所述第三电流通道和所述第四电流通道输入到所述第三像素列105的所述第三像素B1中,以对所述第三像素B1充电。
在第三个时钟单元周期303:
所述第一扫描信号Gate1仍为高电平,所述第二扫描信号Gate2仍为低电平。此时,所述第一像素R1、所述第二像素G1和所述第三像素B1的开关均开启,所述第四像素R2、所述第五像素G2和所述第六像素B2的开关均关闭。
所述第一选择信号MUX1为低电平,所述第二选择信号MUX2为高电平。此时,所述第一电流通道关闭,所述第二电流通道开启,所述第三电流通道开启,所述第四电流通道关闭。所述数据信号通过所述第二电流通道输入到所述第二像素列104的所述第二像素G1中,以对所述第二像素G1充电。
在第四个时钟单元周期304:
所述第一扫描信号Gate1为低电平,所述第二扫描信号Gate2为高电平。此时,所述第一像素R1、所述第二像素G1和所述第三像素B1的开关均关闭,所述第四像素R2、所述第五像素G2和所述第六像素B2的开关均开启。
所述第一选择信号MUX1保持为低电平,所述第二选择信号MUX2保持为高电平。此时,所述第一电流通道关闭,所述第二电流通道开启,所述第三电流通道开启,所述第四电流通道关闭。所述数据信号通过所述第二电流通道输入到所述第二像素列104的所述第五像素G2中,以对所述第五像素G2充电。
在第五个时钟单元周期305:
所述第一扫描信号Gate1仍为低电平,所述第二扫描信号Gate2仍为高电平。此时,所述第一像素R1、所述第二像素G1和所述第三像素B1的开关均关闭,所述第四像素R2、所述第五像素G2和所述第六像素B2的开关均开启。
所述第一选择信号MUX1保持为低电平,所述第二选择信号MUX2为低电平。此时,所述第一电流通道关闭,所述第二电流通道关闭,所述第三电流通道开启,所述第四电流通道开启。所述数据信号通过所述第三电流通道和所述第四电流通道输入到所述第三像素列105的所述第六像素B2中,以对所述第六像素B2充电。
在第六个时钟单元周期306:
所述第一扫描信号Gate1仍为低电平,所述第二扫描信号Gate2仍为高电平。此时,所述第一像素R1、所述第二像素G1和所述第三像素B1的开关均关闭,所述第四像素R2、所述第五像素G2和所述第六像素B2的开关均开启。
所述第一选择信号MUX1为高电平,所述第二选择信号MUX2仍为低电平。此时,所述第一电流通道开启,所述第二电流通道关闭,所述第三电流通道关闭,所述第四电流通道开启。所述数据信号通过所述第一电流通道输入到所述第一像素列103的所述第四像素R2中,以对所述第四像素R2充电。
依此类推,直至完成整个画面的刷新。
通过上述技术方案,可以有效降低所述选择信号的电平转换频率,即,所述选择信号的电平转换频率从N次/帧降低为(N/2)次/帧,其中,所述N为所述像素阵列的像素行的数量。
此外,上述技术方案还有利于减少所述显示面板的布线的数量,从而使得所述显示面板的分辨率的提高不受所述布线数量的限制。
本发明的显示面板的第二实施例与上述第一实施例相似,不同之处在于:
所述第一开关2041和所述第二开关2042均是PMOS(Positive channel Metal Oxide Semiconductor,P沟道金属氧化物半导体)晶体管,所述第三开关2043和所述第四开关2044均是NMOS(Negative channel Metal Oxide Semiconductor,N沟道金属氧化物半导体)晶体管。
尽管已经相对于一个或多个实现方式示出并描述了本发明,但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型,并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能,用于描述这样的组件的术语旨在对应于执行所述组件的指定功能(例如其在功能上是等价的)的任意组件(除非另外指示),即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外,尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开,但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且,就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言,这样的术语旨在以与术语“包含”相似的方式包括。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种驱动电路,其中,所述驱动电路用于控制相应的显示面板中的像素阵列显示图像,所述驱动电路包括:
    一数据信号提供模块,用于生成数据信号,所述数据信号用于提供给所述像素阵列;
    一第一选择信号生成模块,用于提供第一选择信号;
    一第二选择信号生成模块,用于提供第二选择信号;以及
    一选择模块,所述选择模块包括:
    至少两选择开关组合,所述选择开关组合与所述第一选择信号生成模块、所述第二选择信号生成模块、所述数据信号提供模块和所述像素阵列电性连接,所述选择开关组合用于接收所述第一选择信号、所述第二选择信号和所述数据信号,并用于根据所述第一选择信号和所述第二选择信号将所述数据信号输出至所述像素阵列;
    所述选择开关组合包括:
    一第一开关,所述第一开关与所述第一选择信号生成模块、所述数据信号提供模块和所述像素阵列中的第一像素列电性连接;
    一第二开关,所述第二开关与所述第二选择信号生成模块、所述数据信号提供模块和所述像素阵列中的第二像素列电性连接;
    一第三开关,所述第三开关与所述第一选择信号生成模块和所述数据信号提供模块电性连接;以及
    一第四开关,所述第四开关与所述第二选择信号生成模块、所述第三开关和所述像素阵列中的第三像素列电性连接;
    所述驱动电路还包括扫描信号提供模块,所述扫描信号提供模块与所述像素阵列电性连接,所述扫描信号提供模块用于生成扫描信号,并用于将所述扫描信号发送至所述像素阵列。
  2. 根据权利要求1所述的驱动电路,其中,所述第一开关包括:
    一第一控制端,所述第一控制端与所述第一选择信号生成模块电性连接;
    一第一输入端,所述第一输入端与所述数据信号提供模块电性连接;以及
    一第一输出端,所述第一输出端与所述第一像素列电性连接;
    其中,所述第一控制端用于接收所述第一选择信号,并用于根据所述第一选择信号控制所述第一输入端和所述第一输出端之间的第一电流通道的开启和关闭;
    所述第二开关包括:
    一第二控制端,所述第二控制端与所述第二选择信号生成模块电性连接;
    一第二输入端,所述第二输入端与所述数据信号提供模块电性连接;以及
    一第二输出端,所述第二输出端与所述第二像素列电性连接;
    其中,所述第二控制端用于接收所述第二选择信号,并用于根据所述第二选择信号控制所述第二输入端和所述第二输出端之间的第二电流通道的开启和关闭;
    所述第三开关包括:
    一第三控制端,所述第三控制端与所述第一选择信号生成模块电性连接;
    一第三输入端,所述第三输入端与所述数据信号提供模块电性连接;以及
    一第三输出端,所述第三输出端与所述第四开关电性连接;
    其中,所述第三控制端用于接收所述第一选择信号,并用于根据所述第一选择信号控制所述第三输入端和所述第三输出端之间的第三电流通道的开启和关闭;
    所述第四开关包括:
    一第四控制端,所述第四控制端与所述第二选择信号生成模块电性连接;
    一第四输入端,所述第四输入端与所述第三输出端电性连接;以及
    一第四输出端,所述第四输出端与所述第三像素列电性连接;
    其中,所述第四控制端用于接收所述第二选择信号,并用于根据所述第二选择信号控制所述第四输入端和所述第四输出端之间的第四电流通道的开启和关闭。
  3. 根据权利要求2所述的驱动电路,其中,所述第一电流通道用于在所述第三电流通道开启时关闭,以及用于在所述第三电流通道关闭时开启;
    所述第二电流通道用于在所述第四电流通道开启时关闭,以及用于在所述第四电流通道关闭时开启;
    所述第三电流通道用于在所述第一电流通道开启时关闭,以及用于在所述第一电流通道关闭时开启;
    所述第四电流通道用于在所述第二电流通道开启时关闭,以及用于在所述第二电流通道关闭时开启。
  4. 根据权利要求1所述的驱动电路,其中,所述第一选择信号的高电平的持续时间和所述第二选择信号的高电平的持续时间相同,所述第一选择信号的低电平的持续时间和所述第二选择信号的低电平的持续时间相同;
    所述第一选择信号的高电平的持续时间和所述第二选择信号的高电平持续时间均为2K个时钟单元周期,所述第一选择信号的低电平的持续时间和所述第二选择信号的低电平持续时间均为4K个时钟单元周期,其中,所述K为正整数;
    所述像素阵列的扫描信号的高电平的上升沿的开始时间位于所述第一选择信号的高电平的持续时间内或者所述第二选择信号的高电平的持续时间内。
  5. 一种驱动电路,其中,所述驱动电路用于控制相应的显示面板中的像素阵列显示图像,所述驱动电路包括:
    一数据信号提供模块,用于生成数据信号,所述数据信号用于提供给所述像素阵列;
    一第一选择信号生成模块,用于提供第一选择信号;
    一第二选择信号生成模块,用于提供第二选择信号;以及
    一选择模块,所述选择模块包括:
    至少两选择开关组合,所述选择开关组合与所述第一选择信号生成模块、所述第二选择信号生成模块、所述数据信号提供模块和所述像素阵列电性连接,所述选择开关组合用于接收所述第一选择信号、所述第二选择信号和所述数据信号,并用于根据所述第一选择信号和所述第二选择信号将所述数据信号输出至所述像素阵列。
  6. 根据权利要求5所述的驱动电路,其中,所述选择开关组合包括:
    一第一开关,所述第一开关与所述第一选择信号生成模块、所述数据信号提供模块和所述像素阵列中的第一像素列电性连接;
    一第二开关,所述第二开关与所述第二选择信号生成模块、所述数据信号提供模块和所述像素阵列中的第二像素列电性连接;
    一第三开关,所述第三开关与所述第一选择信号生成模块和所述数据信号提供模块电性连接;以及
    一第四开关,所述第四开关与所述第二选择信号生成模块、所述第三开关和所述像素阵列中的第三像素列电性连接。
  7. 根据权利要求6所述的驱动电路,其中,所述第一开关包括:
    一第一控制端,所述第一控制端与所述第一选择信号生成模块电性连接;
    一第一输入端,所述第一输入端与所述数据信号提供模块电性连接;以及
    一第一输出端,所述第一输出端与所述第一像素列电性连接;
    其中,所述第一控制端用于接收所述第一选择信号,并用于根据所述第一选择信号控制所述第一输入端和所述第一输出端之间的第一电流通道的开启和关闭;
    所述第二开关包括:
    一第二控制端,所述第二控制端与所述第二选择信号生成模块电性连接;
    一第二输入端,所述第二输入端与所述数据信号提供模块电性连接;以及
    一第二输出端,所述第二输出端与所述第二像素列电性连接;
    其中,所述第二控制端用于接收所述第二选择信号,并用于根据所述第二选择信号控制所述第二输入端和所述第二输出端之间的第二电流通道的开启和关闭;
    所述第三开关包括:
    一第三控制端,所述第三控制端与所述第一选择信号生成模块电性连接;
    一第三输入端,所述第三输入端与所述数据信号提供模块电性连接;以及
    一第三输出端,所述第三输出端与所述第四开关电性连接;
    其中,所述第三控制端用于接收所述第一选择信号,并用于根据所述第一选择信号控制所述第三输入端和所述第三输出端之间的第三电流通道的开启和关闭;
    所述第四开关包括:
    一第四控制端,所述第四控制端与所述第二选择信号生成模块电性连接;
    一第四输入端,所述第四输入端与所述第三输出端电性连接;以及
    一第四输出端,所述第四输出端与所述第三像素列电性连接;
    其中,所述第四控制端用于接收所述第二选择信号,并用于根据所述第二选择信号控制所述第四输入端和所述第四输出端之间的第四电流通道的开启和关闭。
  8. 根据权利要求7所述的驱动电路,其中,所述第一控制端通过第一信号线与所述第一选择信号生成模块电性连接;
    所述第二控制端通过第二信号线与所述第二选择信号生成模块电性连接;
    所述第三控制端通过所述第一信号线与所述第一选择信号生成模块电性连接;
    所述第四控制端通过所述第二信号线与所述第二选择信号生成模块电性连接。
  9. 根据权利要求7所述的驱动电路,其中,所述第一电流通道用于在所述第三电流通道开启时关闭,以及用于在所述第三电流通道关闭时开启;
    所述第二电流通道用于在所述第四电流通道开启时关闭,以及用于在所述第四电流通道关闭时开启;
    所述第三电流通道用于在所述第一电流通道开启时关闭,以及用于在所述第一电流通道关闭时开启;
    所述第四电流通道用于在所述第二电流通道开启时关闭,以及用于在所述第二电流通道关闭时开启。
  10. 根据权利要求9所述的驱动电路,其中,所述第一开关和所述第二开关均是N沟道金属氧化物半导体晶体管,所述第三开关和所述第四开关均是P沟道金属氧化物半导体晶体管;或者
    所述第一开关和所述第二开关均是P沟道金属氧化物半导体晶体管,所述第三开关和所述第四开关均是N沟道金属氧化物半导体晶体管。
  11. 根据权利要求5所述的驱动电路,其中,所述第一选择信号的高电平的持续时间和所述第二选择信号的高电平的持续时间相同,所述第一选择信号的低电平的持续时间和所述第二选择信号的低电平的持续时间相同;
    所述第一选择信号的高电平的持续时间和所述第二选择信号的高电平持续时间均为2K个时钟单元周期,所述第一选择信号的低电平的持续时间和所述第二选择信号的低电平持续时间均为4K个时钟单元周期,其中,所述K为正整数;
    所述像素阵列的扫描信号的高电平的上升沿的开始时间位于所述第一选择信号的高电平的持续时间内或者所述第二选择信号的高电平的持续时间内。
  12. 根据权利要求11所述的驱动电路,其中,所述扫描信号的高电平的持续时间为3K个时钟单元周期,所述扫描信号的低电平的持续时间也为3K个时钟单元周期。
  13. 一种显示面板,其中,所述显示面板包括:
    一像素阵列;以及
    一驱动电路,所述驱动电路用于控制所述像素阵列显示图像,所述驱动电路包括:
    一数据信号提供模块,用于生成数据信号,所述数据信号用于提供给所述像素阵列;
    一第一选择信号生成模块,用于提供第一选择信号;
    一第二选择信号生成模块,用于提供第二选择信号;以及
    一选择模块,所述选择模块包括:
    至少两选择开关组合,所述选择开关组合与所述第一选择信号生成模块、所述第二选择信号生成模块、所述数据信号提供模块和所述像素阵列电性连接,所述选择开关组合用于接收所述第一选择信号、所述第二选择信号和所述数据信号,并用于根据所述第一选择信号和所述第二选择信号将所述数据信号输出至所述像素阵列。
  14. 根据权利要求13所述的显示面板,其中,所述选择开关组合包括:
    一第一开关,所述第一开关与所述第一选择信号生成模块、所述数据信号提供模块和所述像素阵列中的第一像素列电性连接;
    一第二开关,所述第二开关与所述第二选择信号生成模块、所述数据信号提供模块和所述像素阵列中的第二像素列电性连接;
    一第三开关,所述第三开关与所述第一选择信号生成模块和所述数据信号提供模块电性连接;以及
    一第四开关,所述第四开关与所述第二选择信号生成模块、所述第三开关和所述像素阵列中的第三像素列电性连接。
  15. 根据权利要求14所述的显示面板,其中,所述第一开关包括:
    一第一控制端,所述第一控制端与所述第一选择信号生成模块电性连接;
    一第一输入端,所述第一输入端与所述数据信号提供模块电性连接;以及
    一第一输出端,所述第一输出端与所述第一像素列电性连接;
    其中,所述第一控制端用于接收所述第一选择信号,并用于根据所述第一选择信号控制所述第一输入端和所述第一输出端之间的第一电流通道的开启和关闭;
    所述第二开关包括:
    一第二控制端,所述第二控制端与所述第二选择信号生成模块电性连接;
    一第二输入端,所述第二输入端与所述数据信号提供模块电性连接;以及
    一第二输出端,所述第二输出端与所述第二像素列电性连接;
    其中,所述第二控制端用于接收所述第二选择信号,并用于根据所述第二选择信号控制所述第二输入端和所述第二输出端之间的第二电流通道的开启和关闭;
    所述第三开关包括:
    一第三控制端,所述第三控制端与所述第一选择信号生成模块电性连接;
    一第三输入端,所述第三输入端与所述数据信号提供模块电性连接;以及
    一第三输出端,所述第三输出端与所述第四开关电性连接;
    其中,所述第三控制端用于接收所述第一选择信号,并用于根据所述第一选择信号控制所述第三输入端和所述第三输出端之间的第三电流通道的开启和关闭;
    所述第四开关包括:
    一第四控制端,所述第四控制端与所述第二选择信号生成模块电性连接;
    一第四输入端,所述第四输入端与所述第三输出端电性连接;以及
    一第四输出端,所述第四输出端与所述第三像素列电性连接;
    其中,所述第四控制端用于接收所述第二选择信号,并用于根据所述第二选择信号控制所述第四输入端和所述第四输出端之间的第四电流通道的开启和关闭。
  16. 根据权利要求15所述的显示面板,其中,所述第一控制端通过第一信号线与所述第一选择信号生成模块电性连接;
    所述第二控制端通过第二信号线与所述第二选择信号生成模块电性连接;
    所述第三控制端通过所述第一信号线与所述第一选择信号生成模块电性连接;
    所述第四控制端通过所述第二信号线与所述第二选择信号生成模块电性连接。
  17. 根据权利要求15所述的显示面板,其中,所述第一电流通道用于在所述第三电流通道开启时关闭,以及用于在所述第三电流通道关闭时开启;
    所述第二电流通道用于在所述第四电流通道开启时关闭,以及用于在所述第四电流通道关闭时开启;
    所述第三电流通道用于在所述第一电流通道开启时关闭,以及用于在所述第一电流通道关闭时开启;
    所述第四电流通道用于在所述第二电流通道开启时关闭,以及用于在所述第二电流通道关闭时开启。
  18. 根据权利要求17所述的显示面板,其中,所述第一开关和所述第二开关均是N沟道金属氧化物半导体晶体管,所述第三开关和所述第四开关均是P沟道金属氧化物半导体晶体管;或者
    所述第一开关和所述第二开关均是P沟道金属氧化物半导体晶体管,所述第三开关和所述第四开关均是N沟道金属氧化物半导体晶体管。
  19. 根据权利要求13所述的显示面板,其中,所述第一选择信号的高电平的持续时间和所述第二选择信号的高电平的持续时间相同,所述第一选择信号的低电平的持续时间和所述第二选择信号的低电平的持续时间相同;
    所述第一选择信号的高电平的持续时间和所述第二选择信号的高电平持续时间均为2K个时钟单元周期,所述第一选择信号的低电平的持续时间和所述第二选择信号的低电平持续时间均为4K个时钟单元周期,其中,所述K为正整数;
    所述像素阵列的扫描信号的高电平的上升沿的开始时间位于所述第一选择信号的高电平的持续时间内或者所述第二选择信号的高电平的持续时间内。
  20. 根据权利要求19所述的显示面板,其中,所述扫描信号的高电平的持续时间为3K个时钟单元周期,所述扫描信号的低电平的持续时间也为3K个时钟单元周期。
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