WO2016070516A1 - 用于氧化物半导体薄膜晶体管的扫描驱动电路 - Google Patents

用于氧化物半导体薄膜晶体管的扫描驱动电路 Download PDF

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Publication number
WO2016070516A1
WO2016070516A1 PCT/CN2015/072361 CN2015072361W WO2016070516A1 WO 2016070516 A1 WO2016070516 A1 WO 2016070516A1 CN 2015072361 W CN2015072361 W CN 2015072361W WO 2016070516 A1 WO2016070516 A1 WO 2016070516A1
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Prior art keywords
electrically connected
transistor
node
clock signal
gate
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PCT/CN2015/072361
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English (en)
French (fr)
Inventor
戴超
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to GB1703826.6A priority Critical patent/GB2544933B/en
Priority to US14/424,383 priority patent/US9548036B2/en
Priority to KR1020177007048A priority patent/KR101943236B1/ko
Priority to JP2017519235A priority patent/JP6334060B2/ja
Publication of WO2016070516A1 publication Critical patent/WO2016070516A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to a scan driving circuit for an oxide semiconductor thin film transistor.
  • GOA Gate Drive On Array
  • TFT thin film transistor
  • Array liquid crystal display array
  • the GOA circuit is mainly composed of a pull-up part, a pull-up control part, a transfer part, a pull-down part, and a pull-down sustain circuit part (
  • the pull-down holding part and the boost part responsible for the potential rise are generally composed of a bootstrap capacitor.
  • the pull-up portion is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
  • the pull-up control part is mainly responsible for controlling the opening of the pull-up part, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down portion is mainly responsible for quickly pulling the scan signal (that is, the potential of the gate of the thin film transistor) to a low level after outputting the scan signal.
  • the pull-down sustain circuit portion is mainly responsible for keeping the scan signal and the signal of the pull-up portion in a closed state (ie, a set negative potential).
  • the rising portion is mainly responsible for the secondary rise of the potential of the pull-up portion to ensure the normal output of the pull-up portion.
  • the carrier mobility of the oxide thin film transistor is 20 to 30 times that of the amorphous silicon thin film transistor, which can greatly improve the charge and discharge rate of the TFT electrode, improve the response speed of the pixel, achieve a faster refresh rate, and at the same time, faster.
  • the response also greatly increases the line scan rate of the pixels, making ultra-high resolution possible in TFT-LCDs. Therefore, the GOA circuit of the oxide semiconductor thin film transistor may replace the GOA circuit of amorphous silicon in the future, and the development of the GOA circuit for the oxide semiconductor thin film transistor in the prior art is less, and in particular, it is necessary to overcome many of the oxide thin film transistors.
  • the threshold voltage is generally greater than 0V, and the voltage in the subthreshold region is relatively large with respect to the current swing, so that even in the circuit design, even when some transistors are in operation, the transistor gate is The leakage current generated between the sources Vgs at a frequency equal to 0V is also small.
  • the oxide semiconductor thin film transistor has a significant difference from the amorphous silicon due to the characteristics of the material itself, and its threshold The value of the voltage is around 0V, and the swing in the subthreshold region is small.
  • An object of the present invention is to provide a scan driving circuit for an oxide semiconductor thin film transistor, which solves the influence of the electrical properties of the oxide thin film transistor on the GOA driving circuit, especially the functional defect caused by the leakage problem, and solves the current oxide.
  • the thin-film transistor scan drive circuit has a problem that the pull-down sustain circuit portion cannot be at a higher potential during the inactive period.
  • the present invention provides a scan driving circuit for an oxide semiconductor thin film transistor, comprising a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth stage GOA unit includes a pull-up control portion, a pull-up portion, a next-pass portion, a first pull-down portion, a bootstrap capacitor portion, and a pull-down sustain circuit portion;
  • the pull-up control portion includes an eleventh transistor, and a gate of the eleventh transistor is electrically connected to a driving output end of the N-1th GOA unit of the GOA unit of the previous stage of the Nth stage GOA unit
  • the drain is electrically connected to the output end of the N-1th GOA unit of the previous stage GOA unit of the Nth stage GOA unit, and the source is electrically connected to the first node;
  • the first pull-down portion includes a forty-first transistor, the gate of the forty-first transistor is electrically connected to the M+2 group clock signal, and the drain is electrically connected to the first node, and the source is electrically Connected to the second negative potential or the output;
  • the pull-down sustaining portion includes a fifty-first transistor, the gate and the drain of the fifty-first transistor are electrically connected to a constant voltage high potential, the source is electrically connected to the fourth node; and the fifty-second transistor
  • the gate of the fifty-second transistor is electrically connected to the first node, the drain is electrically connected to the fourth node, the source is electrically connected to the first negative potential, and the fifth thirty-third transistor, the fifth
  • the gate of the thirteenth transistor is electrically connected to the fourth node, the drain is electrically connected to the constant voltage high potential, the source is electrically connected to the second node;
  • the fifty fourth transistor, the gate of the fifty fourth transistor The gate is electrically connected to the first node, the drain is electrically connected to the second node, the source is electrically connected to the third node, and the seventh thirty-third transistor is electrically connected to the fourth a node, the drain is electrically connected to the constant voltage high potential, the source is electrically connected to the third node; the 74th transistor,
  • the fifty-first transistor, the fifty-second transistor, the fifty-third transistor, and the fifty-fourth transistor constitute a main inverter, and the main inverter is used to control the thirty-second transistor and the forty-second transistor
  • the seventy-third transistor and the seventy-fourth transistor constitute an auxiliary inverter, and the auxiliary inverter is supplied to the main inverter at a low potential during the active period, and is supplied to the main inverter at a high potential during the inactive period; ;
  • the relationship between the first negative potential, the second negative potential and the constant voltage low potential is: constant voltage low potential ⁇ second negative potential ⁇ first negative potential.
  • the auxiliary inverter further includes a 71st transistor, wherein the gate and the drain of the 71st transistor are electrically connected to a constant voltage high potential, and the source is electrically connected to the gate of the 73rd transistor.
  • a seventy-second transistor the gate of the seventy-second transistor is electrically connected to the first node, the drain is electrically connected to the gate of the seventy-third transistor, and the source is electrically connected to the constant voltage a potential; the gate of the seventy-third transistor is disconnected from the fourth node.
  • the scan driving circuit for an oxide semiconductor thin film transistor adopts a stage transmission mode in which the N-1th stage is transmitted to the Nth stage.
  • the pull-up portion includes a twenty-first transistor, the gate of the twenty-first transistor is electrically connected to the first node, the drain is electrically connected to the clock signal, and the source is electrically connected to the output end;
  • the downstream portion includes a twenty-second transistor, the gate of the second twelve transistor is electrically connected to the first node, the drain is electrically connected to the clock signal, and the source is electrically connected to the driving output end;
  • the bootstrap capacitor portion includes a capacitor, one end of the capacitor is electrically connected to the first node, and the other end is electrically connected to the output end.
  • the gate and the drain of the eleventh transistor are electrically connected to the start signal end of the circuit.
  • the waveform duty cycle of the clock signal cannot be greater than 25/75.
  • the clock signal has a duty cycle of 25/75.
  • the signal output waveform of the first node is in a "convex" shape.
  • the clock signal includes four sets of clock signals: a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal.
  • the clock signal is a third clock signal
  • the M+2 group clock The signal is a first clock signal
  • the clock signal is a fourth clock signal
  • the M+2 group clock signal is a second clock signal.
  • the present invention provides an oxide semiconductor thin film transistor a scan driving circuit, the pull-down sustain circuit portion of the scan driving circuit for the oxide semiconductor thin film transistor has a main inverter and an auxiliary inverter, introduces a constant voltage low potential, and sets a constant voltage low potential ⁇ second negative
  • the potential ⁇ first negative potential can avoid the influence of the electrical properties of the oxide semiconductor thin film transistor on the scan driving circuit, especially the functional failure caused by the leakage problem, ensuring that the pull-down sustaining circuit portion can be normally pulled low during the action, and is inactive. During the period, it is at a higher potential, effectively maintaining the first node and the output terminal at a low potential.
  • FIG. 1 is a circuit diagram of a first embodiment of a scan driving circuit for an oxide semiconductor thin film transistor of the present invention
  • Figure 2 is a circuit diagram of the first stage GOA unit of the first embodiment shown in Figure 1;
  • FIG. 3 is a circuit diagram of a second embodiment of a scan driving circuit for an oxide semiconductor thin film transistor of the present invention.
  • FIG. 4 is a circuit diagram of a third embodiment of a scan driving circuit for an oxide semiconductor thin film transistor of the present invention.
  • Figure 5 is a circuit diagram of a fourth embodiment of a scan driving circuit for an oxide semiconductor thin film transistor of the present invention.
  • Fig. 6 is a waveform diagram showing the waveform setting and the output waveform of a key node of the scan driving circuit for an oxide semiconductor thin film transistor of the present invention.
  • the scan driving circuit for an oxide semiconductor thin film transistor is a scan driving circuit of an Indium Gallium Zinc Oxide (IGZO) thin film transistor, and includes a plurality of cascaded GOA units.
  • N is a positive integer
  • the Nth stage GOA unit includes a pull-up control portion 100, a pull-up portion 200, a next-pass portion 300, a first pull-down portion 400, a bootstrap capacitor portion 500, and a pull-down sustain circuit portion 600.
  • the pull-up control portion 100 includes an eleventh transistor T11, and the gate of the eleventh transistor T11 is electrically connected to the driving of the N-1th GOA unit of the previous stage GOA unit of the Nth stage GOA unit.
  • the output terminal ST(N-1) is electrically connected to the output terminal G(N-1) of the N-1th GOA unit of the previous stage GOA unit of the Nth stage GOA unit, and the source is electrically connected.
  • the pull-up portion 200 includes a twenty-first transistor T21, the gate of the twenty-first transistor T21 is electrically connected to the first node Q(N), and the drain is electrically connected to the clock signal CK(M). The source is electrically connected to the output terminal G(N);
  • the downstream portion 300 includes a twenty-second transistor T22, the gate of the twenty-second transistor T22 is electrically connected to the first node Q(N), and the drain is electrically connected to the clock signal CK(M).
  • the source is electrically connected to the driving output terminal ST(N);
  • the first pull-down portion 400 includes only a forty-first transistor T41, and the gate of the forty-first transistor T41 is electrically connected to the M+2 group clock signal CK(M+2), and the drain is electrically Connected to the first node Q (N), the source is electrically connected to the second negative potential VSS2;
  • the bootstrap capacitor portion 500 includes a capacitor Cb, one end of the capacitor Cb is electrically connected to the first node Q (N), and the other end is electrically connected to the output terminal G (N);
  • the pull-down maintaining portion 600 includes a fifty-first transistor T51, the gate and the drain of the fifty-first transistor T51 are electrically connected to the constant voltage high potential DCH, and the source is electrically connected to the fourth node S ( N);
  • the fifty-second transistor T52, the gate of the fifty-second transistor T52 is electrically connected to the first node Q(N), the drain is electrically connected to the fourth node S(N), and the source is electrically connected to First negative potential VSS1;
  • the gate of the fifty-third transistor T53 is electrically connected to the fourth node S(N), the drain is electrically connected to the constant voltage high potential DCH, and the source is electrically connected to the second Node P(N);
  • the gate of the fifty-fourth transistor T54 is electrically connected to the first node Q(N), the drain is electrically connected to the second node P(N), and the source is electrically connected.
  • the gate and the drain of the seventy-first transistor T71 are electrically connected to the constant voltage high potential DCH, and the source is electrically connected to the gate of the seventy-third transistor T73;
  • the gate of the seventy-second transistor T72 is electrically connected to the first node Q (N), and the drain is electrically connected to the gate of the seventy-third transistor T73, the source is electrically Connected to a constant voltage low potential DCL;
  • the seventh thirty-third transistor T73, the gate of the seventy-third transistor T73 is electrically connected to the source of the seventy-first transistor T71, and the drain is electrically connected to the constant voltage high potential DCH, and the source is electrically connected. Connected to the third node K(N);
  • the gate of the seventy-fourth transistor T74 is electrically connected to the first node Q(N), the drain is electrically connected to the third node K(N), and the source is electrically connected to Constant voltage low potential DCL;
  • the forty-second transistor T42, the gate of the forty-second transistor T42 is electrically connected to the second node P(N), the drain is electrically connected to the first node Q(N), and the source is electrically connected to a second negative potential VSS2;
  • the thirty-second transistor T32, the gate of the thirty-second transistor T32 is electrically connected to the second node P(N), the drain is electrically connected to the output terminal G(N), and the source is electrically connected to the first A negative potential VSS1.
  • the relationship between the first negative potential VSS1, the second negative potential VSS2, and the constant voltage low potential DCL is: the constant voltage low potential DCL ⁇ the second negative potential VSS2 ⁇ the first negative potential VSS1.
  • the stepping mode adopted by the scan driving circuit is that the N-1th stage is transmitted to the Nth stage.
  • the gate of the eleventh transistor T11 The drain is electrically connected to the start signal terminal STV of the circuit.
  • the first pull-down portion 400 has only the forty-first transistor T41 responsible for pulling down the first node Q(N), and the gate of the forty-first transistor T41 is electrically connected to the M+2 group clock signal CK (M+ 2)
  • the source of T41 is electrically connected to the second negative potential VSS2.
  • the clock signal CK(M) includes four sets of clock signals: a first clock signal CK(1), a second clock signal CK(2), a third clock signal CK(3), and a fourth clock signal CK(4),
  • the clock signal CK(M) is the third clock signal CK(3)
  • the M+2 group clock signal CK(M+2) is the first clock signal CK(1)
  • the clock signal is When CK(M) is the fourth clock signal CK(4)
  • the M+2 group clock signal CK(M+2) is the second clock signal CK(2)
  • the ratio setting cannot be greater than 25/75 to ensure that the signal output waveform of the first node Q(N) is "convex".
  • the clock signal CK(M) has a waveform duty ratio of 25/75.
  • the pull-down sustain circuit portion 600 employs a special dual inverter design.
  • the four transistors of the fifty-first transistor T51, the fifty-second transistor T52, the fifty-third transistor T53, and the fifty-fourth transistor T54 constitute a main inverter, and the seventy-first transistor T71 and the seventy-second transistor T72
  • the seven transistors of the seventy-third transistor T73 and the seventy-fourth transistor T74 constitute an auxiliary inverter.
  • the function of the main inverter is to control the two transistors of the thirty-second transistor T32 and the forty-second transistor T42.
  • the function of the auxiliary inverter is to provide a low potential to the main inverter during the action, in the non-active state. During the period, the main inverter is supplied with an appropriate high potential to reduce the leakage of the fifty-fourth transistor T54 to ensure that the main inverter can generate a higher period during the inactive period. Potential.
  • the fifty-second transistor T52 is pulled down to the first negative potential VSS1, and the seventy-fourth transistor T74, The seventy-second transistor T72 turns on and pulls down the constant voltage high potential DCH when the first node Q(N) is high, causing the third node K(N) to be lower potential, and the second node P(N) is also pulled down.
  • the auxiliary inverter provides a low potential to the main inverter during the operation, so that the thirty-second transistor T32 and the forty-second transistor T42 can be eliminated because the threshold voltage is low or close to 0V.
  • a leakage condition caused by the physical characteristics occurs to ensure that the pull-down sustain circuit portion 600 can be normally pulled low during the action.
  • the fifty-second transistor T52, the fifty-fourth transistor T54, the seventy-second transistor T72, and the seventy-fourth transistor T74 are all turned off. Since the gate of the fifty-fourth transistor T54 is electrically connected to the first node Q(N), the source is electrically connected to the third node K(N), and the gate of the fifty-fourth transistor T54 is at a negative potential. Extremely positive, so that Vgs is a relatively very negative potential, which can turn off the fifty-fourth transistor T54 very well, reducing its leakage, that is, the auxiliary inverter provides the main inverter during the inactive period.
  • a suitable high potential is applied to reduce the leakage of the fifty-fourth transistor T54, ensuring that the pull-down sustain circuit portion 600 is at a higher potential during the inactive period, effectively maintaining the first node Q(N) and the output terminal G(N). At a low potential.
  • the third node K(N) is at a high potential, there is a function of voltage division of the resistor, and the potential of the second node P(N) can be pushed higher, thereby stabilizing the potential of the second node P(N). .
  • FIG. 3 is a second embodiment of a scan driving circuit for an oxide semiconductor thin film transistor of the present invention.
  • the second embodiment is different from the first embodiment in that the source of the forty-first transistor T41 is electrically connected to the output terminal G(N), and the source of the forty-first transistor T41 is electrically connected.
  • the leakage of the first node Q(N) through the forty-first transistor T41 during the action period can be reduced.
  • FIG. 3 and FIG. 1 have the same reference numerals in the composition, connection relationship, function and operation principle, and are not described herein again.
  • FIG. 4 is a third embodiment of a scan driving circuit for an oxide semiconductor thin film transistor of the present invention.
  • the third embodiment is different from the first embodiment in that the auxiliary inverter partially cuts off the seventy-first transistor T71 and the seventy-second transistor T72, and the gate of the seventy-third transistor T73
  • the pole is electrically connected to the fourth node S(N), and only the seventy-third transistor T73 and the seventy-fourth transistor T74 constitute an auxiliary inverter, and the auxiliary inverter refers to the fourth node S in the main inverter.
  • N To control the seventy-third transistor T73, the number of components of the auxiliary inverter can be reduced, and no additional components are required to generate waveform control similar to the S(N) node of the seventy-third transistor T73.
  • the auxiliary inverter is high/low power via the fourth node S(N) and the constant voltage low potential DCL.
  • the fifty-second transistor T52 is pulled down to the first negative potential VSS1, and the seventy-fourth transistor T74 is turned on when the first node Q(N) is high and pulls down the constant voltage high potential DCH, resulting in the third
  • the node K(N) is at a lower potential
  • the second node P(N) is also pulled down to a lower potential, that is, the auxiliary inverter provides a low potential to the main inverter during the action, thereby eliminating the thirtieth
  • the leakage of the second transistor T32 and the forty-second transistor T42 due to the lower threshold voltage or physical characteristics approaching 0V ensures that the pull-down sustain circuit portion 600 can be normally pulled low during the action.
  • the fifty-second transistor T52, the fifty-fourth transistor T54, and the seventy-fourth transistor T74 are all turned off. Since the gate of the fifty-fourth transistor T54 is electrically connected to the first node Q(N), the source is electrically connected to the third node K(N), and the gate of the fifty-fourth transistor T54 is at a negative potential.
  • the source is very positive, so that Vgs is a relatively very negative potential, which can turn off the fifty-fourth transistor T54 very well, reducing its leakage, that is, the auxiliary inverter is given to the main inverter during the inactive period.
  • a suitable high potential is provided to reduce the leakage of the fifty-fourth transistor T54, ensuring that the pull-down sustain circuit portion 600 is at a higher potential during the inactive period, effectively maintaining the first node Q(N) and the output terminal G ( N) is at a low potential.
  • the third node K(N) is at a high potential, there is also a function of voltage division of the resistor, which can push the potential of the second node P(N) higher, thereby stabilizing the second node P(N). Potential.
  • the components, the connection relationship, the function and the operation principle of the same reference numerals in FIG. 4 and FIG. 1 are the same, and are not described herein again.
  • FIG. 5 is a fourth embodiment of a scan driving circuit for an oxide semiconductor thin film transistor of the present invention.
  • the difference between the fourth embodiment and the third embodiment is that the source of the forty-first transistor T41 is electrically connected to the output terminal G(N), and the source of the forty-first transistor T41 is electrically connected. Connected to the output terminal G(N), the leakage of the first node Q(N) through the forty-first transistor T41 during the action can be reduced.
  • the components, the connection relationship, the function and the operation principle of the same reference numerals in FIG. 5 and FIG. 4 are the same, and are not described herein again.
  • FIG. 6 is a waveform diagram of an output of a scan driving circuit for an oxide semiconductor thin film transistor and an output waveform of a key node.
  • STV is the start signal of the circuit
  • CK(1)-CK(4) is the clock signal of the circuit. It can be seen that the waveform duty cycle of the clock signal shown here is 25/75, which can ensure the Q of the first node.
  • the signal output waveform is "convex"; VSS1, VSS2, DCH, and DCL are input constant voltage control signals, DCH is high, VSS1, VSS2, and DCL are constant voltage low, and DCL ⁇ VSS2 ⁇ VSS1; Other output signal waveforms generated for critical nodes of the circuit.
  • the signal output waveform of the first node Q(N) is in a "convex" shape, and the output terminal G(N) is normally output; during the inactive period, the first node Q(N) and the output terminal G(N) are at Low potential.
  • the present invention is applied to a scan driving circuit of an oxide semiconductor thin film transistor
  • the pull-maintaining circuit portion has a main inverter and an auxiliary inverter, introduces a constant voltage low potential, and sets a constant voltage low potential ⁇ second negative potential ⁇ first negative potential, which can prevent the oxide semiconductor thin film transistor from electrically scanning
  • the influence of the driving circuit, especially the leakage caused by the leakage problem ensures that the pull-down sustaining circuit portion can be normally pulled low during the active period, and is at a higher potential during the non-active period, effectively maintaining the first node and the output terminal at a low potential.

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Abstract

一种用于氧化物半导体薄膜晶体管的扫描驱动电路，该用于氧化物半导体薄膜晶体管的扫描驱动电路的下拉维持电路部分(600)具有主反相器与辅助反相器，引入一个恒压低电位(DCL)，且设置恒压低电位(DCL)＜第二负电位(VSS2)＜第一负电位(VSS1)，能够避免氧化物半导体薄膜晶体管电性对扫描驱动电路的影响，尤其是漏电问题带来的功能性不良，确保下拉维持电路部分(600)能够在作用期间正常拉低，在非作用期间处于较高的电位，有效维持第一节点(Q(N))和输出端(G(N))处于低电位。

Description

用于氧化物半导体薄膜晶体管的扫描驱动电路 技术领域
本发明涉及液晶显示领域，尤其涉及一种用于氧化物半导体薄膜晶体管的扫描驱动电路。
背景技术
GOA(Gate Drive On Array)，是利用薄膜晶体管(thin film transistor，TFT)液晶显示器阵列(Array)制程将栅极驱动器制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式。
通常，GOA电路主要由上拉部分(Pull-up part)、上拉控制部分(Pull-up control part)、下传部分(Transfer part)、下拉部分(Pull-down part)、下拉维持电路部分(Pull-down Holding part)、以及负责电位抬升的上升部分(Boost part)组成，上升部分一般由一自举电容构成。
上拉部分主要负责将输入的时钟信号(Clock)输出至薄膜晶体管的栅极，作为液晶显示器的驱动信号。上拉控制部分主要负责控制上拉部分的打开，一般是由上级GOA电路传递来的信号作用。下拉部分主要负责在输出扫描信号后，快速地将扫描信号(亦即薄膜晶体管的栅极的电位)拉低为低电平。下拉保维持电路部分则主要负责将扫描信号和上拉部分的信号保持在关闭状态(即设定的负电位)。上升部分则主要负责对上拉部分的电位进行二次抬升，确保上拉部分的正常输出。
随着氧化物半导体薄膜晶体管的发展，氧化物半导体相应的面板周边集成电路也成为关注的焦点。氧化物薄膜晶体管的载流子迁移率是非晶硅薄膜晶体管的20～30倍，可以大大提高TFT对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率，使得超高分辨率在TFT-LCD中成为可能。因此，氧化物半导体薄膜晶体管的GOA电路未来有可能取代非晶硅的GOA电路，而现有技术中针对氧化物半导体薄膜晶体管的GOA电路的开发较少，尤其需要克服很多由于氧化物薄膜晶体管电性本身带来的问题。例如：传统的非晶硅薄膜晶体管的电学特性中阈值电压一般大于0V，而且亚阈值区域的电压相对于电流的摆幅较大，这样在电路设计中即使某些晶体管在操作时晶体管栅极与源极之间的电压Vgs在等于0V附近产生的漏电流也较小。但氧化物半导体薄膜晶体管由于其材料本身的特性与非晶硅有明显的差异，其阈 值电压值在0V左右，而且亚阈值区域的摆幅较小，而GOA电路在关态时很多元件操作在Vgs＝0V，这样就会增加氧化物半导体薄膜晶体管GOA电路设计的难度，一些适用于非晶硅半导体的扫描驱动电路应用到氧化物半导体时就会存在一些功能性问题。此外，在某些外在因素的诱导和应力作用下，氧化物半导体薄膜晶体管有时候也会产生阈值电压往负值减小的趋势，这样将会直接导致氧化物半导体薄膜晶体管GOA电路无法工作，因此在设计电路时还必须要考虑这种元件特性对GOA电路的影响。
发明内容
本发明的目的在于提供一种用于氧化物半导体薄膜晶体管的扫描驱动电路，解决氧化物薄膜晶体管电性对GOA驱动电路的影响，尤其是漏电问题带来的功能性不良，解决目前的氧化物薄膜晶体管扫描驱动电路中下拉维持电路部分在非作用期间不能处于较高的电位的问题。
针对上述目的，本发明提供了一种用于氧化物半导体薄膜晶体管的扫描驱动电路，包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括一上拉控制部分、一上拉部分、一下传部分、一第一下拉部分、一自举电容部分和一下拉维持电路部分；
所述上拉控制部分包括一第十一晶体管，所述第十一晶体管的栅极电性连接于所述第N级GOA单元的前一级GOA单元第N-1级GOA单元的驱动输出端，漏极电性连接于所述第N级GOA单元的前一级GOA单元第N-1级GOA单元的输出端，源极电性连接于第一节点；
所述第一下拉部分包括一第四十一晶体管，所述第四十一晶体管的栅极电性连接于第M+2组时钟信号，漏极电性连接于第一节点，源极电性连接于第二负电位或输出端；
所述下拉维持部分包括第五十一晶体管，所述第五十一晶体管的栅极与漏极均电性连接于恒压高电位，源极电性连接于第四节点；第五十二晶体管，所述第五十二晶体管的栅极电性连接于第一节点，漏极电性连接于第四节点，源极电性连接于第一负电位；第五十三晶体管，所述第五十三晶体管的栅极电性连接于第四节点，漏极电性连接于恒压高电位，源极电性连接于第二节点；第五十四晶体管，所述第五十四晶体管的栅极电性连接于第一节点，漏极电性连接于第二节点，源极电性连接第三节点；第七十三晶体管，所述第七十三晶体管的栅极电性连接于第四节点，漏极电性连接于恒压高电位，源极电性连接于第三节点；第七十四晶体管，所述第七十四晶体管的栅极电性连接于第一节点，漏极电性连接于第三节点，源 极电性连接于恒压低电位；第四十二晶体管，所述第四十二晶体管的栅极电性连接于第二节点，漏极电性连接于第一节点，源极电性连接于第二负电位；第三十二晶体管，所述第三十二晶体管的栅极电性连接于第二节点，漏极电性连接于输出端，源极电性连接于第一负电位；
所述第五十一晶体管、第五十二晶体管、第五十三晶体管、第五十四晶体管构成主反相器，所述主反相器用于控制第三十二晶体管与第四十二晶体管；所述第七十三晶体管、第七十四晶体管构成辅助反相器，所述辅助反相器在作用期间提供给主反相器低电位，在非作用期间提供给主反相器高电位；
所述第一负电位、第二负电位与恒压低电位的关系为：恒压低电位<第二负电位<第一负电位。
所述辅助反相器还包括第七十一晶体管，所述第七十一晶体管的栅极与漏极均电性连接于恒压高电位，源极电性连接于第七十三晶体管的栅极；第七十二晶体管，所述第七十二晶体管的栅极电性连接于第一节点，漏极电性连接于第七十三晶体管的栅极，源极电性连接于恒压低电位；所述第七十三晶体管的栅极与第四节点断开。
所述用于氧化物半导体薄膜晶体管的扫描驱动电路，采用的级传方式是第N-1级传给第N级。
所述上拉部分，包括第二十一晶体管，所述第二十一晶体管的栅极电性连接于第一节点，漏极电性连接于时钟信号，源极电性连接于输出端；
所述下传部分包括第二十二晶体管，所述第二十二晶体管的栅极电性连接于第一节点，漏极电性连接于时钟信号，源极电性连接于驱动输出端；
所述自举电容部分，包括一电容，所述电容的一端电性连接于第一节点，另一端电性连接于输出端。
所述扫描驱动电路的第一级连接关系中，第十一晶体管的栅极与漏极均电性连接于电路的启动信号端。
所述时钟信号的波形占空比不能大于25/75。
所述时钟信号的波形占空比为25/75。
所述第一节点的信号输出波形呈“凸”字形。
所述时钟信号包含四组时钟信号：第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号，当所述时钟信号为第三时钟信号时，所述第M+2组时钟信号为第一时钟信号，当所述时钟信号为第四时钟信号时，所述第M+2组时钟信号为第二时钟信号。
本发明的有益效果：本发明提供了一种用于氧化物半导体薄膜晶体管 的扫描驱动电路，该用于氧化物半导体薄膜晶体管的扫描驱动电路的下拉维持电路部分具有主反相器与辅助反相器，引入一个恒压低电位，且设置恒压低电位<第二负电位<第一负电位，能够避免氧化物半导体薄膜晶体管电性对扫描驱动电路的影响，尤其是漏电问题带来的功能性不良，确保下拉维持电路部分能够在作用期间正常拉低，在非作用期间处于较高的电位，有效维持第一节点和输出端处于低电位。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明用于氧化物半导体薄膜晶体管的扫描驱动电路的第一实施例的电路图；
图2为图1所示第一实施例的第一级GOA单元的电路图；
图3为本发明用于氧化物半导体薄膜晶体管的扫描驱动电路的第二实施例的电路图；
图4为本发明用于氧化物半导体薄膜晶体管的扫描驱动电路的第三实施例的电路图；
图5为本发明用于氧化物半导体薄膜晶体管的扫描驱动电路的第四实施例的电路图；
图6为本发明用于氧化物半导体薄膜晶体管的扫描驱动电路的波形设置和关键节点的输出波形图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1-2，为本发明用于氧化物半导体薄膜晶体管的扫描驱动电路的第一实施例。如图1所示，所述用于氧化物半导体薄膜晶体管的扫描驱动电路为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)薄膜晶体管的扫描驱动电路，包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括一上拉控制部分100、一上拉部分200、一下传部分300、一第一下拉部分400、一自举电容部分500和一下拉维持电路部分600。
上述各部分的组成以及具体的连接方式如下：
所述上拉控制部分100包括第十一晶体管T11，所述第十一晶体管T11的栅极电性连接于所述第N级GOA单元的前一级GOA单元第N-1级GOA单元的驱动输出端ST(N-1)，漏级电性连接于所述第N级GOA单元的前一级GOA单元第N-1级GOA单元的输出端G(N-1)，源极电性连接于第一节点Q(N)；
所述上拉部分200包括第二十一晶体管T21，所述第二十一晶体管T21的栅极电性连接于第一节点Q(N)，漏极电性连接于时钟信号CK(M)，源极电性连接于输出端G(N)；
所述下传部分300包括第二十二晶体管T22，所述第二十二晶体管T22的栅极电性连接于第一节点Q(N)，漏极电性连接于时钟信号CK(M)，源极电性连接于驱动输出端ST(N)；
所述第一下拉部分400仅包括一第四十一晶体管T41，所述第四十一晶体管T41的栅极电性连接于第M+2组时钟信号CK(M+2)，漏极电性连接于第一节点Q(N)，源极电性连接于第二负电位VSS2；
所述自举电容部分500包括一电容Cb，所述电容Cb的一端电性连接于第一节点Q(N)，另一端电性连接于输出端G(N)；
所述下拉维持部分600包括第五十一晶体管T51，所述第五十一晶体管T51的栅极与漏极均电性连接于恒压高电位DCH，源极电性连接于第四节点S(N)；
第五十二晶体管T52，所述第五十二晶体管T52的栅极电性连接于第一节点Q(N)，漏极电性连接于第四节点S(N)，源极电性连接于第一负电位VSS1；
第五十三晶体管T53，所述第五十三晶体管T53的栅极电性连接于第四节点S(N)，漏极电性连接于恒压高电位DCH，源极电性连接于第二节点P(N)；
第五十四晶体管T54，所述第五十四晶体管T54的栅极电性连接于第一节点Q(N)，漏极电性连接于第二节点P(N)，源极电性连接第三节点K(N)；
第七十一晶体管T71，所述第七十一晶体管T71的栅极与漏极均电性连接于恒压高电位DCH，源极电性连接于第七十三晶体管T73的栅极；
第七十二晶体管T72，所述第七十二晶体管T72的栅极电性连接于第一节点Q(N)，漏极电性连接于第七十三晶体管T73的栅极，源极电性连接于恒压低电位DCL；
第七十三晶体管T73，所述第七十三晶体管T73的栅极电性连接于第七十一晶体管T71的源极，漏极电性连接于恒压高电位DCH，源极电性连 接于第三节点K(N)；
第七十四晶体管T74，所述第七十四晶体管T74的栅极电性连接于第一节点Q(N)，漏极电性连接于第三节点K(N)，源极电性连接于恒压低电位DCL；
第四十二晶体管T42，所述第四十二晶体管T42的栅极电性连接于第二节点P(N)，漏极电性连接于第一节点Q(N)，源极电性连接于第二负电位VSS2；
第三十二晶体管T32，所述第三十二晶体管T32的栅极电性连接于第二节点P(N)，漏极电性连接于输出端G(N)，源极电性连接于第一负电位VSS1。
需要特别说明的是，首先，所述第一负电位VSS1、第二负电位VSS2与恒压低电位DCL的关系为：恒压低电位DCL<第二负电位VSS2<第一负电位VSS1。
其次，该扫描驱动电路采用的级传方式是第N-1级传给第N级，如图2所示，所述扫描驱动电路的第一级连接关系中，第十一晶体管T11的栅极与漏极均电性连接于电路的启动信号端STV。
再次，第一下拉部分400只有第四十一晶体管T41负责下拉第一节点Q(N)，且第四十一晶体管T41的栅极电性连接于第M+2组时钟信号CK(M+2)，T41的源极电性连接于第二负电位VSS2。所述时钟信号CK(M)包含四组时钟信号：第一时钟信号CK(1)、第二时钟信号CK(2)、第三时钟信号CK(3)、第四时钟信号CK(4)，当所述时钟信号CK(M)为第三时钟信号CK(3)时，所述第M+2组时钟信号CK(M+2)为第一时钟信号CK(1)，当所述时钟信号CK(M)为第四时钟信号CK(4)时，所述第M+2组时钟信号CK(M+2)为第二时钟信号CK(2)，而且时钟信号CK(M)的波形占空比设置不能大于25/75，以确保第一节点Q(N)的信号输出波形呈“凸”字形，优选的，所述时钟信号CK(M)的波形占空比为25/75。
最为重要的是，所述下拉维持电路部分600采用了特殊的双重反相器设计。其中第五十一晶体管T51、第五十二晶体管T52、第五十三晶体管T53、第五十四晶体管T54四个晶体管构成主反相器，第七十一晶体管T71、第七十二晶体管T72、第七十三晶体管T73、第七十四晶体管T74四个晶体管构成辅助反相器。所述主反相器的作用是控制第三十二晶体管T32和第四十二晶体管T42这两个晶体管，辅助反相器的作用是在作用期间提供给主反相器低电位，在非作用期间提供给主反相器一个适当的高电位来降低第五十四晶体管T54的漏电，以确保主反相器在非作用期间能够产生较高 的电位。
在作用期间，辅助反相器经恒压高电位DCH与恒压低电位DCL的高/低电压驱动后，第五十二晶体管T52被下拉至第一负电位VSS1，第七十四晶体管T74、第七十二晶体管T72在第一节点Q(N)为高电位时开启并下拉恒压高电位DCH，导致第三节点K(N)为更低电位，第二节点P(N)也被下拉到一更低电位，即辅助反相器在作用期间给主反相器提供了低电位，因而可以杜绝第三十二晶体管T32、第四十二晶体管T42因阈值电压较低或趋近于0V的物理特性所引发的漏电情况发生，确保该下拉维持电路部分600能够在作用期间正常拉低。
在非作用期间，第五十二晶体管T52、第五十四晶体管T54、第七十二晶体管T72、第七十四晶体管T74均截止关闭。由于第五十四晶体管T54的栅极电性连接于第一节点Q(N)，源极电性连接于第三节点K(N)，该第五十四晶体管T54的栅极为负电位，源极为正电位，这样Vgs是一个相对来说非常负值的电位，可以将第五十四晶体管T54关闭得很好，减少它的漏电，即辅助反相器在非作用期间给主反相器提供了一个适当的高电位来降低第五十四晶体管T54的漏电，确保该下拉维持电路部分600在非作用期间处于较高的电位，有效维持第一节点Q(N)和输出端G(N)处于低电位。此外，在第三节点K(N)为高电位时，存在电阻分压的功能，可以将第二节点P(N)的电位推得更高，因而可以稳定第二节点P(N)的电位。
请参阅图3，为本发明用于氧化物半导体薄膜晶体管的扫描驱动电路的第二实施例。该第二实施例与第一实施例的区别在于，所述第四十一晶体管T41的源极电性连接于输出端G(N)，通过将第四十一晶体管T41的源极电性连接于输出端G(N)，可以降低第一节点Q(N)在作用期间通过该第四十一晶体管T41的漏电。除此之外，图3与图1具有相同标号部分的组成、连接关系、功用与操作原理相同，在此不再赘述。
请参阅图4，为本发明用于用于氧化物半导体薄膜晶体管的扫描驱动电路的第三实施例。所述第三实施例与第一实施例的区别在于，所述辅助反相器部分删减了第七十一晶体管T71与第七十二晶体管T72，将所述第七十三晶体管T73的栅极电性连接到第四节点S(N)，仅由第七十三晶体管T73与第七十四晶体管T74构成辅助反相器，该辅助反相器引用主反相器中的第四节点S(N)来控制第七十三晶体管T73，可以减少辅助反相器的元件数量，不需要额外的元件来产生类似于S(N)节点的波形控制第七十三晶体管T73。
在作用期间，辅助反相器经第四节点S(N)与恒压低电位DCL高/低电 压驱动后，第五十二晶体管T52被下拉至第一负电位VSS1，第七十四晶体管T74、在第一节点Q(N)为高电位时开启并下拉恒压高电位DCH，导致第三节点K(N)为更低电位，第二节点P(N)也被下拉到一更低电位，即辅助反相器在作用期间给主反相器提供了低电位，因而可以杜绝第三十二晶体管T32、第四十二晶体管T42因阈值电压较低或趋近于0V的物理特性所引发的漏电情况发生，确保所述下拉维持电路部分600能够在作用期间正常拉低。
在非作用期间，第五十二晶体管T52、第五十四晶体管T54、第七十四晶体管T74均截止关闭。由于第五十四晶体管T54的栅极电性连接于第一节点Q(N)，源极电性连接于第三节点K(N)，所述第五十四晶体管T54的栅极为负电位，源极为正电位，这样Vgs是一个相对来说非常负值的电位，可以将第五十四晶体管T54关闭得很好，减少它的漏电，即辅助反相器在非作用期间给主反相器提供了一个适当的高电位来降低第五十四晶体管T54的漏电，确保所述下拉维持电路部分600在非作用期间处于较高的电位，有效维持第一节点Q(N)和输出端G(N)处于低电位。此外，在第三节点K(N)为高电位时，还存在电阻分压的功能，可以将第二节点P(N)的电位推得更高，因而可以稳定第二节点P(N)的电位。除此之外，图4与图1中具有相同标号部分的组成、连接关系、功用与操作原理相同，在此不再赘述。
请参阅图5，为本发明用于氧化物半导体薄膜晶体管的扫描驱动电路的第四实施例。所述第四实施例与第三实施例的区别在于，所述第四十一晶体管T41的源极电性连接于输出端G(N)，通过将第四十一晶体管T41的源极电性连接于输出端G(N)，可以降低第一节点Q(N)在作用期间通过所述第四十一晶体管T41的漏电。除此之外，图5与图4中具有相同标号部分的组成、连接关系、功用与操作原理相同，在此不再赘述。
请参阅图6，为本发明用于氧化物半导体薄膜晶体管的扫描驱动电路的波形设置和关键节点的输出波形图。其中STV是电路的启动信号；CK(1)-CK(4)是电路的时钟信号，可以看出这里示意的时钟信号的波形占空比为25/75，可以确保第一节点的Q(N)的信号输出波形呈“凸”字形；VSS1、VSS2、DCH、DCL为输入的恒压控制信号，DCH为高电位，VSS1、VSS2、DCL均为恒压低电位，且DCL<VSS2<VSS1；其它为电路关键节点产生的输出信号波形。由图可知：第一节点Q(N)的信号输出波形呈“凸”字形，输出端G(N)正常输出；在非作用期间，第一节点Q(N)和输出端G(N)处于低电位。
综上所述，本发明用于氧化物半导体薄膜晶体管的扫描驱动电路的下 拉维持电路部分具有主反相器与辅助反相器，引入一个恒压低电位，且设置恒压低电位<第二负电位<第一负电位，能够避免氧化物半导体薄膜晶体管电性对扫描驱动电路的影响，尤其是漏电问题带来的功能性不良，确保下拉维持电路部分能够在作用期间正常拉低，在非作用期间处于较高的电位，有效维持第一节点和输出端处于低电位。
虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (13)

  1. 一种用于氧化物半导体薄膜晶体管的扫描驱动电路，包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括一上拉控制部分、一上拉部分、一下传部分、一第一下拉部分、一自举电容部分和一下拉维持电路部分；
    所述上拉控制部分包括一第十一晶体管，所述第十一晶体管的栅极电性连接于所述第N级GOA单元的前一级GOA单元第N-1级GOA单元的驱动输出端，漏极电性连接于所述第N级GOA单元的前一级GOA单元第N-1级GOA单元的输出端，源极电性连接于第一节点；
    所述第一下拉部分包括一第四十一晶体管，所述第四十一晶体管的栅极电性连接于第M+2组时钟信号，漏极电性连接于第一节点，源极电性连接于第二负电位或输出端；
    所述下拉维持电路部分包括第五十一晶体管，所述第五十一晶体管的栅极与漏极均电性连接于恒压高电位，源极电性连接于第四节点；第五十二晶体管，所述第五十二晶体管的栅极电性连接于第一节点，漏极电性连接于第四节点，源极电性连接于第一负电位；第五十三晶体管，所述第五十三晶体管的栅极电性连接于第四节点，漏极电性连接于恒压高电位，源极电性连接于第二节点；第五十四晶体管，所述第五十四晶体管的栅极电性连接于第一节点，漏极电性连接于第二节点，源极电性连接第三节点；第七十三晶体管，所述第七十三晶体管的栅极电性连接于第四节点，漏极电性连接于恒压高电位，源极电性连接于第三节点；第七十四晶体管，所述第七十四晶体管的栅极电性连接于第一节点，漏极电性连接于第三节点，源极电性连接于恒压低电位；第四十二晶体管，所述第四十二晶体管的栅极电性连接于第二节点，漏极电性连接于第一节点，源极电性连接于第二负电位；第三十二晶体管，所述第三十二晶体管的栅极电性连接于第二节点，漏极电性连接于输出端，源极电性连接于第一负电位；
    所述第五十一晶体管、第五十二晶体管、第五十三晶体管、第五十四晶体管构成主反相器，所述主反相器用于控制第三十二晶体管与第四十二晶体管；所述第七十三晶体管、第七十四晶体管构成辅助反相器，所述辅助反相器在作用期间提供给主反相器低电位，在非作用期间提供给主反相器高电位；
    所述第一负电位、第二负电位与恒压低电位的关系为：恒压低电位<第 二负电位<第一负电位。
  2. 如权利要求1所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述辅助反相器还包括第七十一晶体管，所述第七十一晶体管的栅极与漏极均电性连接于恒压高电位，源极电性连接于第七十三晶体管的栅极；第七十二晶体管，所述第七十二晶体管的栅极电性连接于第一节点，漏极电性连接于第七十三晶体管的栅极，源极电性连接于恒压低电位；所述第七十三晶体管的栅极与第四节点断开。
  3. 如权利要求1所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，采用的级传方式是第N-1级传给第N级。
  4. 如权利要求1所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述上拉部分包括第二十一晶体管，所述第二十一晶体管的栅极电性连接于第一节点，漏极电性连接于时钟信号，源极电性连接于输出端；
    所述下传部分包括第二十二晶体管，所述第二十二晶体管的栅极电性连接于第一节点，漏极电性连接于时钟信号，源极电性连接于驱动输出端；
    所述自举电容部分包括一电容，所述电容的一端电性连接于第一节点，另一端电性连接于输出端。
  5. 如权利要求1所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述扫描驱动电路的第一级连接关系中，第十一晶体管的栅极与漏极均电性连接于电路的启动信号端。
  6. 如权利要求4所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述时钟信号的波形占空比不能大于25/75。
  7. 如权利要求6所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述时钟信号的波形占空比为25/75。
  8. 如权利要求1所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述第一节点的信号输出波形呈“凸”字形。
  9. 如权利要求4所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述时钟信号包含四组时钟信号：第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号，当所述时钟信号为第三时钟信号时，所述第M+2组时钟信号为第一时钟信号，当所述时钟信号为第四时钟信号时，所述第M+2组时钟信号为第二时钟信号。
  10. 一种用于氧化物半导体薄膜晶体管的扫描驱动电路，包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括一上拉控制部分、一上拉部分、一下传部分、一第一下拉部分、一自举电容部分和一下拉维持电路部分；
    所述上拉控制部分包括一第十一晶体管，所述第十一晶体管的栅极电性连接于所述第N级GOA单元的前一级GOA单元第N-1级GOA单元的驱动输出端，漏极电性连接于所述第N级GOA单元的前一级GOA单元第N-1级GOA单元的输出端，源极电性连接于第一节点；
    所述第一下拉部分包括一第四十一晶体管，所述第四十一晶体管的栅极电性连接于第M+2组时钟信号，漏极电性连接于第一节点，源极电性连接于第二负电位或输出端；
    所述下拉维持电路部分包括第五十一晶体管，所述第五十一晶体管的栅极与漏极均电性连接于恒压高电位，源极电性连接于第四节点；第五十二晶体管，所述第五十二晶体管的栅极电性连接于第一节点，漏极电性连接于第四节点，源极电性连接于第一负电位；第五十三晶体管，所述第五十三晶体管的栅极电性连接于第四节点，漏极电性连接于恒压高电位，源极电性连接于第二节点；第五十四晶体管，所述第五十四晶体管的栅极电性连接于第一节点，漏极电性连接于第二节点，源极电性连接第三节点；第七十三晶体管，所述第七十三晶体管的栅极电性连接于第四节点，漏极电性连接于恒压高电位，源极电性连接于第三节点；第七十四晶体管，所述第七十四晶体管的栅极电性连接于第一节点，漏极电性连接于第三节点，源极电性连接于恒压低电位；第四十二晶体管，所述第四十二晶体管的栅极电性连接于第二节点，漏极电性连接于第一节点，源极电性连接于第二负电位；第三十二晶体管，所述第三十二晶体管的栅极电性连接于第二节点，漏极电性连接于输出端，源极电性连接于第一负电位；
    所述第五十一晶体管、第五十二晶体管、第五十三晶体管、第五十四晶体管构成主反相器，所述主反相器用于控制第三十二晶体管与第四十二晶体管；所述第七十三晶体管、第七十四晶体管构成辅助反相器，所述辅助反相器在作用期间提供给主反相器低电位，在非作用期间提供给主反相器高电位；
    所述第一负电位、第二负电位与恒压低电位的关系为：恒压低电位<第二负电位<第一负电位；
    其中，所述上拉部分包括第二十一晶体管，所述第二十一晶体管的栅极电性连接于第一节点，漏极电性连接于时钟信号，源极电性连接于输出端；
    所述下传部分包括第二十二晶体管，所述第二十二晶体管的栅极电性连接于第一节点，漏极电性连接于时钟信号，源极电性连接于驱动输出端；
    所述自举电容部分包括一电容，所述电容的一端电性连接于第一节点， 另一端电性连接于输出端；
    其中，所述时钟信号的波形占空比不能大于25/75；
    其中，所述时钟信号的波形占空比为25/75；
    其中，所述第一节点的信号输出波形呈“凸”字形。
  11. 如权利要求10所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，采用的级传方式是第N-1级传给第N级。
  12. 如权利要求10所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述扫描驱动电路的第一级连接关系中，第十一晶体管的栅极与漏极均电性连接于电路的启动信号端。
  13. 如权利要求10所述的用于氧化物半导体薄膜晶体管的扫描驱动电路，其中，所述时钟信号包含四组时钟信号：第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号，当所述时钟信号为第三时钟信号时，所述第M+2组时钟信号为第一时钟信号，当所述时钟信号为第四时钟信号时，所述第M+2组时钟信号为第二时钟信号。
PCT/CN2015/072361 2014-11-07 2015-02-06 用于氧化物半导体薄膜晶体管的扫描驱动电路 Ceased WO2016070516A1 (zh)

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GB1703826.6A GB2544933B (en) 2014-11-07 2015-02-06 Scan driving circuit for oxide semiconductor thin film transistors
US14/424,383 US9548036B2 (en) 2014-11-07 2015-02-06 Scan driving circuit for oxide semiconductor thin film transistors
KR1020177007048A KR101943236B1 (ko) 2014-11-07 2015-02-06 산화물 반도체 박막 트랜지스터용 스캔 구동회로
JP2017519235A JP6334060B2 (ja) 2014-11-07 2015-02-06 酸化物半導体薄膜トランジスタにおけるスキャン駆動回路

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KR20170042353A (ko) 2017-04-18
US9767754B2 (en) 2017-09-19
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