WO2016070513A1 - 低温多晶硅薄膜晶体管goa电路 - Google Patents

低温多晶硅薄膜晶体管goa电路 Download PDF

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Publication number
WO2016070513A1
WO2016070513A1 PCT/CN2015/072358 CN2015072358W WO2016070513A1 WO 2016070513 A1 WO2016070513 A1 WO 2016070513A1 CN 2015072358 W CN2015072358 W CN 2015072358W WO 2016070513 A1 WO2016070513 A1 WO 2016070513A1
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Prior art keywords
type transistor
electrically connected
source
drain
gate
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PCT/CN2015/072358
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English (en)
French (fr)
Inventor
肖军城
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to KR1020177007297A priority Critical patent/KR101933327B1/ko
Priority to GB1703671.6A priority patent/GB2546648B/en
Priority to US14/422,700 priority patent/US9728147B2/en
Priority to JP2017522806A priority patent/JP6440225B2/ja
Publication of WO2016070513A1 publication Critical patent/WO2016070513A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a low temperature polysilicon thin film transistor GOA circuit.
  • GOA Gate Drive On Array
  • TFT thin film transistor
  • Array liquid crystal display array
  • the GOA circuit is mainly composed of a pull-up part, a pull-up control part, a transfer part, a pull-down part, and a pull-down sustain circuit part (
  • the pull-down holding part and the boost part responsible for the potential rise are generally composed of a bootstrap capacitor.
  • the pull-up portion is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
  • the pull-up control part is mainly responsible for controlling the opening of the pull-up part, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down portion is mainly responsible for quickly pulling the scan signal (that is, the potential of the gate of the thin film transistor) to a low level after outputting the scan signal.
  • the pull-down sustain circuit portion is mainly responsible for keeping the scan signal and the signal of the pull-up portion in a closed state (ie, a set negative potential).
  • the rising portion is mainly responsible for the secondary rise of the potential of the pull-up portion to ensure the normal output of the pull-up portion.
  • LTPS-TFT liquid crystal displays have attracted more and more attention.
  • LTPS-TFT liquid crystal displays have high resolution and response. Fast speed, high brightness, high aperture ratio, etc.
  • the low temperature polysilicon has an order of arrangement of amorphous silicon (a-Si)
  • the low temperature polysilicon semiconductor itself has an ultrahigh electron mobility, which is 100 times higher than that of an amorphous silicon semiconductor.
  • the gate driver can be fabricated on the thin film transistor array substrate by using GOA technology to achieve the goal of system integration, space saving and cost of driving the IC.
  • a single type (single N-type or single P-type) GOA circuit has a complicated structure, poor circuit characteristics, and particularly a problem of large power consumption, especially in small and medium sizes, and power consumption becomes An important indicator of its performance research, therefore, how to effectively reduce power consumption, while enhancing the overall stability of circuit structure and performance has become an important issue in the current low temperature polysilicon semiconductor thin film transistor GOA circuit.
  • the object of the present invention is to provide a low-temperature polysilicon semiconductor thin film transistor GOA circuit, which can solve the problem that the device circuit stability of the LTPS single TFT is poor and the power consumption is large; and solve the problem of current TFT leakage of a single type GOA circuit, and optimize The performance of the circuit; and can be designed with ultra-narrow bezel or borderless.
  • the present invention provides a low temperature polysilicon semiconductor thin film transistor GOA circuit for forward and reverse bidirectional scan transmission, including a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth stage GOA unit uses multiple An N-type transistor and a plurality of P-type transistors, the N-th stage GOA unit comprising: a transmission portion, a transmission control portion, a data storage portion, a data clearing portion, an output control portion, and an output buffer portion;
  • the transmission portion is electrically connected to the first low frequency signal, the second low frequency signal, the driving output end of the N-1th GOA unit of the previous stage of the Nth stage GOA unit, and the rear of the Nth stage GOA unit a driving output end of the first N+1th GOA unit and the data storage part;
  • the transmission control part is electrically connected to a driving output of the N+1th GOA unit of the subsequent stage of the Nth stage GOA unit a driving output terminal of the N-1th GOA unit of the previous stage of the Nth stage GOA unit, a timing signal of the M-2th stage, a power supply high potential, a power supply low potential, and a data storage part;
  • the data storage part Electrically connected to the transmission part, the transmission control part, the power supply high potential and the power supply low potential;
  • the data clearing part is electrically connected to the data storage part, the output control part, the data clearing part, the power supply high potential and the reset signal
  • the output control portion is electrically connected to the data clearing portion, the output buffer
  • the potentials of the first low frequency signal and the second low frequency signal are switched with forward and reverse scanning.
  • the first low frequency signal is equivalent to a DC high potential
  • the second low frequency signal is equivalent to a DC low potential
  • the first low frequency signal corresponds to a DC low potential
  • the second low frequency signal corresponds to a DC high potential
  • the transmission part includes:
  • the gate of the first P-type transistor is electrically connected to the second low-frequency signal, and the source is electrically connected to the first-stage N-1th GOA unit of the N-th stage GOA unit a driving output end, the drain is electrically connected to the first node;
  • the gate of the second N-type transistor is electrically connected to the first low-frequency signal, and the source is electrically connected to the first-stage N-1th GOA unit of the N-th stage GOA unit a driving output end, the drain is electrically connected to the first node;
  • the gate of the third P-type transistor is electrically connected to the first low frequency signal, and the source is electrically connected to the N+1th GOA unit of the subsequent stage of the Nth stage GOA unit a driving output end, the drain is electrically connected to the second node;
  • the gate of the fourth N-type transistor is electrically connected to the second low-frequency signal, and the source is electrically connected to the N+1th GOA unit of the subsequent stage of the N-th stage GOA unit a driving output end, the drain is electrically connected to the second node;
  • the transmission control portion includes:
  • the gate of the fifth P-type transistor is electrically connected to a driving output end of the N-1th GOA unit of the previous stage of the Nth stage GOA unit, and the source is electrically connected The power source is high, and the drain is electrically connected to the source of the sixth P-type transistor;
  • the gate of the sixth P-type transistor is electrically connected to a driving output end of the N+1th GOA unit of the subsequent stage of the Nth stage GOA unit, and the source is electrically connected a drain of the fifth P-type transistor, the drain is electrically connected to the source of the seventh N-type transistor;
  • the gate of the seventh N-type transistor is electrically connected to a driving output end of the N-1th GOA unit of the previous stage of the Nth stage GOA unit, and the source is electrically connected a drain of the sixth P-type transistor, the drain is electrically connected to the low potential of the power source;
  • An eighth N-type transistor the gate of the eighth N-type transistor is electrically connected to a driving output end of the N+1th GOA unit of the subsequent stage of the Nth stage GOA unit, and the source is electrically connected a drain of the sixth P-type transistor, the drain is electrically connected to the low potential of the power source;
  • the gate of the ninth P-type transistor is electrically connected to the drain of the sixth P-type transistor, the source is electrically connected to the high potential of the power source, and the drain is electrically connected to the tenth N-type The source of the transistor;
  • the gate of the tenth N-type transistor is electrically connected to the drain of the sixth P-type transistor, the source is electrically connected to the drain of the ninth P-type transistor, and the drain is electrically connected At low power supply;
  • An eleventh P-type transistor the gate of the eleventh P-type transistor is electrically connected to the drain of the sixth P-type transistor, and the source is electrically connected to the source and drain of the twelfth N-type transistor Electrically connected to the M-2th timing signal;
  • the gate of the twelfth N-type transistor is electrically connected to the drain of the ninth P-type transistor, and the source is electrically connected to the source and drain of the eleventh P-type transistor Electrically connected to the M-2th timing signal;
  • the data storage part includes:
  • the gate of the thirteenth N-type transistor is electrically connected to the source of the eleventh P-type transistor, and the source is electrically connected to the drain of the fourteenth P-type transistor, and the drain Extreme electricity sexually connected to the power supply low potential;
  • the gate of the fourteenth P-type transistor is electrically connected to the source of the eleventh P-type transistor, the source is electrically connected to the power supply high potential, and the drain is electrically connected to the first The source of the thirteen N-type transistor;
  • the gate of the fifteenth P-type transistor is electrically connected to the source of the thirteenth N-type transistor, the source is electrically connected to the high potential of the power source, and the drain is electrically connected to the first The source of a sixteen P-type transistor;
  • the gate of the sixteenth P-type transistor is electrically connected to the first node, the source is electrically connected to the drain of the fifteenth P-type transistor, and the drain is electrically connected to the first The source of the seventeen N-type transistor;
  • the gate of the seventeenth N-type transistor is electrically connected to the first node, the source is electrically connected to the drain of the sixteenth P-type transistor, and the drain is electrically connected to the first The source of the eighteen N-type transistor;
  • An eighteenth N-type transistor the gate of the eighteenth N-type transistor is electrically connected to the source of the eleventh P-type transistor, and the source is electrically connected to the drain of the seventeenth N-type transistor, and the drain Very electrically connected to the low potential of the power supply;
  • the gate of the nineteenth P-type transistor is electrically connected to the gate of the thirteenth N-type transistor, the source is electrically connected to the power supply high potential, and the drain is electrically connected to the first The source of the twenty P-type transistor;
  • a twentieth P-type transistor the gate of the twentieth P-type transistor is electrically connected to the second node, the source is electrically connected to the drain of the nineteenth P-type transistor, and the drain is electrically connected to the first The source of the twenty-one N-type transistor;
  • the gate of the twenty-first N-type transistor is electrically connected to the second node, the source is electrically connected to the drain of the twentieth P-type transistor, and the drain is electrically connected a source of the twenty-second N-type transistor;
  • the gate of the twenty-second N-type transistor is electrically connected to the source of the thirteenth N-type transistor, and the source is electrically connected to the drain of the twenty-first N-type transistor The drain is electrically connected to the low potential of the power source;
  • the data clearing part includes:
  • the gate of the twenty-third P-type transistor is electrically connected to the reset signal terminal, the source is electrically connected to the power supply high potential, and the drain is electrically connected to the sixteenth P-type a drain of the transistor and a drain of the twentieth P-type transistor;
  • the output control portion (500) includes
  • the gate of the twenty-fourth P-type transistor is electrically connected to a drain of the sixteenth P-type transistor and a drain of the twentieth P-type transistor, the source is electrically connected to the power supply high potential, and the drain is electrically connected to the driving output end;
  • the gate of the twenty-fifth N-type transistor is electrically connected to the drain of the sixteenth P-type transistor and the drain of the twentieth P-type transistor, and the source is electrically connected At the driving output end, the drain is electrically connected to the low potential of the power source;
  • the gate of the second sixteen P-type transistor is electrically connected to the driving output end, the source is electrically connected to the high potential of the power source, and the drain is electrically connected to the twenty-ninth N The source of the transistor;
  • the gate of the twenty-seventh N-type transistor is electrically connected to the driving output end, and the source is electrically connected to the drain of the twenty-ninth N-type transistor, and the drain is electrically Connected to the low potential of the power supply;
  • the gate of the twenty-eighth P-type transistor is electrically connected to the timing signal, the source is electrically connected to the power supply high potential, and the drain is electrically connected to the twenty-ninth N-type The source of the transistor;
  • the gate of the twenty-ninth N-type transistor is electrically connected to the timing signal, and the source is electrically connected to the drain of the twenty-sixth N-type transistor, and the drain is electrically connected The source of the twenty-seventh N-type transistor;
  • the output buffer portion includes:
  • the gate of the thirtieth P-type transistor is electrically connected to the source of the twenty-ninth N-type transistor, the source is electrically connected to the high potential of the power source, and the drain is electrically connected to the drain The source of the thirty-first N-type transistor;
  • the gate of the 31st N-type transistor is electrically connected to the source of the ninth N-type transistor, and the source is electrically connected to the drain of the thirtieth P-type transistor The drain is electrically connected to the low potential of the power source;
  • the gate of the thirty-second P-type transistor is electrically connected to the drain of the thirtieth P-type transistor, the source is electrically connected to the power supply high potential, and the drain is electrically connected The source of the thirty-third N-type transistor;
  • the gate of the thirty-third N-type transistor is electrically connected to the drain of the thirtieth P-type transistor, and the source is electrically connected to the drain of the thirty-second P-type transistor The drain is electrically connected to the low potential of the power source;
  • the gate of the thirty-fourth P-type transistor is electrically connected to the drain of the thirty-second P-type transistor, and the source is electrically connected to the high potential of the power source, and the drain is electrically Connected to the output;
  • the gate of the thirty-fifth N-type transistor is electrically connected to The drain of the thirty-second P-type transistor is electrically connected to the output end, and the drain is electrically connected to the low potential of the power supply.
  • the GOA circuit further includes a second output control portion and a second output buffer portion;
  • the second output control portion is electrically connected to the output control portion, the driving output terminal, the M+1th timing signal, the power supply high potential and the power supply low potential;
  • the second output buffer portion is electrically connected to the second Output control part, output end of the N+1th GOA unit, power supply high potential and power supply low potential;
  • the second output control portion includes:
  • the gate of the thirty-six P-type transistor is electrically connected to the driving output end, the source is electrically connected to the power supply high potential, and the drain is electrically connected to the thirty-ninth N The source of the transistor;
  • the gate of the thirty-seventh N-type transistor is electrically connected to the driving output end, and the source is electrically connected to the drain of the thirty-ninth N-type transistor, and the drain is electrically Connected to the low potential of the power supply;
  • the gate of the thirty-eighth P-type transistor is electrically connected to the M+1th timing signal, the source is electrically connected to the power supply high potential, and the drain is electrically connected to the first The source of the thirty-nine N-type transistor;
  • the gate of the thirty-ninth N-type transistor is electrically connected to the M+1th timing signal, and the source is electrically connected to the drain of the thirty-sixth P-type transistor.
  • the drain is electrically connected to the source of the thirty-seventh N-type transistor;
  • the second output buffering portion includes:
  • the gate of the fortieth P-type transistor is electrically connected to the source of the thirty-ninth N-type transistor, the source is electrically connected to the high potential of the power source, and the drain is electrically connected to the drain The source of the forty-first N-type transistor;
  • the gate of the forty-first N-type transistor is electrically connected to the source of the thirty-ninth N-type transistor, and the source is electrically connected to the drain of the fortieth P-type transistor The drain is electrically connected to the low potential of the power source;
  • the gate of the forty-second P-type transistor is electrically connected to the drain of the fortieth P-type transistor, the source is electrically connected to the power supply high potential, and the drain is electrically connected The source of the forty-third N-type transistor;
  • the gate of the forty-third N-type transistor is electrically connected to the drain of the fortieth P-type transistor, and the source is electrically connected to the drain of the forty-second P-type transistor The drain is electrically connected to the low potential of the power source;
  • the gate of the forty-fourth P-type transistor is electrically connected to a drain of the forty-two P-type transistor, the source is electrically connected to the high potential of the power source, and the drain is electrically connected to the output end of the N+1th GOA unit;
  • the gate of the forty-fifth N-type transistor is electrically connected to the drain of the forty-second P-type transistor, and the source is electrically connected to the N+1th GOA unit At the output end, the drain is electrically connected to the low potential of the power supply.
  • a source of the first P-type transistor, a source of the second N-type transistor, a gate of the fifth P-type transistor, and a gate of the seventh N-type transistor are both Electrically connected to the start signal end of the circuit.
  • the source of the third P-type transistor, the source of the fourth N-type transistor, the gate of the sixth P-type transistor, and the gate of the eighth N-type transistor are both Electrically connected to the start signal end of the circuit.
  • the first P-type transistor and the second N-type transistor in the transmitting portion form a forward transfer gate for forwardly transmitting the driving output signal of the N-1th GOA unit to the data storage portion;
  • the third P-type transistor And the fourth N-type transistor constitutes a reverse transfer gate for transmitting the driving output signal of the (N+1)th stage GOA unit to the data storage portion.
  • the fifth P-type transistor, the sixth P-type transistor, the seventh N-type transistor, and the eighth N-type transistor form a NAND gate logic unit in the transmission control portion;
  • the ninth P-type transistor and the tenth N-type transistor form an inversion
  • the eleventh P-type transistor and the twelfth N-type transistor constitute a transfer gate;
  • the transfer control portion is configured to control the M-2th timing signal and transmit it to the data storage portion.
  • the fifteenth P-type transistor, the sixteenth P-type transistor, the seventeenth N-type transistor, and the eighteenth N-type transistor constitute a forward timing inverter in the data storage portion;
  • the nineteenth P-type transistor and the second a ten-P transistor, a twenty-first N-type transistor, and a twenty-second N-type transistor constitute a reverse timing inverter;
  • a thirteenth N-type transistor and a fourteenth P-type transistor constitute an inverter;
  • the data clearing portion is used to timely clear the potential of the drive output of the circuit.
  • a twenty-six P-type transistor, a twenty-seventh N-type transistor, a twenty-eighth P-type transistor, and a twenty-ninth N-type transistor in the output control portion constitute a NAND gate logic unit;
  • the transistor and the twenty-fifth N-type transistor constitute an inverter;
  • the output control portion is configured to control the scan signal outputted by the output terminal, and output a scan signal that conforms to the timing.
  • the transistors form three inverters for adjusting the timing-adjusted scan signals. Integral, while enhancing the load capacity.
  • a third hexadecimal P-type transistor, a thirty-seventh N-type transistor, a thirty-eighth P-type transistor, and a thirty-ninth N-type transistor in the second output control portion constitute a NAND gate logic unit, for The scan signal outputted from the output end of the N+1 stage GOA unit is controlled to output a timing-aligned scan signal;
  • the fourth output buffer portion is a fortieth P-type transistor and a forty-first N-type transistor, and the forty-second
  • the P-type transistor and the forty-third N-type transistor, the forty-fourth P-type transistor, and the forty-fifth N-type transistor respectively constitute three inverters for adjusting the timing-adjusted scan signal while enhancing the band Load capacity;
  • the second output control portion and the second output buffer portion are outputted by the output end of the N+1th GOA unit according to the output signal of the driving output terminal and the M+1th timing signal, thereby realizing
  • the timing signal includes four sets of timing signals: a first timing signal, a second timing signal, a third timing signal, and a fourth timing signal.
  • the timing signal is a first timing signal
  • the M-2th timing The signal is a third timing signal.
  • the timing signal is a second timing signal
  • the M-2th timing signal is a fourth timing signal
  • the M+ The level 1 timing signal is the first timing signal.
  • the present invention provides a low temperature polysilicon semiconductor thin film transistor GOA circuit for forward and reverse bidirectional scanning transmission, and the Nth stage GOA unit employs a plurality of N-type transistors and a plurality of P-type transistors, including a transmission portion, A transmission control section, a data storage section, a data clearing section, an output control section, and an output buffer section.
  • the transmission portion has a transfer gate; the transfer control portion has a NOR gate logic unit, an inverter, and a transfer gate; the data storage portion has a timing inverter and an inverter; and the output control portion has a non-gate logic unit, an inverter; the output buffer portion has an inverter; a transmission gate is used to transmit signals to the upper and lower stages, and a signal is converted by a NOR gate logic unit and a NAND gate logic unit, and a timing inverter is used.
  • the inverter stores and transmits the signal, which solves the problem that the device circuit stability of the LTPS single TFT is poor, the power consumption is large, and the TFT leakage of the single type GOA circuit is optimized, and the performance of the circuit is optimized;
  • the second output control portion and the second output buffer portion realize a common drive output end, so that the single-stage GOA unit controls the forward and reverse bidirectional scan output of the two-stage circuit, thereby reducing the number of TFTs and realizing an ultra-narrow bezel or a borderless design.
  • FIG. 1 is a circuit diagram of a first embodiment of a low temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention
  • FIG. 2 is a circuit diagram showing a first-stage connection relationship of a first embodiment of a low-temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention
  • FIG. 3 is a circuit diagram showing the final connection relationship of the first embodiment of the low temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention
  • FIG. 4 is a circuit diagram of a second embodiment of a low temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention.
  • FIG. 5 is a waveform diagram of key nodes of a low-temperature polysilicon semiconductor thin film transistor GOA circuit in forward scanning
  • FIG. 6 is a diagram showing output waveforms of key nodes in a reverse scan of a low temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention.
  • FIG. 1 is a circuit diagram of a first embodiment of the present invention.
  • the present invention provides a low temperature polysilicon thin film transistor GOA circuit for forward and reverse bidirectional scan transmission, including a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth stage GOA unit adopts multiple An N-type transistor and a plurality of P-type transistors, the N-th stage GOA unit includes: a transmission portion 100, a transmission control portion 200, a data storage portion 300, a data clearing portion 400, an output control portion 500, and an output buffer portion 600;
  • the transmission portion 100 is electrically connected to the first low frequency signal UD, the second low frequency signal DU, the driving output terminal ST(N-1) of the N-1th GOA unit of the previous stage of the Nth stage GOA unit, a driving output terminal ST(N+1) of the N+1th GOA unit of the subsequent stage of the Nth stage GOA unit and the data storage portion 300;
  • the transmission control portion 200 is electrically connected to the Nth Drive output terminal ST(N+1) of the N+1th GOA unit of the subsequent stage of the GOA unit, and drive output ST of the N-1th GOA unit of the previous stage of the Nth GOA unit -1), the M-2th timing signal CK (M-2), the power supply high potential H, the power supply low potential L and the data storage portion 300;
  • the data storage portion 300 is electrically connected to the transmission portion 100, and transmits
  • the data clearing part 400 is electrically connected to the data storage part 300
  • the potentials of the first low frequency signal UD and the second low frequency signal DU are switched with forward and backward scanning.
  • the first low frequency signal UD is equivalent to a DC high potential
  • the second low frequency signal DU is equivalent to The DC low potential
  • the first low frequency signal UD corresponds to a DC low potential
  • the second low frequency signal DU corresponds to a DC high potential.
  • the transmitting portion 100 includes a first P-type transistor T1, the gate of the first P-type transistor T1 is electrically connected to the second low-frequency signal DU, and the source is electrically connected to the front of the N-th stage GOA unit.
  • a driving output terminal ST(N-1) of the first-stage N-1th GOA unit, the drain is electrically connected to the first node P(N);
  • the gate is electrically connected to the first low frequency signal UD
  • the source is electrically connected to the driving output terminal ST(N-1) of the N-1th GOA unit of the previous stage of the Nth stage GOA unit, and the drain Electrically connected to the first node P (N);
  • a third P-type transistor T3, the gate of the third P-type transistor T3 is electrically connected to the first low-frequency signal UD, and the source is electrically connected to the first a driving output terminal ST(N+1) of the N+1th GOA unit of the subsequent
  • the first P-type transistor T1 and the second N-type transistor T2 form a forward transfer gate.
  • the forward transfer gate operates to forward the drive output signal ST(N-1) of the N-1th stage GOA unit to the data storage portion 300;
  • the third P-type transistor T3 Forming a reverse transfer gate with the fourth N-type transistor T4, when the first low frequency signal UD is equivalent to a DC low potential, and the second low frequency signal DU is equivalent to a DC high potential, when the reverse scan is performed, the reverse The operation is performed to the transfer gate for inversely transmitting the drive output signal ST(N+1) of the (N+1)th stage GOA unit to the material storage portion 300.
  • the transmission control portion 200 includes a fifth P-type transistor T5, and the gate of the fifth P-type transistor T5 is electrically connected to the driving of the N-1th GOA unit of the previous stage of the Nth stage GOA unit.
  • the output terminal ST(N-1) has a source electrically connected to the power supply high potential H, a drain electrically connected to the source of the sixth P-type transistor T6, and a sixth P-type transistor T6, the sixth P-type
  • the gate of the transistor T6 is electrically connected to the driving output terminal ST(N+1) of the N+1th GOA unit of the subsequent stage of the Nth stage GOA unit, and the source is electrically connected to the fifth P-type transistor T5.
  • a drain a drain electrically connected to the source of the seventh N-type transistor T7; a seventh N-type transistor T7, the gate of the seventh N-type transistor T7 is electrically connected to the Nth-level GOA unit
  • the first level of the N-1 a driving output terminal ST(N-1) of the GOA unit, the source is electrically connected to the drain of the sixth P-type transistor T6, and the drain is electrically connected to the power supply low potential L;
  • an eighth N-type transistor T8 The gate of the eighth N-type transistor T8 is electrically connected to the driving output terminal ST(N+1) of the N+1th GOA unit of the subsequent stage of the Nth stage GOA unit, and the source is electrically connected to the sixth
  • the drain of the P-type transistor T6 is electrically connected to the power supply low potential L; a ninth P-type transistor T9, the gate of the ninth P-type transistor T9 is electrically connected to the drain of the sixth P-type transistor T6.
  • a pole a source electrically connected to the power supply high potential H, a drain electrically connected to the source of the tenth N-type transistor T10; a tenth N-type transistor T10, the gate electrical property of the tenth N-type transistor T10 Connected to the drain of the sixth P-type transistor T6, the source is electrically connected to the drain of the ninth P-type transistor T9, and the drain is electrically connected to the power supply low potential L; an eleventh P-type transistor T11, The gate of the eleventh P-type transistor T11 is electrically connected to the drain of the sixth P-type transistor T6, the source is electrically connected to the source of the twelfth N-type transistor T12, and the drain is electrically connected to the M-th 2 a timing signal CK (M-2); a twelfth N-type transistor T12, the gate of the twelfth N-type transistor T12 is electrically connected to the drain of the ninth P-type transistor T9, and the source is electrically connected The drain of
  • the fifth P-type transistor T5, the sixth P-type transistor T6, the seventh N-type transistor T7, and the eighth N-type transistor T8 constitute a NAND gate logic unit; the ninth P-type transistor T9, the tenth N-type The transistor T10 constitutes an inverter; the eleventh P-type transistor (T11) and the twelfth N-type transistor (T12) constitute a transmission gate; and the transmission control portion 200 is for controlling the M-2th timing signal CK ( M-2) is transmitted to the material storage section 300.
  • the data storage portion 300 includes a thirteenth N-type transistor T13.
  • the gate of the thirteenth N-type transistor T13 is electrically connected to the source of the eleventh P-type transistor T11, and the source is electrically connected to the first
  • the drain of the fourteen P-type transistor T14 is electrically connected to the power supply low potential L; a fourteenth P-type transistor T14, and the gate of the fourteenth P-type transistor T14 is electrically connected to the eleventh P
  • the source of the transistor T11 is electrically connected to the power supply high potential H, and the drain is electrically connected to the source of the thirteenth N-type transistor T13; a fifteenth P-type transistor T15, the fifteenth P
  • the gate of the transistor T15 is electrically connected to the source of the thirteenth N-type transistor T13, the source is electrically connected to the power supply high potential H, and the drain is electrically connected to the source of the sixteenth P-type transistor T16;
  • a source of T20 a twentieth P-type transistor T20, the gate of the twentieth P-type transistor T20 is electrically connected to the first node Q(N), and the source is electrically connected to the nineteenth P-type transistor a drain of the T19, the drain is electrically connected to the source of the 21st N-type transistor T21; a 21st N-type transistor T21, the gate of the 21st N-type transistor T21 is electrically connected to a first node Q(N), the source is electrically connected to the drain of the twentieth P-type transistor T20, and the drain is electrically connected to the source of the twenty-second N-type transistor T22;
  • the transistor T22, the gate of the twenty-second N-type transistor T22 is electrically connected to the source of the thirteenth N-type transistor T13, and the source is electrically connected to the drain of the twenty-first N-type transistor T21.
  • a pole the drain is electrically connected to the power source low potential L;
  • the fifteenth P-type transistor T15, the sixteenth P-type transistor T16, the seventeenth N-type transistor T17, and the eighteenth N-type transistor T18 form a forward timing inverter, and the forward timing is inverted.
  • the device is electrically connected to the forward transfer gate in the transmitting portion 100; the nineteenth P-type transistor T19, the twentieth P-type transistor T20, the twenty-first N-type transistor T21, and the twenty-second N-type transistor T22 Forming a reverse timing inverter, the reverse timing inverter is electrically connected to the reverse transmission gate in the transmission portion 100; the thirteenth N-type transistor T13 and the fourteenth P-type transistor T14 form a reverse
  • the data storage portion 300 is configured to drive the output terminal ST(N-1) of the N-1th GOA unit and the M-2th timing signal CK(M-2) during forward scanning.
  • the incoming signal is stored and transmitted; in the reverse scan, the data storage portion 300 is used to drive the output terminal ST(N+1) and the M-2th timing signal CK by the (N+1)th GOA unit. (M-2) The incoming signal is stored and transmitted.
  • the data clearing portion 400 includes a second thirteen P-type transistor T23.
  • the gate of the twenty-third P-type transistor T23 is electrically connected to the reset signal terminal Reset, and the source is electrically connected to the power supply high potential H.
  • the drain is electrically connected to the drain of the sixteenth P-type transistor T16 and the drain of the twentieth P-type transistor T20; the data clearing portion 400 is for timely clearing the potential of the driving output terminal ST(N) of the circuit Mainly at the beginning of each frame, the reset signal terminal Reset receives a pulse reset signal, and discharges the drive output terminal ST(N), thereby clearing the potential of the drive output terminal ST(N).
  • the output control portion 500 includes a second fourteen P-type transistor T24, and the gate of the twenty-fourth P-type transistor T24 is electrically connected to the drain of the sixteenth P-type transistor T16 and the twentieth P-type a drain of the transistor T20, the source is electrically connected to the power supply high potential H, the drain is electrically connected to the driving output terminal ST(N); a twenty-fifth N-type transistor T25, the twenty-fifth N-type crystal The gate of the body tube T25 is electrically connected to the drain of the sixteenth P-type transistor T16 and the drain of the twentieth P-type transistor T20, and the source is electrically connected to the driving output terminal ST(N), and the drain is electrically Connected to the power supply low potential L; a twenty-six P-type transistor T26, the gate of the twenty-six P-type transistor T26 is electrically connected to the driving output terminal ST (N), the source is electrically connected to the power supply high The potential H, the drain is electrically connected to the ninth
  • the second sixteen P-type transistor T26, the twenty-seventh N-type transistor T27, the twenty-eighth P-type transistor T28, and the twenty-ninth N-type transistor T29 form a NAND gate logic unit;
  • the four P-type transistor T24 and the twenty-fifth N-type transistor T25 constitute an inverter; the output control portion 500 is configured to control the scan signal outputted from the output terminal G(N) to output a scan signal conforming to the timing.
  • the output buffer portion 600 includes a thirtieth P-type transistor T30.
  • the gate of the thirtieth P-type transistor T30 is electrically connected to the source of the twenty-ninth N-type transistor T29, and the source is electrically connected to the source.
  • the power supply high potential H the drain is electrically connected to the source of the 31st N-type transistor T31; a 31st N-type transistor T31, the gate of the 31st N-type transistor T31 is electrically connected to a source of the twenty-ninth N-type transistor T29, the source is electrically connected to the drain of the thirtieth P-type transistor T30, the drain is electrically connected to the power supply low potential L; a thirty-second P-type transistor T32, The gate of the thirty-second P-type transistor T32 is electrically connected to the drain of the thirtieth P-type transistor T30, the source is electrically connected to the power supply high potential H, and the drain is electrically connected to the thirty-third N The source of the transistor T33; a thirty-third N-type transistor T33, the gate of the thirty-third N-type transistor T33 is electrically connected to the drain of the thirtieth P-type transistor T30, and the source is electrically connected The drain of the thirty-two P-type transistor T
  • the five N-type transistors T35 respectively constitute three inverters; they are used to adjust the timing-adjusted scan signals while enhancing the load carrying capability.
  • the source of the first P-type transistor T1, the source of the second N-type transistor T2, and the fifth P The gate of the transistor T5 and the gate of the seventh N-type transistor T7 are electrically connected to the start signal terminal STV of the circuit; in the last stage connection relationship, the source of the third P-type transistor T3, the fourth N The source of the transistor T4, the gate of the sixth P-type transistor T6, and the gate of the eighth N-type transistor T8 are electrically connected to the enable signal terminal STV of the circuit.
  • FIG. 5-6 are waveform diagrams of key nodes in the forward scanning and reverse phase scanning of the low temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention.
  • the first low frequency signal UD and the second low frequency signal DU are low frequency signals capable of high and low potential switching when scanning in forward and reverse directions, and the first low frequency signal UD is equivalent to forward scanning.
  • the second low frequency signal DU is equivalent to a DC low potential
  • the first low frequency signal UD is equivalent to a DC low potential
  • the second low frequency signal DU is equivalent to a DC high potential
  • the clock signal CK (M) is positive In the reverse scan, the order is different
  • the power supply high potential H and the power low potential L are the input constant voltage control signals
  • the signal sent by the reset signal reset is a pulse signal, which is mainly responsible for the circuit at the beginning of each frame.
  • the discharge of the key node; the STV signal is the start signal of the entire GOA circuit, and the circuit part adopts the forward and reverse bidirectional connection, which can realize the forward and reverse bidirectional start.
  • the waveforms of each key node meet the design requirements, wherein the first low frequency signal UD and the second low frequency signal DU are equivalent to a DC high potential and a DC low potential respectively during forward scanning, and the timing signal CK (M)
  • the method includes four sets of timing signals, which are a first timing signal CK(1), a second timing signal CK(2), a third timing signal CK(3), and a fourth timing signal CK(4), when the timing signal When CK(M) is the first timing signal CK(1), the M-2th timing signal CK(M-2) is the third timing signal CK(3), when the timing signal CK(M) is In the second timing signal CK(2), the M-2th timing signal CK(M-2) is the fourth timing signal CK(4), and when the timing signal CK(M) is the fourth timing signal CK (4), the M+1th timing signal CK(M+1) is the first timing signal CK(1).
  • the pulse signals of the timing signal CK(M) sequentially arrive in the order of CK(1)-CK(4), and the third timing signal CK(3) corresponds to the output signal of the first stage output terminal G(1), and the fourth The timing signal CK(4) corresponds to the output signal of the second stage output terminal G(2), the first timing signal CK(1) corresponds to the output signal of the third stage output terminal G(3), and the second timing signal CK(2) Corresponding to the output signal of the fourth stage output terminal G(4), and so on.
  • the waveforms of each key node meet the design requirements, wherein the first low frequency signal UD And the second low-frequency signal DU is equivalent to a DC low potential and a DC high potential at the time of reverse scanning, and the pulse signals of the timing signal CK(M) are sequentially issued in the order of CK(4)-CK(1),
  • the second timing signal CK(2) corresponds to the output signal of the first stage output terminal G(1)
  • the first timing signal CK(1) corresponds to the output signal of the second stage output terminal G(2)
  • the fourth timing signal CK(4) Corresponding to the output signal of the third stage output terminal G(3)
  • the third timing signal CK(3) corresponds to the output signal of the fourth stage output terminal G(4), and so on.
  • FIG. 4 is a circuit diagram of a second embodiment of a low temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention.
  • the second embodiment is different from the first embodiment in that it further includes a second output control.
  • the second output control portion 501 is electrically connected to the output control portion 500, the drive output terminal ST(N), the M+1th timing signal CK(M+1), the power supply high potential H, and the power supply low potential L;
  • the second output buffering portion 601 is electrically connected to the second output control portion 501, the output terminal G(N+1) of the (N+1)th GOA unit, the power supply high potential H, and the power supply low potential L.
  • the second output control portion 501 includes a thirty-six P-type transistor T36.
  • the gate of the third sixteen P-type transistor T36 is electrically connected to the driving output terminal ST(N), and the source is electrically connected to the source.
  • the power supply high potential H the drain is electrically connected to the source of the thirty-ninth N-type transistor T39; a thirty-seventh N-type transistor T37, the gate of the thirty-seventh N-type transistor T37 is electrically connected to Driving output ST (N), the source is electrically connected to the drain of the thirty-ninth N-type transistor T39, the drain is electrically connected to the power supply low potential L; a thirty-eighth P-type transistor T38, the The gate of the thirty-eight P-type transistor T38 is electrically connected to the M+1th timing signal CK(M+1), the source is electrically connected to the power supply high potential H, and the drain is electrically connected to the thirty-ninth N.
  • the second output buffering portion 601 includes a fortieth P-type transistor T40, and the gate of the fortieth P-type transistor T40 is electrically connected to the source of the thirty-ninth N-type transistor T39, and the source is electrically Connected to the power supply high potential H, the drain is electrically connected to the source of the forty-first N-type transistor T41; a forty-first N-type transistor T41, the gate electrical property of the forty-first N-type transistor T41 Connected to the source of the thirty-ninth N-type transistor T39, the source is electrically connected to the drain of the fortieth P-type transistor T40, and the drain is electrically connected to the power supply low potential L; a forty-second P-type transistor T42, the gate of the forty-second P-type transistor T42 is electrically connected to the drain of the fortieth P-type transistor T40, the source is electrically connected to the power supply high potential H, and the drain is electrically connected to the fort
  • the third sixteen P-type transistor T36, the thirty-seventh N-type transistor T37, the thirty-eighth P-type transistor T38, and the thirty-ninth N-type transistor T39 in the second output control portion 501 constitute a NAND gate logic unit And for controlling a scan signal outputted by the output terminal G(N+1) of the (N+1)th GOA unit to output a scan signal conforming to the timing;
  • the fourth output buffer portion 601 of the fortieth P-type transistor T40 And the forty-first N-type transistor T41, the forty-second P-type transistor T42 and the forty-third N-type transistor T43, the forty-fourth P-type transistor T44 and the forty-fifth N-type transistor T45 respectively constitute three anti- a direction indicator for adjusting the timing-adjusted scan signal while enhancing the load carrying capability;
  • the second output control portion 501 and the second output buffer portion 601 are based on the output signal of the drive output terminal ST(N) and the Mth +1
  • the effect of the single-stage GOA unit controlling the forward and reverse bidirectional scan output of the two-stage circuit can be achieved by adding the second output control portion 501 and the second output buffer portion 601, and the second output control portion 501 shares a drive with the output control portion 500.
  • the output terminal ST(N) can reduce the number of TFTs by sharing the output terminal ST(N), and realizes an ultra-narrow bezel or a borderless design.
  • the low temperature polysilicon semiconductor thin film transistor GOA circuit of the present invention is used for forward and reverse bidirectional scanning transmission
  • the Nth stage GOA unit uses a plurality of N type transistors and a plurality of P type transistors, including a transmission part and a transmission control. Part, data storage part, data clearing part, output control part, and output buffer part.
  • the transmission portion has a transfer gate; the transfer control portion has a NOR gate logic unit, an inverter, and a transfer gate; the data storage portion has a timing inverter and an inverter; and the output control portion has a non-gate logic unit and an inverter; the output buffer portion has an inverter; the transmission gate is used for transmitting signals to the upper and lower stages, and the signals are converted by the NOR gate logic unit and the NAND gate logic unit, and the timing is inverted.
  • the device and the inverter store and transmit the signal, which solves the problem that the device circuit stability of the LTPS single TFT is not good, the power consumption is large, and the TFT leakage of the single type GOA circuit is optimized, and the performance of the circuit is optimized;
  • the second output control part and the second output buffer part are arranged to realize a common drive output end, so that the single-stage GOA unit controls the forward and reverse bidirectional scan output of the two-stage circuit, which can be reduced
  • the number of TFTs enables ultra-narrow bezel or borderless design.

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Abstract

一种低温多晶硅薄膜晶体管GOA电路，用于正反双向扫描传输，包括级联的多个GOA单元，设N为正整数，第N级GOA单元采用多个N型晶体管与多个P型晶体管，所述第N级GOA单元包括：传输部分(100)、传输控制部分(200)、资料存储部分(300)、数据清除部分(400)、输出控制部分(500)及输出缓冲部分(600)。采用传输闸进行上下级传输信号，采用或非门逻辑单元和与非门逻辑单元对信号进行转换，采用时序反相器和反相器对信号进行储存和传输，解决了LTPS单一型TFT的器件电路稳定性不佳，功耗较大的问题以及单一型GOA电路的TFT漏电的问题，优化了电路的性能，并可实现超窄边框或无边框的设计。

Description

低温多晶硅薄膜晶体管GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种低温多晶硅薄膜晶体管GOA电路。
背景技术
GOA(Gate Drive On Array)，是利用薄膜晶体管(thin film transistor，TFT)液晶显示器阵列(Array)制程将栅极驱动器制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式。
通常，GOA电路主要由上拉部分(Pull-up part)、上拉控制部分(Pull-up control part)、下传部分(Transfer part)、下拉部分(Pull-down part)、下拉维持电路部分(Pull-down Holding part)、以及负责电位抬升的上升部分(Boost part)组成，上升部分一般由一自举电容构成。
上拉部分主要负责将输入的时钟信号(Clock)输出至薄膜晶体管的栅极，作为液晶显示器的驱动信号。上拉控制部分主要负责控制上拉部分的打开，一般是由上级GOA电路传递来的信号作用。下拉部分主要负责在输出扫描信号后，快速地将扫描信号(亦即薄膜晶体管的栅极的电位)拉低为低电平。下拉维持电路部分则主要负责将扫描信号和上拉部分的信号保持在关闭状态(即设定的负电位)。上升部分则主要负责对上拉部分的电位进行二次抬升，确保上拉部分的正常输出。
随着低温多晶硅(Low Temperature Poly-silicon，LTPS)半导体薄膜晶体管(Thin-film transistor，TFT)的发展，LTPS-TFT液晶显示器也越来越受关注，LTPS-TFT液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点，由于低温多晶硅较非晶硅(a-Si)的排列有次序，低温多晶硅半导体本身具有超高的电子迁移率，比非晶硅半导体相对高100倍以上，可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上，达到系统整合的目标、节省空间及驱动IC的成本。然而，对于低温多晶硅薄膜晶体管来说，单一型(单一N型或单一P型)的GOA电路存在结构复杂，电路特性差，特别是功耗大的问题，尤其是用到中小尺寸，功耗成为其性能考证的重要指标，因此，如何有效的减小功耗，同时增强电路结构和性能的整体稳定性成为了目前低温多晶硅半导体薄膜晶体管GOA电路所面临一个重要问题。
发明内容
本发明的目的在于提供一种低温多晶硅半导体薄膜晶体管GOA电路，能够解决LTPS单一型TFT的器件电路稳定性不佳，功耗较大的问题；解决目前单一型GOA电路的TFT漏电的问题，优化电路的性能；并可实现超窄边框或无边框的设计。
为实现上述目的，本发明提供了一种低温多晶硅半导体薄膜晶体管GOA电路，用于正反双向扫描传输，包括级联的多个GOA单元，设N为正整数，第N级GOA单元采用多个N型晶体管与多个P型晶体管，所述第N级GOA单元包括：传输部分、传输控制部分、资料存储部分、数据清除部分、输出控制部分及输出缓冲部分；
所述传输部分电性连接于第一低频信号、第二低频信号、所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端、所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端与所述资料存储部分；所述传输控制部分电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端、所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端、第M-2级时序信号、电源高电位、电源低电位与资料存储部分；所述资料存储部分电性连接于所述传输部分、传输控制部分、电源高电位与电源低电位；所述数据清除部分电性连接于所述资料存储部分、输出控制部分、数据清除部分、电源高电位与复位信号端；所述输出控制部分电性连接于所述数据清除部分、输出缓冲部分、驱动输出端、时序信号、电源高电位与电源低电位；所述输出缓冲部分电性连于所述输出控制部分、输出端、电源高电位与电源低电位；
所述第一低频信号和第二低频信号的电位随着正反扫描进行切换，正向扫描时，所述第一低频信号相当于直流高电位，所述第二低频信号相当于直流低电位；反向扫描时，所述第一低频信号相当于直流低电位，所述第二低频信号相当于直流高电位；
所述传输部分包括：
一第一P型晶体管，所述第一P型晶体管的栅极电性连接于第二低频信号，源极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端，漏极电性连接于第一节点；
一第二N型晶体管，所述第二N型晶体管的栅极电性连接于第一低频信号，源极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端，漏极电性连接于第一节点；
一第三P型晶体管，所述第三P型晶体管的栅极电性连接于第一低频信号，源极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端，漏极电性连接于第二节点；
一第四N型晶体管，所述第四N型晶体管的栅极电性连接于第二低频信号，源极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端，漏极电性连接于第二节点；
所述传输控制部分包括：
一第五P型晶体管，所述第五P型晶体管的栅极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端，源极电性连接于电源高电位，漏极电性连接于第六P型晶体管的源极；
一第六P型晶体管，所述第六P型晶体管的栅极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端，源极电性连接于第五P型晶体管的漏极，漏极电性连接于第七N型晶体管的源极；
一第七N型晶体管，所述第七N型晶体管的栅极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端，源极电性连接于第六P型晶体管的漏极，漏极电性连接于电源低电位；
一第八N型晶体管，所述第八N型晶体管的栅极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端，源极电性连接于第六P型晶体管的漏极，漏极电性连接于电源低电位；
一第九P型晶体管，所述第九P型晶体管的栅极电性连接于第六P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于第十N型晶体管的源极；
一第十N型晶体管，所述第十N型晶体管的栅极电性连接于第六P型晶体管的漏极，源极电性连接于第九P型晶体管的漏极，漏极电性连接于电源低电位；
一第十一P型晶体管，所述第十一P型晶体管的栅极电性连接于第六P型晶体管的漏极，源极电性连接于第十二N型晶体管的源极，漏极电性连接于第M-2级时序信号；
一第十二N型晶体管，所述第十二N型晶体管的栅极电性连接于第九P型晶体管的漏极，源极电性连接于第十一P型晶体管的源极，漏极电性连接于第M-2级时序信号；
所述资料存储部分包括：
一第十三N型晶体管，所述第十三N型晶体管的栅极电性连接于第十一P型晶体管的源极，源极电性连接于第十四P型晶体管的漏极，漏极电 性连接于电源低电位；
一第十四P型晶体管，所述第十四P型晶体管的栅极电性连接于第十一P型晶体管的源极，源极电性连接于电源高电位，漏极电性连接于第十三N型晶体管的源极；
一第十五P型晶体管，所述第十五P型晶体管的栅极电性连接于第十三N型晶体管的源极，源极电性连接于电源高电位，漏极电性连接于第十六P型晶体管的源极；
一第十六P型晶体管，所述第十六P型晶体管的栅极电性连接于第一节点，源极电性连接于第十五P型晶体管的漏极，漏极电性连接于第十七N型晶体管的源极；
一第十七N型晶体管，所述第十七N型晶体管的栅极电性连接于第一节点，源极电性连接于第十六P型晶体管的漏极，漏极电性连接于第十八N型晶体管的源极；
一第十八N型晶体管，所述第十八N型晶体管的栅极电性连接于第十一P型晶体管的源极，源极电性连接于第十七N型晶体管的漏极，漏极电性连接于电源低电位；
一第十九P型晶体管，所述第十九P型晶体管的栅极电性连接于第十三N型晶体管的栅极，源极电性连接于电源高电位，漏极电性连接于第二十P型晶体管的源极；
一第二十P型晶体管，所述第二十P型晶体管的栅极电性连接于第二节点，源极电性连接于第十九P型晶体管的漏极，漏极电性连接于第二十一N型晶体管的源极；
一第二十一N型晶体管，所述第二十一N型晶体管的栅极电性连接于第二节点，源极电性连接于第二十P型晶体管的漏极，漏极电性连接于第二十二N型晶体管的源极；
一第二十二N型晶体管，所述第二十二N型晶体管的栅极电性连接于第十三N型晶体管的源极，源极电性连接于第二十一N型晶体管的漏极，漏极电性连接于电源低电位；
所述数据清除部分包括：
一第二十三P型晶体管，所述第二十三P型晶体管的栅极电性连接于复位信号端，源极电性连接于电源高电位，漏极电性连接于第十六P型晶体管的漏极及第二十P型晶体管的漏极；
所述输出控制部分(500)包括
一第二十四P型晶体管，所述第二十四P型晶体管的栅极电性连接于 第十六P型晶体管的漏极及第二十P型晶体管的漏极，，源极电性连接于电源高电位，漏极电性连接于驱动输出端；
一第二十五N型晶体管，所述第二十五N型晶体管的栅极电性连接于第十六P型晶体管的漏极及第二十P型晶体管的漏极，源极电性连接于驱动输出端，漏极电性连接于电源低电位；
一第二十六P型晶体管，所述第二十六P型晶体管的栅极电性连接于驱动输出端，源极电性连接于电源高电位，漏极电性连接于第二十九N型晶体管的源极；
一第二十七N型晶体管，所述第二十七N型晶体管的栅极电性连接于驱动输出端，源极电性连接于第二十九N型晶体管的漏极，漏极电性连接于电源低电位；
一第二十八P型晶体管，所述第二十八P型晶体管的栅极电性连接于时序信号，源极电性连接于电源高电位，漏极电性连接于第二十九N型晶体管的源极；
一第二十九N型晶体管，所述第二十九N型晶体管的栅极电性连接于时序信号，源极电性连接于第二十六N型晶体管的漏极，漏极电性连接于第二十七N型晶体管的源极；
所述输出缓冲部分包括:
一第三十P型晶体管，所述第三十P型晶体管的栅极电性连接于第二十九N型晶体管的源极，源极电性连接于电源高电位，漏极电性连接于第三十一N型晶体管的源极；
一第三十一N型晶体管，所述第三十一N型晶体管的栅极电性连接于第二十九N型晶体管的源极，源极电性连接于第三十P型晶体管的漏极，漏极电性连接于电源低电位；
一第三十二P型晶体管，所述第三十二P型晶体管的栅极电性连接于第三十P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于第三十三N型晶体管的源极；
一第三十三N型晶体管，所述第三十三N型晶体管的栅极电性连接于第三十P型晶体管的漏极，源极电性连接于第三十二P型晶体管的漏极，漏极电性连接于电源低电位；
一第三十四P型晶体管，所述第三十四P型晶体管的栅极电性连接于第三十二P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于输出端；
一第三十五N型晶体管，所述第三十五N型晶体管的栅极电性连接于 第三十二P型晶体管的漏极，源极电性连接于输出端，漏极电性连接于电源低电位。
所述GOA电路还包括第二输出控制部分、第二输出缓冲部分；
所述第二输出控制部分电性连接于输出控制部分、驱动输出端、第M+1级时序信号、电源高电位与电源低电位；所述第二输出缓冲部分电性连接于所述第二输出控制部分、第N+1级GOA单元的输出端、电源高电位与电源低电位；
所述第二输出控制部分包括：
一第三十六P型晶体管，所述第三十六P型晶体管的栅极电性连接于驱动输出端，源极电性连接于电源高电位，漏极电性连接于第三十九N型晶体管的源极；
一第三十七N型晶体管，所述第三十七N型晶体管的栅极电性连接于驱动输出端，源极电性连接于第三十九N型晶体管的漏极，漏极电性连接于电源低电位；
一第三十八P型晶体管，所述第三十八P型晶体管的栅极电性连接于第M+1级时序信号，源极电性连接于电源高电位，漏极电性连接于第三十九N型晶体管的源极；
一第三十九N型晶体管，所述第三十九N型晶体管的栅极电性连接于第M+1级时序信号，源极电性连接于第三十六P型晶体管的漏极，漏极电性连接于第三十七N型晶体管的源极；
所述第二输出缓冲部分包括：
一第四十P型晶体管，所述第四十P型晶体管的栅极电性连接于第三十九N型晶体管的源极，源极电性连接于电源高电位，漏极电性连接于第四十一N型晶体管的源极；
一第四十一N型晶体管，所述第四十一N型晶体管的栅极电性连接于第三十九N型晶体管的源极，源极电性连接于第四十P型晶体管的漏极，漏极电性连接于电源低电位；
一第四十二P型晶体管，所述第四十二P型晶体管的栅极电性连接于第四十P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于第四十三N型晶体管的源极；
一第四十三N型晶体管，所述第四十三N型晶体管的栅极电性连接于第四十P型晶体管的漏极，源极电性连接于第四十二P型晶体管的漏极，漏极电性连接于电源低电位；
一第四十四P型晶体管，所述第四十四P型晶体管的栅极电性连接于 第四十二P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于第N+1级GOA单元的输出端；
一第四十五N型晶体管，所述第四十五N型晶体管的栅极电性连接于第四十二P型晶体管的漏极，源极电性连接于第N+1级GOA单元的输出端，漏极电性连接于电源低电位。
所述GOA电路的第一级连接关系中，所述第一P型晶体管的源极、第二N型晶体管的源极、第五P型晶体管的栅极、第七N型晶体管的栅极均电性连接于电路的启动信号端。
所述GOA电路的最后一级连接关系中，所述第三P型晶体管的源极、第四N型晶体管的源极、第六P型晶体管的栅极、第八N型晶体管的栅极均电性连接于电路的启动信号端。
所述传输部分中第一P型晶体管和第二N型晶体管构成一正向传输闸，用于将第N-1级GOA单元的驱动输出信号正向传输至资料存储部分；第三P型晶体管和第四N型晶体管构成一反向传输闸，用于将第N+1级GOA单元的驱动输出信号反向传输至资料存储部分。
所述传输控制部分中第五P型晶体管、第六P型晶体管、第七N型晶体管、第八N型晶体管构成或非门逻辑单元；第九P型晶体管、第十N型晶体管构成反相器；第十一P型晶体管和第十二N型晶体管构成传输闸；所述传输控制部分用于控制第M-2级时序信号，并将其传输到资料存储部分。
所述资料存储部分中第十五P型晶体管、第十六P型晶体管、第十七N型晶体管、第十八N型晶体管构成正向时序反向器；第十九P型晶体管、第二十P型晶体管、第二十一N型晶体管、第二十二N型晶体管构成反向时序反向器；第十三N型晶体管、第十四P型晶体管构成反向器；所述资料存储部分用于对由第N-1级GOA单元的驱动输出端、第N+1级GOA单元的驱动输出端和第M-2级时序信号传入的信号进行存储和传输。
所述数据清除部分用于对电路的驱动输出端电位的适时清除。
所述输出控制部分中第二十六P型晶体管、第二十七N型晶体管、第二十八P型晶体管、第二十九N型晶体管构成与非门逻辑单元；第二十四P型晶体管、第二十五N型晶体管构成反向器；所述输出控制部分用于对输出端输出的扫描信号进行控制，输出符合时序的扫描信号。
所述输出缓冲部分中第三十P型晶体管和第三十一N型晶体管、第三十二P型晶体管和第三十三N型晶体管、第三十四P型晶体管和第三十五N型晶体管分别构成三个反向器，用于对经过时序调整的扫描信号进行调 整，同时增强带负载能力。
所述第二输出控制部分中第三十六P型晶体管、第三十七N型晶体管、第三十八P型晶体管、第三十九N型晶体管构成与非门逻辑单元，用于对第N+1级GOA单元的输出端输出的扫描信号进行控制，输出符合时序的扫描信号；所述第二输出缓冲部分中第四十P型晶体管和第四十一N型晶体管、第四十二P型晶体管和第四十三N型晶体管、第四十四P型晶体管和第四十五N型晶体管分别构成三个反向器，用于对经过时序调整的扫描信号进行调整，同时增强带负载能力；所述第二输出控制部分和第二输出缓冲部分依据驱动输出端的输出信号与第M+1级时序信号，由第N+1级GOA单元的输出端输出后一级扫描信号，实现单级GOA单元控制两级电路正反双向扫描输出。
所述时序信号包括四组时序信号：第一时序信号、第二时序信号、第三时序信号、第四时序信号，当所述时序信号为第一时序信号时，所述第M-2级时序信号为第三时序信号，当所述时序信号为第二时序信号时，所述第M-2级时序信号为第四时序信号，当所述时序信号为第四时序信号，所述第M+1级时序信号为第一时序信号。
本发明的有益效果：本发明提供的一种低温多晶硅半导体薄膜晶体管GOA电路，用于正反双向扫描传输，第N级GOA单元采用多个N型晶体管与多个P型晶体管，包括传输部分、传输控制部分、资料存储部分、数据清除部分、输出控制部分、及输出缓冲部分。所述传输部分具有传输闸；所述传输控制部分具有或非门逻辑单元、反相器、与传输闸；所述资料存储部分具有时序反相器、反相器；所述输出控制部分具有与非门逻辑单元、反相器；所述输出缓冲部分具有反相器；采用传输闸进行上下级传输信号，采用或非门逻辑单元和与非门逻辑单元对信号进行转换，用时序反相器和反相器对信号进行储存和传输，解决了LTPS单一型TFT的器件电路稳定性不佳，功耗较大的问题以及单一型GOA电路的TFT漏电的问题，优化了电路的性能；通过设置第二输出控制部分与第二输出缓冲部分，实现共用驱动输出端，使得单级GOA单元控制两级电路正反双向扫描输出，可减少TFT数目，实现超窄边框或无边框的设计。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明低温多晶硅半导体薄膜晶体管GOA电路的第一实施例的电路图；
图2为本发明低温多晶硅半导体薄膜晶体管GOA电路的第一实施例的第一级连接关系的电路图；
图3为本发明低温多晶硅半导体薄膜晶体管GOA电路的第一实施例的最后一级连接关系的电路图；
图4为本发明低温多晶硅半导体薄膜晶体管GOA电路的第二实施例的电路图；
图5为本发明低温多晶硅半导体薄膜晶体管GOA电路正向扫描时关键节点的波形图；
图6为本发明低温多晶硅半导体薄膜晶体管GOA电路反向扫描时关键节点的输出波形图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，为本发明的第一实施例的电路图。如图1所示，本发明提供了一种低温多晶硅薄膜晶体管GOA电路，用于正反双向扫描传输，包括级联的多个GOA单元，设N为正整数，第N级GOA单元采用多个N型晶体管与多个P型晶体管，所述第N级GOA单元包括：传输部分100、传输控制部分200、资料存储部分300、数据清除部分400、输出控制部分500及输出缓冲部分600；
所述传输部分100电性连接于第一低频信号UD、第二低频信号DU、所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端ST(N-1)、所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端ST(N+1)与所述资料存储部分300；所述传输控制部分200电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端ST(N+1)、所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端ST(N-1)、第M-2级时序信号CK(M-2)、电源高电位H、电源低电位L与资料存储部分300；所述资料存储部分300电性连接于所述传输部分100、传输控制部分200、数据清除部分400、电源高电位H与电源低电位L；所述数据清除部分400电性连接于所述资料存储部分300、输出控制部分500、电源高电位H与复位信号端Reset；所述输出控制部分500电性连接于所述数据清除部分400、输出缓冲部分600、驱动输出端ST(N)、时序信号CK(M)、电源高电位H 与电源低电位L；所述输出缓冲部分600电性连于所述输出控制部分500、输出端G(N)、电源高电位H与电源低电位L；
所述第一低频信号UD和第二低频信号DU的电位随着正反扫描进行切换，正向扫描时，所述第一低频信号UD相当于直流高电位，所述第二低频信号DU相当于直流低电位；反向扫描时，所述第一低频信号UD相当于直流低电位，所述第二低频信号DU相当于直流高电位。
所述传输部分100包括一第一P型晶体管T1，所述第一P型晶体管T1的栅极电性连接于第二低频信号DU，源极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端ST(N-1)，漏极电性连接于第一节点P(N)；一第二N型晶体管T2，所述第二N型晶体管T2的栅极电性连接于第一低频信号UD，源极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端ST(N-1)，漏极电性连接于第一节点P(N)；一第三P型晶体管T3，所述第三P型晶体管T3的栅极电性连接于第一低频信号UD，源极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端ST(N+1)，漏极电性连接于第二节点Q(N)；一第四N型晶体管T4，所述第四N型晶体管T4的栅极电性连接于第二低频信号DU，源极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端ST(N+1)，漏极电性连接于第二节点Q(N)。
所述第一P型晶体管T1和第二N型晶体管T2构成一正向传输闸，当所述第一低频信号UD相当于直流高电位，所述第二低频信号DU相当于直流低电位，进行正向扫描时，所述正向传输闸工作，用于将第N-1级GOA单元的驱动输出信号ST(N-1)正向传输至资料存储部分300；所述第三P型晶体管T3和第四N型晶体管T4构成一反向传输闸，当所述第一低频信号UD相当于直流低电位，所述第二低频信号DU相当于直流高电位，进行反向扫描时，所述反向传输闸工作，用于将第N+1级GOA单元的驱动输出信号ST(N+1)反向传输至资料存储部分300。
所述传输控制部分200包括一第五P型晶体管T5，所述第五P型晶体管T5的栅极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端ST(N-1)，源极电性连接于电源高电位H，漏极电性连接于第六P型晶体管T6的源极；一第六P型晶体管T6，所述第六P型晶体管T6的栅极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端ST(N+1)，源极电性连接于第五P型晶体管T5的漏极，漏极电性连接于第七N型晶体管T7的源极；一第七N型晶体管T7，所述第七N型晶体管T7的栅极电性连接于所述第N级GOA单元的前一级第N-1级 GOA单元的驱动输出端ST(N-1)，源极电性连接于第六P型晶体管T6的漏极，漏极电性连接于电源低电位L；一第八N型晶体管T8，所述第八N型晶体管T8的栅极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端ST(N+1)，源极电性连接于第六P型晶体管T6的漏极，漏极电性连接于电源低电位L；一第九P型晶体管T9，所述第九P型晶体管T9的栅极电性连接于第六P型晶体管T6的漏极，源极电性连接于电源高电位H，漏极电性连接于第十N型晶体管T10的源极；一第十N型晶体管T10，所述第十N型晶体管T10的栅极电性连接于第六P型晶体管T6的漏极，源极电性连接于第九P型晶体管T9的漏极，漏极电性连接于电源低电位L；一第十一P型晶体管T11，所述第十一P型晶体管T11的栅极电性连接于第六P型晶体管T6的漏极，源极电性连接于第十二N型晶体管T12的源极，漏极电性连接于第M-2级时序信号CK(M-2)；一第十二N型晶体管T12，所述第十二N型晶体管T12的栅极电性连接于第九P型晶体管T9的漏极，源极电性连接于第十一N型晶体管T11的源极，漏极电性连接于第M-2级时序信号CK(M-2)；
其中，所述第五P型晶体管T5、第六P型晶体管T6、第七N型晶体管T7、第八N型晶体管T8构成一或非门逻辑单元；第九P型晶体管T9、第十N型晶体管T10构成一反相器；第十一P型晶体管(T11)和第十二N型晶体管(T12)构成一传输闸；所述传输控制部分200用于控制第M-2级时序信号CK(M-2)，并将其传输到资料存储部分300。
所述资料存储部分300包括一第十三N型晶体管T13，所述第十三N型晶体管T13的栅极电性连接于第十一P型晶体管T11的源极，源极电性连接于第十四P型晶体管T14的漏极，漏极电性连接于电源低电位L；一第十四P型晶体管T14，所述第十四P型晶体管T14的栅极电性连接于第十一P型晶体管T11的源极，源极电性连接于电源高电位H，漏极电性连接于第十三N型晶体管T13的源极；一第十五P型晶体管T15，所述第十五P型晶体管T15的栅极电性连接于第十三N型晶体管T13的源极，源极电性连接于电源高电位H，漏极电性连接于第十六P型晶体管T16的源极；一第十六P型晶体管T16，所述第十六P型晶体管T16的栅极电性连接于第一节点P(N)，源极电性连接于第十五P型晶体管T15的漏极，漏极电性连接于第十七N型晶体管T17的源极；一第十七N型晶体管T17，所述第十七N型晶体管T17的栅极电性连接于第一节点P(N)，源极电性连接于第十六P型晶体管T16的漏极，漏极电性连接于第十八N型晶体管T18的源极；一第十八N型晶体管T18，所述第十八N型晶体管T18的栅极电性连 接于第十一P型晶体管T11的源极，源极电性连接于第十七N型晶体管T17的漏极，漏极电性连接于电源低电位L；一第十九P型晶体管T19，所述第十九P型晶体管T19的栅极电性连接于第十三N型晶体管T13的栅极，源极电性连接于电源高电位H，漏极电性连接于第二十P型晶体管T20的源极；一第二十P型晶体管T20，所述第二十P型晶体管T20的栅极电性连接于第一节点Q(N)，源极电性连接于第十九P型晶体管T19的漏极，漏极电性连接于第二十一N型晶体管T21的源极；一第二十一N型晶体管T21，所述第二十一N型晶体管T21的栅极电性连接于第一节点Q(N)，源极电性连接于第二十P型晶体管T20的漏极，漏极电性连接于第二十二N型晶体管T22的源极；一第二十二N型晶体管T22，所述第二十二N型晶体管T22的栅极电性连接于第十三N型晶体管T13的源极，源极电性连接于第二十一N型晶体管T21的漏极，漏极电性连接于电源低电位L；
其中，所述第十五P型晶体管T15、第十六P型晶体管T16、第十七N型晶体管T17、第十八N型晶体管T18构成一正向时序反向器，该正向时序反相器与所述传输部分100中的正向传输闸电性连接；第十九P型晶体管T19、第二十P型晶体管T20、第二十一N型晶体管T21、第二十二N型晶体管T22构成一反向时序反向器，该反向时序反相器与所述传输部分100中的反向传输闸电性连接；第十三N型晶体管T13、第十四P型晶体管T14构成一反向器；正向扫描时，所述资料存储部分300用于对由第N-1级GOA单元的驱动输出端ST(N-1)、和第M-2级时序信号CK(M-2)传入的信号进行存储和传输；反向扫描时，所述资料存储部分300用于对由第N+1级GOA单元的驱动输出端ST(N+1)和第M-2级时序信号CK(M-2)传入的信号进行存储和传输。
所述数据清除部分400包括一第二十三P型晶体管T23，所述第二十三P型晶体管T23的栅极电性连接于复位信号端Reset，源极电性连接于电源高电位H，漏极电性连接于第十六P型晶体管T16的漏极及第二十P型晶体管T20的漏极；所述数据清除部分400用于对电路的驱动输出端ST(N)电位的适时清除，主要是在每一帧开始的时候，复位信号端Reset接收一脉冲复位信号，对驱动输出端ST(N)进行放电，从而将驱动输出端ST(N)的电位进行清除。
所述输出控制部分500包括一第二十四P型晶体管T24，所述第二十四P型晶体管T24的栅极电性连接于第十六P型晶体管T16的漏极及第二十P型晶体管T20的漏极，源极电性连接于电源高电位H，漏极电性连接于驱动输出端ST(N)；一第二十五N型晶体管T25，所述第二十五N型晶 体管T25的栅极电性连接于第十六P型晶体管T16的漏极及第二十P型晶体管T20的漏极，源极电性连接于驱动输出端ST(N)，漏极电性连接于电源低电位L；一第二十六P型晶体管T26，所述第二十六P型晶体管T26的栅极电性连接于驱动输出端ST(N)，源极电性连接于电源高电位H，漏极电性连接于第二十九N型晶体管T29的源极；一第二十七N型晶体管T27，所述第二十七N型晶体管T27的栅极电性连接于驱动输出端ST(N)，源极电性连接于第二十九N型晶体管T29的漏极，漏极电性连接于电源低电位L；一第二十八P型晶体管T28，所述第二十八P型晶体管T28的栅极电性连接于时序信号CK(M)，源极电性连接于电源高电位H，漏极电性连接于第二十九N型晶体管T29的源极；一第二十九N型晶体管T29，所述第二十九N型晶体管T29的栅极电性连接于时序信号CK(M)，源极电性连接于第二十六P型晶体管T26的漏极，漏极电性连接于第二十七N型晶体管T27的源极；
其中，所述第二十六P型晶体管T26、第二十七N型晶体管T27、第二十八P型晶体管T28、第二十九N型晶体管T29构成一与非门逻辑单元；第二十四P型晶体管T24、第二十五N型晶体管T25构成一反向器；所述输出控制部分500用于对输出端G(N)输出的扫描信号进行控制，输出符合时序的扫描信号。
所述输出缓冲部分600包括一第三十P型晶体管T30，所述第三十P型晶体管T30的栅极电性连接于第二十九N型晶体管T29的源极，源极电性连接于电源高电位H，漏极电性连接于第三十一N型晶体管T31的源极；一第三十一N型晶体管T31，所述第三十一N型晶体管T31的栅极电性连接于第二十九N型晶体管T29的源极，源极电性连接于第三十P型晶体管T30的漏极，漏极电性连接于电源低电位L；一第三十二P型晶体管T32，所述第三十二P型晶体管T32的栅极电性连接于第三十P型晶体管T30的漏极，源极电性连接于电源高电位H，漏极电性连接于第三十三N型晶体管T33的源极；一第三十三N型晶体管T33，所述第三十三N型晶体管T33的栅极电性连接于第三十P型晶体管T30的漏极，源极电性连接于第三十二P型晶体管T32的漏极，漏极电性连接于电源低电位L；一第三十四P型晶体管T34，所述第三十四P型晶体管T34的栅极电性连接于第三十二P型晶体管T32的漏极，源极电性连接于电源高电位H，漏极电性连接于输出端G(N)；一第三十五N型晶体管T35，所述第三十五N型晶体管T35的栅极电性连接于第三十二P型晶体管T32的漏极，源极电性连接于输出端G(N)，漏极电性连接于电源低电位L。
其中，所述第三十P型晶体管T30和第三十一N型晶体管T31、第三十二P型晶体管T32第三十三N型晶体管T33、第三十四P型晶体管T34和第三十五N型晶体管T35分别构成了三个反向器；用于对经过时序调整的扫描信号进行调整，同时增强带负载能力。
如图2-3所示，本发明的低温多晶硅薄膜晶体管GOA电路的第一级连接关系中，所述第一P型晶体管T1的源极、第二N型晶体管T2的源极、第五P型晶体管T5的栅极、第七N型晶体管T7的栅极均电性连接于电路的启动信号端STV；最后一级连接关系中，所述第三P型晶体管T3的源极、第四N型晶体管T4的源极、第六P型晶体管T6的栅极、第八N型晶体管T8的栅极均电性连接于电路的启动信号端STV。
请参阅图5-6，分别为本发明低温多晶硅半导体薄膜晶体管GOA电路正向扫描、反相扫描时关键节点输出波形图。如图5、图6所示，第一低频信号UD和第二低频信号DU是随着正反向扫描时，可以进行高低电位切换的低频信号，正向扫描时，第一低频信号UD相当于直流高电位，第二低频信号DU相当于直流低电位，反向扫描时，第一低频信号UD相当于直流低电位，第二低频信号DU相当于直流高电位；时钟信号CK(M)在正反向扫描时，先后顺序有差别；电源高电位H和电源低电位L为输入的恒压控制信号；复位信号端Reset发出的信号是一个脉冲信号，主要负责在每一帧开始的时候对电路的关键节点的放电；STV信号为整个GOA电路的启动信号，电路部分采用正反向双向连接，可以实现正反向双向启动。
请参阅图5，各关键节点的波形满足设计要求，其中第一低频信号UD和第二低频信号DU在正向扫描的时候分别相当于是直流高电位和直流低电位，所述时序信号CK(M)包括四组时序信号，分别为第一时序信号CK(1)、第二时序信号CK(2)、第三时序信号CK(3)、第四时序信号CK(4)，当所述时序信号CK(M)为第一时序信号CK(1)时，所述第M-2级时序信号CK(M-2)为第三时序信号CK(3)，当所述时序信号CK(M)为第二时序信号CK(2)时，所述第M-2级时序信号CK(M-2)为第四时序信号CK(4)，当所述时序信号CK(M)为第四时序信号CK(4)时，所述第M+1级时序信号CK(M+1)为第一时序信号CK(1)。所述时序信号CK(M)的脉冲信号按照CK(1)-CK(4)的顺序依次到来，第三时序信号CK(3)对应第一级输出端G(1)的输出信号，第四时序信号CK(4)对应第二级输出端G(2)的输出信号，第一时序信号CK(1)对应第三级输出端G(3)的输出信号，第二时序信号CK(2)对应第四级输出端G(4)的输出信号，依次类推。
请参阅图6，各关键节点的波形满足设计要求，其中第一低频信号UD 和第二低频信号DU在反向扫描的时候分别相当于是直流低电位和直流高电位，所述时序信号CK(M)的脉冲信号按照CK(4)-CK(1)的顺序依次到来，第二时序信号CK(2)对应第一级输出端G(1)的输出信号，第一时序信号CK(1)对应第二级输出端G(2)的输出信号，第四时序信号CK(4)对应第三级输出端G(3)的输出信号，第三时序信号CK(3)对应第四级输出端G(4)的输出信号，依次类推。
请参阅图4，为本发明低温多晶硅半导体薄膜晶体管GOA电路的第二实施例的电路图，如图4所示，所述第二实施例与第一实施例的区别在于，还包括第二输出控制部分501、第二输出缓冲部分601。所述第二输出控制部分501电性连接于输出控制部分500、驱动输出端ST(N)、第M+1级时序信号CK(M+1)、电源高电位H与电源低电位L；所述第二输出缓冲部分601电性连接于所述第二输出控制部分501、第N+1级GOA单元的输出端G(N+1)、电源高电位H与电源低电位L。
所述第二输出控制部分501包括一第三十六P型晶体管T36，所述第三十六P型晶体管T36的栅极电性连接于驱动输出端ST(N)，源极电性连接于电源高电位H，漏极电性连接于第三十九N型晶体管T39的源极；一第三十七N型晶体管T37，所述第三十七N型晶体管T37的栅极电性连接于驱动输出端ST(N)，源极电性连接于第三十九N型晶体管T39的漏极，漏极电性连接于电源低电位L；一第三十八P型晶体管T38，所述第三十八P型晶体管T38的栅极电性连接于第M+1级时序信号CK(M+1)，源极电性连接于电源高电位H，漏极电性连接于第三十九N型晶体管T39的源极；一第三十九N型晶体管T39，所述第三十九N型晶体管T39的栅极电性连接于第M+1级时序信号CK(M+1)，源极电性连接于第三十六P型晶体管T36的漏极，漏极电性连接于第三十七N型晶体管T37的源极；
所述第二输出缓冲部分601包括一第四十P型晶体管T40，所述第四十P型晶体管T40的栅极电性连接于第三十九N型晶体管T39的源极，源极电性连接于电源高电位H，漏极电性连接于第四十一N型晶体管T41的源极；一第四十一N型晶体管T41，所述第四十一N型晶体管T41的栅极电性连接于第三十九N型晶体管T39的源极，源极电性连接于第四十P型晶体管T40的漏极，漏极电性连接于电源低电位L；一第四十二P型晶体管T42，所述第四十二P型晶体管T42的栅极电性连接于第四十P型晶体管T40的漏极，源极电性连接于电源高电位H，漏极电性连接于第四十三N型晶体管T43的源极；一第四十三N型晶体管T43，所述第四十三N型晶体管T43的栅极电性连接于第四十P型晶体管T40的漏极，源极电性连 接于第四十二P型晶体管T42的漏极，漏极电性连接于电源低电位L；一第四十四P型晶体管T44，所述第四十四P型晶体管T44的栅极电性连接于第四十二P型晶体管T42的漏极，源极电性连接于电源高电位H，漏极电性连接于第N+1级GOA单元的输出端G(N+1)；一第四十五N型晶体管T45，所述第四十五N型晶体管T45的栅极电性连接于第四十二P型晶体管T42的漏极，源极电性连接于第N+1级GOA单元的输出端G(N+1)，漏极电性连接于电源低电位L。
所述第二输出控制部分501中第三十六P型晶体管T36、第三十七N型晶体管T37、第三十八P型晶体管T38、第三十九N型晶体管T39构成与非门逻辑单元，用于对第N+1级GOA单元的输出端G(N+1)输出的扫描信号进行控制，输出符合时序的扫描信号；所述第二输出缓冲部分601中第四十P型晶体管T40和第四十一N型晶体管T41、第四十二P型晶体管T42和第四十三N型晶体管T43、第四十四P型晶体管T44和第四十五N型晶体管T45分别构成三个反向器，用于对经过时序调整的扫描信号进行调整，同时增强带负载能力；所述第二输出控制部分501和第二输出缓冲部分601依据驱动输出端ST(N)的输出信号与第M+1级时序信号CK(M+1)，由第N+1级GOA单元的输出端G(N+1)输出后一级扫描信号，实现单级GOA单元控制两级电路正反双向扫描输出。
通过增加第二输出控制部分501、第二输出缓冲部分601可以达到单级GOA单元控制两级电路正反双向扫描输出的效果，并且所述第二输出控制部分501与输出控制部分500共用一个驱动输出端ST(N)，通过驱动输出端ST(N)共用可减少TFT数目，实现超窄边框或无边框的设计。
综上所述，本发明的一种低温多晶硅半导体薄膜晶体管GOA电路，用于正反双向扫描传输，第N级GOA单元采用多个N型晶体管与多个P型晶体管，包括传输部分、传输控制部分、资料存储部分、数据清除部分、输出控制部分、及输出缓冲部分。所述传输部分具有传输闸；所述传输控制部分具有或非门逻辑单元、反相器、与传输闸；所述资料存储部分具有时序反相器、反相器；所述输出控制部分具有与非门逻辑单元、反相器；所述输出缓冲部分具有反相器；采用传输闸进行上下级传输信号，采用或非门逻辑单元和与非门逻辑单元对信号进行转换，采用用时序反相器和反相器对信号进行储存和传输，解决了LTPS单一型TFT的器件电路稳定性不佳，功耗较大的问题以及单一型GOA电路的TFT漏电的问题，优化了电路的性能；通过设置第二输出控制部分与第二输出缓冲部分，实现共用驱动输出端，使得单级GOA单元控制两级电路正反双向扫描输出，可减少 TFT数目，实现超窄边框或无边框的设计。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种低温多晶硅薄膜晶体管GOA电路，用于正反双向扫描传输，包括级联的多个GOA单元，设N为正整数，第N级GOA单元采用多个N型晶体管与多个P型晶体管，所述第N级GOA单元包括：传输部分、传输控制部分、资料存储部分、数据清除部分、输出控制部分及输出缓冲部分；
    所述传输部分电性连接于第一低频信号、第二低频信号、所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端、所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端与所述资料存储部分；所述传输控制部分电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端、所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端、第M-2级时序信号、电源高电位、电源低电位与资料存储部分；所述资料存储部分电性连接于所述传输部分、传输控制部分、数据清除部分、电源高电位与电源低电位；所述数据清除部分电性连接于所述资料存储部分、输出控制部分、电源高电位与复位信号端；所述输出控制部分电性连接于所述数据清除部分、输出缓冲部分、驱动输出端、时序信号、电源高电位与电源低电位；所述输出缓冲部分电性连于所述输出控制部分、输出端、电源高电位与电源低电位；
    所述第一低频信号和第二低频信号的电位随着正反扫描进行切换，正向扫描时，所述第一低频信号相当于直流高电位，所述第二低频信号相当于直流低电位；反向扫描时，所述第一低频信号相当于直流低电位，所述第二低频信号相当于直流高电位；
    所述传输部分包括一第一P型晶体管，所述第一P型晶体管的栅极电性连接于第二低频信号，源极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端，漏极电性连接于第一节点；一第二N型晶体管，所述第二N型晶体管的栅极电性连接于第一低频信号，源极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端，漏极电性连接于第一节点；一第三P型晶体管，所述第三P型晶体管的栅极电性连接于第一低频信号，源极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端，漏极电性连接于第二节点；一第四N型晶体管，所述第四N型晶体管的栅极电性连接于第二低频信号，源极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端， 漏极电性连接于第二节点；
    所述传输控制部分包括：
    一第五P型晶体管，所述第五P型晶体管的栅极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端，源极电性连接于电源高电位，漏极电性连接于第六P型晶体管的源极；
    一第六P型晶体管，所述第六P型晶体管的栅极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端，源极电性连接于第五P型晶体管的漏极，漏极电性连接于第七N型晶体管的源极；
    一第七N型晶体管，所述第七N型晶体管的栅极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端，源极电性连接于第六P型晶体管的漏极，漏极电性连接于电源低电位；
    一第八N型晶体管，所述第八N型晶体管的栅极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端，源极电性连接于第六P型晶体管的漏极，漏极电性连接于电源低电位；
    一第九P型晶体管，所述第九P型晶体管的栅极电性连接于第六P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于第十N型晶体管的源极；
    一第十N型晶体管，所述第十N型晶体管的栅极电性连接于第六P型晶体管的漏极，源极电性连接于第九P型晶体管的漏极，漏极电性连接于电源低电位；
    一第十一P型晶体管，所述第十一P型晶体管的栅极电性连接于第六P型晶体管的漏极，源极电性连接于第十二N型晶体管的源极，漏极电性连接于第M-2级时序信号；
    一第十二N型晶体管，所述第十二N型晶体管的栅极电性连接于第九P型晶体管的漏极，源极电性连接于第十一P型晶体管的源极，漏极电性连接于第M-2级时序信号；
    所述资料存储部分包括：
    一第十三N型晶体管，所述第十三N型晶体管的栅极电性连接于第十一P型晶体管的源极，源极电性连接于第十四P型晶体管的漏极，漏极电性连接于电源低电位；
    一第十四P型晶体管，所述第十四P型晶体管的栅极电性连接于第十一P型晶体管的源极，源极电性连接于电源高电位，漏极电性连接于第十三N型晶体管的源极；
    一第十五P型晶体管，所述第十五P型晶体管的栅极电性连接于第十 三N型晶体管的源极，源极电性连接于电源高电位，漏极电性连接于第十六P型晶体管的源极；
    一第十六P型晶体管，所述第十六P型晶体管的栅极电性连接于第一节点，源极电性连接于第十五P型晶体管的漏极，漏极电性连接于第十七N型晶体管的源极；
    一第十七N型晶体管，所述第十七N型晶体管的栅极电性连接于第一节点，源极电性连接于第十六P型晶体管的漏极，漏极电性连接于第十八N型晶体管的源极；
    一第十八N型晶体管，所述第十八N型晶体管的栅极电性连接于第十一P型晶体管的源极，源极电性连接于第十七N型晶体管的漏极，漏极电性连接于电源低电位；
    一第十九P型晶体管，所述第十九P型晶体管的栅极电性连接于第十三N型晶体管的栅极，源极电性连接于电源高电位，漏极电性连接于第二十P型晶体管的源极；
    一第二十P型晶体管，所述第二十P型晶体管的栅极电性连接于第二节点，源极电性连接于第十九P型晶体管的漏极，漏极电性连接于第二十一N型晶体管的源极；
    一第二十一N型晶体管，所述第二十一N型晶体管的栅极电性连接于第二节点，源极电性连接于第二十P型晶体管的漏极，漏极电性连接于第二十二N型晶体管的源极；
    一第二十二N型晶体管，所述第二十二N型晶体管的栅极电性连接于第十三N型晶体管的源极，源极电性连接于第二十一N型晶体管的漏极，漏极电性连接于电源低电位；
    所述数据清除部分包括：
    一第二十三P型晶体管，所述第二十三P型晶体管的栅极电性连接于复位信号端，源极电性连接于电源高电位，漏极电性连接于第十六P型晶体管的漏极及第二十P型晶体管的漏极；
    所述输出控制部分包括：
    一第二十四P型晶体管，所述第二十四P型晶体管的栅极电性连接于第十六P型晶体管的漏极及第二十P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于驱动输出端；
    一第二十五N型晶体管，所述第二十五N型晶体管的栅极电性连接于第十六P型晶体管的漏极及第二十P型晶体管的漏极，源极电性连接于驱动输出端，漏极电性连接于电源低电位；
    一第二十六P型晶体管，所述第二十六P型晶体管的栅极电性连接于驱动输出端，源极电性连接于电源高电位，漏极电性连接于第二十九N型晶体管的源极；
    一第二十七N型晶体管，所述第二十七N型晶体管的栅极电性连接于驱动输出端，源极电性连接于第二十九N型晶体管的漏极，漏极电性连接于电源低电位；
    一第二十八P型晶体管，所述第二十八P型晶体管的栅极电性连接于时序信号，源极电性连接于电源高电位，漏极电性连接于第二十九N型晶体管的源极；
    一第二十九N型晶体管，所述第二十九N型晶体管的栅极电性连接于时序信号，源极电性连接于第二十六N型晶体管的漏极，漏极电性连接于第二十七N型晶体管的源极；
    所述输出缓冲部分包括：
    一第三十P型晶体管，所述第三十P型晶体管的栅极电性连接于第二十九N型晶体管的源极，源极电性连接于电源高电位，漏极电性连接于第三十一N型晶体管的源极；
    一第三十一N型晶体管，所述第三十一N型晶体管的栅极电性连接于第二十九N型晶体管的源极，源极电性连接于第三十P型晶体管的漏极，漏极电性连接于电源低电位；
    一第三十二P型晶体管，所述第三十二P型晶体管的栅极电性连接于第三十P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于第三十三N型晶体管的源极；
    一第三十三N型晶体管，所述第三十三N型晶体管的栅极电性连接于第三十P型晶体管的漏极，源极电性连接于第三十二P型晶体管的漏极，漏极电性连接于电源低电位；
    一第三十四P型晶体管，所述第三十四P型晶体管的栅极电性连接于第三十二P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于输出端；
    一第三十五N型晶体管，所述第三十五N型晶体管的栅极电性连接于第三十二P型晶体管的漏极，源极电性连接于输出端，漏极电性连接于电源低电位。
  2. 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路，其中，所述GOA电路还包括第二输出控制部分、第二输出缓冲部分；
    所述第二输出控制部分电性连接于输出控制部分、驱动输出端、第M+1 级时序信号、电源高电位与电源低电位；所述第二输出缓冲部分电性连接于所述第二输出控制部分、第N+1级GOA单元的输出端、电源高电位与电源低电位；
    所述第二输出控制部分包括：
    一第三十六P型晶体管，所述第三十六P型晶体管的栅极电性连接于驱动输出端，源极电性连接于电源高电位，漏极电性连接于第三十九N型晶体管的源极；
    一第三十七N型晶体管，所述第三十七N型晶体管的栅极电性连接于驱动输出端，源极电性连接于第三十九N型晶体管的漏极，漏极电性连接于电源低电位；
    一第三十八P型晶体管，所述第三十八P型晶体管的栅极电性连接于第M+1级时序信号，源极电性连接于电源高电位，漏极电性连接于第三十九N型晶体管的源极；
    一第三十九N型晶体管，所述第三十九N型晶体管的栅极电性连接于第M+1级时序信号，源极电性连接于第三十六P型晶体管的漏极，漏极电性连接于第三十七N型晶体管的源极；
    所述第二输出缓冲部分包括：
    一第四十P型晶体管，所述第四十P型晶体管的栅极电性连接于第三十九N型晶体管的源极，源极电性连接于电源高电位，漏极电性连接于第四十一N型晶体管的源极；
    一第四十一N型晶体管，所述第四十一N型晶体管的栅极电性连接于第三十九N型晶体管的源极，源极电性连接于第四十P型晶体管的漏极，漏极电性连接于电源低电位；
    一第四十二P型晶体管，所述第四十二P型晶体管的栅极电性连接于第四十P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于第四十三N型晶体管的源极；
    一第四十三N型晶体管，所述第四十三N型晶体管的栅极电性连接于第四十P型晶体管的漏极，源极电性连接于第四十二P型晶体管的漏极，漏极电性连接于电源低电位；
    一第四十四P型晶体管，所述第四十四P型晶体管的栅极电性连接于第四十二P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于第N+1级GOA单元的输出端；
    一第四十五N型晶体管，所述第四十五N型晶体管的栅极电性连接于第四十二P型晶体管的漏极，源极电性连接于第N+1级GOA单元的输出 端，漏极电性连接于电源低电位。
  3. 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路，其中，所述GOA电路的第一级连接关系中，所述第一P型晶体管的源极、第二N型晶体管的源极、第五P型晶体管的栅极、第七N型晶体管的栅极均电性连接于电路的启动信号端。
  4. 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路，其中，所述GOA电路的最后一级连接关系中，所述第三P型晶体管的源极、第四N型晶体管的源极、第六P型晶体管的栅极、第八N型晶体管的栅极均电性连接于电路的启动信号端。
  5. 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路，其中，所述传输部分中第一P型晶体管和第二N型晶体管构成一正向传输闸，用于将第N-1级GOA单元的驱动输出信号正向传输至资料存储部分；第三P型晶体管和第四N型晶体管构成一反向传输闸，用于将第N+1级GOA单元的驱动输出信号反向传输至资料存储部分。
  6. 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路，其中，所述传输控制部分中第五P型晶体管、第六P型晶体管、第七N型晶体管、第八N型晶体管构成或非门逻辑单元；第九P型晶体管、第十N型晶体管构成反相器；第十一P型晶体管和第十二N型晶体管构成传输闸；所述传输控制部分用于控制第M-2级时序信号，并将其传输到资料存储部分。
  7. 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路，其中，所述资料存储部分中第十五P型晶体管、第十六P型晶体管、第十七N型晶体管、第十八N型晶体管构成正向时序反向器；第十九P型晶体管、第二十P型晶体管、第二十一N型晶体管、第二十二N型晶体管构成反向时序反向器；第十三N型晶体管、第十四P型晶体管构成反向器；所述资料存储部分用于对由第N-1级GOA单元的驱动输出端、第N+1级GOA单元的驱动输出端和第M-2级时序信号传入的信号进行存储和传输。
  8. 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路，其中，所述数据清除部分用于对电路的驱动输出端电位的适时清除。
  9. 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路，其中，所述输出控制部分中第二十六P型晶体管、第二十七N型晶体管、第二十八P型晶体管、第二十九N型晶体管构成与非门逻辑单元；第二十四P型晶体管、第二十五N型晶体管构成反向器；所述输出控制部分用于对输出端输出的扫描信号进行控制，输出符合时序的扫描信号。
  10. 如权利要求1所述的低温多晶硅薄膜晶体管GOA电路，其中，所 述输出缓冲部分中第三十P型晶体管和第三十一N型晶体管、第三十二P型晶体管和第三十三N型晶体管、第三十四P型晶体管和第三十五N型晶体管分别构成三个反向器，用于对经过时序调整的扫描信号进行调整，同时增强带负载能力。
  11. 如权利要求2所述的低温多晶硅薄膜晶体管GOA电路，其中，所述第二输出控制部分中第三十六P型晶体管，第三十七N型晶体管，第三十八P型晶体管、第三十九N型晶体管构成与非门逻辑单元，用于对第N+1级GOA单元的输出端输出的扫描信号进行控制，输出符合时序的扫描信号；所述第二输出缓冲部分中第四十P型晶体管和第四十一N型晶体管、第四十二P型晶体管和第四十三N型晶体管、第四十四P型晶体管和第四十五N型晶体管分别构成三个反向器，用于对经过时序调整的扫描信号进行调整，同时增强带负载能力；所述第二输出控制部分和第二输出缓冲部分依据驱动输出端的输出信号与第M+1级时序信号，由第N+1级GOA单元的输出端输出后一级扫描信号，实现单级GOA单元控制两级电路正反双向扫描输出。
  12. 如权利要求2所述的低温多晶硅薄膜晶体管GOA电路，其中，所述时序信号包括四组时序信号：第一时序信号、第二时序信号、第三时序信号、第四时序信号，当所述时序信号为第一时序信号时，所述第M-2级时序信号为第三时序信号，当所述时序信号为第二时序信号时，所述第M-2级时序信号为第四时序信号，当所述时序信号为第四时序信号，所述第M+1级时序信号为第一时序信号。
  13. 一种低温多晶硅薄膜晶体管GOA电路，用于正反双向扫描传输，包括级联的多个GOA单元，设N为正整数，第N级GOA单元采用多个N型晶体管与多个P型晶体管，所述第N级GOA单元包括：传输部分、传输控制部分、资料存储部分、数据清除部分、输出控制部分及输出缓冲部分；
    所述传输部分电性连接于第一低频信号、第二低频信号、所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端、所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端与所述资料存储部分；所述传输控制部分电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端、所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端、第M-2级时序信号、电源高电位、电源低电位与资料存储部分；所述资料存储部分电性连接于所述传输部分、传输控制部分、数据清除部分、电源高电位与电源低电位；所述数据清除部分电性连接于所述资 料存储部分、输出控制部分、电源高电位与复位信号端；所述输出控制部分电性连接于所述数据清除部分、输出缓冲部分、驱动输出端、时序信号、电源高电位与电源低电位；所述输出缓冲部分电性连于所述输出控制部分、输出端、电源高电位与电源低电位；
    所述第一低频信号和第二低频信号的电位随着正反扫描进行切换，正向扫描时，所述第一低频信号相当于直流高电位，所述第二低频信号相当于直流低电位；反向扫描时，所述第一低频信号相当于直流低电位，所述第二低频信号相当于直流高电位；
    所述传输部分包括一第一P型晶体管，所述第一P型晶体管的栅极电性连接于第二低频信号，源极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端，漏极电性连接于第一节点；一第二N型晶体管，所述第二N型晶体管的栅极电性连接于第一低频信号，源极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端，漏极电性连接于第一节点；一第三P型晶体管，所述第三P型晶体管的栅极电性连接于第一低频信号，源极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端，漏极电性连接于第二节点；一第四N型晶体管，所述第四N型晶体管的栅极电性连接于第二低频信号，源极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端，漏极电性连接于第二节点；
    所述传输控制部分包括：
    一第五P型晶体管，所述第五P型晶体管的栅极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端，源极电性连接于电源高电位，漏极电性连接于第六P型晶体管的源极；
    一第六P型晶体管，所述第六P型晶体管的栅极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端，源极电性连接于第五P型晶体管的漏极，漏极电性连接于第七N型晶体管的源极；
    一第七N型晶体管，所述第七N型晶体管的栅极电性连接于所述第N级GOA单元的前一级第N-1级GOA单元的驱动输出端，源极电性连接于第六P型晶体管的漏极，漏极电性连接于电源低电位；
    一第八N型晶体管，所述第八N型晶体管的栅极电性连接于所述第N级GOA单元的后一级第N+1级GOA单元的驱动输出端，源极电性连接于第六P型晶体管的漏极，漏极电性连接于电源低电位；
    一第九P型晶体管，所述第九P型晶体管的栅极电性连接于第六P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于第十N型晶 体管的源极；
    一第十N型晶体管，所述第十N型晶体管的栅极电性连接于第六P型晶体管的漏极，源极电性连接于第九P型晶体管的漏极，漏极电性连接于电源低电位；
    一第十一P型晶体管，所述第十一P型晶体管的栅极电性连接于第六P型晶体管的漏极，源极电性连接于第十二N型晶体管的源极，漏极电性连接于第M-2级时序信号；
    一第十二N型晶体管，所述第十二N型晶体管的栅极电性连接于第九P型晶体管的漏极，源极电性连接于第十一P型晶体管的源极，漏极电性连接于第M-2级时序信号；
    所述资料存储部分包括：
    一第十三N型晶体管，所述第十三N型晶体管的栅极电性连接于第十一P型晶体管的源极，源极电性连接于第十四P型晶体管的漏极，漏极电性连接于电源低电位；
    一第十四P型晶体管，所述第十四P型晶体管的栅极电性连接于第十一P型晶体管的源极，源极电性连接于电源高电位，漏极电性连接于第十三N型晶体管的源极；
    一第十五P型晶体管，所述第十五P型晶体管的栅极电性连接于第十三N型晶体管的源极，源极电性连接于电源高电位，漏极电性连接于第十六P型晶体管的源极；
    一第十六P型晶体管，所述第十六P型晶体管的栅极电性连接于第一节点，源极电性连接于第十五P型晶体管的漏极，漏极电性连接于第十七N型晶体管的源极；
    一第十七N型晶体管，所述第十七N型晶体管的栅极电性连接于第一节点，源极电性连接于第十六P型晶体管的漏极，漏极电性连接于第十八N型晶体管的源极；
    一第十八N型晶体管，所述第十八N型晶体管的栅极电性连接于第十一P型晶体管的源极，源极电性连接于第十七N型晶体管的漏极，漏极电性连接于电源低电位；
    一第十九P型晶体管，所述第十九P型晶体管的栅极电性连接于第十三N型晶体管的栅极，源极电性连接于电源高电位，漏极电性连接于第二十P型晶体管的源极；
    一第二十P型晶体管，所述第二十P型晶体管的栅极电性连接于第二节点，源极电性连接于第十九P型晶体管的漏极，漏极电性连接于第二十 一N型晶体管的源极；
    一第二十一N型晶体管，所述第二十一N型晶体管的栅极电性连接于第二节点，源极电性连接于第二十P型晶体管的漏极，漏极电性连接于第二十二N型晶体管的源极；
    一第二十二N型晶体管，所述第二十二N型晶体管的栅极电性连接于第十三N型晶体管的源极，源极电性连接于第二十一N型晶体管的漏极，漏极电性连接于电源低电位；
    所述数据清除部分包括：
    一第二十三P型晶体管，所述第二十三P型晶体管的栅极电性连接于复位信号端，源极电性连接于电源高电位，漏极电性连接于第十六P型晶体管的漏极及第二十P型晶体管的漏极；
    所述输出控制部分包括：
    一第二十四P型晶体管，所述第二十四P型晶体管的栅极电性连接于第十六P型晶体管的漏极及第二十P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于驱动输出端；
    一第二十五N型晶体管，所述第二十五N型晶体管的栅极电性连接于第十六P型晶体管的漏极及第二十P型晶体管的漏极，源极电性连接于驱动输出端，漏极电性连接于电源低电位；
    一第二十六P型晶体管，所述第二十六P型晶体管的栅极电性连接于驱动输出端，源极电性连接于电源高电位，漏极电性连接于第二十九N型晶体管的源极；
    一第二十七N型晶体管，所述第二十七N型晶体管的栅极电性连接于驱动输出端，源极电性连接于第二十九N型晶体管的漏极，漏极电性连接于电源低电位；
    一第二十八P型晶体管，所述第二十八P型晶体管的栅极电性连接于时序信号，源极电性连接于电源高电位，漏极电性连接于第二十九N型晶体管的源极；
    一第二十九N型晶体管，所述第二十九N型晶体管的栅极电性连接于时序信号，源极电性连接于第二十六N型晶体管的漏极，漏极电性连接于第二十七N型晶体管的源极；
    所述输出缓冲部分包括：
    一第三十P型晶体管，所述第三十P型晶体管的栅极电性连接于第二十九N型晶体管的源极，源极电性连接于电源高电位，漏极电性连接于第三十一N型晶体管的源极；
    一第三十一N型晶体管，所述第三十一N型晶体管的栅极电性连接于第二十九N型晶体管的源极，源极电性连接于第三十P型晶体管的漏极，漏极电性连接于电源低电位；
    一第三十二P型晶体管，所述第三十二P型晶体管的栅极电性连接于第三十P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于第三十三N型晶体管的源极；
    一第三十三N型晶体管，所述第三十三N型晶体管的栅极电性连接于第三十P型晶体管的漏极，源极电性连接于第三十二P型晶体管的漏极，漏极电性连接于电源低电位；
    一第三十四P型晶体管，所述第三十四P型晶体管的栅极电性连接于第三十二P型晶体管的漏极，源极电性连接于电源高电位，漏极电性连接于输出端；
    一第三十五N型晶体管，所述第三十五N型晶体管的栅极电性连接于第三十二P型晶体管的漏极，源极电性连接于输出端，漏极电性连接于电源低电位；
    其中，所述传输部分中第一P型晶体管和第二N型晶体管构成一正向传输闸，用于将第N-1级GOA单元的驱动输出信号正向传输至资料存储部分；第三P型晶体管和第四N型晶体管构成一反向传输闸，用于将第N+1级GOA单元的驱动输出信号反向传输至资料存储部分；
    其中，所述传输控制部分中第五P型晶体管、第六P型晶体管、第七N型晶体管、第八N型晶体管构成或非门逻辑单元；第九P型晶体管、第十N型晶体管构成反相器；第十一P型晶体管和第十二N型晶体管构成传输闸；所述传输控制部分用于控制第M-2级时序信号，并将其传输到资料存储部分；
    其中，所述资料存储部分中第十五P型晶体管、第十六P型晶体管、第十七N型晶体管、第十八N型晶体管构成正向时序反向器；第十九P型晶体管、第二十P型晶体管、第二十一N型晶体管、第二十二N型晶体管构成反向时序反向器；第十三N型晶体管、第十四P型晶体管构成反向器；所述资料存储部分用于对由第N-1级GOA单元的驱动输出端、第N+1级GOA单元的驱动输出端和第M-2级时序信号传入的信号进行存储和传输。
    其中，所述数据清除部分用于对电路的驱动输出端电位的适时清除；
    其中，所述输出控制部分中第二十六P型晶体管、第二十七N型晶体管、第二十八P型晶体管、第二十九N型晶体管构成与非门逻辑单元；第二十四P型晶体管、第二十五N型晶体管构成反向器；所述输出控制部分 用于对输出端输出的扫描信号进行控制，输出符合时序的扫描信号；
    其中，所述输出缓冲部分中第三十P型晶体管和第三十一N型晶体管、第三十二P型晶体管和第三十三N型晶体管、第三十四P型晶体管和第三十五N型晶体管分别构成三个反向器，用于对经过时序调整的扫描信号进行调整，同时增强带负载能力。
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