WO2016045402A1 - 高密度封装基板孔上盘产品及其制备方法 - Google Patents

高密度封装基板孔上盘产品及其制备方法 Download PDF

Info

Publication number
WO2016045402A1
WO2016045402A1 PCT/CN2015/080246 CN2015080246W WO2016045402A1 WO 2016045402 A1 WO2016045402 A1 WO 2016045402A1 CN 2015080246 W CN2015080246 W CN 2015080246W WO 2016045402 A1 WO2016045402 A1 WO 2016045402A1
Authority
WO
WIPO (PCT)
Prior art keywords
copper
hole
substrate
thickness
preparation
Prior art date
Application number
PCT/CN2015/080246
Other languages
English (en)
French (fr)
Inventor
王名浩
谢添华
李志东
Original Assignee
广州兴森快捷电路科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 广州兴森快捷电路科技有限公司 filed Critical 广州兴森快捷电路科技有限公司
Publication of WO2016045402A1 publication Critical patent/WO2016045402A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections

Definitions

  • the invention relates to the technical field of printed circuit board manufacturing, in particular to a high-density package substrate hole upper disc product and a preparation method thereof.
  • the Flip-chip structure package substrate is characterized in that the connection points are changed from a peripheral distribution to a planar array, and the connection mode with the chip is also changed from a conventional gold/copper wire to a small-sized solder ball.
  • the technology of directly connecting the array-type surface-distributing solder balls to the chip requires very high flatness of the package substrate, and also poses many new challenges to the fabrication process of the package substrate. One of the most critical ones is the high-flatness soldering surface. Production.
  • the hole-on-disk structure has been used in a large number of interconnected products due to its very low position of the via hole.
  • the hole-on-disk structure used in the industry is mostly based on plug hole or electroplating hole filling process, wherein the plug hole process requires mechanical grinding, which is difficult to correspond to products with a thickness of 0.1 mm or less; although the plating hole filling process can correspond to thin plate processing,
  • the interlayer conduction structure is limited by the MSAP (modified semi-additive) process.
  • the double-layer product is usually limited to the via structure. In the case of electroplating filling, the indentation of the aperture is inevitable, and it is difficult to meet the high flatness of the soldering surface. Requirements.
  • the flatness of the bottom of the blind hole is not affected by the hole structure.
  • the use of a semi-through blind hole instead of the through hole for electroplating filling is expected to solve the problem of pad flatness.
  • the thin copper substrate used in the MSAP process is easily penetrated during the processing, and it is difficult to ensure the flatness, and the through hole is more likely to cause poor plating and affect product reliability.
  • an object of the present invention is to provide a method for preparing a high-density package substrate on-hole disk product.
  • a method for preparing a high-density package substrate hole upper disc product comprises the following steps:
  • a baking sheet baking a thin copper substrate having a thickness of ⁇ 0.1 mm, wherein a surface of the copper foil of the thin copper substrate is adhered with a protective film layer;
  • Drying operation can increase the dimensional stability of the product.
  • Making a positioning hole making at least one set of positioning through holes in a non-functional area of the thin copper substrate;
  • Laser drilling removing the protective film layer on the side of the thin copper substrate, exposing the laser processing region, and performing a drilling operation using a laser to form a semi-through hole having a depth of copper on the side of the thin copper substrate The sum of the thickness of the foil and the thickness of the dielectric layer of the thin copper substrate;
  • the present invention controls the amount of microetching to be between 0.5 and 1 ⁇ m, and then uses short pulse laser parameters to concentrate energy to remove the surface copper foil.
  • the energy of the laser used for processing is 1.5-15 mJ
  • the pulse width of the laser is controlled at 5-12 ⁇ s
  • the number of control pulses is 3-8 times. The energy gradually eliminates the copper foil and the resin one by one, without local overheating causing damage to the bottom copper;
  • Micro-etching etching the thin copper substrate after laser drilling, controlling the micro-etching amount to be 0.5-1 ⁇ m;
  • Copper sinking removing the protective film layer on the other side of the thin copper substrate, and then performing a full-plate copper sinking operation;
  • Pattern transfer the full-board copper-plated circuit board is subjected to dry film deposition and exposure development operation to expose the plating area and the semi-through hole;
  • Electroplating and filling holes performing electroplating operation on the circuit board after the transfer of the pattern, so that the semi-through holes are filled with copper;
  • Ejection etching the circuit board after the electroplating copper operation is subjected to a film-removing and etching operation, and then a post-process (the post-process may include a process of solder resist fabrication and surface treatment) to obtain the high-density package substrate. Hole plate product.
  • the copper foil has a copper foil thickness of 2-4 ⁇ m and the protective film layer has a thickness of 18-35 ⁇ m.
  • the baking process parameters are: baking at 150-190 ° C for 2-4 h.
  • the energy of the laser used is 1.5-15 mJ
  • the pulse width of the laser is controlled at 5-12 ⁇ s
  • the number of control pulses is 3-8 times.
  • the operation also includes roughening the copper surface by 0.5-1 ⁇ m.
  • the open end aperture to the bottom aperture ratio of the semi-through hole is 1:0.6-0.8, and the open end aperture to hole depth ratio is 1:0.3-1.
  • the copper thickness of the full plate sinking copper is 0.5-1 ⁇ m.
  • the electroplated copper in the electroplating copper step, has a current density of 3-20 ASF (amperes per square foot), a current time of 30-120 min, and a copper plating thickness of 5-25 ⁇ m.
  • the current density of the electroplated copper is 3-12 ASF, the current time is 80-120 min, and the copper thickness of the electroplated copper is 5-15 ⁇ m.
  • Another object of the present invention is to provide a high density package substrate hole upper disc product.
  • the high-density package substrate hole-upper product prepared by the above preparation method.
  • the invention uses a thin copper substrate with a protective film layer, adopts a method of removing the protective layer in batches, optimizes the laser processing flow, forms a complete semi-through hole structure, and realizes interlayer interconnection after being filled by electroplating. According to the normal MSAP, a hole-up structure product with a very flat welding surface is produced.
  • the invention intelligently utilizes the function of the protective layer of the thin copper substrate.
  • the protective film layer can resist the impact on the bottom copper when the hole is formed, and has a certain strength supporting effect, and on the other hand, the excess heat of the bottom can be timely Pass around. Therefore, the present invention overcomes the problem of the bottom copper foil penetration during the processing of the thin copper in the past.
  • a complete semi-through-hole structure is formed on the thin copper substrate; at the same time, the technology utilizes direct laser processing technology, does not affect the thickness of the copper foil, and is well matched with the MSAP process, and can produce a high-flatness upper-hole structure. Density Flip-chip products.
  • FIG. 1 is a schematic structural view of a substrate used in an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a circuit board obtained after laser drilling according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a circuit board obtained after a full-plate copper sinking operation according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a circuit board obtained after a graphics transfer operation according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural view of a circuit board obtained after copper plating operation according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural view of a circuit board obtained after a film stripping operation according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural view of a circuit board obtained after an etching operation according to an embodiment of the present invention.
  • Figure 8 is a schematic view showing the structure of the product after the post-process of the present invention.
  • Fig. 9 is a schematic view of a product obtained by a conventional through hole manufacturing method.
  • a method for preparing a high-density package substrate hole upper disc product comprises the following steps:
  • the substrate material used for the material discharge is as shown in FIG. 1 (the thin copper substrate includes the dielectric layer 101, the copper foil 102, and the protective film layer 103).
  • the substrate has a thickness of 0.1 mm, and a copper foil (having a thickness of 2-4 ⁇ m) has a protective copper foil having a thickness of about 18-35 ⁇ m on the outer side.
  • the protective layer and the copper foil are connected by an extremely thin adhesive, which can be mechanically separated from the substrate. The adhesive is easily removed by the degreased glue and does not remain on the surface of the substrate.
  • Thin copper substrate material is an indispensable raw material for making fine lines. Generally, the thinner the copper thickness, the line The higher the manufacturing capability, the higher the wiring density of the package substrate. However, since the thickness of the copper foil is only 2-4 ⁇ m, it is extremely easy to penetrate during the drilling operation.
  • Drying board The thin copper substrate is baked at 150-190 ° C for 2-4 h; the baking operation can improve the dimensional stability of the product.
  • each set of positioning through holes is composed of at least four mechanical through holes having a hole diameter of 0.5-3.5 mm.
  • the non-functional area that is, the edge portion or the board surface of the package substrate has no graphic portion, and the positioning through hole is formed in the non-functional area of the package substrate, thereby minimizing the influence of the positioning through hole on the basic line and function of the package, and the straight type mechanical mechanism
  • the through hole can reduce the influence of the positional deviation of the positioning target on the alignment of the front and back, and can obtain a more accurate positioning effect.
  • Laser drilling removing the protective film layer on one side of the thin copper substrate (the process of removing the upper surface protective layer needs to start from one side or one corner at a uniform speed to prevent substrate damage.
  • the upper layer is removed.
  • the asymmetric structure is easy to warp.
  • the steel plate is baked for more than half an hour to make the substrate flat.
  • the laser processing area is exposed, and the laser is used for drilling operation to form a semi-through.
  • a hole 107 shown in Figure 2
  • the depth of the semi-through hole is the sum of the thickness of the copper foil and the thickness of the thin copper substrate dielectric layer, leaving the copper foil on the other side;
  • the copper surface laser reflection ability is very strong, it is usually necessary to roughen the copper surface by 1-2 ⁇ m before the carbon dioxide laser processing to increase the absorption rate of the copper surface.
  • the substrate itself is thin copper, it is generally controlled to have a micro-etching amount of 0.5-1 ⁇ m, and then processed using a short-pulse high-energy laser.
  • the energy of the laser used for processing is 1.5-15 mJ, the pulse width of the laser is controlled at 5-12 ⁇ s, and the number of control pulses is 3-8 times. The energy quickly and quickly eliminates the copper foil and the resin without local overheating causing damage to the bottom copper.
  • the pore sizes corresponding to Experiments 1-3 were 60 um, 80 um, and 100 um, respectively. By increasing the number of pulses and reducing the pulse width, a good hole-forming effect can be obtained.
  • the pulse width is long, the energy is diffused on the upper surface, the energy in the middle region is too large, and the energy in the peripheral region is too small, so that it is difficult to form a complete pore shape, and the penetration and resin residue coexist.
  • the ratio of the aperture end aperture to the bottom aperture of the semi-through hole is 1:0.6-0.8, and the aperture diameter to hole depth ratio of the open end is 1:05-1.
  • Micro-etching controlling the amount of micro-etching to be 0.5-1 ⁇ m;
  • Copper sinking removing the protective film layer on the other side of the thin copper substrate, and then performing a full-plate copper sinking operation (as shown in FIG. 3), and the copper-thickness layer 104 obtained by sinking the whole copper plate has a copper thickness of 0.5-1 ⁇ m. ;
  • Pattern transfer the full-board copper-plated circuit board is adhered to the dry film 105, and the exposure and development operation is performed to expose the plating area and the semi-through hole (as shown in FIG. 4);
  • Electroplating and filling the circuit board after the transfer of the pattern is subjected to electroplating copper operation, so that the semi-through hole is filled with copper 106 (as shown in FIG. 5, the case of filling the hole as shown in the figure is an ideal state, actually The copper surface filled in the opening of the semi-through hole in production cannot be completely flat), the current density of electroplated copper is 3-20ASF (amperes per square foot), the current time is 30-120min, and the copper thickness of electroplated copper is 5 -25 ⁇ m;
  • Ejection etching the circuit board after the electroplating copper operation is subjected to film peeling (as shown in FIG. 6), an etching operation (as shown in FIG. 7), and then a post-process (the post-process may include solder resist fabrication, The step of surface treatment) is to produce the high-density package substrate hole-upper product.
  • the position marked 4 is the copper surface filled in the opening of the semi-through hole, and the copper surface may not be completely flat in actual production, but the solder ball is filled due to the post process. 2
  • the volume is large, and the unevenness of the copper surface does not affect the height of the solder ball of the whole plate;
  • the position marked with 3 is the copper surface corresponding to the bottom of the semi-through hole, and the copper surface at this position is not penetrated due to the operation in the drilling.
  • the copper foil of the substrate enables the copper surface to be kept flat at all times, and the height of each solder ball can be ensured even when the volume of the solder ball 1 filled in the later process is small, and a high-flatness welding surface is obtained to ensure the electrical quality of the entire product. performance.
  • FIG. 9 The schematic diagram of the product obtained by the existing through hole manufacturing method is shown in FIG. 9, wherein the depression in the upper part of the through hole absorbs part of the solder paste, resulting in insufficient height of the solder ball and failure to be soldered normally.
  • the invention uses a thin copper substrate with a protective film layer, adopts a method of removing the protective layer in batches, optimizes the laser processing flow, forms a complete semi-through hole structure, and realizes interlayer interconnection after being filled by electroplating. According to the normal MSAP, a hole-up structure product with a very flat welding surface is produced.
  • the invention intelligently utilizes the function of the protective layer of the thin copper substrate, overcomes the problem of the bottom copper foil penetration in the process of the thin copper processing, and forms a complete semi-through hole structure on the thin copper substrate; at the same time, the technology utilizes direct laser processing technology It does not affect the thickness of the copper foil, and is well matched with the MSAP process to produce a high-density Flip-chip product with a high-flatness hole-on-disk structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Laser Beam Processing (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

一种高密度封装基板孔上盘产品及其制备方法，制备方法包括如下步骤：烘板、制作定位孔、激光钻孔、微蚀、沉铜、图形转移、电镀填孔、退膜蚀刻即得高密度封装基板孔上盘产品。利用薄铜基板保护膜层（103）的作用，克服了以往薄铜加工过程中底部铜箔（102）贯通问题，在薄铜基板上制作出完整的半贯通孔（107）结构；同时该技术利用直接激光加工技术，不影响铜箔厚度，与MSAP工艺很好的匹配，可制作出具有高平整度孔上盘结构的高密度Flip-chip产品。

Description

高密度封装基板孔上盘产品及其制备方法 技术领域
本发明涉及印制线路板制作技术领域，特别是涉及一种高密度封装基板孔上盘产品及其制备方法。
背景技术
作为半导体芯片的载体，封装基板的主要功能之一是芯片和线路板之间的过度结构。为适应更高密度封装要求，超薄Flip-chip结构的封装产品已引起业内的广泛兴趣并在近年得到迅速发展。与传统Wire-bonding结构相比，Flip-chip结构封装基板的特点是连接点由周边分布变为平面阵列分布，与芯片连接方式也由传统的金/铜线变为小尺寸锡球。这种阵列式面分布锡球直接与芯片连接的技术对封装基板的平整度要求非常高，也对封装基板的制作工艺提出了很多新的挑战，其中非常关键的一项就是高平整度焊接面的制作。
孔上盘结构因其非常低的导通孔位置占比优势已在更高互联产品中大量使用。而目前业内使用的孔上盘结构大多基于塞孔或电镀填孔工艺，其中塞孔工艺需使用机械研磨，难以对应厚度0.1mm及以下的产品；电镀填孔工艺虽可对应薄板加工，但其层间导通结构受MSAP(改良半加成)制程的限制，双层产品通常仅限于通孔结构，在电镀填充时孔口不可避免的存在凹陷或凸起，也难以满足焊接面高平整度的要求。
盲孔底部平整性不受孔结构的影响，如使用半贯通的盲孔取代通孔进行电镀填充，有望解决焊盘平整性问题。但MSAP制程使用的薄铜基板在加工过程中底部铜箔极易被贯通，很难保证平整度，且具备贯穿孔更容易导致电镀不良，影响产品可靠性。
发明内容
基于此，本发明的目的是提供一种高密度封装基板孔上盘产品的制备方法。
具体的技术方案如下：
一种高密度封装基板孔上盘产品的制备方法，包括如下步骤：
烘板：将薄铜基板进行烘烤，所述薄铜基板的厚度为≤0.1mm，所述薄铜基板的铜箔表面粘覆有保护膜层；
烘板操作可以提高产品的尺寸稳定性。
制作定位孔：在所述薄铜基板的非功能区域制作至少一组定位通孔；
激光钻孔：移除所述薄铜基板一侧的保护膜层，露出激光加工区域，采用激光进行钻孔操作，形成半贯通孔，所述半贯通孔的深度为薄铜基板一侧的铜箔的厚度与薄铜基板介质层的厚度的总和；
由于铜面激光反射能力很强，通常二氧化碳激光加工前需对铜面进行1-2μm的粗化处理，以提高铜面的吸光率。但由于基板本身是薄铜，难以进行有效粗化，因而本发明控制微蚀量为0.5-1μm之间，然后使用短脉冲激光参数使能量集中以去除表面铜箔。此外，为避免过高的能量损坏底铜的完整性，加工所用激光的能量为1.5-15毫焦，激光的脉冲宽度控制在5-12μs，控制脉冲次数为3-8次，可以尽量使激光能量逐次快速的消除铜箔和树脂，而不至于局部过热导致底铜损伤；
微蚀：将激光钻孔后的薄铜基板进行蚀刻操作，控制微蚀量为0.5-1μm；
控制合适的微蚀量，即消除孔口的残留铜，同时避免底铜过度蚀刻；微蚀步骤后还可以进行除胶操作，清理整平孔内树脂，去除孔底杂物，提高孔的导通性；
沉铜：移除所述薄铜基板另一侧的保护膜层，然后进行全板沉铜操作；
图形转移：将全板沉铜后的线路板进行贴干膜、曝光显影操作，露出电镀区域和所述半贯通孔；
电镀填孔：将图形转移后的线路板进行电镀铜操作，使所述半贯通孔中填满铜；
退膜蚀刻：将进行电镀铜操作后的线路板进行退膜、蚀刻操作，然后再进行后工序(所述后工序可以包括阻焊制作、表面处理的工序)制作即得所述高密度封装基板孔上盘产品。
在其中一个实施例中，所述薄铜基板的铜箔厚度为2-4μm，所述保护膜层的厚度为18-35μm。
在其中一个实施例中，所述烘烤的工艺参数为：在150-190℃条件下烘烤2-4h。
在其中一个实施例中，所述激光钻孔步骤中，采用的激光的能量为1.5-15毫焦，激光的脉冲宽度控制在5-12μs，控制脉冲次数为3-8次，所述钻孔操作还包括对铜面进行0.5-1μm的粗化处理。
在其中一个实施例中，所述激光钻孔步骤中，所述半贯通孔的开口端孔径与底部孔径比为1:0.6-0.8，开口端孔径与孔深度比为1:0.3-1。
在其中一个实施例中，所述沉铜步骤中，全板沉铜的铜厚为0.5-1μm。
在其中一个实施例中，所述电镀铜步骤中，电镀铜的电流密度为3-20ASF(安培/平方英尺)，电流时间为30-120min，电镀铜的铜厚为5-25μm。
在其中一个实施例中，所述电镀铜步骤中，电镀铜的电流密度为3-12ASF，电流时间为80-120min，电镀铜的铜厚为5-15μm。
本发明的另一目的是提供一种高密度封装基板孔上盘产品。
具体的技术方案如下：
上述制备方法制备得到的高密度封装基板孔上盘产品。
本发明的有益效果如下：
本发明使用一种带保护膜层的薄铜基板，采用分批次去除保护层的方式，优化了激光加工流程，形成了完整的半贯通孔结构，再经电镀填充后实现层间互联，可按照正常MSAP制作出焊接面非常平整的孔上盘结构产品。
本发明巧妙的利用薄铜基板保护膜层的作用，一方面保护膜层可抵挡成孔时对底铜的冲击，起到一定的强度支撑作用，另一方面也可以及时将底部多余的热量向四周传递。因而本发明克服了以往薄铜加工过程中底部铜箔贯通问题， 在薄铜基板上制作出完整的半贯通孔结构；同时该技术利用直接激光加工技术，不影响铜箔厚度，与MSAP工艺很好的匹配，可制作出具有高平整度孔上盘结构的高密度Flip-chip产品。
附图说明
图1为本发明实施例所使用的基板结构示意图；
图2为本发明实施例激光钻孔后得到的线路板的结构示意图；
图3为本发明实施例全板沉铜操作后得到的线路板的结构示意图；
图4为本发明实施例图形转移操作后得到的线路板的结构示意图；
图5为本发明实施例电镀铜操作后得到的线路板的结构示意图；
图6为本发明实施例退膜操作后得到的线路板的结构示意图；
图7为本发明实施例蚀刻操作后得到的线路板的结构示意图；
图8为本发明后工序制作后的产品结构示意图；
图9为现有的通孔制作方法得到的产品示意图。
具体实施方式
以下结合实施例和附图对本申请做进一步的阐述。
参考图1-7，一种高密度封装基板孔上盘产品的制备方法，包括如下步骤：
开料—烘板——制作定位孔——移除上表面保护层——激光钻孔——微蚀——移除下表面保护层——除胶——沉化学铜——MSAP流程——电镀填孔——MSAP退膜——MSAP蚀刻——后工序。
其中开料使用的基板材料如图1所示(薄铜基板包括介质层101、铜箔102和保护膜层103)。与传统的覆铜基板材料不同，该基板的厚度为0.1mm，其铜箔(厚度为2-4μm)的外侧带有一层厚度约18-35μm的保护铜箔。保护层与铜箔之间通过极薄的粘结剂连接，可以利用机械方式将其与基板分离。粘结剂极易被除胶药水去除，不会在基板表面残留。
薄铜基板材料是制作精细线路必不可少的原材料，通常铜厚越薄，其线路 制作能力越高，可对应更高布线密度的封装基板。但由于铜箔的厚度仅2-4μm，钻孔操作中极易贯穿。
烘板：将薄铜基板在150-190℃条件下烘烤2-4h；烘板操作可以提高产品的尺寸稳定性。
制作定位孔：在所述薄铜基板的非功能区域制作至少一组定位通孔；每组定位通孔由至少四个孔径为0.5-3.5mm的机械通孔组成。所述非功能区域即封装基板的边缘部分或板面无图形部分，在封装基板非功能区域制作定位通孔，最大限度的降低定位通孔对封装基本线路和功能的影响，并且直型的机械通孔可以减小定位靶标位置偏差对正反面对准度的影响，能够得到更加准确的定位效果。
激光钻孔：移除所述薄铜基板一侧的保护膜层(移除上表面保护层工序需以均匀的速度从一侧或一角开始，防止基板损伤。此外，由于基板薄，移除上表面铜箔后会形成不对称结构很容易翘曲，为避免产生翘曲，用钢板压板烘烤半小时以上，使基板恢复平整)，露出激光加工区域，采用激光进行钻孔操作，形成半贯通孔107(如图2所示)，所述半贯通孔的深度为铜箔的厚度与薄铜基板介质层的厚度的总和，保留另一侧的铜箔；
由于铜面激光反射能力很强，通常二氧化碳激光加工前需对铜面进行1-2μm的粗化处理，以提高铜面的吸光率。但由于基板本身是薄铜，一般控制微蚀量为0.5-1μm，然后使用短脉冲的高能激光加工。此外，为避免过高的能量损坏底铜的完整性，加工所用激光的能量为1.5-15毫焦，激光的脉冲宽度控制在5-12μs，控制脉冲次数为3-8次，可尽量使激光能量逐次快速的消除铜箔和树脂，而不至于局部过热导致底铜损伤。
采用不同激光参数钻孔的效果比较如下表：
Figure PCTCN2015080246-appb-000001
Figure PCTCN2015080246-appb-000002
实验1-3对应的孔径分别为60um、80um、100um。通过增加脉冲次数，减小脉冲宽度，均可得到良好成孔效果。
实验4中的能量高，大量的能量集中在底部，导致底铜击穿；
实验5中的脉宽长，能量在上表面扩散，中部区域能量过大，周边区域能量过小，因而难以形成完整的孔型，穿透、树脂残留并存。
所述半贯通孔的开口端孔径与底部孔径比为1:0.6-0.8，开口端孔径与孔深度比为1:05-1。
微蚀：控制微蚀量为0.5-1μm；
控制合适的微蚀量，即消除孔口的残留铜，同时避免底铜过度蚀刻；微蚀步骤后还可以进行除胶操作，清理整平孔内树脂，去除孔底杂物，提高孔的导通性；
沉铜：移除所述薄铜基板另一侧的保护膜层，然后进行全板沉铜操作(如图3所示)，全板沉铜得到的沉铜层104的铜厚为0.5-1μm；
图形转移：将全板沉铜后的线路板进行贴干膜105、曝光显影操作，露出电镀区域和所述半贯通孔(如图4所示)；
电镀填孔：将图形转移后的线路板进行电镀铜操作，使所述半贯通孔中填满铜106(如图5所示，图中所示填孔的情况是理想状态下的情形，实际生产中半贯通孔的开口部填充的铜面不可能是完全平整的)，电镀铜的电流密度为3-20ASF(安培/平方英尺)，电流时间为30-120min，电镀铜的铜厚为5-25μm；
该步骤中需要对电镀铜的工艺参数进行很好的控制，以保证填孔的效果：
实验序号 电流密度 电流时间 铜厚 平整度
1 10.5 120 15 高
2 3 120 5 高
3 20 75 25 一般
4 25 75 30 一般
实验1和2使用小电流密度(3-12ASF)，长电流时间(80-120min)加工，其表面平整度效果更好(得到的铜厚为2-15μm)。实验3和4中孔口凹陷明显，但也满足5μm规格要求。
退膜蚀刻：将进行电镀铜操作后的线路板进行退膜(如图6所示)、蚀刻操作(如图7所示)，然后再进行后工序(所述后工序可以包括阻焊制作、表面处理的工序)制作即得所述高密度封装基板孔上盘产品。
图8为后工序制作后的产品示意图，其中标注④的位置是半贯通孔的开口部填充的铜面，在实际生产中该铜面不可能是完全平整的，但由于后工序填充的锡球②体积较大，铜面细微的不平整不会影响版面整体的锡球高度；其中标注③的位置是半贯通孔底部对应的铜面，该位置的铜面由于在钻孔的操作中没有贯通基板的铜箔，使得铜面始终能够保持平整，在后工序填充的锡球①体积较小的情况下也能够保证各个锡球的高度一致，得到高平整度的焊接面，保证整个产品的电气性能。
采用现有的通孔制作方法得到的产品示意图如图9所示，其中通孔上部的凹陷会吸收部分锡膏，导致锡球高度不够，无法正常焊接。
本发明使用一种带保护膜层的薄铜基板，采用分批次去除保护层的方式，优化了激光加工流程，形成了完整的半贯通孔结构，再经电镀填充后实现层间互联，可按照正常MSAP制作出焊接面非常平整的孔上盘结构产品。
本发明巧妙的利用薄铜基板保护膜层的作用，克服了以往薄铜加工过程中底部铜箔贯通问题，在薄铜基板上制作出完整的半贯通孔结构；同时该技术利用直接激光加工技术，不影响铜箔厚度，与MSAP工艺很好的匹配，可制作出具有高平整度孔上盘结构的高密度Flip-chip产品。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种高密度封装基板孔上盘产品的制备方法，其特征在于，包括如下步骤：
    烘板：将薄铜基板进行烘烤，所述薄铜基板的厚度为≤0.1mm，所述薄铜基板的铜箔表面粘覆有保护膜层；
    制作定位孔：在所述薄铜基板的非功能区域制作至少一组定位通孔；
    激光钻孔：移除所述薄铜基板一侧的保护膜层，露出激光加工区域，采用激光进行钻孔操作，形成半贯通孔，所述半贯通孔的深度为薄铜基板一侧的铜箔的厚度与薄铜基板介质层的厚度的总和；
    微蚀：将激光钻孔后的薄铜基板进行蚀刻操作；
    沉铜：移除所述薄铜基板另一侧的保护膜层，然后进行全板沉铜操作；
    图形转移：将全板沉铜后的线路板进行贴干膜、曝光显影操作，露出电镀区域和所述半贯通孔；
    电镀填孔：将图形转移后的线路板进行电镀铜操作，使所述半贯通孔中填满铜；
    退膜蚀刻：将进行电镀铜操作后的线路板进行退膜、蚀刻操作，然后再进行后工序制作即得所述高密度封装基板孔上盘产品。
  2. 根据权利要求1所述的制备方法，其特征在于，所述薄铜基板的铜箔厚度为2-4μm，所述保护膜层的厚度为18-35μm。
  3. 根据权利要求1所述的制备方法，其特征在于，所述烘烤的工艺参数为：在150-190℃条件下烘烤2-4h。
  4. 根据权利要求1所述的制备方法，其特征在于，所述激光钻孔步骤中，采用的激光的能量为1.5-15毫焦，激光的脉冲宽度控制在5-12μs，控制脉冲次数为3-8次，所述钻孔操作还包括对铜面进行0.5-1μm的粗化处理。
  5. 根据权利要求1所述的制备方法，其特征在于，所述激光钻孔步骤中， 所述半贯通孔的开口端孔径与底部孔径比为1:0.6-0.8，开口端孔径与孔深度比为1:0.3-1。
  6. 根据权利要求1所述的制备方法，其特征在于，所述微蚀步骤中，控制微蚀量为0.5-1μm。
  7. 根据权利要求1所述的制备方法，其特征在于，所述沉铜步骤中，全板沉铜的铜厚为0.5-1μm。
  8. 根据权利要求1所述的制备方法，其特征在于，所述电镀铜步骤中，电镀铜的电流密度为3-20ASF，电流时间为30-120min，电镀铜的铜厚为5-25μm。
  9. 根据权利要求8所述的制备方法，其特征在于，所述电镀铜步骤中，电镀铜的电流密度为3-12ASF，电流时间为80-120min，电镀铜的铜厚为5-15μm。
  10. 权利要求1-9任一项所述制备方法制备得到的高密度封装基板孔上盘产品。
PCT/CN2015/080246 2014-09-28 2015-05-29 高密度封装基板孔上盘产品及其制备方法 WO2016045402A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410512534.2 2014-09-28
CN201410512534.2A CN104270888B (zh) 2014-09-28 2014-09-28 高密度封装基板孔上盘产品及其制备方法

Publications (1)

Publication Number Publication Date
WO2016045402A1 true WO2016045402A1 (zh) 2016-03-31

Family

ID=52162349

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/080246 WO2016045402A1 (zh) 2014-09-28 2015-05-29 高密度封装基板孔上盘产品及其制备方法

Country Status (2)

Country Link
CN (1) CN104270888B (zh)
WO (1) WO2016045402A1 (zh)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106061141A (zh) * 2016-07-28 2016-10-26 江苏博敏电子有限公司 一种高密度印制线路薄板的制作方法
CN107278036A (zh) * 2017-08-07 2017-10-20 四川九立微波有限公司 一种数控衰减器qfn封装器件接地焊盘的电路板的加工方法
CN109392256A (zh) * 2017-08-14 2019-02-26 东莞市国盈电子有限公司 一种防止残铜的半沉铜孔线路板及其制造方法
CN111343800A (zh) * 2020-03-18 2020-06-26 四川英创力电子科技股份有限公司 一种盲埋孔局部电镀的加工工艺
CN111698836A (zh) * 2020-06-02 2020-09-22 湖南维胜科技有限公司 一种vcm弹片及其加工方法
CN113784521A (zh) * 2021-09-06 2021-12-10 大连崇达电路有限公司 一种改善pth通孔上锣沉孔或平台时扯铜的制作方法
CN113811090A (zh) * 2021-09-29 2021-12-17 上达电子（黄石）股份有限公司 一种微孔工艺替代盲孔工艺的fpc制作方法及fpc板
CN114222445A (zh) * 2021-11-09 2022-03-22 深圳市景旺电子股份有限公司 一种电路板制作方法及电路板
CN114980528A (zh) * 2022-06-28 2022-08-30 生益电子股份有限公司 一种背钻对准度检测方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104270888B (zh) * 2014-09-28 2017-10-17 广州兴森快捷电路科技有限公司 高密度封装基板孔上盘产品及其制备方法
CN105451447A (zh) * 2015-10-22 2016-03-30 苏州市华扬电子有限公司 一种手机电池板制作时线路的对位方法
CN109219251B (zh) * 2018-08-30 2020-11-13 广州广合科技股份有限公司 一种挠性电路板精细线路的制作方法
CN109511225B (zh) * 2018-09-25 2021-01-08 通元科技(惠州)有限公司 一种半金属化孔线路板加工方法
CN109348651A (zh) * 2018-10-16 2019-02-15 欣强电子（清远）有限公司 一种elic pcb板件内层对位加工方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030064325A1 (en) * 2001-10-03 2003-04-03 Unitech Printed Circuit Board Corp. Method of manufacturing printed circuit board having wiring layers electrically connected via solid cylindrical copper interconnecting bodies
CN102711385A (zh) * 2012-06-26 2012-10-03 北京凯迪思电路板有限公司 一种加成法制作线路板的方法
CN103369867A (zh) * 2012-04-01 2013-10-23 北大方正集团有限公司 印刷电路板（pcb）的制作方法以及pcb
CN104270888A (zh) * 2014-09-28 2015-01-07 广州兴森快捷电路科技有限公司 高密度封装基板孔上盘产品及其制备方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100632556B1 (ko) * 2005-01-28 2006-10-11 삼성전기주식회사 인쇄회로기판의 제조방법
KR101701380B1 (ko) * 2010-08-17 2017-02-01 해성디에스 주식회사 소자 내장형 연성회로기판 및 이의 제조방법
CN103442529B (zh) * 2013-08-22 2016-08-10 电子科技大学 一种印制电路高密度叠孔互连方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030064325A1 (en) * 2001-10-03 2003-04-03 Unitech Printed Circuit Board Corp. Method of manufacturing printed circuit board having wiring layers electrically connected via solid cylindrical copper interconnecting bodies
CN103369867A (zh) * 2012-04-01 2013-10-23 北大方正集团有限公司 印刷电路板（pcb）的制作方法以及pcb
CN102711385A (zh) * 2012-06-26 2012-10-03 北京凯迪思电路板有限公司 一种加成法制作线路板的方法
CN104270888A (zh) * 2014-09-28 2015-01-07 广州兴森快捷电路科技有限公司 高密度封装基板孔上盘产品及其制备方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106061141A (zh) * 2016-07-28 2016-10-26 江苏博敏电子有限公司 一种高密度印制线路薄板的制作方法
CN107278036A (zh) * 2017-08-07 2017-10-20 四川九立微波有限公司 一种数控衰减器qfn封装器件接地焊盘的电路板的加工方法
CN109392256A (zh) * 2017-08-14 2019-02-26 东莞市国盈电子有限公司 一种防止残铜的半沉铜孔线路板及其制造方法
CN111343800A (zh) * 2020-03-18 2020-06-26 四川英创力电子科技股份有限公司 一种盲埋孔局部电镀的加工工艺
CN111698836A (zh) * 2020-06-02 2020-09-22 湖南维胜科技有限公司 一种vcm弹片及其加工方法
CN111698836B (zh) * 2020-06-02 2023-03-24 湖南维胜科技有限公司 一种vcm弹片及其加工方法
CN113784521A (zh) * 2021-09-06 2021-12-10 大连崇达电路有限公司 一种改善pth通孔上锣沉孔或平台时扯铜的制作方法
CN113811090A (zh) * 2021-09-29 2021-12-17 上达电子（黄石）股份有限公司 一种微孔工艺替代盲孔工艺的fpc制作方法及fpc板
CN114222445A (zh) * 2021-11-09 2022-03-22 深圳市景旺电子股份有限公司 一种电路板制作方法及电路板
CN114980528A (zh) * 2022-06-28 2022-08-30 生益电子股份有限公司 一种背钻对准度检测方法

Also Published As

Publication number Publication date
CN104270888A (zh) 2015-01-07
CN104270888B (zh) 2017-10-17

Similar Documents

Publication Publication Date Title
WO2016045402A1 (zh) 高密度封装基板孔上盘产品及其制备方法
JP5456103B2 (ja) 配線基板及び半導体装置の製造方法
US11881414B2 (en) Method for manufacturing glass device, and glass device
JP4658974B2 (ja) キャビティの形成された基板製造方法
WO2017071394A1 (zh) 印制线路板及其制作方法
CN105517370B (zh) 电路板焊盘加工方法
CN103687337A (zh) 封装基板通孔的激光加工方法
JP4648277B2 (ja) キャビティを備えた基板の製造方法
US10874021B2 (en) Manufacturing method for wiring board
JP4384157B2 (ja) キャビティを備えた基板の製造方法
WO2022156321A1 (zh) 一种用于制作高密度互连线路板的方法
JP2013051397A (ja) 配線基板の製造方法
JP4817139B2 (ja) 孔版印刷用のマスク及びその製造方法
JP2005144973A (ja) 孔版印刷用のマスク
JP2007208153A (ja) 半導体装置及びその製造方法
KR20060070930A (ko) 패키지 기판의 제조 방법
JP2012099768A (ja) 配線基板の製造方法
CN109661116B (zh) 一种线路板定位盲孔底盘缺损补救方法
CN105575923A (zh) 基板结构及其制法
KR20080100111A (ko) 고밀도 패키지 기판 제조 방법
JP5163840B2 (ja) 孔版印刷用のマスク及びその製造方法
CN118173451A (zh) Fcbga封装基板及其制备方法
WO2019090860A1 (zh) 一种选择性厚铜线路制作方法
CN116634684A (zh) 一种减少半电镀通孔孔口铜皮拉扯应力的加工方法
CN117500191A (zh) 一种嵌铜块基板及其制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15845248

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC

122 Ep: pct application non-entry in european phase

Ref document number: 15845248

Country of ref document: EP

Kind code of ref document: A1