WO2016042738A1 - Dispositif à semi-conducteur au carbure de silicium et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur au carbure de silicium et son procédé de fabrication Download PDF

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WO2016042738A1
WO2016042738A1 PCT/JP2015/004569 JP2015004569W WO2016042738A1 WO 2016042738 A1 WO2016042738 A1 WO 2016042738A1 JP 2015004569 W JP2015004569 W JP 2015004569W WO 2016042738 A1 WO2016042738 A1 WO 2016042738A1
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region
silicon carbide
drift layer
trench
layer
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PCT/JP2015/004569
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English (en)
Japanese (ja)
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拓高 西角
榊原　純
水野　祥司
竹内　有一
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株式会社デンソー
トヨタ自動車株式会社
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Priority claimed from JP2015110167A external-priority patent/JP6428489B2/ja
Application filed by 株式会社デンソー, トヨタ自動車株式会社 filed Critical 株式会社デンソー
Priority to US15/505,267 priority Critical patent/US10374079B2/en
Publication of WO2016042738A1 publication Critical patent/WO2016042738A1/fr
Priority to US16/421,849 priority patent/US20190288107A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present disclosure relates to a semiconductor device made of silicon carbide (hereinafter referred to as SiC) having a trench gate structure and a method for manufacturing the same.
  • SiC silicon carbide
  • an SiC semiconductor device having a trench gate structure as a structure in which a channel density is increased so that a large current can flow.
  • the breakdown electric field strength of SiC is high, and there is a possibility that dielectric breakdown may occur due to the application of a high electric field to the bottom of the trench. For this reason, dielectric breakdown is prevented by forming an electric field relaxation layer having a single-layer structure below the base layer between the opposing trench gates to relax the electric field.
  • an electric field relaxation effect to the trench gate portion can be obtained by providing the electric field relaxation layer having a single layer structure, a depletion layer extends between adjacent electric field relaxation layers to generate a JFET resistance region, thereby increasing the on-resistance. The problem occurs.
  • the carrier density in the drift layer can be lowered within the range sandwiched between the lateral regions, so that the electric field strength distribution can be suppressed deeper than the bottom of the trench, and the breakdown voltage characteristics can be improved. Is possible. Furthermore, since the interval between the lateral regions is determined only by the position where the lateral regions are formed, it is possible to avoid the influence of misalignment caused by manufacturing errors between the trench gate and the electric field relaxation layer.
  • the electric field relaxation layer formed from the substrate surface to a portion deeper than the trench gate is configured with the same concentration, but if it is configured with a low concentration, the electric field relaxation effect cannot be obtained. Consists of concentration. However, if the electric field relaxation layer is formed at a high concentration, the depletion layer from the electric field relaxation layer is likely to extend in the vicinity of the trench, and as a result, a JFET resistance region is generated, resulting in a problem that the on-resistance is increased.
  • the electric field relaxation layer is formed to have a two-layer structure with different impurity concentrations in the depth direction while forming the electric field relaxation layer so as to intersect with the trench gate whose longitudinal direction is one direction, and a deep portion Has a structure in which a high concentration region and a shallow portion become a low concentration region.
  • the effect of relaxing the electric field at the bottom of the trench in the deep layer made the high concentration region, and the extension of the depletion layer in the vicinity of the trench in the shallow layer made the low concentration region are suppressed. Both have the effect of reducing.
  • Patent Document 1 Although an electric field relaxation effect, a JFET resistance reduction effect, and an allowable manufacturing error can be obtained, a trench gate is formed on the damage in the crystal structure caused when the electric field relaxation layer is formed. As a result, the reliability of the trench gate decreases. That is, after an electric field relaxation layer is formed by ion implantation, a base region or the like is epitaxially grown on the electric field relaxation layer and then intersected with the electric field relaxation layer. For this reason, crystal defects at the time of ion implantation are inherited by the layer formed thereon, and the trench gate is formed so as to intersect the portion where the crystal defects are inherited. Or a leak path is formed. For this reason, there arises a problem that the reliability of the trench gate is lowered.
  • An object of the present disclosure is to provide a SiC semiconductor device having a trench gate structure with high breakdown voltage and high reliability, and a method for manufacturing the same.
  • a silicon carbide semiconductor device in a first aspect of the present disclosure, includes a first or second conductivity type substrate made of silicon carbide, and a first impurity formed on the substrate and having a lower impurity concentration than the substrate.
  • a drift layer made of conductive silicon carbide; a base region made of silicon carbide of the second conductivity type formed on the drift layer; and a higher concentration than the drift layer formed in the upper layer portion of the base region.
  • a plurality of source regions made of silicon carbide of the first conductivity type and an upper layer portion of the base region formed between the opposing source regions and having a second conductivity type having a higher concentration than the base layer A contact region made of silicon carbide, a trench formed from the surface of the source region to a depth deeper than the base region, and a plurality of parallel trenches with one direction as a longitudinal direction, and an inner wall of the trench
  • the plurality of electric field relaxation layers include a first region formed deeper than the trench and a lower concentration than the first region, and is formed from the surface of the drift layer to the first region. And a second region having a uniform density.
  • the structure is provided with the electric field relaxation layer deeper than the trench, and the high-concentration first region is formed at a deep position. For this reason, the depletion layer at the PN junction between the first region and the drift layer in the electric field relaxation layer greatly extends to the drift layer side, and a high voltage due to the influence of the drain voltage hardly enters the gate insulating film. Therefore, electric field concentration in the gate insulating film, particularly electric field concentration at the bottom of the trench in the gate insulating film can be reduced. Thereby, it is possible to prevent the gate insulating film from being destroyed.
  • the impurity concentration in the second region is made uniform.
  • the depletion layer extends due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers is narrowed. Cause an increase.
  • the second region has a uniform concentration, there is no variation in the extension of the depletion layer, and there is no place where the current path between the electric field relaxation layers becomes narrow. Therefore, it is possible to obtain an electric field relaxation effect while suppressing an increase in on-resistance.
  • a method for manufacturing a silicon carbide semiconductor device includes: a first conductivity type carbonization having a lower impurity concentration than that of a first or second conductivity type substrate made of silicon carbide. Forming a drift layer made of silicon, and forming a second conductivity type electric field relaxation layer in which a plurality of parallel layers with one direction as a longitudinal direction are formed in parallel with the drift layer, and over the electric field relaxation layer and the drift layer A base region made of silicon carbide of the second conductivity type is formed on the base region, and a plurality of layers made of silicon carbide of the first conductivity type higher in concentration than the drift layer are formed in an upper layer portion of the base region in the base region And a contact region made of silicon carbide of a second conductivity type higher in concentration than the base layer is formed between the opposing source regions in the upper layer portion of the base region.
  • a trench arranged at a distance is formed, a gate insulating film is formed on the surface of the trench, a gate electrode is formed on the gate insulating film in the trench, and the source region and the contact region are electrically connected.
  • a first region is formed at a position deeper than the trench, and a second region is formed at a lower concentration and a uniform concentration than the first region from the surface of the drift layer to the first region. Including doing.
  • the above-described method for manufacturing a silicon carbide semiconductor device has a structure including an electric field relaxation layer deeper than the trench, and constitutes a high-concentration first region at a deep position. For this reason, the depletion layer at the PN junction between the first region and the drift layer in the electric field relaxation layer greatly extends to the drift layer side, and a high voltage due to the influence of the drain voltage hardly enters the gate insulating film. Therefore, electric field concentration in the gate insulating film, particularly electric field concentration at the bottom of the trench in the gate insulating film can be reduced. Thereby, it is possible to prevent the gate insulating film from being destroyed.
  • the impurity concentration in the second region is made uniform.
  • the depletion layer extends due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers is narrowed. Cause an increase.
  • the second region has a uniform concentration, there is no variation in the extension of the depletion layer, and there is no place where the current path between the electric field relaxation layers becomes narrow. Therefore, it is possible to obtain an electric field relaxation effect while suppressing an increase in on-resistance.
  • a silicon carbide semiconductor device in a third aspect of the present disclosure, includes a first or second conductivity type substrate made of silicon carbide, and a first impurity formed on the substrate and having a lower impurity concentration than the substrate.
  • a drift layer made of conductive silicon carbide; a base region made of silicon carbide of the second conductivity type formed on the drift layer; and a higher concentration than the drift layer formed in the upper layer portion of the base region.
  • a plurality of source regions made of silicon carbide of the first conductivity type and an upper layer portion of the base region formed between the opposing source regions and having a second conductivity type having a higher concentration than the base layer A contact region made of silicon carbide, a trench formed from the surface of the source region to a depth deeper than the base region, and a plurality of parallel trenches with one direction as a longitudinal direction, and an inner wall of the trench
  • a plurality of electric field relaxation layers made of silicon carbide of the second conductivity type and spaced from the side surface of the trench.
  • the relationship between W1> W2 is satisfied, where W1 is the distance between the adjacent second regions, and W2 is the distance between the adjacent first regions.
  • the width of the trench gate structure formed by disposing the gate insulating film and the gate electrode in the trench is W3, and the relationship of W2> W3 is satisfied.
  • the structure is provided with the electric field relaxation layer deeper than the trench, and the high-concentration first region is formed at a deep position. For this reason, the depletion layer at the PN junction between the first region and the drift layer in the electric field relaxation layer greatly extends to the drift layer side, and a high voltage due to the influence of the drain voltage hardly enters the gate insulating film. Therefore, electric field concentration in the gate insulating film, particularly electric field concentration at the bottom of the trench in the gate insulating film can be reduced. Thereby, it is possible to prevent the gate insulating film from being destroyed.
  • the impurity concentration in the second region is made uniform.
  • the depletion layer extends due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers is narrowed. Cause an increase.
  • the second region has a uniform concentration, there is no variation in the extension of the depletion layer, and there is no place where the current path between the electric field relaxation layers becomes narrow. Therefore, it is possible to obtain an electric field relaxation effect while suppressing an increase in on-resistance.
  • FIG. 1 is a diagram illustrating a cross-sectional configuration of the SiC semiconductor device according to the first embodiment of the present disclosure.
  • 2 (a) to 2 (e) are cross-sectional views showing the manufacturing process of the SiC semiconductor device shown in FIG. 3 (a) to 3 (d) are cross-sectional views showing the manufacturing process of the SiC semiconductor device following FIG. 2 (e).
  • FIG. 4 is a cross-sectional view of the SiC semiconductor device when the high impurity region and the low impurity concentration region are not misaligned.
  • FIG. 5 is a cross-sectional view of the SiC semiconductor device in a case where a positional shift between the high impurity region and the low impurity concentration region occurs.
  • FIG. 6 is a diagram illustrating a cross-sectional configuration of the SiC semiconductor device according to the second embodiment of the present disclosure
  • FIG. 7A to FIG. 7C are cross-sectional views illustrating manufacturing steps of the SiC semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 8 is a diagram illustrating a cross-sectional configuration of the SiC semiconductor device according to the fourth embodiment of the present disclosure.
  • 9 (a) to 9 (e) are cross-sectional views showing the manufacturing process of the SiC semiconductor device shown in FIG.
  • FIG. 10 (a) to 10 (e) are cross-sectional views showing the manufacturing process of the SiC semiconductor device following FIG. 9 (e),
  • FIG. 11 is a cross-sectional view of a SiC semiconductor device described in another embodiment
  • FIG. 12 is a cross-sectional view of a SiC semiconductor device described in another embodiment
  • FIG. 13 is a cross-sectional view of a SiC semiconductor device described in another embodiment
  • FIG. 14 is a cross-sectional view of a SiC semiconductor device described in another embodiment
  • FIG. 15 is a cross-sectional view of a SiC semiconductor device described in another embodiment
  • 16A is a cross-sectional view of a conventional SiC semiconductor device
  • FIG. 16B is an enlarged view of a portion XVIB in FIG.
  • FIG. 16A is a cross-sectional view of a conventional SiC semiconductor device
  • FIG. 16B is an enlarged view of a portion XVIB in FIG.
  • FIG. 16A is a cross-sectional view
  • FIG. 17A is a cross-sectional view of the SiC semiconductor device according to the first embodiment of the present disclosure
  • FIG. 17B is an enlarged view of a portion XVIIB in FIG.
  • FIG. 18 is a diagram illustrating the concentration distribution of the upper portion of the electric field relaxation layer of the SiC semiconductor device according to the conventional technique and the first embodiment of the present disclosure.
  • FIG. 1 An SiC semiconductor device having a vertical MOSFET having an inverted trench gate structure according to the present embodiment will be described with reference to FIG. In FIG. 1, only one cell of the vertical MOSFET is shown, but a plurality of cells having the same structure as the vertical MOSFET shown in FIG. 1 are arranged adjacent to each other.
  • an SiC single crystal having a thickness of about 300 ⁇ m is doped with an n-type impurity (such as phosphorus or nitrogen) at a high concentration, for example, an impurity concentration of 1 ⁇ 10 19 to 1 ⁇ 10 20 cm ⁇ 3.
  • An n + type semiconductor substrate 1 is used.
  • an n type drift layer made of SiC having a thickness of about 10 to 15 ⁇ m doped with an n type impurity at an impurity concentration of 1 ⁇ 10 15 to 1 ⁇ 10 16 cm ⁇ 3 , for example. 2 is formed.
  • the n-type drift layer 2 is formed with a recessed portion (first recessed portion) 2a that is partially recessed.
  • the concave portion 2a is formed in a linear shape having one direction (perpendicular to the paper surface) as a longitudinal direction, and extends to a position deeper than a trench 7 constituting a trench gate structure to be described later, and the same direction as the trench 7 is a longitudinal direction. It is formed as.
  • An electric field relaxation layer 3 doped with a p-type impurity (such as boron or aluminum) is formed below the bottom of the recess 2a and in the recess 2a with the same direction as the longitudinal direction of the recess 2a. .
  • a portion located below the bottom of the recess 2 a, that is, a portion deeper than the trench 7 is a high concentration region (first region) 3 a in which the p-type impurity concentration is high. Yes.
  • a portion of the electric field relaxation layer 3 located inside the recess 2a is a low concentration region (second region) 3b in which the p-type impurity concentration is lower than that of the high concentration region 3a.
  • the electric field relaxation layer 3 is constituted by the high concentration region 3a and the low concentration region 3b having different impurity concentrations.
  • the high concentration region 3a is, for example, about 1 ⁇ 10 17 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the low concentration region 3b is set to about 1 ⁇ 10 15 to 1 ⁇ 10 18 cm ⁇ 3 so that the concentration is set lower than that of the high concentration region 3a.
  • the low concentration region 3b is configured with a uniform impurity concentration throughout the region.
  • the high concentration region 3a is wider than the low concentration region 3b with respect to the width of the electric field relaxation layer 3, that is, the dimension perpendicular to the longitudinal direction of the electric field relaxation layer 3 in the plane direction parallel to the substrate plane.
  • the electric field relaxation layer 3 is disposed on both sides of a trench 7 constituting a trench gate structure described later so that the low concentration region 3b is separated from the side surface of the trench 7 by a predetermined distance.
  • W1> W2 and W3 where W1 is the distance between adjacent low concentration regions 3b located on both sides of the trench gate structure, W2 is the distance between the high concentration regions 3a, and W3 is the width of the trench gate structure. And preferably the relationship of W2> W3 is also satisfied.
  • W2> W3 it is possible to prevent the JFET region from expanding between the adjacent electric field relaxation layers 3 and to secure the shortest current path between the trench gate structure and the drain electrode 12 described later, thereby increasing the on-resistance. Can be suppressed.
  • the depth of the electric field relaxation layer 3 is such that the low concentration region 3b is formed to a position deeper than the bottom of the trench 7 in the trench gate structure, so that the entire region of the high concentration region 3a is deeper than the bottom of the trench 7. It is designed to be formed at a position.
  • a p-type base region 4 is formed on the surfaces of the n-type drift layer 2 and the electric field relaxation layer 3.
  • the p-type base region 4 is a layer constituting a channel of the vertical MOSFET, and is formed on both sides of a trench 7 constituting a trench gate structure described later so as to be in contact with the side surface of the trench 7.
  • n + -type source region 5 doped with an n-type impurity at a high concentration so as to be in contact with the trench gate structure is located closer to the trench gate structure side than the position corresponding to the electric field relaxation layer 3 in the surface layer portion of the p-type base region 4. Is formed.
  • the n + -type source region 5 is formed with an impurity concentration of about 1 ⁇ 10 21 cm ⁇ 3 and a thickness of about 0.3 ⁇ m.
  • a p + -type contact region doped with a p-type impurity at a high concentration is provided between the surface layer portion of the p-type base region 4 and the position corresponding to the electric field relaxation layer 3, that is, between the opposing n + -type source region 5. 6 is formed.
  • the p + -type contact region 6 is formed with an impurity concentration of about 1 ⁇ 10 21 cm ⁇ 3 and a thickness of about 0.3 ⁇ m.
  • the n-type drift layer 2 is reached through the p-type base region 4 and the n + -type source region 5 at the center position of the electric field relaxation layers 3 arranged adjacent to each other, and A trench 7 which is shallower than the bottom of the relaxation layer 3 is formed.
  • a p-type base region 4 and an n + -type source region 5 are arranged in contact with the side surface of the trench 7.
  • the inner wall surface of the trench 7 is covered with a gate insulating film 8 made of an oxide film or the like, and the gate electrode 9 made of doped Poly-Si formed on the surface of the gate insulating film 8 makes it possible to Is filled up.
  • the trench gate structure is configured by the structure in which the gate insulating film 8 and the gate electrode 9 are provided in the trench 7.
  • the trench gate structure is, for example, a strip with the vertical direction on the paper as the longitudinal direction, and a plurality of trench gate structures are arranged in stripes at equal intervals in the horizontal direction of the paper. As a result, the structure is provided with a plurality of cells.
  • a source electrode 10 is formed on the surfaces of the n + type source region 5 and the p + type contact region 6.
  • the source electrode 10 is composed of a plurality of metals (for example, Ni / Al). Specifically, the portion connected to n + type source region 5 is made of a metal capable of ohmic contact with n type SiC, and the portion connected to p type base region 4 via p + type contact region 6 is It is made of a metal capable of ohmic contact with p-type SiC.
  • the source electrode 10 is electrically separated from a gate wiring (not shown) that is electrically connected to the gate electrode 9 via the interlayer insulating film 11.
  • the source electrode 10 is in electrical contact with the n + type source region 5 and the p + type contact region 6 through a contact hole formed in the interlayer insulating film 11.
  • n + -type semiconductor substrate 1 On the back side of the n + -type semiconductor substrate 1 n + -type semiconductor substrate 1 and electrically connected to the drain electrode 12 are formed. With such a structure, an n-channel type inverted MOSFET having a trench gate structure is formed.
  • a high voltage eg, 1200 V
  • SiC having an electric field breakdown strength nearly 10 times that of a silicon device
  • an electric field close to 10 times that of a silicon device is applied to the gate insulating film 8 due to the influence of this voltage, and the gate insulating film 8 (in particular, the trench in the gate insulating film 8).
  • An electric field concentration can occur at the bottom of 7).
  • the electric field relaxation layer 3 is deeper than the trench 7 and the high concentration region 3a is formed at a deep position. For this reason, the depletion layer at the PN junction between the high concentration region 3a and the n-type drift layer 2 in the electric field relaxation layer 3 greatly extends toward the n-type drift layer 2, and the high voltage due to the influence of the drain voltage is It becomes difficult to enter the insulating film 8. In particular, since the high concentration region 3a is wider than the low concentration region 3b and the distance W2 between the high concentration regions 3a is narrowed, a high voltage due to the influence of the drain voltage is less likely to enter the gate insulating film 8. .
  • the high concentration region 3a deeper than the trench gate structure in the electric field relaxation layer 3, a portion shallower than the high concentration region 3a is used as the low concentration region 3b.
  • the low concentration region 3b is arranged in the portion to be formed. For this reason, it is possible to suppress the spread of the depletion layer extending from the low concentration region 3b to the n-type drift layer 2 on the trench 7 side, that is, the channel side, as compared with the case where the entire electric field relaxation layer 3 is configured with a high concentration. Thus, the effect of suppressing the JFET resistance can be obtained.
  • the electric field relaxation layer 3 and the trench gate structure are arranged in parallel and are not in a state of intersecting. For this reason, as will be described later, even if the high concentration region 3a in the electric field relaxation layer 3 is formed by ion implantation, damage due to ion implantation in the high concentration region 3a and each part formed by epitaxial growth on the high concentration region 3a.
  • the trench gate structure can be separated from the remaining portion. Furthermore, since the ion-implanted region is only the high-concentration region 3a, damage caused by ion implantation in the crystal can be minimized.
  • FIG. 1 Next, a method of manufacturing the trench gate type vertical MOSFET shown in FIG. 1 will be described with reference to FIGS. 2 (a) to 3 (d).
  • an epitaxial substrate is prepared in which an n type drift layer 2 is epitaxially grown on the surface of an n + type semiconductor substrate 1 made of a SiC single crystal doped with an n type impurity at a high concentration.
  • Step shown in FIG. 2 (b)] After depositing a mask material such as an oxide film on the n-type drift layer 2, the mask 20 is opened by opening the region to be formed with the recess 2a, that is, the region to be formed with the p-type deep layer 3b. Form. Then, anisotropic etching such as RIE (Reactive Ion Etching) is performed using the mask 20. Thereby, the surface layer portion of the n-type drift layer 2 is removed at the opening of the mask 20 to form the recess 2a. The depth and width of the recess 2a are set so that the final depth and width of the final low-concentration region 3b become target values in consideration of thermal diffusion in each process performed thereafter. In the case of SiC, since the diffusion amount due to thermal diffusion is very small, the dimensions of the recess 2a are determined with the same dimensions as the final depth and width of the final low-concentration region 3b without taking into account thermal diffusion. Also good.
  • RIE Reactive Ion Etching
  • Step shown in FIG. 2 (c)] After removing the mask 20 used to form the recess 2a, p-type impurities are ion-implanted into the bottom of the recess 2a using an ion implantation mask (not shown). Then, the high concentration region 3a is formed by activating the implanted impurities by heat treatment or the like. The lateral expansion of the high-concentration region 3a at this time is partly due to thermal diffusion, but basically the high-concentration region is obtained by implanting p-type impurities in a laterally expanded state by oblique ion implantation. 3a is configured to have a desired width.
  • the low concentration region 3b is epitaxially grown in the recess 2a.
  • the p-type impurity layer 3 can be formed by performing epitaxial growth using a CVD (Chemical Vapor Deposition) apparatus while introducing a gas containing a dopant into the atmosphere.
  • the p-type base region 4 can be simultaneously formed on the surface of the p-type drift layer 2, but here, only the low concentration region 3 b is formed, and it is not necessary to be formed on the p-type drift layer 2.
  • the portion is removed by CMP (Chemical Mechanical Polishing) or the like.
  • the low concentration region 3b is epitaxially grown in the recess 2a by a technique such as CVD, the entire low concentration region 3b can be formed with a uniform impurity concentration.
  • the p-type base region 4 is epitaxially grown by the same method as the low concentration region 3b. At this time, as described above, the p-type base region 4 can be formed simultaneously with the low-concentration region 3b, so that the manufacturing process can be simplified. It is also possible to set the density separately.
  • the gate insulating film 8 is formed by performing a gate oxidation process after removing the etching mask. Further, after forming a polysilicon layer doped with impurities on the surface of the gate insulating film 8, the gate electrode 9 is formed by patterning the polysilicon layer. Thereby, a trench gate structure is formed.
  • Step shown in FIG. 3B After forming a mask (not shown) in which a region where the n + type source region 5 is to be formed is opened on the surface of the p type base region 4, n type impurities are ion-implanted at a high concentration from above to form an n + type. A source region 5 is formed. Similarly, after forming a mask (not shown) in which a region where the p + -type contact region 6 is to be formed is opened on the surface of the p-type base region 4, p-type impurities are ion-implanted at a high concentration from above. A p + -type contact region 6 is formed.
  • the cross section is formed differently from the cross section. Then, after depositing an electrode material so as to fill the contact hole, the source material 10 and a gate wiring (not shown) are formed by patterning the electrode material.
  • a drain electrode 12 is formed on the back side of the n + type semiconductor substrate 1. Thereby, the vertical MOSFET shown in FIG. 1 is completed.
  • the structure includes the electric field relaxation layer 3 deeper than the trench 7, and the high concentration region 3a is formed at a deep position, and the shallower region is defined as the low concentration region 3b. It is said. For this reason, the electric field relaxation effect and the JFET resistance reduction effect can be obtained.
  • the electric field relaxation layer 3 and the trench gate structure are arranged in parallel so that they do not intersect. For this reason, the trench gate structure can be separated from the high-concentration region 3a and a portion where damage due to ion implantation among the portions formed by epitaxial growth thereon can remain. Furthermore, since the ion-implanted region is only the high-concentration region 3a, damage caused by ion implantation in the crystal can be minimized. Therefore, it is possible to suppress the occurrence of variations in the quality of the gate insulating film 8, to suppress the formation of a leak path, and to suppress a decrease in the reliability of the trench gate. An SiC semiconductor device having a high trench gate structure can be obtained.
  • the impurity concentration of the low concentration region 3b is uniform throughout the entire region.
  • the impurity concentration of the low impurity region 3b varies in the depth direction, the depletion layer expands due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers 3 is narrowed. This causes an increase in resistance.
  • the impurity concentration of the low concentration region 3b is uniform throughout the region as in the present embodiment, there is no variation in the expansion of the depletion layer and the current path between the electric field relaxation layers 3 is narrow. Does not occur. Therefore, it is possible to obtain an electric field relaxation effect while suppressing an increase in on-resistance.
  • the depletion layer is likely to vary in elongation due to the concentration of the impurity concentration, and the influence is likely to occur. By doing so, it becomes possible to obtain an effect of suppressing an increase in on-resistance.
  • FIGS. 16A and 16B are a cross-sectional view and a partially enlarged view of a SiC semiconductor device according to the prior art (Japanese Patent No. 5539931).
  • Japanese Patent No. 5539931 Japanese Patent No. 5539931.
  • the depletion layer extends due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers is narrowed. Cause an increase.
  • the impurity concentration of the low concentration region 3b that is, the second region is set to a uniform concentration.
  • 17A and 17B are a cross-sectional view and a partially enlarged view of the SiC semiconductor device of this example.
  • FIG. 18 shows the depth distribution of the impurity concentration in the upper part of the electric field relaxation layer of the SiC semiconductor device of the prior art and this example, that is, the second region.
  • the impurity concentration varies between yi and yd, whereas in the SiC semiconductor device of this example, the impurity concentration is larger than the lowest impurity concentration of the prior art and lower than the highest impurity concentration. Yes.
  • the formation position of the high impurity region 3a and the low impurity region 3b can be set by self-alignment (self-alignment) with respect to the formation position of the recess 2a. For this reason, the formation position shift with respect to a trench gate structure can be suppressed.
  • the high impurity region 3a and the low impurity region 3b are formed by ion implantation, the high impurity region 3a and the low impurity region 3b are formed as shown in FIGS. Forming position deviation may occur. Then, when the formation position deviation occurs as shown in FIG. 5, the formation of the high impurity region 3a with respect to the trench gate structure is compared with the case where the formation position deviation does not occur as shown in FIG. By shifting the position, the current path indicated by the arrow in the figure becomes longer.
  • the manufacturing method of the present embodiment a structure in which the formation position shift does not occur as shown in FIG. 4 can be obtained, and the current path can be made the shortest current path. As a result, it is possible to further suppress an increase in on-resistance.
  • the width of the high concentration region 3a is set to be equal to or less than the width of the low concentration region 3b.
  • the distance W2 between the high concentration regions 3a is set to satisfy W1 ⁇ W2 with respect to the distance W1 between the low concentration regions 3b located on both sides of the trench gate structure.
  • the width of the high concentration region 3a is reduced to the low concentration region. You may set below the width
  • the p-type impurity is not directed to the oblique ion implantation in the step of FIG.
  • an ion implantation mask having a width of the opening of the ion implantation mask smaller than the width of the recess 2a may be used.
  • a third embodiment of the present disclosure will be described.
  • the method of forming the electric field relaxation layer 3 is changed with respect to the first and second embodiments.
  • the other aspects are the same as those in the first and second embodiments. Only portions different from the embodiment will be described.
  • the electric field relaxation layer 3 can be formed with the same method also with respect to 2nd Embodiment. .
  • an epitaxial substrate having an n type drift layer 2 formed on the surface of an n + type semiconductor substrate 1 is prepared in the same manner as the step shown in FIG.
  • an ion implantation mask (not shown) is arranged on the surface of the n-type drift layer 2, and then a high-concentration region 3a and a low-concentration region 3b are formed by ion implantation of p-type impurities.
  • a first mask having an opening having a width corresponding to the high concentration region 3a is disposed, and then p-type impurities are ion-implanted using the first mask as an ion implantation mask.
  • Ion implantation for forming the low concentration region 3b is performed by a box profile. Thereby, the low concentration region 3b is formed with a uniform impurity concentration.
  • the implanted p-type ions are activated to form the high concentration region 3a and the low concentration region 3b.
  • the acceleration voltage of the ion implantation is changed so that the ion implantation for forming the high concentration region 3a has a higher acceleration voltage than the ion implantation for forming the low concentration region 3b.
  • the high concentration region 3a is formed at a deeper position. Further, by changing the dose amount of the p-type impurity at the time of ion implantation, the high concentration region 3a is formed with a higher impurity concentration than the low concentration region 3b.
  • the p-type base region 4 is formed in the same manner as the step shown in FIG. 2C, and then, FIG. 2D, FIG. 2E, FIG. Steps a) to steps similar to those shown in FIG. Thereby, the SiC semiconductor device having the trench gate type vertical MOSFET according to the present embodiment is completed.
  • the high concentration region 3a but also the low concentration region 3b of the electric field relaxation layer 3 can be formed by ion implantation. Even if it does in this way, it becomes possible to acquire the effect similar to 1st, 2nd embodiment.
  • the impurity concentration of the portion of the n-type drift layer 2 located above the high-concentration region 3a is made higher than that of the other portions of the n-type drift layer 2.
  • the high concentration layer 2b is used.
  • the n-type impurity concentration of the high concentration layer 2b is set to be higher by about 2.0 ⁇ 10 15 cm ⁇ 3 than the other portions of the n-type drift layer 2.
  • the width of the depletion layer extending into the n-type drift layer 2 in the vicinity of the trench 7 can be reduced. Therefore, in addition to the decrease in internal resistance due to the increase in the impurity concentration of the high concentration layer 2b, the width of the depletion layer in the n-type drift layer 2 can be reduced, so that the JFET resistance can be further reduced. Become.
  • an epi substrate in which a part of the n type drift layer 2 is formed on the surface of the n + type semiconductor substrate 1 is prepared in the same manner as the step shown in FIG. . 9B, an ion implantation mask (not shown) is disposed on a part of the surface of the n-type drift layer 2, and then a high-concentration region 3a is formed by ion implantation of p-type impurities. At this time, the high concentration region 3 a is formed from a part of the surface of the n-type drift layer 2.
  • the high concentration region 3a is formed by ion implantation.
  • a recess is formed in a region where the high concentration region 3a is to be formed by etching, a p-type impurity layer is buried in the recess by epitaxial growth, and then flattened by polishing, thereby forming the high concentration region 3a. It is good also as the manufacturing method of forming.
  • the high-concentration layer 2b which remains the n-type drift layer 2 is epitaxially grown on the surface of the high-concentration region 3a and a part of the n-type drift layer 2.
  • the step similar to FIG. 2B is performed to form the recess 2a in the high concentration layer 2b, and then in the step shown in FIG. 9E.
  • the low concentration region 3b is formed by performing the same process as in FIG.
  • the side surface of the low concentration region 3b is illustrated as being perpendicular to the surface of the n + type semiconductor substrate 1, but it is not always necessary to be perpendicular.
  • the width of the upper portion of the low concentration region 3b is made narrower than the lower portion, thereby tilting the side surface of the low concentration region 3b. It may be a tapered shape. As shown in FIG.
  • the width of the lower portion of the low concentration region 3b is narrower than that of the upper portion in the direction parallel to the surface of the n + type semiconductor substrate 1, so that the side surface of the low concentration region 3b is opposite to that of FIG. It may be made into the reverse taper shape made to incline.
  • the side surface of the recess 2a is The taper shape or the inverse taper shape may be used.
  • the etching conditions for forming the concave portion 2a may be adjusted.
  • the shape of the high concentration region 3a is also shown as a quadrangular shape with rounded corners in the cross section cut in the direction perpendicular to the longitudinal direction of the trench gate structure in each of the above embodiments, as shown in FIG.
  • the cross-sectional shape may be an oval shape.
  • the impurity concentration of the high concentration region 3a does not need to be uniform over the entire region. For example, the impurity concentration may be increased as it becomes deeper, that is, as it approaches the n + type semiconductor substrate 1.
  • region 3a among the n-type drift layers 2 is made into the high concentration layer 2b.
  • the high-concentration layer 2b does not need to be formed in the entire region of the n-type drift layer 2 that is located above the high-concentration region 3a, and more specifically so as to surround at least the bottom of the trench gate structure. May be formed in a portion to be a current path.
  • the high concentration layer 2 b is formed in the entire region above a predetermined distance from the high concentration region 3 a, or while surrounding the bottom of the trench gate structure as shown in FIG. 15,
  • the high concentration layer 2b may be formed so as to be away from the high concentration region 3a and the low concentration region 3b.
  • the high concentration layer 1b can be formed by selective epitaxial growth or ion implantation.
  • an n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example.
  • the present disclosure can be applied to a channel type MOSFET.
  • a MOSFET having a trench gate structure has been described as an example, but the present disclosure can be applied to an IGBT having a similar trench gate structure.
  • the IGBT only changes the conductivity type of the substrate 1 from the n-type to the p-type with respect to the above-described embodiments, and the other structures and manufacturing methods are the same as those of the above-described embodiments.

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Abstract

La présente invention concerne un dispositif à semi-conducteur au carbure de silicium qui comprend : un substrat (1) ; une couche de migration (2) qui se trouve au-dessus du substrat ; une zone de base (4) qui se trouve au-dessus de la couche de migration ; une pluralité de zones de source (5) dans la partie couche supérieure de la zone de base ; une zone de contact (6) entre les zones de source dans la partie couche supérieure de la zone de base ; une pluralité de tranchées (7) formées à partir de la surface des zones de source jusqu'à un emplacement qui est plus profond que la zone de base ; une électrode de grille (9) qui se trouve au-dessus d'un film d'isolation de grille dans les tranchées ; une électrode de source (10) connectée aux zones de source et aux zones de contact ; une électrode de drain (12) sur l'arrière du substrat ; et une pluralité de couches de relaxation de champ (3) entre les tranchées à l'intérieur de la couche de migration. La pluralité de couches de relaxation de champ comprennent chacune une première zone (3a) plus profonde que les tranchées et une seconde zone (3b) formée de la surface de la couche de migration à la première zone.
PCT/JP2015/004569 2014-09-16 2015-09-08 Dispositif à semi-conducteur au carbure de silicium et son procédé de fabrication WO2016042738A1 (fr)

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CN112262478A (zh) * 2018-03-20 2021-01-22 株式会社电装 半导体装置及其制造方法
CN113196500A (zh) * 2019-01-16 2021-07-30 株式会社电装 半导体装置及其制造方法
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CN109416421B (zh) * 2016-06-30 2020-11-24 日本板硝子株式会社 红外线截止滤波器以及摄像光学系统
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JP2018022854A (ja) * 2016-08-05 2018-02-08 富士電機株式会社 半導体装置および半導体装置の製造方法
JPWO2018088063A1 (ja) * 2016-11-11 2019-09-26 住友電気工業株式会社 炭化珪素半導体装置
WO2018088063A1 (fr) * 2016-11-11 2018-05-17 住友電気工業株式会社 Appareil semiconducteur au carbure de silicium
CN108574001B (zh) * 2017-03-13 2021-02-19 丰田合成株式会社 半导体装置
CN108574001A (zh) * 2017-03-13 2018-09-25 丰田合成株式会社 半导体装置
CN106784011A (zh) * 2017-03-23 2017-05-31 北京世纪金光半导体有限公司 具有浪涌电压自抑和自过压保护的碳化硅umosfet器件元胞结构
CN111133588A (zh) * 2017-09-18 2020-05-08 株式会社电装 半导体装置及其制造方法
CN111133588B (zh) * 2017-09-18 2023-05-30 株式会社电装 半导体装置及其制造方法
JP2019102555A (ja) * 2017-11-29 2019-06-24 国立研究開発法人産業技術総合研究所 半導体装置
JP7057555B2 (ja) 2017-11-29 2022-04-20 国立研究開発法人産業技術総合研究所 半導体装置
CN112262478A (zh) * 2018-03-20 2021-01-22 株式会社电装 半导体装置及其制造方法
CN112262478B (zh) * 2018-03-20 2024-04-09 株式会社电装 半导体装置及其制造方法
CN113196500B (zh) * 2019-01-16 2024-04-09 株式会社电装 半导体装置及其制造方法
CN113196500A (zh) * 2019-01-16 2021-07-30 株式会社电装 半导体装置及其制造方法
CN113767478B (zh) * 2019-04-23 2023-12-05 株式会社电装 半导体装置及其制造方法
CN113767478A (zh) * 2019-04-23 2021-12-07 株式会社电装 半导体装置及其制造方法

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