WO2016042738A1 - Silicon carbide semiconductor device and method for manufacturing same - Google Patents

Silicon carbide semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2016042738A1
WO2016042738A1 PCT/JP2015/004569 JP2015004569W WO2016042738A1 WO 2016042738 A1 WO2016042738 A1 WO 2016042738A1 JP 2015004569 W JP2015004569 W JP 2015004569W WO 2016042738 A1 WO2016042738 A1 WO 2016042738A1
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region
silicon carbide
drift layer
trench
layer
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PCT/JP2015/004569
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French (fr)
Japanese (ja)
Inventor
拓高 西角
榊原　純
水野　祥司
竹内　有一
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株式会社デンソー
トヨタ自動車株式会社
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Priority claimed from JP2015110167A external-priority patent/JP6428489B2/en
Application filed by 株式会社デンソー, トヨタ自動車株式会社 filed Critical 株式会社デンソー
Priority to US15/505,267 priority Critical patent/US10374079B2/en
Publication of WO2016042738A1 publication Critical patent/WO2016042738A1/en
Priority to US16/421,849 priority patent/US20190288107A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present disclosure relates to a semiconductor device made of silicon carbide (hereinafter referred to as SiC) having a trench gate structure and a method for manufacturing the same.
  • SiC silicon carbide
  • an SiC semiconductor device having a trench gate structure as a structure in which a channel density is increased so that a large current can flow.
  • the breakdown electric field strength of SiC is high, and there is a possibility that dielectric breakdown may occur due to the application of a high electric field to the bottom of the trench. For this reason, dielectric breakdown is prevented by forming an electric field relaxation layer having a single-layer structure below the base layer between the opposing trench gates to relax the electric field.
  • an electric field relaxation effect to the trench gate portion can be obtained by providing the electric field relaxation layer having a single layer structure, a depletion layer extends between adjacent electric field relaxation layers to generate a JFET resistance region, thereby increasing the on-resistance. The problem occurs.
  • the carrier density in the drift layer can be lowered within the range sandwiched between the lateral regions, so that the electric field strength distribution can be suppressed deeper than the bottom of the trench, and the breakdown voltage characteristics can be improved. Is possible. Furthermore, since the interval between the lateral regions is determined only by the position where the lateral regions are formed, it is possible to avoid the influence of misalignment caused by manufacturing errors between the trench gate and the electric field relaxation layer.
  • the electric field relaxation layer formed from the substrate surface to a portion deeper than the trench gate is configured with the same concentration, but if it is configured with a low concentration, the electric field relaxation effect cannot be obtained. Consists of concentration. However, if the electric field relaxation layer is formed at a high concentration, the depletion layer from the electric field relaxation layer is likely to extend in the vicinity of the trench, and as a result, a JFET resistance region is generated, resulting in a problem that the on-resistance is increased.
  • the electric field relaxation layer is formed to have a two-layer structure with different impurity concentrations in the depth direction while forming the electric field relaxation layer so as to intersect with the trench gate whose longitudinal direction is one direction, and a deep portion Has a structure in which a high concentration region and a shallow portion become a low concentration region.
  • the effect of relaxing the electric field at the bottom of the trench in the deep layer made the high concentration region, and the extension of the depletion layer in the vicinity of the trench in the shallow layer made the low concentration region are suppressed. Both have the effect of reducing.
  • Patent Document 1 Although an electric field relaxation effect, a JFET resistance reduction effect, and an allowable manufacturing error can be obtained, a trench gate is formed on the damage in the crystal structure caused when the electric field relaxation layer is formed. As a result, the reliability of the trench gate decreases. That is, after an electric field relaxation layer is formed by ion implantation, a base region or the like is epitaxially grown on the electric field relaxation layer and then intersected with the electric field relaxation layer. For this reason, crystal defects at the time of ion implantation are inherited by the layer formed thereon, and the trench gate is formed so as to intersect the portion where the crystal defects are inherited. Or a leak path is formed. For this reason, there arises a problem that the reliability of the trench gate is lowered.
  • An object of the present disclosure is to provide a SiC semiconductor device having a trench gate structure with high breakdown voltage and high reliability, and a method for manufacturing the same.
  • a silicon carbide semiconductor device in a first aspect of the present disclosure, includes a first or second conductivity type substrate made of silicon carbide, and a first impurity formed on the substrate and having a lower impurity concentration than the substrate.
  • a drift layer made of conductive silicon carbide; a base region made of silicon carbide of the second conductivity type formed on the drift layer; and a higher concentration than the drift layer formed in the upper layer portion of the base region.
  • a plurality of source regions made of silicon carbide of the first conductivity type and an upper layer portion of the base region formed between the opposing source regions and having a second conductivity type having a higher concentration than the base layer A contact region made of silicon carbide, a trench formed from the surface of the source region to a depth deeper than the base region, and a plurality of parallel trenches with one direction as a longitudinal direction, and an inner wall of the trench
  • the plurality of electric field relaxation layers include a first region formed deeper than the trench and a lower concentration than the first region, and is formed from the surface of the drift layer to the first region. And a second region having a uniform density.
  • the structure is provided with the electric field relaxation layer deeper than the trench, and the high-concentration first region is formed at a deep position. For this reason, the depletion layer at the PN junction between the first region and the drift layer in the electric field relaxation layer greatly extends to the drift layer side, and a high voltage due to the influence of the drain voltage hardly enters the gate insulating film. Therefore, electric field concentration in the gate insulating film, particularly electric field concentration at the bottom of the trench in the gate insulating film can be reduced. Thereby, it is possible to prevent the gate insulating film from being destroyed.
  • the impurity concentration in the second region is made uniform.
  • the depletion layer extends due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers is narrowed. Cause an increase.
  • the second region has a uniform concentration, there is no variation in the extension of the depletion layer, and there is no place where the current path between the electric field relaxation layers becomes narrow. Therefore, it is possible to obtain an electric field relaxation effect while suppressing an increase in on-resistance.
  • a method for manufacturing a silicon carbide semiconductor device includes: a first conductivity type carbonization having a lower impurity concentration than that of a first or second conductivity type substrate made of silicon carbide. Forming a drift layer made of silicon, and forming a second conductivity type electric field relaxation layer in which a plurality of parallel layers with one direction as a longitudinal direction are formed in parallel with the drift layer, and over the electric field relaxation layer and the drift layer A base region made of silicon carbide of the second conductivity type is formed on the base region, and a plurality of layers made of silicon carbide of the first conductivity type higher in concentration than the drift layer are formed in an upper layer portion of the base region in the base region And a contact region made of silicon carbide of a second conductivity type higher in concentration than the base layer is formed between the opposing source regions in the upper layer portion of the base region.
  • a trench arranged at a distance is formed, a gate insulating film is formed on the surface of the trench, a gate electrode is formed on the gate insulating film in the trench, and the source region and the contact region are electrically connected.
  • a first region is formed at a position deeper than the trench, and a second region is formed at a lower concentration and a uniform concentration than the first region from the surface of the drift layer to the first region. Including doing.
  • the above-described method for manufacturing a silicon carbide semiconductor device has a structure including an electric field relaxation layer deeper than the trench, and constitutes a high-concentration first region at a deep position. For this reason, the depletion layer at the PN junction between the first region and the drift layer in the electric field relaxation layer greatly extends to the drift layer side, and a high voltage due to the influence of the drain voltage hardly enters the gate insulating film. Therefore, electric field concentration in the gate insulating film, particularly electric field concentration at the bottom of the trench in the gate insulating film can be reduced. Thereby, it is possible to prevent the gate insulating film from being destroyed.
  • the impurity concentration in the second region is made uniform.
  • the depletion layer extends due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers is narrowed. Cause an increase.
  • the second region has a uniform concentration, there is no variation in the extension of the depletion layer, and there is no place where the current path between the electric field relaxation layers becomes narrow. Therefore, it is possible to obtain an electric field relaxation effect while suppressing an increase in on-resistance.
  • a silicon carbide semiconductor device in a third aspect of the present disclosure, includes a first or second conductivity type substrate made of silicon carbide, and a first impurity formed on the substrate and having a lower impurity concentration than the substrate.
  • a drift layer made of conductive silicon carbide; a base region made of silicon carbide of the second conductivity type formed on the drift layer; and a higher concentration than the drift layer formed in the upper layer portion of the base region.
  • a plurality of source regions made of silicon carbide of the first conductivity type and an upper layer portion of the base region formed between the opposing source regions and having a second conductivity type having a higher concentration than the base layer A contact region made of silicon carbide, a trench formed from the surface of the source region to a depth deeper than the base region, and a plurality of parallel trenches with one direction as a longitudinal direction, and an inner wall of the trench
  • a plurality of electric field relaxation layers made of silicon carbide of the second conductivity type and spaced from the side surface of the trench.
  • the relationship between W1> W2 is satisfied, where W1 is the distance between the adjacent second regions, and W2 is the distance between the adjacent first regions.
  • the width of the trench gate structure formed by disposing the gate insulating film and the gate electrode in the trench is W3, and the relationship of W2> W3 is satisfied.
  • the structure is provided with the electric field relaxation layer deeper than the trench, and the high-concentration first region is formed at a deep position. For this reason, the depletion layer at the PN junction between the first region and the drift layer in the electric field relaxation layer greatly extends to the drift layer side, and a high voltage due to the influence of the drain voltage hardly enters the gate insulating film. Therefore, electric field concentration in the gate insulating film, particularly electric field concentration at the bottom of the trench in the gate insulating film can be reduced. Thereby, it is possible to prevent the gate insulating film from being destroyed.
  • the impurity concentration in the second region is made uniform.
  • the depletion layer extends due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers is narrowed. Cause an increase.
  • the second region has a uniform concentration, there is no variation in the extension of the depletion layer, and there is no place where the current path between the electric field relaxation layers becomes narrow. Therefore, it is possible to obtain an electric field relaxation effect while suppressing an increase in on-resistance.
  • FIG. 1 is a diagram illustrating a cross-sectional configuration of the SiC semiconductor device according to the first embodiment of the present disclosure.
  • 2 (a) to 2 (e) are cross-sectional views showing the manufacturing process of the SiC semiconductor device shown in FIG. 3 (a) to 3 (d) are cross-sectional views showing the manufacturing process of the SiC semiconductor device following FIG. 2 (e).
  • FIG. 4 is a cross-sectional view of the SiC semiconductor device when the high impurity region and the low impurity concentration region are not misaligned.
  • FIG. 5 is a cross-sectional view of the SiC semiconductor device in a case where a positional shift between the high impurity region and the low impurity concentration region occurs.
  • FIG. 6 is a diagram illustrating a cross-sectional configuration of the SiC semiconductor device according to the second embodiment of the present disclosure
  • FIG. 7A to FIG. 7C are cross-sectional views illustrating manufacturing steps of the SiC semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 8 is a diagram illustrating a cross-sectional configuration of the SiC semiconductor device according to the fourth embodiment of the present disclosure.
  • 9 (a) to 9 (e) are cross-sectional views showing the manufacturing process of the SiC semiconductor device shown in FIG.
  • FIG. 10 (a) to 10 (e) are cross-sectional views showing the manufacturing process of the SiC semiconductor device following FIG. 9 (e),
  • FIG. 11 is a cross-sectional view of a SiC semiconductor device described in another embodiment
  • FIG. 12 is a cross-sectional view of a SiC semiconductor device described in another embodiment
  • FIG. 13 is a cross-sectional view of a SiC semiconductor device described in another embodiment
  • FIG. 14 is a cross-sectional view of a SiC semiconductor device described in another embodiment
  • FIG. 15 is a cross-sectional view of a SiC semiconductor device described in another embodiment
  • 16A is a cross-sectional view of a conventional SiC semiconductor device
  • FIG. 16B is an enlarged view of a portion XVIB in FIG.
  • FIG. 16A is a cross-sectional view of a conventional SiC semiconductor device
  • FIG. 16B is an enlarged view of a portion XVIB in FIG.
  • FIG. 16A is a cross-sectional view
  • FIG. 17A is a cross-sectional view of the SiC semiconductor device according to the first embodiment of the present disclosure
  • FIG. 17B is an enlarged view of a portion XVIIB in FIG.
  • FIG. 18 is a diagram illustrating the concentration distribution of the upper portion of the electric field relaxation layer of the SiC semiconductor device according to the conventional technique and the first embodiment of the present disclosure.
  • FIG. 1 An SiC semiconductor device having a vertical MOSFET having an inverted trench gate structure according to the present embodiment will be described with reference to FIG. In FIG. 1, only one cell of the vertical MOSFET is shown, but a plurality of cells having the same structure as the vertical MOSFET shown in FIG. 1 are arranged adjacent to each other.
  • an SiC single crystal having a thickness of about 300 ⁇ m is doped with an n-type impurity (such as phosphorus or nitrogen) at a high concentration, for example, an impurity concentration of 1 ⁇ 10 19 to 1 ⁇ 10 20 cm ⁇ 3.
  • An n + type semiconductor substrate 1 is used.
  • an n type drift layer made of SiC having a thickness of about 10 to 15 ⁇ m doped with an n type impurity at an impurity concentration of 1 ⁇ 10 15 to 1 ⁇ 10 16 cm ⁇ 3 , for example. 2 is formed.
  • the n-type drift layer 2 is formed with a recessed portion (first recessed portion) 2a that is partially recessed.
  • the concave portion 2a is formed in a linear shape having one direction (perpendicular to the paper surface) as a longitudinal direction, and extends to a position deeper than a trench 7 constituting a trench gate structure to be described later, and the same direction as the trench 7 is a longitudinal direction. It is formed as.
  • An electric field relaxation layer 3 doped with a p-type impurity (such as boron or aluminum) is formed below the bottom of the recess 2a and in the recess 2a with the same direction as the longitudinal direction of the recess 2a. .
  • a portion located below the bottom of the recess 2 a, that is, a portion deeper than the trench 7 is a high concentration region (first region) 3 a in which the p-type impurity concentration is high. Yes.
  • a portion of the electric field relaxation layer 3 located inside the recess 2a is a low concentration region (second region) 3b in which the p-type impurity concentration is lower than that of the high concentration region 3a.
  • the electric field relaxation layer 3 is constituted by the high concentration region 3a and the low concentration region 3b having different impurity concentrations.
  • the high concentration region 3a is, for example, about 1 ⁇ 10 17 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the low concentration region 3b is set to about 1 ⁇ 10 15 to 1 ⁇ 10 18 cm ⁇ 3 so that the concentration is set lower than that of the high concentration region 3a.
  • the low concentration region 3b is configured with a uniform impurity concentration throughout the region.
  • the high concentration region 3a is wider than the low concentration region 3b with respect to the width of the electric field relaxation layer 3, that is, the dimension perpendicular to the longitudinal direction of the electric field relaxation layer 3 in the plane direction parallel to the substrate plane.
  • the electric field relaxation layer 3 is disposed on both sides of a trench 7 constituting a trench gate structure described later so that the low concentration region 3b is separated from the side surface of the trench 7 by a predetermined distance.
  • W1> W2 and W3 where W1 is the distance between adjacent low concentration regions 3b located on both sides of the trench gate structure, W2 is the distance between the high concentration regions 3a, and W3 is the width of the trench gate structure. And preferably the relationship of W2> W3 is also satisfied.
  • W2> W3 it is possible to prevent the JFET region from expanding between the adjacent electric field relaxation layers 3 and to secure the shortest current path between the trench gate structure and the drain electrode 12 described later, thereby increasing the on-resistance. Can be suppressed.
  • the depth of the electric field relaxation layer 3 is such that the low concentration region 3b is formed to a position deeper than the bottom of the trench 7 in the trench gate structure, so that the entire region of the high concentration region 3a is deeper than the bottom of the trench 7. It is designed to be formed at a position.
  • a p-type base region 4 is formed on the surfaces of the n-type drift layer 2 and the electric field relaxation layer 3.
  • the p-type base region 4 is a layer constituting a channel of the vertical MOSFET, and is formed on both sides of a trench 7 constituting a trench gate structure described later so as to be in contact with the side surface of the trench 7.
  • n + -type source region 5 doped with an n-type impurity at a high concentration so as to be in contact with the trench gate structure is located closer to the trench gate structure side than the position corresponding to the electric field relaxation layer 3 in the surface layer portion of the p-type base region 4. Is formed.
  • the n + -type source region 5 is formed with an impurity concentration of about 1 ⁇ 10 21 cm ⁇ 3 and a thickness of about 0.3 ⁇ m.
  • a p + -type contact region doped with a p-type impurity at a high concentration is provided between the surface layer portion of the p-type base region 4 and the position corresponding to the electric field relaxation layer 3, that is, between the opposing n + -type source region 5. 6 is formed.
  • the p + -type contact region 6 is formed with an impurity concentration of about 1 ⁇ 10 21 cm ⁇ 3 and a thickness of about 0.3 ⁇ m.
  • the n-type drift layer 2 is reached through the p-type base region 4 and the n + -type source region 5 at the center position of the electric field relaxation layers 3 arranged adjacent to each other, and A trench 7 which is shallower than the bottom of the relaxation layer 3 is formed.
  • a p-type base region 4 and an n + -type source region 5 are arranged in contact with the side surface of the trench 7.
  • the inner wall surface of the trench 7 is covered with a gate insulating film 8 made of an oxide film or the like, and the gate electrode 9 made of doped Poly-Si formed on the surface of the gate insulating film 8 makes it possible to Is filled up.
  • the trench gate structure is configured by the structure in which the gate insulating film 8 and the gate electrode 9 are provided in the trench 7.
  • the trench gate structure is, for example, a strip with the vertical direction on the paper as the longitudinal direction, and a plurality of trench gate structures are arranged in stripes at equal intervals in the horizontal direction of the paper. As a result, the structure is provided with a plurality of cells.
  • a source electrode 10 is formed on the surfaces of the n + type source region 5 and the p + type contact region 6.
  • the source electrode 10 is composed of a plurality of metals (for example, Ni / Al). Specifically, the portion connected to n + type source region 5 is made of a metal capable of ohmic contact with n type SiC, and the portion connected to p type base region 4 via p + type contact region 6 is It is made of a metal capable of ohmic contact with p-type SiC.
  • the source electrode 10 is electrically separated from a gate wiring (not shown) that is electrically connected to the gate electrode 9 via the interlayer insulating film 11.
  • the source electrode 10 is in electrical contact with the n + type source region 5 and the p + type contact region 6 through a contact hole formed in the interlayer insulating film 11.
  • n + -type semiconductor substrate 1 On the back side of the n + -type semiconductor substrate 1 n + -type semiconductor substrate 1 and electrically connected to the drain electrode 12 are formed. With such a structure, an n-channel type inverted MOSFET having a trench gate structure is formed.
  • a high voltage eg, 1200 V
  • SiC having an electric field breakdown strength nearly 10 times that of a silicon device
  • an electric field close to 10 times that of a silicon device is applied to the gate insulating film 8 due to the influence of this voltage, and the gate insulating film 8 (in particular, the trench in the gate insulating film 8).
  • An electric field concentration can occur at the bottom of 7).
  • the electric field relaxation layer 3 is deeper than the trench 7 and the high concentration region 3a is formed at a deep position. For this reason, the depletion layer at the PN junction between the high concentration region 3a and the n-type drift layer 2 in the electric field relaxation layer 3 greatly extends toward the n-type drift layer 2, and the high voltage due to the influence of the drain voltage is It becomes difficult to enter the insulating film 8. In particular, since the high concentration region 3a is wider than the low concentration region 3b and the distance W2 between the high concentration regions 3a is narrowed, a high voltage due to the influence of the drain voltage is less likely to enter the gate insulating film 8. .
  • the high concentration region 3a deeper than the trench gate structure in the electric field relaxation layer 3, a portion shallower than the high concentration region 3a is used as the low concentration region 3b.
  • the low concentration region 3b is arranged in the portion to be formed. For this reason, it is possible to suppress the spread of the depletion layer extending from the low concentration region 3b to the n-type drift layer 2 on the trench 7 side, that is, the channel side, as compared with the case where the entire electric field relaxation layer 3 is configured with a high concentration. Thus, the effect of suppressing the JFET resistance can be obtained.
  • the electric field relaxation layer 3 and the trench gate structure are arranged in parallel and are not in a state of intersecting. For this reason, as will be described later, even if the high concentration region 3a in the electric field relaxation layer 3 is formed by ion implantation, damage due to ion implantation in the high concentration region 3a and each part formed by epitaxial growth on the high concentration region 3a.
  • the trench gate structure can be separated from the remaining portion. Furthermore, since the ion-implanted region is only the high-concentration region 3a, damage caused by ion implantation in the crystal can be minimized.
  • FIG. 1 Next, a method of manufacturing the trench gate type vertical MOSFET shown in FIG. 1 will be described with reference to FIGS. 2 (a) to 3 (d).
  • an epitaxial substrate is prepared in which an n type drift layer 2 is epitaxially grown on the surface of an n + type semiconductor substrate 1 made of a SiC single crystal doped with an n type impurity at a high concentration.
  • Step shown in FIG. 2 (b)] After depositing a mask material such as an oxide film on the n-type drift layer 2, the mask 20 is opened by opening the region to be formed with the recess 2a, that is, the region to be formed with the p-type deep layer 3b. Form. Then, anisotropic etching such as RIE (Reactive Ion Etching) is performed using the mask 20. Thereby, the surface layer portion of the n-type drift layer 2 is removed at the opening of the mask 20 to form the recess 2a. The depth and width of the recess 2a are set so that the final depth and width of the final low-concentration region 3b become target values in consideration of thermal diffusion in each process performed thereafter. In the case of SiC, since the diffusion amount due to thermal diffusion is very small, the dimensions of the recess 2a are determined with the same dimensions as the final depth and width of the final low-concentration region 3b without taking into account thermal diffusion. Also good.
  • RIE Reactive Ion Etching
  • Step shown in FIG. 2 (c)] After removing the mask 20 used to form the recess 2a, p-type impurities are ion-implanted into the bottom of the recess 2a using an ion implantation mask (not shown). Then, the high concentration region 3a is formed by activating the implanted impurities by heat treatment or the like. The lateral expansion of the high-concentration region 3a at this time is partly due to thermal diffusion, but basically the high-concentration region is obtained by implanting p-type impurities in a laterally expanded state by oblique ion implantation. 3a is configured to have a desired width.
  • the low concentration region 3b is epitaxially grown in the recess 2a.
  • the p-type impurity layer 3 can be formed by performing epitaxial growth using a CVD (Chemical Vapor Deposition) apparatus while introducing a gas containing a dopant into the atmosphere.
  • the p-type base region 4 can be simultaneously formed on the surface of the p-type drift layer 2, but here, only the low concentration region 3 b is formed, and it is not necessary to be formed on the p-type drift layer 2.
  • the portion is removed by CMP (Chemical Mechanical Polishing) or the like.
  • the low concentration region 3b is epitaxially grown in the recess 2a by a technique such as CVD, the entire low concentration region 3b can be formed with a uniform impurity concentration.
  • the p-type base region 4 is epitaxially grown by the same method as the low concentration region 3b. At this time, as described above, the p-type base region 4 can be formed simultaneously with the low-concentration region 3b, so that the manufacturing process can be simplified. It is also possible to set the density separately.
  • the gate insulating film 8 is formed by performing a gate oxidation process after removing the etching mask. Further, after forming a polysilicon layer doped with impurities on the surface of the gate insulating film 8, the gate electrode 9 is formed by patterning the polysilicon layer. Thereby, a trench gate structure is formed.
  • Step shown in FIG. 3B After forming a mask (not shown) in which a region where the n + type source region 5 is to be formed is opened on the surface of the p type base region 4, n type impurities are ion-implanted at a high concentration from above to form an n + type. A source region 5 is formed. Similarly, after forming a mask (not shown) in which a region where the p + -type contact region 6 is to be formed is opened on the surface of the p-type base region 4, p-type impurities are ion-implanted at a high concentration from above. A p + -type contact region 6 is formed.
  • the cross section is formed differently from the cross section. Then, after depositing an electrode material so as to fill the contact hole, the source material 10 and a gate wiring (not shown) are formed by patterning the electrode material.
  • a drain electrode 12 is formed on the back side of the n + type semiconductor substrate 1. Thereby, the vertical MOSFET shown in FIG. 1 is completed.
  • the structure includes the electric field relaxation layer 3 deeper than the trench 7, and the high concentration region 3a is formed at a deep position, and the shallower region is defined as the low concentration region 3b. It is said. For this reason, the electric field relaxation effect and the JFET resistance reduction effect can be obtained.
  • the electric field relaxation layer 3 and the trench gate structure are arranged in parallel so that they do not intersect. For this reason, the trench gate structure can be separated from the high-concentration region 3a and a portion where damage due to ion implantation among the portions formed by epitaxial growth thereon can remain. Furthermore, since the ion-implanted region is only the high-concentration region 3a, damage caused by ion implantation in the crystal can be minimized. Therefore, it is possible to suppress the occurrence of variations in the quality of the gate insulating film 8, to suppress the formation of a leak path, and to suppress a decrease in the reliability of the trench gate. An SiC semiconductor device having a high trench gate structure can be obtained.
  • the impurity concentration of the low concentration region 3b is uniform throughout the entire region.
  • the impurity concentration of the low impurity region 3b varies in the depth direction, the depletion layer expands due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers 3 is narrowed. This causes an increase in resistance.
  • the impurity concentration of the low concentration region 3b is uniform throughout the region as in the present embodiment, there is no variation in the expansion of the depletion layer and the current path between the electric field relaxation layers 3 is narrow. Does not occur. Therefore, it is possible to obtain an electric field relaxation effect while suppressing an increase in on-resistance.
  • the depletion layer is likely to vary in elongation due to the concentration of the impurity concentration, and the influence is likely to occur. By doing so, it becomes possible to obtain an effect of suppressing an increase in on-resistance.
  • FIGS. 16A and 16B are a cross-sectional view and a partially enlarged view of a SiC semiconductor device according to the prior art (Japanese Patent No. 5539931).
  • Japanese Patent No. 5539931 Japanese Patent No. 5539931.
  • the depletion layer extends due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers is narrowed. Cause an increase.
  • the impurity concentration of the low concentration region 3b that is, the second region is set to a uniform concentration.
  • 17A and 17B are a cross-sectional view and a partially enlarged view of the SiC semiconductor device of this example.
  • FIG. 18 shows the depth distribution of the impurity concentration in the upper part of the electric field relaxation layer of the SiC semiconductor device of the prior art and this example, that is, the second region.
  • the impurity concentration varies between yi and yd, whereas in the SiC semiconductor device of this example, the impurity concentration is larger than the lowest impurity concentration of the prior art and lower than the highest impurity concentration. Yes.
  • the formation position of the high impurity region 3a and the low impurity region 3b can be set by self-alignment (self-alignment) with respect to the formation position of the recess 2a. For this reason, the formation position shift with respect to a trench gate structure can be suppressed.
  • the high impurity region 3a and the low impurity region 3b are formed by ion implantation, the high impurity region 3a and the low impurity region 3b are formed as shown in FIGS. Forming position deviation may occur. Then, when the formation position deviation occurs as shown in FIG. 5, the formation of the high impurity region 3a with respect to the trench gate structure is compared with the case where the formation position deviation does not occur as shown in FIG. By shifting the position, the current path indicated by the arrow in the figure becomes longer.
  • the manufacturing method of the present embodiment a structure in which the formation position shift does not occur as shown in FIG. 4 can be obtained, and the current path can be made the shortest current path. As a result, it is possible to further suppress an increase in on-resistance.
  • the width of the high concentration region 3a is set to be equal to or less than the width of the low concentration region 3b.
  • the distance W2 between the high concentration regions 3a is set to satisfy W1 ⁇ W2 with respect to the distance W1 between the low concentration regions 3b located on both sides of the trench gate structure.
  • the width of the high concentration region 3a is reduced to the low concentration region. You may set below the width
  • the p-type impurity is not directed to the oblique ion implantation in the step of FIG.
  • an ion implantation mask having a width of the opening of the ion implantation mask smaller than the width of the recess 2a may be used.
  • a third embodiment of the present disclosure will be described.
  • the method of forming the electric field relaxation layer 3 is changed with respect to the first and second embodiments.
  • the other aspects are the same as those in the first and second embodiments. Only portions different from the embodiment will be described.
  • the electric field relaxation layer 3 can be formed with the same method also with respect to 2nd Embodiment. .
  • an epitaxial substrate having an n type drift layer 2 formed on the surface of an n + type semiconductor substrate 1 is prepared in the same manner as the step shown in FIG.
  • an ion implantation mask (not shown) is arranged on the surface of the n-type drift layer 2, and then a high-concentration region 3a and a low-concentration region 3b are formed by ion implantation of p-type impurities.
  • a first mask having an opening having a width corresponding to the high concentration region 3a is disposed, and then p-type impurities are ion-implanted using the first mask as an ion implantation mask.
  • Ion implantation for forming the low concentration region 3b is performed by a box profile. Thereby, the low concentration region 3b is formed with a uniform impurity concentration.
  • the implanted p-type ions are activated to form the high concentration region 3a and the low concentration region 3b.
  • the acceleration voltage of the ion implantation is changed so that the ion implantation for forming the high concentration region 3a has a higher acceleration voltage than the ion implantation for forming the low concentration region 3b.
  • the high concentration region 3a is formed at a deeper position. Further, by changing the dose amount of the p-type impurity at the time of ion implantation, the high concentration region 3a is formed with a higher impurity concentration than the low concentration region 3b.
  • the p-type base region 4 is formed in the same manner as the step shown in FIG. 2C, and then, FIG. 2D, FIG. 2E, FIG. Steps a) to steps similar to those shown in FIG. Thereby, the SiC semiconductor device having the trench gate type vertical MOSFET according to the present embodiment is completed.
  • the high concentration region 3a but also the low concentration region 3b of the electric field relaxation layer 3 can be formed by ion implantation. Even if it does in this way, it becomes possible to acquire the effect similar to 1st, 2nd embodiment.
  • the impurity concentration of the portion of the n-type drift layer 2 located above the high-concentration region 3a is made higher than that of the other portions of the n-type drift layer 2.
  • the high concentration layer 2b is used.
  • the n-type impurity concentration of the high concentration layer 2b is set to be higher by about 2.0 ⁇ 10 15 cm ⁇ 3 than the other portions of the n-type drift layer 2.
  • the width of the depletion layer extending into the n-type drift layer 2 in the vicinity of the trench 7 can be reduced. Therefore, in addition to the decrease in internal resistance due to the increase in the impurity concentration of the high concentration layer 2b, the width of the depletion layer in the n-type drift layer 2 can be reduced, so that the JFET resistance can be further reduced. Become.
  • an epi substrate in which a part of the n type drift layer 2 is formed on the surface of the n + type semiconductor substrate 1 is prepared in the same manner as the step shown in FIG. . 9B, an ion implantation mask (not shown) is disposed on a part of the surface of the n-type drift layer 2, and then a high-concentration region 3a is formed by ion implantation of p-type impurities. At this time, the high concentration region 3 a is formed from a part of the surface of the n-type drift layer 2.
  • the high concentration region 3a is formed by ion implantation.
  • a recess is formed in a region where the high concentration region 3a is to be formed by etching, a p-type impurity layer is buried in the recess by epitaxial growth, and then flattened by polishing, thereby forming the high concentration region 3a. It is good also as the manufacturing method of forming.
  • the high-concentration layer 2b which remains the n-type drift layer 2 is epitaxially grown on the surface of the high-concentration region 3a and a part of the n-type drift layer 2.
  • the step similar to FIG. 2B is performed to form the recess 2a in the high concentration layer 2b, and then in the step shown in FIG. 9E.
  • the low concentration region 3b is formed by performing the same process as in FIG.
  • the side surface of the low concentration region 3b is illustrated as being perpendicular to the surface of the n + type semiconductor substrate 1, but it is not always necessary to be perpendicular.
  • the width of the upper portion of the low concentration region 3b is made narrower than the lower portion, thereby tilting the side surface of the low concentration region 3b. It may be a tapered shape. As shown in FIG.
  • the width of the lower portion of the low concentration region 3b is narrower than that of the upper portion in the direction parallel to the surface of the n + type semiconductor substrate 1, so that the side surface of the low concentration region 3b is opposite to that of FIG. It may be made into the reverse taper shape made to incline.
  • the side surface of the recess 2a is The taper shape or the inverse taper shape may be used.
  • the etching conditions for forming the concave portion 2a may be adjusted.
  • the shape of the high concentration region 3a is also shown as a quadrangular shape with rounded corners in the cross section cut in the direction perpendicular to the longitudinal direction of the trench gate structure in each of the above embodiments, as shown in FIG.
  • the cross-sectional shape may be an oval shape.
  • the impurity concentration of the high concentration region 3a does not need to be uniform over the entire region. For example, the impurity concentration may be increased as it becomes deeper, that is, as it approaches the n + type semiconductor substrate 1.
  • region 3a among the n-type drift layers 2 is made into the high concentration layer 2b.
  • the high-concentration layer 2b does not need to be formed in the entire region of the n-type drift layer 2 that is located above the high-concentration region 3a, and more specifically so as to surround at least the bottom of the trench gate structure. May be formed in a portion to be a current path.
  • the high concentration layer 2 b is formed in the entire region above a predetermined distance from the high concentration region 3 a, or while surrounding the bottom of the trench gate structure as shown in FIG. 15,
  • the high concentration layer 2b may be formed so as to be away from the high concentration region 3a and the low concentration region 3b.
  • the high concentration layer 1b can be formed by selective epitaxial growth or ion implantation.
  • an n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example.
  • the present disclosure can be applied to a channel type MOSFET.
  • a MOSFET having a trench gate structure has been described as an example, but the present disclosure can be applied to an IGBT having a similar trench gate structure.
  • the IGBT only changes the conductivity type of the substrate 1 from the n-type to the p-type with respect to the above-described embodiments, and the other structures and manufacturing methods are the same as those of the above-described embodiments.

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Abstract

A silicon carbide semiconductor device of the present invention comprises: a substrate (1); a drift layer (2) which is above the substrate; a base region (4) which is above the drift layer; a plurality of source regions (5) in the upper layer section of the base region; a contact region (6) between the source regions in the upper layer section of the base region; a plurality of trenches (7) formed from the surface of the source regions to a location which is deeper than the base region; a gate electrode (9) which is above a gate insulation film within the trenches; a source electrode (10) connected to the source regions and the contact regions; a drain electrode (12) on the back of the substrate; and a plurality of field relaxing layers (3) between the trenches within the drift layer. Each of the plurality of field relaxing layers has a first region (3a) deeper than the trenches and a second region (3b) formed from the surface of the drift layer to the first region.

Description

炭化珪素半導体装置およびその製造方法Silicon carbide semiconductor device and manufacturing method thereof 関連出願の相互参照Cross-reference of related applications
　本出願は、２０１４年９月１６日に出願された日本出願番号２０１４－１８７９４６号および２０１５年５月２９日に出願された日本出願番号２０１５－１１０１６７号に基づくもので、ここにその記載内容を援用する。 This application is based on Japanese application number 2014-187946 filed on September 16, 2014 and Japanese application number 2015-110167 filed on May 29, 2015. Incorporate.
　本開示は、トレンチゲート構造を有する炭化珪素（以下、ＳｉＣという）にて構成された半導体装置およびその製造方法に関するものである。 The present disclosure relates to a semiconductor device made of silicon carbide (hereinafter referred to as SiC) having a trench gate structure and a method for manufacturing the same.
　従来より、大電流が流せるようにチャネル密度を高くした構造としてトレンチゲート構造を有するＳｉＣ半導体装置がある。このようなトレンチゲート構造のＳｉＣ半導体装置では、ＳｉＣの破壊電界強度が高く、トレンチ底部に高電界が加わることで絶縁破壊が生じる可能性がある。このため、対向するトレンチゲート間のベース層の下部に１層構造の電界緩和層を形成して電界を緩和することで、絶縁破壊を防止することが行われている。 Conventionally, there is an SiC semiconductor device having a trench gate structure as a structure in which a channel density is increased so that a large current can flow. In the SiC semiconductor device having such a trench gate structure, the breakdown electric field strength of SiC is high, and there is a possibility that dielectric breakdown may occur due to the application of a high electric field to the bottom of the trench. For this reason, dielectric breakdown is prevented by forming an electric field relaxation layer having a single-layer structure below the base layer between the opposing trench gates to relax the electric field.
　しかしながら、１層構造の電界緩和層を備えることでトレンチゲート部への電界緩和効果が得られるものの、隣り合う電界緩和層間で空乏層が伸びてＪＦＥＴ抵抗領域を生じさせるため、オン抵抗が増大するという問題が発生する。 However, although an electric field relaxation effect to the trench gate portion can be obtained by providing the electric field relaxation layer having a single layer structure, a depletion layer extends between adjacent electric field relaxation layers to generate a JFET resistance region, thereby increasing the on-resistance. The problem occurs.
　一方、基板表面からトレンチゲートより深い箇所に至るまで電界緩和層を形成した構造とし、電界緩和層を底部において横方向に幅を拡張した横領域を設け、トレンチゲートよりも下方に横領域が配置されるようにした構造のＭＯＳＦＥＴも提案されている。このような構造すれば、各横領域に挟まれた範囲内においてドリフト層内のキャリア密度を低くできることから、トレンチ底部より深い位置で電界強度分布を抑ることができ、耐圧特性を向上させることが可能となる。さらに、横領域の間の間隔が横領域の形成位置のみによって決まることから、トレンチゲートと電界緩和層の製造誤差に伴う位置ズレの影響を受けないようにできる。 On the other hand, it has a structure in which an electric field relaxation layer is formed from the substrate surface to a deeper position than the trench gate, and a lateral region is formed in which the electric field relaxation layer extends in the lateral direction at the bottom, and the lateral region is disposed below the trench gate. A MOSFET having such a structure has also been proposed. With such a structure, the carrier density in the drift layer can be lowered within the range sandwiched between the lateral regions, so that the electric field strength distribution can be suppressed deeper than the bottom of the trench, and the breakdown voltage characteristics can be improved. Is possible. Furthermore, since the interval between the lateral regions is determined only by the position where the lateral regions are formed, it is possible to avoid the influence of misalignment caused by manufacturing errors between the trench gate and the electric field relaxation layer.
　このような構造とする場合、基板表面からトレンチゲートより深い箇所に至るまで形成された電界緩和層が一律同濃度で構成されるが、低濃度で構成すると電界緩和効果が得られないため、高濃度で構成することになる。ところが、電界緩和層を高濃度で構成すると、電界緩和層からの空乏層がトレンチ近傍に伸び易くなり、その結果、ＪＦＥＴ抵抗領域が生じるため、オン抵抗が増大するという問題が発生する。 In the case of such a structure, the electric field relaxation layer formed from the substrate surface to a portion deeper than the trench gate is configured with the same concentration, but if it is configured with a low concentration, the electric field relaxation effect cannot be obtained. Consists of concentration. However, if the electric field relaxation layer is formed at a high concentration, the depletion layer from the electric field relaxation layer is likely to extend in the vicinity of the trench, and as a result, a JFET resistance region is generated, resulting in a problem that the on-resistance is increased.
　そこで、上記各構造において生じる問題の改善策として、特許文献１に示すＳｉＣ半導体装置が提案されている。具体的には、一方向を長手方向とするトレンチゲートに対して交差するように電界緩和層を形成しつつ、電界緩和層を深さ方向において不純物濃度が異なる二層構造で構成し、深い部分が高濃度領域、浅い部分が低濃度領域となる構造としている。このような構造とすることで、高濃度領域とされた深い層でトレンチ底部の電界を緩和する効果と、低濃度領域とされた浅い層でトレンチ近傍に空乏層が延びることを抑えてＪＦＥＴ抵抗を低減する効果の両方を得ている。また、電界緩和層とトレンチの位置ズレによる製造誤差を起こり難くすることも可能となる。 Therefore, an SiC semiconductor device shown in Patent Document 1 has been proposed as a measure for improving the problems that occur in each of the above structures. Specifically, the electric field relaxation layer is formed to have a two-layer structure with different impurity concentrations in the depth direction while forming the electric field relaxation layer so as to intersect with the trench gate whose longitudinal direction is one direction, and a deep portion Has a structure in which a high concentration region and a shallow portion become a low concentration region. With such a structure, the effect of relaxing the electric field at the bottom of the trench in the deep layer made the high concentration region, and the extension of the depletion layer in the vicinity of the trench in the shallow layer made the low concentration region are suppressed. Both have the effect of reducing. In addition, it is possible to make it difficult to cause a manufacturing error due to the positional deviation between the electric field relaxation layer and the trench.
　しかしながら、特許文献１の構造では、電界緩和効果やＪＦＥＴ抵抗低減効果および製造誤差許容大という効果が得られるものの、電界緩和層形成の際に生じた結晶構造中のダメージ上にトレンチゲートを形成することになるため、トレンチゲートの信頼性が低下する。すなわち、イオン注入によって電界緩和層を形成したのち、この上にベース領域等をエピタキシャル成長させてから電界緩和層に交差するようにしている。このため、イオン注入時の結晶欠陥がその上に形成される層にも引き継がれ、その結晶欠陥が引き継がれる部分を交差するようにトレンチゲートを形成しているため、ゲート絶縁膜の出来栄えにバラツキが発生したり、リークパスが形成されたりする。このため、トレンチゲートの信頼性を低下させてしまうという問題が発生する。 However, in the structure of Patent Document 1, although an electric field relaxation effect, a JFET resistance reduction effect, and an allowable manufacturing error can be obtained, a trench gate is formed on the damage in the crystal structure caused when the electric field relaxation layer is formed. As a result, the reliability of the trench gate decreases. That is, after an electric field relaxation layer is formed by ion implantation, a base region or the like is epitaxially grown on the electric field relaxation layer and then intersected with the electric field relaxation layer. For this reason, crystal defects at the time of ion implantation are inherited by the layer formed thereon, and the trench gate is formed so as to intersect the portion where the crystal defects are inherited. Or a leak path is formed. For this reason, there arises a problem that the reliability of the trench gate is lowered.
特開２０１２－１６９３８６号公報JP 2012-169386 A
　本開示は、高耐圧かつ信頼性の高いトレンチゲート構造を有するＳｉＣ半導体装置およびその製造方法を提供することを目的とする。 An object of the present disclosure is to provide a SiC semiconductor device having a trench gate structure with high breakdown voltage and high reliability, and a method for manufacturing the same.
　本開示の第一の態様において、炭化珪素半導体装置は、炭化珪素からなる第１または第２導電型の基板と、前記基板の上に形成され、前記基板よりも低不純物濃度とされた第１導電型の炭化珪素からなるドリフト層と、前記ドリフト層の上に形成された第２導電型の炭化珪素からなるベース領域と、前記ベース領域の上層部に形成され、前記ドリフト層よりも高濃度の第１導電型の炭化珪素にて構成された複数のソース領域と、前記ベース領域の上層部において、対向する前記ソース領域の間に形成され、前記ベース層よりも高濃度の第２導電型の炭化珪素にて構成されたコンタクト領域と、前記ソース領域の表面から前記ベース領域よりも深くまで形成され、一方向を長手方向として複数本が並列されたトレンチと、前記トレンチの内壁面に形成されたゲート絶縁膜と、前記トレンチ内において、前記ゲート絶縁膜の上に形成されたゲート電極と、前記ソース領域および前記コンタクト領域に電気的に接続されたソース電極と、前記基板の裏面側に形成されたドレイン電極と、前記ベース領域よりも下方に位置する前記ドリフト層内に配置され、前記トレンチの長手方向と平行方向を長手方向として、複数本の前記トレンチの間のそれぞれにおいて該トレンチの側面から離間して配置され、第２導電型の炭化珪素で構成された複数本の電界緩和層と、を有する。前記複数本の電界緩和層には、前記トレンチよりも深い位置に形成された第１領域と、前記第１領域よりも低濃度で構成され、前記ドリフト層の表面から前記第１領域まで形成されていると共に均一濃度とされた第２領域とが備えられている。 In a first aspect of the present disclosure, a silicon carbide semiconductor device includes a first or second conductivity type substrate made of silicon carbide, and a first impurity formed on the substrate and having a lower impurity concentration than the substrate. A drift layer made of conductive silicon carbide; a base region made of silicon carbide of the second conductivity type formed on the drift layer; and a higher concentration than the drift layer formed in the upper layer portion of the base region. A plurality of source regions made of silicon carbide of the first conductivity type and an upper layer portion of the base region formed between the opposing source regions and having a second conductivity type having a higher concentration than the base layer A contact region made of silicon carbide, a trench formed from the surface of the source region to a depth deeper than the base region, and a plurality of parallel trenches with one direction as a longitudinal direction, and an inner wall of the trench A gate electrode formed on the gate insulating film in the trench, a source electrode electrically connected to the source region and the contact region, and a back surface of the substrate And a drain electrode formed on the side, and disposed in the drift layer located below the base region, and the longitudinal direction parallel to the longitudinal direction of the trench is the longitudinal direction of the trench between the trenches. And a plurality of electric field relaxation layers made of silicon carbide of the second conductivity type and spaced from the side surface of the trench. The plurality of electric field relaxation layers include a first region formed deeper than the trench and a lower concentration than the first region, and is formed from the surface of the drift layer to the first region. And a second region having a uniform density.
　このように、トレンチよりも深い電界緩和層を備えた構造としており、かつ、深い位置において高濃度な第１領域を構成している。このため、電界緩和層における第１領域とドリフト層とのＰＮ接合部での空乏層がドリフト層側に大きく伸びることになり、ドレイン電圧の影響による高電圧がゲート絶縁膜に入り込み難くなる。したがって、ゲート絶縁膜内での電界集中、特にゲート絶縁膜のうちのトレンチの底部での電界集中を緩和することが可能となる。これにより、ゲート絶縁膜が破壊されることを防止することが可能となる。 Thus, the structure is provided with the electric field relaxation layer deeper than the trench, and the high-concentration first region is formed at a deep position. For this reason, the depletion layer at the PN junction between the first region and the drift layer in the electric field relaxation layer greatly extends to the drift layer side, and a high voltage due to the influence of the drain voltage hardly enters the gate insulating film. Therefore, electric field concentration in the gate insulating film, particularly electric field concentration at the bottom of the trench in the gate insulating film can be reduced. Thereby, it is possible to prevent the gate insulating film from being destroyed.
　また、第２領域の不純物濃度を均一濃度としている。第２領域の不純物濃度が深さ方向にバラツキを有する場合、不純物濃度の濃淡による空乏層の伸びのバラツキが生じ、電界緩和層の間における電流経路が狭くなる場所が発生して、オン抵抗の増加の原因となる。これに対して、第２領域が均一濃度とされている場合、空乏層の伸びのバラツキが無く、電界緩和層の間における電流経路が狭くなる場所が発生しない。したがって、オン抵抗の増加を抑制しつつ、電界緩和効果を得ることが可能となる。 In addition, the impurity concentration in the second region is made uniform. When the impurity concentration of the second region varies in the depth direction, the depletion layer extends due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers is narrowed. Cause an increase. On the other hand, when the second region has a uniform concentration, there is no variation in the extension of the depletion layer, and there is no place where the current path between the electric field relaxation layers becomes narrow. Therefore, it is possible to obtain an electric field relaxation effect while suppressing an increase in on-resistance.
　本開示の第二の態様において、炭化珪素半導体装置の製造方法は、炭化珪素からなる第１または第２導電型の基板上に、該基板よりも低不純物濃度とされた第１導電型の炭化珪素からなるドリフト層を形成し、前記ドリフト層に対して、一方向を長手方向として複数本が並列された第２導電型の電界緩和層を形成し、前記電界緩和層および前記ドリフト層の上に第２導電型の炭化珪素からなるベース領域を形成し、前記ベース領域内における該ベース領域の上層部に、前記ドリフト層よりも高濃度の第１導電型の炭化珪素にて構成された複数のソース領域を形成し、前記ベース領域の上層部のうち、対向する前記ソース領域の間に、前記ベース層よりも高濃度の第２導電型の炭化珪素にて構成されたコンタクト領域を形成し、前記ソース領域の表面から前記ベース領域を貫通し、前記ドリフト層に達し、底面が前記電界緩和層の底面よりも浅く、かつ、前記電界緩和層の長手方向と平行方向を長手方向として、前記電界緩和層から離間して配置されたトレンチを形成し、前記トレンチの表面にゲート絶縁膜を形成し、前記トレンチ内において、前記ゲート絶縁膜の上にゲート電極を形成し、前記ソース領域および前記コンタクト領域に電気的に接続されるソース電極を形成し、前記基板の裏面側にドレイン電極を形成することを含む。前記電界緩和層の形成は、前記トレンチよりも深い位置に第１領域を形成し、前記ドリフト層の表面から前記第１領域まで該第１領域よりも低濃度かつ均一濃度で第２領域を形成することを含む。 In a second aspect of the present disclosure, a method for manufacturing a silicon carbide semiconductor device includes: a first conductivity type carbonization having a lower impurity concentration than that of a first or second conductivity type substrate made of silicon carbide. Forming a drift layer made of silicon, and forming a second conductivity type electric field relaxation layer in which a plurality of parallel layers with one direction as a longitudinal direction are formed in parallel with the drift layer, and over the electric field relaxation layer and the drift layer A base region made of silicon carbide of the second conductivity type is formed on the base region, and a plurality of layers made of silicon carbide of the first conductivity type higher in concentration than the drift layer are formed in an upper layer portion of the base region in the base region And a contact region made of silicon carbide of a second conductivity type higher in concentration than the base layer is formed between the opposing source regions in the upper layer portion of the base region. , The source region Penetrating the base region from the surface, reaching the drift layer, the bottom surface being shallower than the bottom surface of the electric field relaxation layer, and the longitudinal direction parallel to the longitudinal direction of the electric field relaxation layer from the electric field relaxation layer A trench arranged at a distance is formed, a gate insulating film is formed on the surface of the trench, a gate electrode is formed on the gate insulating film in the trench, and the source region and the contact region are electrically connected. Forming a source electrode connected to the substrate, and forming a drain electrode on the back side of the substrate. In the formation of the electric field relaxation layer, a first region is formed at a position deeper than the trench, and a second region is formed at a lower concentration and a uniform concentration than the first region from the surface of the drift layer to the first region. Including doing.
　上記の炭化珪素半導体装置の製造方法は、トレンチよりも深い電界緩和層を備えた構造としており、かつ、深い位置において高濃度な第１領域を構成している。このため、電界緩和層における第１領域とドリフト層とのＰＮ接合部での空乏層がドリフト層側に大きく伸びることになり、ドレイン電圧の影響による高電圧がゲート絶縁膜に入り込み難くなる。したがって、ゲート絶縁膜内での電界集中、特にゲート絶縁膜のうちのトレンチの底部での電界集中を緩和することが可能となる。これにより、ゲート絶縁膜が破壊されることを防止することが可能となる。 The above-described method for manufacturing a silicon carbide semiconductor device has a structure including an electric field relaxation layer deeper than the trench, and constitutes a high-concentration first region at a deep position. For this reason, the depletion layer at the PN junction between the first region and the drift layer in the electric field relaxation layer greatly extends to the drift layer side, and a high voltage due to the influence of the drain voltage hardly enters the gate insulating film. Therefore, electric field concentration in the gate insulating film, particularly electric field concentration at the bottom of the trench in the gate insulating film can be reduced. Thereby, it is possible to prevent the gate insulating film from being destroyed.
　また、第２領域の不純物濃度を均一濃度としている。第２領域の不純物濃度が深さ方向にバラツキを有する場合、不純物濃度の濃淡による空乏層の伸びのバラツキが生じ、電界緩和層の間における電流経路が狭くなる場所が発生して、オン抵抗の増加の原因となる。これに対して、第２領域が均一濃度とされている場合、空乏層の伸びのバラツキが無く、電界緩和層の間における電流経路が狭くなる場所が発生しない。したがって、オン抵抗の増加を抑制しつつ、電界緩和効果を得ることが可能となる。 In addition, the impurity concentration in the second region is made uniform. When the impurity concentration of the second region varies in the depth direction, the depletion layer extends due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers is narrowed. Cause an increase. On the other hand, when the second region has a uniform concentration, there is no variation in the extension of the depletion layer, and there is no place where the current path between the electric field relaxation layers becomes narrow. Therefore, it is possible to obtain an electric field relaxation effect while suppressing an increase in on-resistance.
　本開示の第三の態様において、炭化珪素半導体装置は、炭化珪素からなる第１または第２導電型の基板と、前記基板の上に形成され、前記基板よりも低不純物濃度とされた第１導電型の炭化珪素からなるドリフト層と、前記ドリフト層の上に形成された第２導電型の炭化珪素からなるベース領域と、前記ベース領域の上層部に形成され、前記ドリフト層よりも高濃度の第１導電型の炭化珪素にて構成された複数のソース領域と、前記ベース領域の上層部において、対向する前記ソース領域の間に形成され、前記ベース層よりも高濃度の第２導電型の炭化珪素にて構成されたコンタクト領域と、前記ソース領域の表面から前記ベース領域よりも深くまで形成され、一方向を長手方向として複数本が並列されたトレンチと、前記トレンチの内壁面に形成されたゲート絶縁膜と、前記トレンチ内において、前記ゲート絶縁膜の上に形成されたゲート電極と、前記ソース領域および前記コンタクト領域に電気的に接続されたソース電極と、前記基板の裏面側に形成されたドレイン電極と、前記ベース領域よりも下方に位置する前記ドリフト層内に配置され、前記トレンチの長手方向と平行方向を長手方向として、複数本の前記トレンチの間のそれぞれにおいて該トレンチの側面から離間して配置され、第２導電型の炭化珪素で構成された複数本の電界緩和層と、を有する。前記複数本の電界緩和層には、前記トレンチよりも深い位置に形成された第１領域と、前記ドリフト層の表面から前記第１領域まで形成されていると共に均一濃度とされた第２領域とが備えられている。隣り合う前記第２領域の間の距離をＷ１、隣り合う前記第１領域の間の距離をＷ２として、Ｗ１＞Ｗ２の関係を満たしている。前記トレンチ内に前記ゲート絶縁膜および前記ゲート電極が配置されることにより構成されるトレンチゲート構造の幅をＷ３として、Ｗ２＞Ｗ３の関係を満たしている。 In a third aspect of the present disclosure, a silicon carbide semiconductor device includes a first or second conductivity type substrate made of silicon carbide, and a first impurity formed on the substrate and having a lower impurity concentration than the substrate. A drift layer made of conductive silicon carbide; a base region made of silicon carbide of the second conductivity type formed on the drift layer; and a higher concentration than the drift layer formed in the upper layer portion of the base region. A plurality of source regions made of silicon carbide of the first conductivity type and an upper layer portion of the base region formed between the opposing source regions and having a second conductivity type having a higher concentration than the base layer A contact region made of silicon carbide, a trench formed from the surface of the source region to a depth deeper than the base region, and a plurality of parallel trenches with one direction as a longitudinal direction, and an inner wall of the trench A gate electrode formed on the gate insulating film in the trench, a source electrode electrically connected to the source region and the contact region, and a back surface of the substrate And a drain electrode formed on the side, and disposed in the drift layer located below the base region, and the longitudinal direction parallel to the longitudinal direction of the trench is the longitudinal direction of the trench between the trenches. And a plurality of electric field relaxation layers made of silicon carbide of the second conductivity type and spaced from the side surface of the trench. In the plurality of electric field relaxation layers, a first region formed deeper than the trench, a second region formed from the surface of the drift layer to the first region and having a uniform concentration, Is provided. The relationship between W1> W2 is satisfied, where W1 is the distance between the adjacent second regions, and W2 is the distance between the adjacent first regions. The width of the trench gate structure formed by disposing the gate insulating film and the gate electrode in the trench is W3, and the relationship of W2> W3 is satisfied.
　このように、トレンチよりも深い電界緩和層を備えた構造としており、かつ、深い位置において高濃度な第１領域を構成している。このため、電界緩和層における第１領域とドリフト層とのＰＮ接合部での空乏層がドリフト層側に大きく伸びることになり、ドレイン電圧の影響による高電圧がゲート絶縁膜に入り込み難くなる。したがって、ゲート絶縁膜内での電界集中、特にゲート絶縁膜のうちのトレンチの底部での電界集中を緩和することが可能となる。これにより、ゲート絶縁膜が破壊されることを防止することが可能となる。 Thus, the structure is provided with the electric field relaxation layer deeper than the trench, and the high-concentration first region is formed at a deep position. For this reason, the depletion layer at the PN junction between the first region and the drift layer in the electric field relaxation layer greatly extends to the drift layer side, and a high voltage due to the influence of the drain voltage hardly enters the gate insulating film. Therefore, electric field concentration in the gate insulating film, particularly electric field concentration at the bottom of the trench in the gate insulating film can be reduced. Thereby, it is possible to prevent the gate insulating film from being destroyed.
　また、第２領域の不純物濃度を均一濃度としている。第２領域の不純物濃度が深さ方向にバラツキを有する場合、不純物濃度の濃淡による空乏層の伸びのバラツキが生じ、電界緩和層の間における電流経路が狭くなる場所が発生して、オン抵抗の増加の原因となる。これに対して、第２領域が均一濃度とされている場合、空乏層の伸びのバラツキが無く、電界緩和層の間における電流経路が狭くなる場所が発生しない。したがって、オン抵抗の増加を抑制しつつ、電界緩和効果を得ることが可能となる。 In addition, the impurity concentration in the second region is made uniform. When the impurity concentration of the second region varies in the depth direction, the depletion layer extends due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers is narrowed. Cause an increase. On the other hand, when the second region has a uniform concentration, there is no variation in the extension of the depletion layer, and there is no place where the current path between the electric field relaxation layers becomes narrow. Therefore, it is possible to obtain an electric field relaxation effect while suppressing an increase in on-resistance.
　本開示についての上記目的およびその他の目的、特徴や利点は、添付の図面を参照しながら下記の詳細な記述により、より明確になる。その図面は、
図１は、本開示の第１実施形態にかかるＳｉＣ半導体装置の断面構成を示す図であり、 図２（ａ）から図２（ｅ）は、図１に示すＳｉＣ半導体装置の製造工程を示した断面図であり、 図３（ａ）から図３（ｄ）は、図２（ｅ）に続くＳｉＣ半導体装置の製造工程を示した断面図であり、 図４は、高不純物領域と低不純物濃度領域との位置ずれが発生していない場合のＳｉＣ半導体装置の断面図であり、 図５は、高不純物領域と低不純物濃度領域との位置ずれが発生した場合のＳｉＣ半導体装置の断面図であり、 図６は、本開示の第２実施形態にかかるＳｉＣ半導体装置の断面構成を示す図であり、 図７（ａ）から図７（ｃ）は、本開示の第３実施形態にかかるＳｉＣ半導体装置の製造工程を示した断面図であり、 図８は、本開示の第４実施形態にかかるＳｉＣ半導体装置の断面構成を示す図であり、 図９（ａ）から図９（ｅ）は、図６に示すＳｉＣ半導体装置の製造工程を示した断面図であり、 図１０（ａ）から図１０（ｅ）は、図９（ｅ）に続くＳｉＣ半導体装置の製造工程を示した断面図であり、 図１１は、他の実施形態で説明するＳｉＣ半導体装置の断面図であり、 図１２は、他の実施形態で説明するＳｉＣ半導体装置の断面図であり、 図１３は、他の実施形態で説明するＳｉＣ半導体装置の断面図であり、 図１４は、他の実施形態で説明するＳｉＣ半導体装置の断面図であり、 図１５は、他の実施形態で説明するＳｉＣ半導体装置の断面図であり、 図１６（ａ）は、従来技術のＳｉＣ半導体装置の断面図であり、図１６（ｂ）は、図１６（ａ）の部分ＸＶＩＢの拡大図であり、 図１７（ａ）は、本開示の第１実施形態にかかるＳｉＣ半導体装置の断面図であり、図１７（ｂ）は、図１７（ａ）の部分ＸＶＩＩＢの拡大図であり、 図１８は、従来技術と本開示の第１実施形態にかかるＳｉＣ半導体装置の電界緩和層上部の部分の濃度分布を示す図である。 The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
FIG. 1 is a diagram illustrating a cross-sectional configuration of the SiC semiconductor device according to the first embodiment of the present disclosure. 2 (a) to 2 (e) are cross-sectional views showing the manufacturing process of the SiC semiconductor device shown in FIG. 3 (a) to 3 (d) are cross-sectional views showing the manufacturing process of the SiC semiconductor device following FIG. 2 (e). FIG. 4 is a cross-sectional view of the SiC semiconductor device when the high impurity region and the low impurity concentration region are not misaligned. FIG. 5 is a cross-sectional view of the SiC semiconductor device in a case where a positional shift between the high impurity region and the low impurity concentration region occurs. FIG. 6 is a diagram illustrating a cross-sectional configuration of the SiC semiconductor device according to the second embodiment of the present disclosure, FIG. 7A to FIG. 7C are cross-sectional views illustrating manufacturing steps of the SiC semiconductor device according to the third embodiment of the present disclosure. FIG. 8 is a diagram illustrating a cross-sectional configuration of the SiC semiconductor device according to the fourth embodiment of the present disclosure. 9 (a) to 9 (e) are cross-sectional views showing the manufacturing process of the SiC semiconductor device shown in FIG. 10 (a) to 10 (e) are cross-sectional views showing the manufacturing process of the SiC semiconductor device following FIG. 9 (e), FIG. 11 is a cross-sectional view of a SiC semiconductor device described in another embodiment, FIG. 12 is a cross-sectional view of a SiC semiconductor device described in another embodiment, FIG. 13 is a cross-sectional view of a SiC semiconductor device described in another embodiment, FIG. 14 is a cross-sectional view of a SiC semiconductor device described in another embodiment, FIG. 15 is a cross-sectional view of a SiC semiconductor device described in another embodiment, 16A is a cross-sectional view of a conventional SiC semiconductor device, FIG. 16B is an enlarged view of a portion XVIB in FIG. FIG. 17A is a cross-sectional view of the SiC semiconductor device according to the first embodiment of the present disclosure, and FIG. 17B is an enlarged view of a portion XVIIB in FIG. FIG. 18 is a diagram illustrating the concentration distribution of the upper portion of the electric field relaxation layer of the SiC semiconductor device according to the conventional technique and the first embodiment of the present disclosure.
　（第１実施形態）
　本開示の第１実施形態について説明する。まず、本実施形態にかかる反転型のトレンチゲート構造の縦型ＭＯＳＦＥＴを有するＳｉＣ半導体装置について、図１を参照して説明する。なお、図１では、縦型ＭＯＳＦＥＴの１セル分しか記載していないが、図１に示す縦型ＭＯＳＦＥＴと同様の構造のものが複数セル隣り合うように配置されている。 (First embodiment)
A first embodiment of the present disclosure will be described. First, an SiC semiconductor device having a vertical MOSFET having an inverted trench gate structure according to the present embodiment will be described with reference to FIG. In FIG. 1, only one cell of the vertical MOSFET is shown, but a plurality of cells having the same structure as the vertical MOSFET shown in FIG. 1 are arranged adjacent to each other.
　図１に示すように、ｎ型不純物（リンもしくは窒素など）が高濃度、例えば１×１０19～１×１０20ｃｍ-3の不純物濃度でドープされた厚さ３００μｍ程度のＳｉＣ単結晶からなるｎ+型半導体基板１を用いている。このｎ+型半導体基板１の上に、ｎ型不純物が例えば１×１０15～１×１０16ｃｍ-3の不純物濃度でドープされた厚さが１０～１５μｍ程度のＳｉＣからなるｎ型ドリフト層２が形成されている。 As shown in FIG. 1, an SiC single crystal having a thickness of about 300 μm is doped with an n-type impurity (such as phosphorus or nitrogen) at a high concentration, for example, an impurity concentration of 1 × 10 19 to 1 × 10 20 cm −3. An n + type semiconductor substrate 1 is used. On this n + type semiconductor substrate 1, an n type drift layer made of SiC having a thickness of about 10 to 15 μm doped with an n type impurity at an impurity concentration of 1 × 10 15 to 1 × 10 16 cm −3 , for example. 2 is formed.
　また、ｎ型ドリフト層２には部分的に凹まされた凹部（第１凹部）２ａが形成されている。凹部２ａは、一方向（紙面垂直方向）を長手方向とした直線形状で構成されており、後述するトレンチゲート構造を構成するトレンチ７よりも深い位置まで、かつ、トレンチ７と同方向を長手方向として形成されている。 Further, the n-type drift layer 2 is formed with a recessed portion (first recessed portion) 2a that is partially recessed. The concave portion 2a is formed in a linear shape having one direction (perpendicular to the paper surface) as a longitudinal direction, and extends to a position deeper than a trench 7 constituting a trench gate structure to be described later, and the same direction as the trench 7 is a longitudinal direction. It is formed as.
　この凹部２ａの底部よりも下方と凹部２ａ内に、凹部２ａの長手方向と同方向を長手方向とした、ｐ型不純物（ボロンもしくはアルミニウムなど）がドープされた電界緩和層３が形成されている。電界緩和層３のうち、凹部２ａの底部よりも下方に位置する部分、つまりトレンチ７よりも深い部分は、ｐ型不純物濃度が高濃度とされた高濃度領域（第１領域）３ａとされている。また、電界緩和層３のうち凹部２ａ内部に位置する部分は、高濃度領域３ａよりもｐ型不純物濃度が低濃度とされた低濃度領域（第２領域）３ｂとされている。これら不純物濃度が異なる高濃度領域３ａおよび低濃度領域３ｂによって電界緩和層３が構成されている。 An electric field relaxation layer 3 doped with a p-type impurity (such as boron or aluminum) is formed below the bottom of the recess 2a and in the recess 2a with the same direction as the longitudinal direction of the recess 2a. . Of the electric field relaxation layer 3, a portion located below the bottom of the recess 2 a, that is, a portion deeper than the trench 7 is a high concentration region (first region) 3 a in which the p-type impurity concentration is high. Yes. Further, a portion of the electric field relaxation layer 3 located inside the recess 2a is a low concentration region (second region) 3b in which the p-type impurity concentration is lower than that of the high concentration region 3a. The electric field relaxation layer 3 is constituted by the high concentration region 3a and the low concentration region 3b having different impurity concentrations.
　高濃度領域３ａについては、例えば１×１０17～１×１０19ｃｍ-3程度としている。一方、低濃度領域３ｂについては１×１０15～１×１０18ｃｍ-3程度としており、高濃度領域３ａより濃度が低く設定されるようにしている。低濃度領域３ｂは、全域において均一の不純物濃度で構成されている。 The high concentration region 3a is, for example, about 1 × 10 17 to 1 × 10 19 cm −3 . On the other hand, the low concentration region 3b is set to about 1 × 10 15 to 1 × 10 18 cm −3 so that the concentration is set lower than that of the high concentration region 3a. The low concentration region 3b is configured with a uniform impurity concentration throughout the region.
　また、電界緩和層３の幅、つまり基板平面と平行な平面方向のうち電界緩和層３の長手方向に対する垂直方向の寸法について、高濃度領域３ａの方が低濃度領域３ｂよりも広くされている。具体的には、電界緩和層３は、後述するトレンチゲート構造を構成するトレンチ７の両側において、低濃度領域３ｂがトレンチ７の側面から所定距離離間するようにして配置されている。そして、トレンチゲート構造の両側に位置する隣り合う低濃度領域３ｂ間の距離をＷ１、高濃度領域３ａの間の距離をＷ２、トレンチゲート構造の幅をＷ３として、少なくともＷ１＞Ｗ２、Ｗ３の関係を満たし、好ましくはＷ２＞Ｗ３の関係も満たすようにしている。Ｗ２＞Ｗ３にすることにより、隣接する電界緩和層３同士でＪＦＥＴ領域が拡がるのを防ぐと共に、トレンチゲート構造と後述するドレイン電極１２との間の最短電流経路を確保でき、オン抵抗の上昇を抑えることができる。 Also, the high concentration region 3a is wider than the low concentration region 3b with respect to the width of the electric field relaxation layer 3, that is, the dimension perpendicular to the longitudinal direction of the electric field relaxation layer 3 in the plane direction parallel to the substrate plane. . Specifically, the electric field relaxation layer 3 is disposed on both sides of a trench 7 constituting a trench gate structure described later so that the low concentration region 3b is separated from the side surface of the trench 7 by a predetermined distance. A relationship between at least W1> W2 and W3, where W1 is the distance between adjacent low concentration regions 3b located on both sides of the trench gate structure, W2 is the distance between the high concentration regions 3a, and W3 is the width of the trench gate structure. And preferably the relationship of W2> W3 is also satisfied. By setting W2> W3, it is possible to prevent the JFET region from expanding between the adjacent electric field relaxation layers 3 and to secure the shortest current path between the trench gate structure and the drain electrode 12 described later, thereby increasing the on-resistance. Can be suppressed.
　さらに、電界緩和層３の深さについては、低濃度領域３ｂがトレンチゲート構造におけるトレンチ７の底部よりも深い位置まで形成されることで、高濃度領域３ａの全域がトレンチ７の底部よりも深い位置に形成されるようにしてある。 Furthermore, the depth of the electric field relaxation layer 3 is such that the low concentration region 3b is formed to a position deeper than the bottom of the trench 7 in the trench gate structure, so that the entire region of the high concentration region 3a is deeper than the bottom of the trench 7. It is designed to be formed at a position.
　また、ｎ型ドリフト層２および電界緩和層３の表面上に、ｐ型ベース領域４が形成されている。ｐ型ベース領域４は、縦型ＭＯＳＦＥＴのチャネルを構成する層であり、後述するトレンチゲート構造を構成するトレンチ７の両側において、トレンチ７の側面に接するように形成されている。 Further, a p-type base region 4 is formed on the surfaces of the n-type drift layer 2 and the electric field relaxation layer 3. The p-type base region 4 is a layer constituting a channel of the vertical MOSFET, and is formed on both sides of a trench 7 constituting a trench gate structure described later so as to be in contact with the side surface of the trench 7.
　ｐ型ベース領域４の表層部のうち電界緩和層３と対応する位置よりもトレンチゲート構造側には、トレンチゲート構造に接するようにｎ型不純物が高濃度にドープされたｎ+型ソース領域５が形成されている。本実施形態の場合、例えばｎ+型ソース領域５を不純物濃度が１×１０21ｃｍ-3程度、厚さが０．３μｍ程度で形成している。また、ｐ型ベース領域４の表層部のうち電界緩和層３と対応する位置、つまり対向するｎ+型ソース領域５の間には、ｐ型不純物が高濃度にドープされたｐ+型コンタクト領域６が形成されている。本実施形態の場合、例えばｐ+型コンタクト領域６を不純物濃度が１×１０21ｃｍ-3程度、厚さが０．３μｍ程度で形成している。 An n + -type source region 5 doped with an n-type impurity at a high concentration so as to be in contact with the trench gate structure is located closer to the trench gate structure side than the position corresponding to the electric field relaxation layer 3 in the surface layer portion of the p-type base region 4. Is formed. In the present embodiment, for example, the n + -type source region 5 is formed with an impurity concentration of about 1 × 10 21 cm −3 and a thickness of about 0.3 μm. Further, a p + -type contact region doped with a p-type impurity at a high concentration is provided between the surface layer portion of the p-type base region 4 and the position corresponding to the electric field relaxation layer 3, that is, between the opposing n + -type source region 5. 6 is formed. In this embodiment, for example, the p + -type contact region 6 is formed with an impurity concentration of about 1 × 10 21 cm −3 and a thickness of about 0.3 μm.
　さらに、図１の断面において、隣り合って配置された電界緩和層３の中央位置に、ｐ型ベース領域４およびｎ+型ソース領域５を貫通してｎ型ドリフト層２に達し、かつ、電界緩和層３の底部よりも浅くされたトレンチ７が形成されている。このトレンチ７の側面と接するようにｐ型ベース領域４およびｎ+型ソース領域５が配置されている。トレンチ７の内壁面は酸化膜などによって構成されたゲート絶縁膜８で覆われており、ゲート絶縁膜８の表面に形成されたドープトＰｏｌｙ－Ｓｉにて構成されたゲート電極９により、トレンチ７内が埋め尽くされている。このように、トレンチ７内にゲート絶縁膜８およびゲート電極９を備えた構造により、トレンチゲート構造が構成されている。 Further, in the cross section of FIG. 1, the n-type drift layer 2 is reached through the p-type base region 4 and the n + -type source region 5 at the center position of the electric field relaxation layers 3 arranged adjacent to each other, and A trench 7 which is shallower than the bottom of the relaxation layer 3 is formed. A p-type base region 4 and an n + -type source region 5 are arranged in contact with the side surface of the trench 7. The inner wall surface of the trench 7 is covered with a gate insulating film 8 made of an oxide film or the like, and the gate electrode 9 made of doped Poly-Si formed on the surface of the gate insulating film 8 makes it possible to Is filled up. Thus, the trench gate structure is configured by the structure in which the gate insulating film 8 and the gate electrode 9 are provided in the trench 7.
　なお、図１では示されていないが、トレンチゲート構造は、例えば紙面垂直方向を長手方向とした短冊状とされており、複数本のトレンチゲート構造が紙面左右方向に等間隔にストライプ状に並べられることで複数セルが備えられた構造とされている。 Although not shown in FIG. 1, the trench gate structure is, for example, a strip with the vertical direction on the paper as the longitudinal direction, and a plurality of trench gate structures are arranged in stripes at equal intervals in the horizontal direction of the paper. As a result, the structure is provided with a plurality of cells.
　また、ｎ+型ソース領域５およびｐ+型コンタクト領域６の表面には、ソース電極１０が形成されている。ソース電極１０は、複数の金属（例えばＮｉ／Ａｌ等）にて構成されている。具体的には、ｎ+型ソース領域５に接続される部分はｎ型ＳｉＣとオーミック接触可能な金属で構成され、ｐ+型コンタクト領域６を介してｐ型ベース領域４に接続される部分はｐ型ＳｉＣとオーミック接触可能な金属で構成されている。なお、ソース電極１０は、層間絶縁膜１１を介して、ゲート電極９に電気的に接続される図示しないゲート配線と電気的に分離されている。そして、層間絶縁膜１１に形成されたコンタクトホールを通じて、ソース電極１０はｎ+型ソース領域５およびｐ+型コンタクト領域６と電気的に接触させられている。 A source electrode 10 is formed on the surfaces of the n + type source region 5 and the p + type contact region 6. The source electrode 10 is composed of a plurality of metals (for example, Ni / Al). Specifically, the portion connected to n + type source region 5 is made of a metal capable of ohmic contact with n type SiC, and the portion connected to p type base region 4 via p + type contact region 6 is It is made of a metal capable of ohmic contact with p-type SiC. The source electrode 10 is electrically separated from a gate wiring (not shown) that is electrically connected to the gate electrode 9 via the interlayer insulating film 11. The source electrode 10 is in electrical contact with the n + type source region 5 and the p + type contact region 6 through a contact hole formed in the interlayer insulating film 11.
　さらに、ｎ+型半導体基板１の裏面側にはｎ+型半導体基板１と電気的に接続されたドレイン電極１２が形成されている。このような構造により、ｎチャネルタイプの反転型のトレンチゲート構造の縦型ＭＯＳＦＥＴが構成されている。 Further, on the back side of the n + -type semiconductor substrate 1 n + -type semiconductor substrate 1 and electrically connected to the drain electrode 12 are formed. With such a structure, an n-channel type inverted MOSFET having a trench gate structure is formed.
　このように構成された縦型ＭＯＳＦＥＴは、ゲート電極９に対してゲート電圧を印加すると、ｐ型ベース領域４のうちトレンチ７の側面に接する部分が反転型チャネルとなり、ソース電極１０とドレイン電極１２との間に電流を流す。 In the vertical MOSFET configured as described above, when a gate voltage is applied to the gate electrode 9, the portion of the p-type base region 4 that is in contact with the side surface of the trench 7 becomes an inversion channel, and the source electrode 10 and the drain electrode 12. Current flows between the two.
　一方、ゲート電圧を印加しない場合はドレイン電圧として高電圧（例えば１２００Ｖ）が印加される。シリコンデバイスの１０倍近い電界破壊強度を有するＳｉＣでは、この電圧の影響によりゲート絶縁膜８にもシリコンデバイスの１０倍近い電界がかかり、ゲート絶縁膜８（特に、ゲート絶縁膜８のうちのトレンチ７の底部において）に電界集中が発生し得る。 On the other hand, when no gate voltage is applied, a high voltage (eg, 1200 V) is applied as the drain voltage. In SiC having an electric field breakdown strength nearly 10 times that of a silicon device, an electric field close to 10 times that of a silicon device is applied to the gate insulating film 8 due to the influence of this voltage, and the gate insulating film 8 (in particular, the trench in the gate insulating film 8). An electric field concentration can occur at the bottom of 7).
　しかしながら、本実施形態では、トレンチ７よりも深い電界緩和層３を備えた構造としており、かつ、深い位置において高濃度領域３ａを構成している。このため、電界緩和層３における高濃度領域３ａとｎ型ドリフト層２とのＰＮ接合部での空乏層がｎ型ドリフト層２側に大きく伸びることになり、ドレイン電圧の影響による高電圧がゲート絶縁膜８に入り込み難くなる。特に、高濃度領域３ａを低濃度領域３ｂよりも幅広として、高濃度領域３ａの間の距離Ｗ２を狭くしていることから、よりドレイン電圧の影響による高電圧がゲート絶縁膜８に入り込み難くなる。 However, in the present embodiment, the electric field relaxation layer 3 is deeper than the trench 7 and the high concentration region 3a is formed at a deep position. For this reason, the depletion layer at the PN junction between the high concentration region 3a and the n-type drift layer 2 in the electric field relaxation layer 3 greatly extends toward the n-type drift layer 2, and the high voltage due to the influence of the drain voltage is It becomes difficult to enter the insulating film 8. In particular, since the high concentration region 3a is wider than the low concentration region 3b and the distance W2 between the high concentration regions 3a is narrowed, a high voltage due to the influence of the drain voltage is less likely to enter the gate insulating film 8. .
　したがって、ゲート絶縁膜８内での電界集中、特にゲート絶縁膜８のうちのトレンチ７の底部での電界集中を緩和することが可能となる。これにより、ゲート絶縁膜８が破壊されることを防止することが可能な高耐圧のＳｉＣ半導体装置となる。 Therefore, it is possible to alleviate electric field concentration in the gate insulating film 8, particularly electric field concentration at the bottom of the trench 7 in the gate insulating film 8. As a result, a high breakdown voltage SiC semiconductor device capable of preventing the gate insulating film 8 from being destroyed is obtained.
　また、電界緩和層３のうちトレンチゲート構造よりも深い位置に高濃度領域３ａを構成しつつ、高濃度領域３ａよりも浅い部分を低濃度領域３ｂとすることで、トレンチ７の側面においてチャネルが形成される部分には低濃度領域３ｂが配置されるようにしている。このため、電界緩和層３の全体を高濃度で構成する場合と比較して、低濃度領域３ｂからトレンチ７側、つまりチャネル側においてｎ型ドリフト層２に広がる空乏層の広がりを抑えることが可能となり、ＪＦＥＴ抵抗を抑える効果を得ることができる。 Further, by forming the high concentration region 3a deeper than the trench gate structure in the electric field relaxation layer 3, a portion shallower than the high concentration region 3a is used as the low concentration region 3b. The low concentration region 3b is arranged in the portion to be formed. For this reason, it is possible to suppress the spread of the depletion layer extending from the low concentration region 3b to the n-type drift layer 2 on the trench 7 side, that is, the channel side, as compared with the case where the entire electric field relaxation layer 3 is configured with a high concentration. Thus, the effect of suppressing the JFET resistance can be obtained.
　さらに、本実施形態の場合、電界緩和層３とトレンチゲート構造とが平行に並べられ、これらが交差していない状態となっている。このため、後述するように、電界緩和層３における高濃度領域３ａがイオン注入によって構成されていても、高濃度領域３ａやその上にエピタキシャル成長にて形成される各部のうちのイオン注入によるダメージが残り得る部分からトレンチゲート構造を離せる。さらに、イオン注入する領域が高濃度領域３ａのみであることから、結晶中のイオン注入によるダメージも最小限に抑えることができる。 Furthermore, in the case of this embodiment, the electric field relaxation layer 3 and the trench gate structure are arranged in parallel and are not in a state of intersecting. For this reason, as will be described later, even if the high concentration region 3a in the electric field relaxation layer 3 is formed by ion implantation, damage due to ion implantation in the high concentration region 3a and each part formed by epitaxial growth on the high concentration region 3a. The trench gate structure can be separated from the remaining portion. Furthermore, since the ion-implanted region is only the high-concentration region 3a, damage caused by ion implantation in the crystal can be minimized.
　よって、ゲート絶縁膜８の出来栄えにバラツキが発生することを抑制できると共に、リークパスが形成されることを抑制でき、トレンチゲートの信頼性の低下を抑制することが可能となる。これにより、高耐圧かつ信頼性の高いトレンチゲート構造を有するＳｉＣ半導体装置とすることが可能となる。 Therefore, it is possible to suppress the occurrence of variations in the quality of the gate insulating film 8 and to suppress the formation of a leak path, thereby suppressing a decrease in the reliability of the trench gate. As a result, it is possible to obtain a SiC semiconductor device having a trench gate structure with high breakdown voltage and high reliability.
　次に、図１に示すトレンチゲート型の縦型ＭＯＳＦＥＴの製造方法について、図２（ａ）～図３（ｄ）を参照して説明する。 Next, a method of manufacturing the trench gate type vertical MOSFET shown in FIG. 1 will be described with reference to FIGS. 2 (a) to 3 (d).
　〔図２（ａ）に示す工程〕
　まず、高濃度にｎ型不純物がドープされたＳｉＣ単結晶からなるｎ+型半導体基板１の表面にｎ型ドリフト層２がエピタキシャル成長させられたエピ基板を用意する。 [Step shown in FIG. 2 (a)]
First, an epitaxial substrate is prepared in which an n type drift layer 2 is epitaxially grown on the surface of an n + type semiconductor substrate 1 made of a SiC single crystal doped with an n type impurity at a high concentration.
　〔図２（ｂ）に示す工程〕
　ｎ型ドリフト層２の上に、酸化膜などのマスク材料をデポジションしたのち、これをパターニングすることで、凹部２ａの形成予定領域、つまりｐ型ディープ層３ｂの形成予定領域が開口するマスク２０を形成する。そして、このマスク２０を用いて、ＲＩＥ（Reactive Ion Etching）などの異方性エッチングを行う。これにより、マスク２０の開口部においてｎ型ドリフト層２の表層部を除去し、凹部２ａを形成する。凹部２ａの深さおよび幅については、この後に行われる各工程による熱拡散を考慮して、最終的な低濃度領域３ｂの出来上がりの深さおよび幅が狙い値となるように設定している。なお、ＳｉＣの場合、熱拡散による拡散量が非常に少ないことから、熱拡散を加味しないで最終的な低濃度領域３ｂの出来上がりの深さおよび幅と同一寸法で凹部２ａの寸法を決定しても良い。 [Step shown in FIG. 2 (b)]
After depositing a mask material such as an oxide film on the n-type drift layer 2, the mask 20 is opened by opening the region to be formed with the recess 2a, that is, the region to be formed with the p-type deep layer 3b. Form. Then, anisotropic etching such as RIE (Reactive Ion Etching) is performed using the mask 20. Thereby, the surface layer portion of the n-type drift layer 2 is removed at the opening of the mask 20 to form the recess 2a. The depth and width of the recess 2a are set so that the final depth and width of the final low-concentration region 3b become target values in consideration of thermal diffusion in each process performed thereafter. In the case of SiC, since the diffusion amount due to thermal diffusion is very small, the dimensions of the recess 2a are determined with the same dimensions as the final depth and width of the final low-concentration region 3b without taking into account thermal diffusion. Also good.
　〔図２（ｃ）に示す工程〕
　凹部２ａの形成に用いたマスク２０を除去したのち、図示しないイオン注入用マスクを用いて、凹部２ａの底部にｐ型不純物をイオン注入する。そして、熱処理などによって注入された不純物を活性化することで、高濃度領域３ａを形成する。このときの高濃度領域３ａの横方向の広がりについては、熱拡散による部分もあるが、基本的にはｐ型不純物を斜めイオン注入によって横方向に広がった状態で注入することで、高濃度領域３ａが所望の幅で構成されるようにしている。 [Step shown in FIG. 2 (c)]
After removing the mask 20 used to form the recess 2a, p-type impurities are ion-implanted into the bottom of the recess 2a using an ion implantation mask (not shown). Then, the high concentration region 3a is formed by activating the implanted impurities by heat treatment or the like. The lateral expansion of the high-concentration region 3a at this time is partly due to thermal diffusion, but basically the high-concentration region is obtained by implanting p-type impurities in a laterally expanded state by oblique ion implantation. 3a is configured to have a desired width.
　〔図２（ｄ）に示す工程〕
　イオン注入用のマスクを除去したのち、凹部２ａ内に低濃度領域３ｂをエピタキシャル成長させる。例えば、ＣＶＤ（Chemical Vapor Deposition）装置を用いて、雰囲気中にドーパントを含むガスを導入しながらエピタキシャル成長を行うことで、ｐ型不純物層３を形成できる。このとき、ｐ型ドリフト層２の表面にｐ型ベース領域４を同時に形成することもできるが、ここでは低濃度領域３ｂのみを形成しており、ｐ型ドリフト層２の上に形成される不要部分はＣＭＰ（Chemical Mechanical Polishing）などによって除去するようにしている。また、ＣＶＤなどの手法によって、凹部２ａ内に低濃度領域３ｂをエピタキシャル成長させていることから、低濃度領域３ｂの全域を均一な不純物濃度で形成することができる。 [Step shown in FIG. 2 (d)]
After removing the ion implantation mask, the low concentration region 3b is epitaxially grown in the recess 2a. For example, the p-type impurity layer 3 can be formed by performing epitaxial growth using a CVD (Chemical Vapor Deposition) apparatus while introducing a gas containing a dopant into the atmosphere. At this time, the p-type base region 4 can be simultaneously formed on the surface of the p-type drift layer 2, but here, only the low concentration region 3 b is formed, and it is not necessary to be formed on the p-type drift layer 2. The portion is removed by CMP (Chemical Mechanical Polishing) or the like. Further, since the low concentration region 3b is epitaxially grown in the recess 2a by a technique such as CVD, the entire low concentration region 3b can be formed with a uniform impurity concentration.
　〔図２（ｅ）に示す工程〕
　低濃度領域３ｂと同様の手法によって、ｐ型ベース領域４をエピタキシャル成長させる。このとき、上記したようにｐ型ベース領域４を低濃度領域３ｂと同時に形成することもでき、製造工程の簡略化を図ることができるが、これらを別々の工程で形成すれば、各部の不純物濃度を別々に設定することも可能となる。 [Step shown in FIG. 2 (e)]
The p-type base region 4 is epitaxially grown by the same method as the low concentration region 3b. At this time, as described above, the p-type base region 4 can be formed simultaneously with the low-concentration region 3b, so that the manufacturing process can be simplified. It is also possible to set the density separately.
　〔図３（ａ）に示す工程〕
　ｐ型ベース領域４の表面を覆いつつ、トレンチ７の形成予定領域が開口する図示しないエッチングマスクを配置する。そして、エッチングマスクを用いた異方性エッチングを行ったのち、必要に応じて等方性エッチングや犠牲酸化工程を行うことでトレンチ７を形成する。これにより、ｐ型ベース領域４を貫通してｎ型ドリフト層２に達しつつ、電界緩和層３よりも浅く、かつ、隣り合う低濃度領域３ｂの間において、低濃度領域３ｂから離間するように配置されたトレンチ７を形成することができる。 [Step shown in FIG. 3 (a)]
While covering the surface of the p-type base region 4, an etching mask (not shown) in which a region where the trench 7 is to be formed is opened is disposed. Then, after performing anisotropic etching using an etching mask, the trench 7 is formed by performing isotropic etching or sacrificial oxidation process as necessary. As a result, while penetrating the p-type base region 4 and reaching the n-type drift layer 2, it is shallower than the electric field relaxation layer 3 and is spaced from the low-concentration region 3b between the adjacent low-concentration regions 3b. Arranged trenches 7 can be formed.
　次に、エッチングマスクを除去してからゲート酸化工程を行うことでゲート絶縁膜８を形成する。また、ゲート絶縁膜８の表面に不純物をドーピングしたポリシリコン層を成膜したのち、これをパターニングすることでゲート電極９を形成する。これにより、トレンチゲート構造が形成される。 Next, the gate insulating film 8 is formed by performing a gate oxidation process after removing the etching mask. Further, after forming a polysilicon layer doped with impurities on the surface of the gate insulating film 8, the gate electrode 9 is formed by patterning the polysilicon layer. Thereby, a trench gate structure is formed.
　〔図３（ｂ）に示す工程〕
　ｐ型ベース領域４の表面にｎ+型ソース領域５の形成予定領域が開口するマスク（図示せず）を形成したのち、この上からｎ型不純物を高濃度にイオン注入することでｎ+型ソース領域５を形成する。同様に、ｐ型ベース領域４の表面にｐ+型コンタクト領域６の形成予定領域が開口するマスク（図示せず）を形成したのち、この上からｐ型不純物を高濃度にイオン注入することでｐ+型コンタクト領域６を形成する。 [Step shown in FIG. 3B]
After forming a mask (not shown) in which a region where the n + type source region 5 is to be formed is opened on the surface of the p type base region 4, n type impurities are ion-implanted at a high concentration from above to form an n + type. A source region 5 is formed. Similarly, after forming a mask (not shown) in which a region where the p + -type contact region 6 is to be formed is opened on the surface of the p-type base region 4, p-type impurities are ion-implanted at a high concentration from above. A p + -type contact region 6 is formed.
　〔図３（ｃ）に示す工程〕
　層間絶縁膜１１を成膜したのち、層間絶縁膜１１をパターニングしてｎ+型ソース領域５やｐ型ベース領域４を露出させるコンタクトホールを形成すると共に、ゲート電極９を露出させるコンタクトホールを図示断面とは別断面に形成する。そして、コンタクトホール内を埋め込むように電極材料を成膜したのち、これをパターニングすることでソース電極１０や図示しないゲート配線を形成する。 [Step shown in FIG. 3 (c)]
After the interlayer insulating film 11 is formed, the interlayer insulating film 11 is patterned to form contact holes that expose the n + -type source region 5 and the p-type base region 4, and the contact holes that expose the gate electrode 9 are shown in the figure. The cross section is formed differently from the cross section. Then, after depositing an electrode material so as to fill the contact hole, the source material 10 and a gate wiring (not shown) are formed by patterning the electrode material.
　〔図３（ｄ）に示す工程〕
　ｎ+型半導体基板１の裏面側にドレイン電極１２を形成する。これにより、図１に示した縦型ＭＯＳＦＥＴが完成する。 [Step shown in FIG. 3 (d)]
A drain electrode 12 is formed on the back side of the n + type semiconductor substrate 1. Thereby, the vertical MOSFET shown in FIG. 1 is completed.
　以上説明したように、本実施形態では、トレンチ７よりも深い電界緩和層３を備えた構造としており、かつ、深い位置において高濃度領域３ａを構成し、それよりも浅い領域を低濃度領域３ｂとしている。このため、電界緩和効果やＪＦＥＴ抵抗低減効果を得ることができる。 As described above, in the present embodiment, the structure includes the electric field relaxation layer 3 deeper than the trench 7, and the high concentration region 3a is formed at a deep position, and the shallower region is defined as the low concentration region 3b. It is said. For this reason, the electric field relaxation effect and the JFET resistance reduction effect can be obtained.
　また、電界緩和層３とトレンチゲート構造とが平行に並べられ、これらが交差していないようにしている。このため、高濃度領域３ａやその上にエピタキシャル成長にて形成される各部のうちのイオン注入によるダメージが残り得る部分からトレンチゲート構造を離せる。さらに、イオン注入する領域が高濃度領域３ａのみであることから、結晶中のイオン注入によるダメージも最小限に抑えることができる。よって、ゲート絶縁膜８の出来栄えにバラツキが発生することを抑制できると共に、リークパスが形成されることを抑制でき、トレンチゲートの信頼性の低下を抑制することが可能となって、より信頼性の高いトレンチゲート構造を有するＳｉＣ半導体装置にできる。 Also, the electric field relaxation layer 3 and the trench gate structure are arranged in parallel so that they do not intersect. For this reason, the trench gate structure can be separated from the high-concentration region 3a and a portion where damage due to ion implantation among the portions formed by epitaxial growth thereon can remain. Furthermore, since the ion-implanted region is only the high-concentration region 3a, damage caused by ion implantation in the crystal can be minimized. Therefore, it is possible to suppress the occurrence of variations in the quality of the gate insulating film 8, to suppress the formation of a leak path, and to suppress a decrease in the reliability of the trench gate. An SiC semiconductor device having a high trench gate structure can be obtained.
　また、本実施形態のように、低濃度領域３ｂの不純物濃度を全域において均一としている。低不純物領域３ｂの不純物濃度が深さ方向にバラツキを有する場合、不純物濃度の濃淡による空乏層の伸びのバラツキが生じ、電界緩和層３の間における電流経路が狭くなる場所が発生して、オン抵抗の増加の原因となる。これに対して、本実施形態のように低濃度領域３ｂの不純物濃度が全域において均一とされている場合、空乏層の伸びのバラツキが無く、電界緩和層３の間における電流経路が狭くなる場所が発生しない。したがって、オン抵抗の増加を抑制しつつ、電界緩和効果を得ることが可能となる。特に、電界緩和層３を１μｍ以上の深さとして使用する場合には、不純物濃度の濃淡による空乏層の伸びのバラツキが生じ易く、その影響が出やすいことから、本実施形態のような構成とすることで、よりオン抵抗の増加の抑制効果を得ることが可能となる。 Further, as in the present embodiment, the impurity concentration of the low concentration region 3b is uniform throughout the entire region. When the impurity concentration of the low impurity region 3b varies in the depth direction, the depletion layer expands due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers 3 is narrowed. This causes an increase in resistance. On the other hand, when the impurity concentration of the low concentration region 3b is uniform throughout the region as in the present embodiment, there is no variation in the expansion of the depletion layer and the current path between the electric field relaxation layers 3 is narrow. Does not occur. Therefore, it is possible to obtain an electric field relaxation effect while suppressing an increase in on-resistance. In particular, when the electric field relaxation layer 3 is used at a depth of 1 μm or more, the depletion layer is likely to vary in elongation due to the concentration of the impurity concentration, and the influence is likely to occur. By doing so, it becomes possible to obtain an effect of suppressing an increase in on-resistance.
　図１６（ａ）および図１６（ｂ）に従来技術（特許５５３９９３１）のＳｉＣ半導体装置の断面図およびその部分拡大図を示す。第２領域の不純物濃度が深さ方向にバラツキを有する場合、不純物濃度の濃淡による空乏層の伸びのバラツキが生じ、電界緩和層の間における電流経路が狭くなる場所が発生して、オン抵抗の増加の原因となる。 FIGS. 16A and 16B are a cross-sectional view and a partially enlarged view of a SiC semiconductor device according to the prior art (Japanese Patent No. 5539931). When the impurity concentration of the second region varies in the depth direction, the depletion layer extends due to the concentration of the impurity concentration, and the current path between the electric field relaxation layers is narrowed. Cause an increase.
　それに対して、本実施例のＳｉＣ半導体装置においては、低濃度領域３ｂつまり第２領域の不純物濃度を均一濃度としている。図１７（ａ）および図１７（ｂ）に本実施例のＳｉＣ半導体装置の断面図およびその部分拡大図を示す。第２領域が均一濃度とされている場合、空乏層の伸びのバラツキが無く、電界緩和層の間における電流経路が狭くなる場所が発生しない。したがって、オン抵抗の増加を抑制しつつ、電界緩和効果を得ることが可能となる。 On the other hand, in the SiC semiconductor device of the present embodiment, the impurity concentration of the low concentration region 3b, that is, the second region is set to a uniform concentration. 17A and 17B are a cross-sectional view and a partially enlarged view of the SiC semiconductor device of this example. When the second region has a uniform concentration, there is no variation in the extension of the depletion layer, and there is no place where the current path between the electric field relaxation layers becomes narrow. Therefore, it is possible to obtain an electric field relaxation effect while suppressing an increase in on-resistance.
　図１８に、従来技術および本実施例のＳｉＣ半導体装置の電界緩和層上部、つまり、第２領域の不純物濃度の深さ分布を示す。従来技術では、yi-yd間で不純物濃度がばらついているのに対し、本実施例のＳｉＣ半導体装置では、従来技術の最低不純物濃度より大きく、最高不純物濃度より小さい不純物濃度で、一定となっている。 FIG. 18 shows the depth distribution of the impurity concentration in the upper part of the electric field relaxation layer of the SiC semiconductor device of the prior art and this example, that is, the second region. In the prior art, the impurity concentration varies between yi and yd, whereas in the SiC semiconductor device of this example, the impurity concentration is larger than the lowest impurity concentration of the prior art and lower than the highest impurity concentration. Yes.
　さらに、本実施形態では、凹部２ａの底面にｐ型不純物をイオン注入して高不純物領域３ａを形成すると共に凹部２ａ内へのエピタキシャル成長によって低不純物領域３ｂを形成している。このような製造方法によれば、凹部２ａの形成位置に対して高不純物領域３ａの形成位置および低不純物領域３ｂをセルフアライン（自己整合）で設定できる。このため、トレンチゲート構造に対しての形成位置ずれを抑制できる。 Furthermore, in this embodiment, p-type impurities are ion-implanted into the bottom surface of the recess 2a to form the high impurity region 3a, and the low impurity region 3b is formed by epitaxial growth in the recess 2a. According to such a manufacturing method, the formation position of the high impurity region 3a and the low impurity region 3b can be set by self-alignment (self-alignment) with respect to the formation position of the recess 2a. For this reason, the formation position shift with respect to a trench gate structure can be suppressed.
　例えば、高不純物領域３ａと低不純物領域３ｂとをイオン注入によって形成する場合においては、マスクずれの有無に応じて、図４、図５に示すように高不純物領域３ａと低不純物領域３ｂとの形成位置ずれが発生し得る。そして、図５に示すように形成位置ずれが発生した場合には、図４に示すように形成位置ずれが発生していない場合と比較して、トレンチゲート構造に対して高不純物領域３ａの形成位置がずれることで、図中矢印で示した電流経路が長くなる。 For example, in the case where the high impurity region 3a and the low impurity region 3b are formed by ion implantation, the high impurity region 3a and the low impurity region 3b are formed as shown in FIGS. Forming position deviation may occur. Then, when the formation position deviation occurs as shown in FIG. 5, the formation of the high impurity region 3a with respect to the trench gate structure is compared with the case where the formation position deviation does not occur as shown in FIG. By shifting the position, the current path indicated by the arrow in the figure becomes longer.
　したがって、本実施形態の製造方法によれば、図４に示すように形成位置ずれが発生していない構造とすることができ、電流経路を最短電流経路にできる。これにより、さらにオン抵抗の上昇を抑えることが可能となる。 Therefore, according to the manufacturing method of the present embodiment, a structure in which the formation position shift does not occur as shown in FIG. 4 can be obtained, and the current path can be made the shortest current path. As a result, it is possible to further suppress an increase in on-resistance.
　（第２実施形態）
　本開示の第２実施形態について説明する。本実施形態は、第１実施形態に対して高濃度領域３ａの構成を変更したものであり、その他については第１実施形態と同様であるため、第１実施形態と異なる部分についてのみ説明する。 (Second Embodiment)
A second embodiment of the present disclosure will be described. In the present embodiment, the configuration of the high-concentration region 3a is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Therefore, only portions different from the first embodiment will be described.
　図６に示すように、本実施形態では、高濃度領域３ａの幅を低濃度領域３ｂの幅以下に設定している。そして、トレンチゲート構造の両側に位置する低濃度領域３ｂ間の距離Ｗ１に対して、高濃度領域３ａの間の距離Ｗ２がＷ１≦Ｗ２となるようにしている。 As shown in FIG. 6, in this embodiment, the width of the high concentration region 3a is set to be equal to or less than the width of the low concentration region 3b. The distance W2 between the high concentration regions 3a is set to satisfy W1 ≦ W2 with respect to the distance W1 between the low concentration regions 3b located on both sides of the trench gate structure.
　高濃度領域３ａの不純物濃度が高ければ、ドレイン電圧の影響による高電圧がゲート絶縁膜８に入り込み難くなることから、高濃度領域３ａの不純物濃度によっては、高濃度領域３ａの幅を低濃度領域３ｂの幅以下に設定しても良い。このような構造としても、第１実施形態と同様の効果を得ることができる。 If the impurity concentration of the high concentration region 3a is high, a high voltage due to the influence of the drain voltage is difficult to enter the gate insulating film 8. Therefore, depending on the impurity concentration of the high concentration region 3a, the width of the high concentration region 3a is reduced to the low concentration region. You may set below the width | variety of 3b. Even with such a structure, the same effect as in the first embodiment can be obtained.
　なお、このような構造のＳｉＣ半導体装置は、上記した図２（ｃ）の工程において、ｐ型不純物を斜めイオン注入ではなく、基板垂直方向に向けて行うようにすれば良い。高濃度領域３ａを低濃度領域３ｂより幅が小さくなるようにする場合、イオン注入マスクとして、イオン注入マスクの開口部の幅が凹部２ａの幅よりも小さなものを用いるようにすれば良い。 In the SiC semiconductor device having such a structure, the p-type impurity is not directed to the oblique ion implantation in the step of FIG. When the width of the high concentration region 3a is made smaller than that of the low concentration region 3b, an ion implantation mask having a width of the opening of the ion implantation mask smaller than the width of the recess 2a may be used.
　（第３実施形態）
　本開示の第３実施形態について説明する。本実施形態は、第１、第２実施形態に対して電界緩和層３の形成方法を変更したものであり、その他については第１、第２実施形態と同様であるため、第１、第２実施形態と異なる部分についてのみ説明する。なお、ここでは、第１実施形態に対して電界緩和層３の形成方法を変更した場合について説明するが、第２実施形態に対しても同様の方法によって電界緩和層３を形成することができる。 (Third embodiment)
A third embodiment of the present disclosure will be described. In the present embodiment, the method of forming the electric field relaxation layer 3 is changed with respect to the first and second embodiments. The other aspects are the same as those in the first and second embodiments. Only portions different from the embodiment will be described. In addition, although the case where the formation method of the electric field relaxation layer 3 is changed with respect to 1st Embodiment is demonstrated here, the electric field relaxation layer 3 can be formed with the same method also with respect to 2nd Embodiment. .
　まず、図７（ａ）に示す工程において、図２（ａ）に示す工程と同様に、ｎ+型半導体基板１の表面にｎ型ドリフト層２が形成されたエピ基板を用意する。そして、図７（ｂ）に示す工程では、ｎ型ドリフト層２の表面に図示しないイオン注入マスクを配置したのち、ｐ型不純物をイオン注入することで高濃度領域３ａおよび低濃度領域３ｂを形成する。具体的には、高濃度領域３ａと対応する幅の開口部が形成された第１マスクを配置した後、これをイオン注入マスクとして用いてｐ型不純物をイオン注入する。続いて、第１マスクを除去した後、低濃度領域３ｂと対応する幅の開口部が形成された第２マスクを配置した後、これをイオン注入マスクとして用いてｐ型不純物をイオン注入する。この低濃度領域３ｂを形成する際のイオン注入はボックスプロファイルにて行う。これにより、低濃度領域３ｂは均一な不純物濃度で形成される。そして、熱処理を行うことで、注入されたｐ型イオンを活性化させ高濃度領域３ａおよび低濃度領域３ｂを形成する。このとき、イオン注入の加速電圧を変化させ、高濃度領域３ａを形成するためのイオン注入の際には低濃度領域３ｂを形成するためのイオン注入の際よりも高加速電圧となるようにし、高濃度領域３ａがより深い位置に形成されるように作り分けを行う。また、イオン注入時のｐ型不純物のドーズ量を変えることで、高濃度領域３ａが低濃度領域３ｂよりも高不純物濃度で形成されるようにする。 First, in the step shown in FIG. 7A, an epitaxial substrate having an n type drift layer 2 formed on the surface of an n + type semiconductor substrate 1 is prepared in the same manner as the step shown in FIG. In the step shown in FIG. 7B, an ion implantation mask (not shown) is arranged on the surface of the n-type drift layer 2, and then a high-concentration region 3a and a low-concentration region 3b are formed by ion implantation of p-type impurities. To do. Specifically, a first mask having an opening having a width corresponding to the high concentration region 3a is disposed, and then p-type impurities are ion-implanted using the first mask as an ion implantation mask. Subsequently, after removing the first mask, a second mask in which an opening having a width corresponding to the low concentration region 3b is formed, and then p-type impurities are ion-implanted using the second mask as an ion implantation mask. Ion implantation for forming the low concentration region 3b is performed by a box profile. Thereby, the low concentration region 3b is formed with a uniform impurity concentration. Then, by performing heat treatment, the implanted p-type ions are activated to form the high concentration region 3a and the low concentration region 3b. At this time, the acceleration voltage of the ion implantation is changed so that the ion implantation for forming the high concentration region 3a has a higher acceleration voltage than the ion implantation for forming the low concentration region 3b. Separately, the high concentration region 3a is formed at a deeper position. Further, by changing the dose amount of the p-type impurity at the time of ion implantation, the high concentration region 3a is formed with a higher impurity concentration than the low concentration region 3b.
　この後は、図７（ｃ）に示す工程において、図２（ｃ）に示す工程と同様にｐ型ベース領域４を形成したのち、図２（ｄ）、図２（ｅ）、図３（ａ）～図３（ｄ）に示す工程と同様の工程を行う。これにより、本実施形態にかかるトレンチゲート型の縦型ＭＯＳＦＥＴを有するＳｉＣ半導体装置が完成する。 Thereafter, in the step shown in FIG. 7C, the p-type base region 4 is formed in the same manner as the step shown in FIG. 2C, and then, FIG. 2D, FIG. 2E, FIG. Steps a) to steps similar to those shown in FIG. Thereby, the SiC semiconductor device having the trench gate type vertical MOSFET according to the present embodiment is completed.
　以上説明したように、電界緩和層３のうちの高濃度領域３ａのみでなく、低濃度領域３ｂについてもイオン注入によって形成することができる。このようにしても、第１、第２実施形態と同様の効果を得ることが可能となる。 As described above, not only the high concentration region 3a but also the low concentration region 3b of the electric field relaxation layer 3 can be formed by ion implantation. Even if it does in this way, it becomes possible to acquire the effect similar to 1st, 2nd embodiment.
　（第４実施形態）
　本開示の第４実施形態について説明する。本実施形態は、第１～第３実施形態に対してｎ型ドリフト層２の構成を変更したものであり、その他については第１～第３実施形態と同様であるため、第１～第３実施形態と異なる部分についてのみ説明する。なお、ここでは、第１実施形態に対してｎ型ドリフト層２の構成を変更した場合について説明するが、第２、第３実施形態に対しても同様の構成を適用することができる。 (Fourth embodiment)
A fourth embodiment of the present disclosure will be described. In the present embodiment, the configuration of the n-type drift layer 2 is changed with respect to the first to third embodiments, and the others are the same as those of the first to third embodiments. Only portions different from the embodiment will be described. Here, a case where the configuration of the n-type drift layer 2 is changed with respect to the first embodiment will be described, but the same configuration can be applied to the second and third embodiments.
　図８に示すように、本実施形態では、ｎ型ドリフト層２のうち高濃度領域３ａよりも上方に位置している部分について、ｎ型ドリフト層２の他の部分よりも不純物濃度を高くした高濃度層２ｂとしている。例えば、高濃度層２ｂは、ｎ型ドリフト層２のうちの他の部分よりもｎ型不純物濃度が２．０×１０15ｃｍ-3程度高く設定されている。 As shown in FIG. 8, in the present embodiment, the impurity concentration of the portion of the n-type drift layer 2 located above the high-concentration region 3a is made higher than that of the other portions of the n-type drift layer 2. The high concentration layer 2b is used. For example, the n-type impurity concentration of the high concentration layer 2b is set to be higher by about 2.0 × 10 15 cm −3 than the other portions of the n-type drift layer 2.
　このように、高濃度層２ｂを形成することにより、トレンチ７の近傍において、ｎ型ドリフト層２内に伸びる空乏層の幅を小さくすることが可能となる。したがって、高濃度層２ｂの不純物濃度が高くされることによる内部抵抗の低下に加えて、ｎ型ドリフト層２内の空乏層幅を小さくするできることで、ＪＦＥＴ抵抗の更なる低減を図ることが可能となる。 Thus, by forming the high concentration layer 2b, the width of the depletion layer extending into the n-type drift layer 2 in the vicinity of the trench 7 can be reduced. Therefore, in addition to the decrease in internal resistance due to the increase in the impurity concentration of the high concentration layer 2b, the width of the depletion layer in the n-type drift layer 2 can be reduced, so that the JFET resistance can be further reduced. Become.
　次に、図８に示すトレンチゲート型の縦型ＭＯＳＦＥＴの製造方法について、図９（ａ）～図１０（ｅ）を参照して説明する。 Next, a method of manufacturing the trench gate type vertical MOSFET shown in FIG. 8 will be described with reference to FIGS. 9 (a) to 10 (e).
　まず、図９（ａ）に示す工程において、図２（ａ）に示す工程と同様に、ｎ+型半導体基板１の表面にｎ型ドリフト層２の一部が形成されたエピ基板を用意する。そして、図９（ｂ）に示す工程において、ｎ型ドリフト層２の一部の表面に図示しないイオン注入マスクを配置したのち、ｐ型不純物をイオン注入することで高濃度領域３ａを形成する。このとき、高濃度領域３ａがｎ型ドリフト層２の一部の表面から形成されるようにしている。 First, in the step shown in FIG. 9A, an epi substrate in which a part of the n type drift layer 2 is formed on the surface of the n + type semiconductor substrate 1 is prepared in the same manner as the step shown in FIG. . 9B, an ion implantation mask (not shown) is disposed on a part of the surface of the n-type drift layer 2, and then a high-concentration region 3a is formed by ion implantation of p-type impurities. At this time, the high concentration region 3 a is formed from a part of the surface of the n-type drift layer 2.
　なお、ここでは、図９（ｂ）の工程において、高濃度領域３ａをイオン注入によって形成した。これに対して、エッチングによって高濃度領域３ａの形成予定領域に凹部を形成しておき、その凹部内にｐ型不純物層をエピタキシャル成長で埋め込んだのち研磨で平坦化することで、高濃度領域３ａを形成するという製法としても良い。 Here, in the step of FIG. 9B, the high concentration region 3a is formed by ion implantation. On the other hand, a recess is formed in a region where the high concentration region 3a is to be formed by etching, a p-type impurity layer is buried in the recess by epitaxial growth, and then flattened by polishing, thereby forming the high concentration region 3a. It is good also as the manufacturing method of forming.
　続いて、図９（ｃ）に示す工程において、高濃度領域３ａおよびｎ型ドリフト層２の一部の表面の上に、ｎ型ドリフト層２の残りとなる高濃度層２ｂをエピタキシャル成長させる。さらに、図９（ｄ）に示す工程において、図２（ｂ）と同様の工程を行うことで、高濃度層２ｂに対して凹部２ａを形成したのち、図９（ｅ）に示す工程において、図２（ｄ）と同様の工程を行うことで低濃度領域３ｂを形成する。 Subsequently, in the step shown in FIG. 9C, the high-concentration layer 2b which remains the n-type drift layer 2 is epitaxially grown on the surface of the high-concentration region 3a and a part of the n-type drift layer 2. Further, in the step shown in FIG. 9D, the step similar to FIG. 2B is performed to form the recess 2a in the high concentration layer 2b, and then in the step shown in FIG. 9E. The low concentration region 3b is formed by performing the same process as in FIG.
　この後、図１０（ａ）～図１０（ｅ）に示す工程において、図２（ｅ）、図３（ａ）～図３（ｄ）と同様の工程を行うことで、図８に示した縦型ＭＯＳＦＥＴが完成する。 Thereafter, in the steps shown in FIGS. 10 (a) to 10 (e), the same steps as those in FIGS. 2 (e) and 3 (a) to 3 (d) are performed, so that the steps shown in FIG. A vertical MOSFET is completed.
　（他の実施形態）
　例えば、上記各実施形態では、低濃度領域３ｂの側面をｎ+型半導体基板１の表面に対する垂直方向となるように図示してあるが、必ずしも垂直方向とされている必要はない。例えば、図１１に示すように、ｎ+型半導体基板１の表面と平行な方向において、低濃度領域３ｂの上部を下部よりも幅を狭くすることで、低濃度領域３ｂの側面を傾斜させたテーパ形状とされていても良い。図１２に示すように、ｎ+型半導体基板１の表面と平行な方向において、低濃度領域３ｂの下部を上部よりも幅を狭くすることで、低濃度領域３ｂの側面を図１１と逆方向に傾斜させた逆テーパ形状とされていても良い。 (Other embodiments)
For example, in each of the above embodiments, the side surface of the low concentration region 3b is illustrated as being perpendicular to the surface of the n + type semiconductor substrate 1, but it is not always necessary to be perpendicular. For example, as shown in FIG. 11, in the direction parallel to the surface of the n + type semiconductor substrate 1, the width of the upper portion of the low concentration region 3b is made narrower than the lower portion, thereby tilting the side surface of the low concentration region 3b. It may be a tapered shape. As shown in FIG. 12, the width of the lower portion of the low concentration region 3b is narrower than that of the upper portion in the direction parallel to the surface of the n + type semiconductor substrate 1, so that the side surface of the low concentration region 3b is opposite to that of FIG. It may be made into the reverse taper shape made to incline.
　なお、このような形状の低濃度領域３ｂを形成するには、例えば第１、第３実施形態のように凹部２ａ内へのエピタキシャル成長によって低濃度領域３ｂを形成する場合、凹部２ａの側面が上記したテーパ形状もしくは逆テーパ形状となるようにすれば良い。凹部２ａの側面をテーパ形状もしくは逆テーパ形状となるようにするには、凹部２ａを形成する際のエッチング条件を調整すればよい。 In order to form the low concentration region 3b having such a shape, for example, when the low concentration region 3b is formed by epitaxial growth in the recess 2a as in the first and third embodiments, the side surface of the recess 2a is The taper shape or the inverse taper shape may be used. In order to make the side surface of the concave portion 2a have a tapered shape or an inversely tapered shape, the etching conditions for forming the concave portion 2a may be adjusted.
　また、高濃度領域３ａの形状についても、上記各実施形態では、トレンチゲート構造の長手方向に対する垂直方向に切断した断面において角部が丸まった四角形状で示してあるが、図１３に示すように断面形状が長円形状などであっても良い。また、高濃度領域３ａの不純物濃度については全域で均一である必要はなく、例えば深くなるほど、つまりｎ+型半導体基板１に近づくほど不純物濃度が濃くなるようにしても良い。 Further, the shape of the high concentration region 3a is also shown as a quadrangular shape with rounded corners in the cross section cut in the direction perpendicular to the longitudinal direction of the trench gate structure in each of the above embodiments, as shown in FIG. The cross-sectional shape may be an oval shape. Further, the impurity concentration of the high concentration region 3a does not need to be uniform over the entire region. For example, the impurity concentration may be increased as it becomes deeper, that is, as it approaches the n + type semiconductor substrate 1.
　さらに、上記第４実施形態では、ｎ型ドリフト層２のうち高濃度領域３ａよりも上方に位置している部分を高濃度層２ｂとしている。この高濃度層２ｂについては、ｎ型ドリフト層２のうち高濃度領域３ａよりも上方に位置している部分の全域に形成する必要はなく、少なくともトレンチゲート構造の底部を囲むように、より詳しくは電流経路となる部分に形成されていれば良い。例えば、図１４に示すように高濃度領域３ａから所定離れた位置よりも上方の全域に高濃度層２ｂが形成されるようにしたり、図１５に示すようにトレンチゲート構造の底部を囲みつつ、高濃度領域３ａおよび低濃度領域３ｂから離れるように高濃度層２ｂを形成しても良い。なお、図１５に示す構造の場合、高濃度層１ｂを選択エピタキシャル成長もしくはイオン注入によって形成することができる。 Furthermore, in the said 4th Embodiment, the part located above the high concentration area | region 3a among the n-type drift layers 2 is made into the high concentration layer 2b. The high-concentration layer 2b does not need to be formed in the entire region of the n-type drift layer 2 that is located above the high-concentration region 3a, and more specifically so as to surround at least the bottom of the trench gate structure. May be formed in a portion to be a current path. For example, as shown in FIG. 14, the high concentration layer 2 b is formed in the entire region above a predetermined distance from the high concentration region 3 a, or while surrounding the bottom of the trench gate structure as shown in FIG. 15, The high concentration layer 2b may be formed so as to be away from the high concentration region 3a and the low concentration region 3b. In the case of the structure shown in FIG. 15, the high concentration layer 1b can be formed by selective epitaxial growth or ion implantation.
　また、上記各実施形態では、第１導電型をｎ型、第２導電型をｐ型としたｎチャネルタイプのＭＯＳＦＥＴを例に挙げて説明したが、各構成要素の導電型を反転させたｐチャネルタイプのＭＯＳＦＥＴに対しても本開示を適用することができる。また、上記説明では、トレンチゲート構造のＭＯＳＦＥＴを例に挙げて説明したが、同様のトレンチゲート構造のＩＧＢＴに対しても本開示を適用することができる。ＩＧＢＴは、上記各実施形態に対して基板１の導電型をｎ型からｐ型に変更するだけであり、その他の構造や製造方法に関しては上記各実施形態と同様である。 In each of the above-described embodiments, an n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. The present disclosure can be applied to a channel type MOSFET. In the above description, a MOSFET having a trench gate structure has been described as an example, but the present disclosure can be applied to an IGBT having a similar trench gate structure. The IGBT only changes the conductivity type of the substrate 1 from the n-type to the p-type with respect to the above-described embodiments, and the other structures and manufacturing methods are the same as those of the above-described embodiments.
　本開示は、実施例に準拠して記述されたが、本開示は当該実施例や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。 Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims (18)

  1. 　炭化珪素からなる第１または第２導電型の基板（１）と、
    　前記基板の上に形成され、前記基板よりも低不純物濃度とされた第１導電型の炭化珪素からなるドリフト層（２）と、
    　前記ドリフト層の上に形成された第２導電型の炭化珪素からなるベース領域（４）と、
    　前記ベース領域の上層部に形成され、前記ドリフト層よりも高濃度の第１導電型の炭化珪素にて構成された複数のソース領域（５）と、
    　前記ベース領域の上層部において、対向する前記ソース領域の間に形成され、前記ベース層よりも高濃度の第２導電型の炭化珪素にて構成されたコンタクト領域（６）と、
    　前記ソース領域の表面から前記ベース領域よりも深くまで形成され、一方向を長手方向として複数本が並列されたトレンチ（７）と、
    　前記トレンチの内壁面に形成されたゲート絶縁膜（８）と、
    　前記トレンチ内において、前記ゲート絶縁膜の上に形成されたゲート電極（９）と、
    　前記ソース領域および前記コンタクト領域に電気的に接続されたソース電極（１０）と、
    　前記基板の裏面側に形成されたドレイン電極（１２）と、
    　前記ベース領域よりも下方に位置する前記ドリフト層内に配置され、前記トレンチの長手方向と平行方向を長手方向として、複数本の前記トレンチの間のそれぞれにおいて該トレンチの側面から離間して配置され、第２導電型の炭化珪素で構成された複数本の電界緩和層（３）と、を有し、
    　前記複数本の電界緩和層には、前記トレンチよりも深い位置に形成された第１領域（３ａ）と、前記第１領域よりも低濃度で構成され、前記ドリフト層の表面から前記第１領域まで形成されていると共に均一濃度とされた第２領域（３ｂ）とが備えられている炭化珪素半導体装置。     A first or second conductivity type substrate (1) made of silicon carbide;
    A drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate and having a lower impurity concentration than the substrate;
    A base region (4) made of silicon carbide of the second conductivity type formed on the drift layer;
    A plurality of source regions (5) formed in the upper layer portion of the base region and made of silicon carbide of the first conductivity type having a higher concentration than the drift layer;
    A contact region (6) formed between the opposing source regions in the upper layer portion of the base region and made of silicon carbide of the second conductivity type having a higher concentration than the base layer;
    A trench (7) formed from the surface of the source region to a depth deeper than the base region, and a plurality of trenches arranged in parallel with one direction as a longitudinal direction;
    A gate insulating film (8) formed on the inner wall surface of the trench;
    A gate electrode (9) formed on the gate insulating film in the trench;
    A source electrode (10) electrically connected to the source region and the contact region;
    A drain electrode (12) formed on the back side of the substrate;
    It is disposed in the drift layer located below the base region, and is disposed apart from the side surface of the trench in each of the plurality of trenches, with the longitudinal direction parallel to the longitudinal direction of the trench. A plurality of electric field relaxation layers (3) made of silicon carbide of the second conductivity type,
    The plurality of electric field relaxation layers include a first region (3a) formed at a position deeper than the trench, and a lower concentration than the first region, and the first region extends from the surface of the drift layer. And a second region (3b) having a uniform concentration.
  2. 　前記ドリフト層のうち、前記第２領域と対応する位置に凹部（２ａ）が形成されており、
    　前記第２領域は、前記凹部内に第２導電型の炭化珪素の埋め込み領域である請求項１に記載の炭化珪素半導体装置。     A recess (2a) is formed at a position corresponding to the second region in the drift layer,
    2. The silicon carbide semiconductor device according to claim 1, wherein the second region is a buried region of a second conductivity type silicon carbide in the recess.
  3. 　前記第１領域は、前記凹部の底部においての第２導電型不純物のイオン注入領域である請求項２に記載の炭化珪素半導体装置。 3. The silicon carbide semiconductor device according to claim 2, wherein the first region is an ion implantation region of a second conductivity type impurity at the bottom of the recess.
  4. 　前記第１領域および前記第２領域は、前記ドリフト層に対しての第２導電型不純物のイオン注入領域であり、
    　前記イオン注入領域は、ボックスプロファイルにて提供されている請求項１に記載の炭化珪素半導体装置。     The first region and the second region are ion implantation regions of a second conductivity type impurity for the drift layer;
    The silicon carbide semiconductor device according to claim 1, wherein the ion implantation region is provided in a box profile.
  5. 　前記複数本の電界緩和層のうち、隣り合う前記第２領域の間の距離をＷ１、隣り合う前記第１領域の間の距離をＷ２として、
    　Ｗ１＞Ｗ２の関係を満たしている請求項１ないし４のいずれか１つに記載の炭化珪素半導体装置。     Among the plurality of electric field relaxation layers, the distance between the adjacent second regions is W1, and the distance between the adjacent first regions is W2.
    The silicon carbide semiconductor device according to claim 1, wherein a relationship of W1> W2 is satisfied.
  6. 　前記複数本の電界緩和層のうち、隣り合う前記第１領域の間の距離をＷ２として、
    　前記トレンチ内に前記ゲート絶縁膜および前記ゲート電極が配置されることにより構成されるトレンチゲート構造の幅をＷ３として、
    　Ｗ２＞Ｗ３の関係を満たしている請求項１ないし５のいずれか１つに記載の炭化珪素半導体装置。     Of the plurality of electric field relaxation layers, the distance between the adjacent first regions is W2,
    The width of the trench gate structure formed by arranging the gate insulating film and the gate electrode in the trench is W3,
    The silicon carbide semiconductor device according to claim 1, wherein a relationship of W2> W3 is satisfied.
  7. 　前記ドリフト層のうち、前記第１領域よりも上方に位置する部分であって、前記トレンチ内に前記ゲート絶縁膜および前記ゲート電極が配置されることにより構成されるトレンチゲート構造の少なくとも底部を囲む部分は、該ドリフト層のうちの残りの部分よりも第１導電型不純物の濃度が高くされた高濃度層（２ｂ）とされている請求項１ないし６のいずれか１つに記載の炭化珪素半導体装置。 A portion of the drift layer that is located above the first region and surrounds at least a bottom portion of a trench gate structure configured by disposing the gate insulating film and the gate electrode in the trench. The silicon carbide according to claim 1, wherein the portion is a high concentration layer (2 b) in which the concentration of the first conductivity type impurity is higher than that of the remaining portion of the drift layer. Semiconductor device.
  8. 　炭化珪素からなる第１または第２導電型の基板（１）上に、該基板（１）よりも低不純物濃度とされた第１導電型の炭化珪素からなるドリフト層（２）を形成し、
    　前記ドリフト層に対して、一方向を長手方向として複数本が並列された第２導電型の電界緩和層（３）を形成し、
    　前記電界緩和層および前記ドリフト層の上に第２導電型の炭化珪素からなるベース領域（４）を形成し、
    　前記ベース領域内における該ベース領域の上層部に、前記ドリフト層よりも高濃度の第１導電型の炭化珪素にて構成された複数のソース領域（４）を形成し、
    　前記ベース領域の上層部のうち、対向する前記ソース領域の間に、前記ベース層よりも高濃度の第２導電型の炭化珪素にて構成されたコンタクト領域（６）を形成し、
    　前記ソース領域の表面から前記ベース領域を貫通し、前記ドリフト層に達し、底面が前記電界緩和層の底面よりも浅く、かつ、前記電界緩和層の長手方向と平行方向を長手方向として、前記電界緩和層から離間して配置されたトレンチ（７）を形成し、
    　前記トレンチの表面にゲート絶縁膜（８）を形成し、
    　前記トレンチ内において、前記ゲート絶縁膜の上にゲート電極（９）を形成し、
    　前記ソース領域および前記コンタクト領域に電気的に接続されるソース電極（１０）を形成し、
    　前記基板の裏面側にドレイン電極（１２）を形成することを含み、
    　前記電界緩和層の形成は、前記トレンチよりも深い位置に第１領域（３ａ）を形成し、前記ドリフト層の表面から前記第１領域まで該第１領域よりも低濃度かつ均一濃度で第２領域（３ｂ）を形成することを含む炭化珪素半導体装置の製造方法。     A drift layer (2) made of silicon carbide of the first conductivity type having a lower impurity concentration than the substrate (1) is formed on the first or second conductivity type substrate (1) made of silicon carbide,
    Forming a second conductivity type electric field relaxation layer (3) in which a plurality of the drift layers are arranged in parallel with respect to the drift layer;
    Forming a base region (4) made of silicon carbide of the second conductivity type on the electric field relaxation layer and the drift layer;
    Forming a plurality of source regions (4) made of silicon carbide of the first conductivity type at a higher concentration than the drift layer in an upper layer portion of the base region in the base region;
    A contact region (6) made of silicon carbide of a second conductivity type higher in concentration than the base layer is formed between the opposing source regions in the upper layer portion of the base region;
    The electric field passes through the base region from the surface of the source region, reaches the drift layer, has a bottom surface shallower than a bottom surface of the electric field relaxation layer, and a longitudinal direction parallel to the longitudinal direction of the electric field relaxation layer. Forming a trench (7) spaced apart from the relaxation layer;
    Forming a gate insulating film (8) on the surface of the trench;
    Forming a gate electrode (9) on the gate insulating film in the trench;
    Forming a source electrode (10) electrically connected to the source region and the contact region;
    Forming a drain electrode (12) on the back side of the substrate;
    The electric field relaxation layer is formed by forming a first region (3a) at a position deeper than the trench, and having a lower concentration and a uniform concentration than the first region from the surface of the drift layer to the first region. A method for manufacturing a silicon carbide semiconductor device, including forming region (3b).
  9. 　前記電界緩和層の形成は、
    　前記ドリフト層のうち前記第２領域と対応する位置に凹部（２ａ）を形成し、
    　前記ドリフト層のうちの前記凹部の底面より下方に第２導電型不純物をイオン注入することによって前記第１領域を形成し、
    　前記第１領域の形成後、エピタキシャル成長によって前記凹部内に前記第２領域を形成することを含む請求項８に記載の炭化珪素半導体装置の製造方法。     The electric field relaxation layer is formed by:
    Forming a recess (2a) at a position corresponding to the second region of the drift layer;
    Forming the first region by ion-implanting a second conductivity type impurity below the bottom surface of the recess in the drift layer;
    The method for manufacturing a silicon carbide semiconductor device according to claim 8, further comprising forming the second region in the recess by epitaxial growth after the formation of the first region.
  10. 　前記第２領域の形成は、前記凹部内に前記第２領域をエピタキシャル成長によって形成し、同時に、前記ベース領域の形成として、前記ドリフト層の上に前記ベース領域をエピタキシャル成長により形成する請求項９に記載の炭化珪素半導体装置の製造方法。 10. The second region is formed by epitaxially growing the second region in the recess, and simultaneously forming the base region on the drift layer by epitaxial growth as the base region. A method for manufacturing a silicon carbide semiconductor device.
  11. 　前記電界緩和層の形成は、
    　前記ドリフト層の形成後、該ドリフト層の表面から第２導電型不純物を加速電圧の違うイオン注入で前記第１領域と前記第２領域とを作り分け、
    　前記第２領域を形成する際のイオン注入をボックスプロファイルにて行う請求項８に記載の炭化珪素半導体装置の製造方法。     The electric field relaxation layer is formed by:
    After the formation of the drift layer, the first region and the second region are separately formed from the surface of the drift layer by ion implantation of a second conductivity type impurity having a different acceleration voltage,
    The method for manufacturing a silicon carbide semiconductor device according to claim 8, wherein ion implantation for forming the second region is performed by a box profile.
  12. 　前記ドリフト層の形成は、該ドリフト層のうち前記第１領域の上方に位置する部分を該ドリフト層のうちの残りの部分よりも第２導電型不純物の濃度を高くすることを含む請求項８ないし１１のいずれか１つに記載の炭化珪素半導体装置の製造方法。 The formation of the drift layer includes increasing a concentration of the second conductivity type impurity in a portion of the drift layer located above the first region, compared to the remaining portion of the drift layer. The manufacturing method of the silicon carbide semiconductor device as described in any one of thru | or 11.
  13. 　前記ドリフト層の形成は、該ドリフト層のうち前記第１領域の上方に位置する部分であって、前記トレンチ内に前記ゲート絶縁膜および前記ゲート電極が配置されることにより構成されるトレンチゲート構造の少なくとも底部を囲む部分を該ドリフト層のうちの残りの部分よりも第１導電型不純物の濃度を高くすることを含み、
    　前記第１領域の形成は、前記ドリフト層のうちの残りの部分を形成したのち第２導電型不純物をイオン注入することによって前記第１領域を形成し、
    　前記第１領域の形成後、前記ドリフト層のうちの前記第１領域の上方に位置する部分を形成し、
    　さらに、前記第２領域の形成は、前記ドリフト層における前記第１領域の上方に位置する部分のうち前記第２領域と対応する位置に凹部（２ａ）を形成し、その後、エピタキシャル成長によって前記凹部内に前記第２領域を形成することを含む請求項８に記載の炭化珪素半導体装置の製造方法。     The formation of the drift layer is a portion of the drift layer that is located above the first region, and is formed by arranging the gate insulating film and the gate electrode in the trench. The concentration of the first conductivity type impurity in the portion surrounding at least the bottom of the drift layer is higher than the remaining portion of the drift layer,
    The first region is formed by forming the remaining portion of the drift layer and then ion-implanting a second conductivity type impurity to form the first region,
    After forming the first region, forming a portion of the drift layer located above the first region,
    Further, the second region is formed by forming a recess (2a) at a position corresponding to the second region in a portion of the drift layer located above the first region, and then epitaxially growing in the recess. The method for manufacturing a silicon carbide semiconductor device according to claim 8, further comprising forming the second region.
  14. 　炭化珪素からなる第１または第２導電型の基板（１）と、
    　前記基板の上に形成され、前記基板よりも低不純物濃度とされた第１導電型の炭化珪素からなるドリフト層（２）と、
    　前記ドリフト層の上に形成された第２導電型の炭化珪素からなるベース領域（４）と、
    　前記ベース領域の上層部に形成され、前記ドリフト層よりも高濃度の第１導電型の炭化珪素にて構成された複数のソース領域（５）と、
    　前記ベース領域の上層部において、対向する前記ソース領域の間に形成され、前記ベース層よりも高濃度の第２導電型の炭化珪素にて構成されたコンタクト領域（６）と、
    　前記ソース領域の表面から前記ベース領域よりも深くまで形成され、一方向を長手方向として複数本が並列されたトレンチ（７）と、
    　前記トレンチの内壁面に形成されたゲート絶縁膜（８）と、
    　前記トレンチ内において、前記ゲート絶縁膜の上に形成されたゲート電極（９）と、
    　前記ソース領域および前記コンタクト領域に電気的に接続されたソース電極（１０）と、
    　前記基板の裏面側に形成されたドレイン電極（１２）と、
    　前記ベース領域よりも下方に位置する前記ドリフト層内に配置され、前記トレンチの長手方向と平行方向を長手方向として、複数本の前記トレンチの間のそれぞれにおいて該トレンチの側面から離間して配置され、第２導電型の炭化珪素で構成された複数本の電界緩和層（３）と、を有し、
    　前記複数本の電界緩和層には、前記トレンチよりも深い位置に形成された第１領域（３ａ）と、前記ドリフト層の表面から前記第１領域まで形成されていると共に均一濃度とされた第２領域（３ｂ）とが備えられており、
    　隣り合う前記第２領域の間の距離をＷ１、隣り合う前記第１領域の間の距離をＷ２として、Ｗ１＞Ｗ２の関係を満たしており、
    　前記トレンチ内に前記ゲート絶縁膜および前記ゲート電極が配置されることにより構成されるトレンチゲート構造の幅をＷ３として、Ｗ２＞Ｗ３の関係を満たしている炭化珪素半導体装置。     A first or second conductivity type substrate (1) made of silicon carbide;
    A drift layer (2) made of silicon carbide of the first conductivity type formed on the substrate and having a lower impurity concentration than the substrate;
    A base region (4) made of silicon carbide of the second conductivity type formed on the drift layer;
    A plurality of source regions (5) formed in the upper layer portion of the base region and made of silicon carbide of the first conductivity type having a higher concentration than the drift layer;
    A contact region (6) formed between the opposing source regions in the upper layer portion of the base region and made of silicon carbide of the second conductivity type having a higher concentration than the base layer;
    A trench (7) formed from the surface of the source region to a depth deeper than the base region, and a plurality of trenches arranged in parallel with one direction as a longitudinal direction;
    A gate insulating film (8) formed on the inner wall surface of the trench;
    A gate electrode (9) formed on the gate insulating film in the trench;
    A source electrode (10) electrically connected to the source region and the contact region;
    A drain electrode (12) formed on the back side of the substrate;
    It is disposed in the drift layer located below the base region, and is disposed apart from the side surface of the trench in each of the plurality of trenches, with the longitudinal direction parallel to the longitudinal direction of the trench. A plurality of electric field relaxation layers (3) made of silicon carbide of the second conductivity type,
    In the plurality of electric field relaxation layers, a first region (3a) formed at a position deeper than the trench, and a first region (3a) formed from the surface of the drift layer to the first region and having a uniform concentration. Two regions (3b),
    The distance between the adjacent second regions is W1, the distance between the adjacent first regions is W2, and the relationship of W1> W2 is satisfied.
    A silicon carbide semiconductor device satisfying a relationship of W2> W3, where W3 is a width of a trench gate structure formed by disposing the gate insulating film and the gate electrode in the trench.
  15. 　前記ドリフト層のうち、前記第２領域と対応する位置に凹部（２ａ）が形成されており、前記第２領域は、前記凹部内に第２導電型の炭化珪素の埋め込み領域である請求項１４に記載の炭化珪素半導体装置。 The recessed part (2a) is formed in the position corresponding to the said 2nd area | region among the said drift layers, The said 2nd area | region is a buried area | region of the 2nd conductivity type silicon carbide in the said recessed part. The silicon carbide semiconductor device described in 1.
  16. 　前記第１領域は、前記凹部の底部において第２導電型不純物のイオン注入領域である請求項１５に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 15, wherein the first region is an ion implantation region of a second conductivity type impurity at a bottom portion of the concave portion.
  17. 　前記第１領域および前記第２領域は、前記ドリフト層に対しての第２導電型不純物のイオン注入領域であり、
    　前記第２領域のイオン注入領域は、イオン注入のボックスプロファイルにて提供される請求項１４に記載の炭化珪素半導体装置。     The first region and the second region are ion implantation regions of a second conductivity type impurity for the drift layer;
    The silicon carbide semiconductor device according to claim 14, wherein the ion implantation region of the second region is provided by an ion implantation box profile.
  18. 　前記ドリフト層のうち、前記第１領域よりも上方に位置する部分であって、前記トレンチ内に前記ゲート絶縁膜および前記ゲート電極が配置されることにより構成されるトレンチゲート構造の少なくとも底部を囲む部分は、該ドリフト層のうちの残りの部分よりも第１導電型不純物の濃度が高くされた高濃度層（２ｂ）とされている請求項１４ないし１６のいずれか１つに記載の炭化珪素半導体装置。 A portion of the drift layer that is located above the first region and surrounds at least a bottom portion of a trench gate structure configured by disposing the gate insulating film and the gate electrode in the trench. The silicon carbide according to any one of claims 14 to 16, wherein the portion is a high concentration layer (2b) in which the concentration of the first conductivity type impurity is higher than that of the remaining portion of the drift layer. Semiconductor device.
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