WO2016041229A1 - 基于边沿相加的时钟延迟调节电路及其集成芯片 - Google Patents
基于边沿相加的时钟延迟调节电路及其集成芯片 Download PDFInfo
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- WO2016041229A1 WO2016041229A1 PCT/CN2014/088913 CN2014088913W WO2016041229A1 WO 2016041229 A1 WO2016041229 A1 WO 2016041229A1 CN 2014088913 W CN2014088913 W CN 2014088913W WO 2016041229 A1 WO2016041229 A1 WO 2016041229A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00078—Fixed delay
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00163—Layout of the delay element using bipolar transistors
Definitions
- the present invention relates to the field of integrated circuits, and more particularly to an adjustment circuit for clock delay.
- sampling circuit In time-sampling ADCs, precise timing of sample generation is required.
- the sampling circuit is controlled by the sampling clock, and the sampling occurrence time can be controlled by adjusting the sampling clock generation time, and the sampling clock generation time can be realized by adjusting the sampling clock transmission path delay.
- the control of the sampling occurrence timing is mainly realized by using a clock delay adjustment circuit based on the delay unit selection method.
- a clock delay adjustment circuit based on delay cell selection comprising a plurality of delay cells connected in series and a selection circuit, the outputs of which are respectively connected to the selection Circuit.
- the clock delay adjustment principle is as follows: the input clock signal K in sequentially passes through a plurality of delay units to obtain a plurality of clock signals K1, K2, K3, K4 having different delays, which sequentially add a delay unit delay with respect to the original input clock signal K in after the clock K1, K2, K3, K4 are fed to the selection circuit for selecting one of the delayed clock signal to be output K out different values of the digital codes S0 and S1.
- the adjustment accuracy of the conventional clock delay adjustment circuit based on delay cell selection is one delay unit delay time.
- the delay time of the delay unit can only be on the order of 10 -12 seconds, which is far from meeting the requirements of accurate clock delay adjustment for high speed, high precision time-division sampling ADC.
- a clock delay adjustment circuit based on edge addition includes: a clock delay unit for performing equal interval delay on a clock signal input from an input terminal thereof to obtain at least three delayed clock signals of equal intervals and outputting the same; a weight coefficient unit, configured to generate a weight signal having the same number of the delayed clock signal according to a digital code input at an input end thereof, and output the same; an edge addition unit configured to receive the delayed clock signal and the weight signal, And based on the weighted letter The delayed clock signal is subjected to weighted summation processing and outputted to obtain a new continuous clock rising edge with the same number of delayed clock signals as the number of the delayed clock signals. Clock signal.
- one of the three weight signals is an average value of other weight signals.
- the three delayed clock signals include a first delayed clock signal, a second delayed clock signal, and a third delayed clock signal.
- the three weight signals are sequentially a first weight signal, a third weight signal, and a second weight signal, and the second weight signal is an average of the first weight signal and the third weight signal. value.
- the clock delay unit includes four delay circuits having the same structure, which are a first delay circuit, a second delay circuit, a third delay circuit, and a fourth a delay circuit, an input end of the first delay circuit is configured to receive the clock signal, and an output end of the first delay circuit outputs the first delayed clock signal and is connected to an input end of the second delay circuit, An output end of the second delay circuit outputs the second delayed clock signal and is connected to an input end of the third delay circuit, and an output end of the third delay circuit outputs the third delayed clock signal and connects the An input end of the fourth delay circuit, the output of the fourth delay circuit is suspended.
- the driving circuit includes the driving circuit including a first emitter follower, a second emitter follower, and first and second resistors, wherein the first resistor and The resistance of the second resistor is equal, and: the first emitter follower is composed of a third resistor, a first transistor, and a first DC current source and a source voltage, wherein the base of the first transistor Extremely the input end of the driving circuit, the emitter of the first triode is connected to one end of the first direct current source, and the other end of the first direct current source is connected to the negative pole of the source voltage, the first The collector of the triode is connected to one end of the third resistor, the other end of the third resistor is connected to the anode of the source voltage; the second emitter follower is composed of the fourth resistor, the second triode and the second direct current a source and a source voltage, wherein a base of the second transistor is an input end of the driving circuit, and an emitter of the second transistor is connected to
- the edge addition unit is composed of a fifth resistor and a sixth resistor, a third DC current source, a source voltage, and a differential pair circuit having the same number of the delayed clock signals.
- the differential pair circuit includes a first differential pair circuit, a second differential pair circuit, and a third differential pair circuit, and: the first differential pair circuit is composed of a third triode, a fourth triode, and a ninth three-pole a tube, the bases of the third transistor and the fourth transistor being the first input of the first differential pair circuit, and the set of the third transistor and the fourth transistor An electrode is used as an output end of the first differential pair circuit, and emitters of the third transistor and the fourth transistor are commonly connected to a collector of the ninth transistor, the ninth three a base of the pole tube as a second input end of the first differential pair circuit; the second differential pair circuit is composed of a fifth triode, a sixth triode, and a thirteenth pole tube, the The base of the fifth triode and the sixth triode is the first input of the
- FIG. 1 shows a schematic diagram of a clock delay adjustment circuit based on delay cell selection in the prior art.
- FIG. 2 is a schematic diagram showing a clock delay adjustment circuit based on edge addition according to the present invention.
- Fig. 3 is a diagram showing the principle of a clock delay adjustment circuit based on edge addition.
- FIG. 4 is a schematic diagram of a clock delay unit in a clock delay adjustment circuit based on edge addition in an embodiment of the present invention.
- FIG. 5 is a schematic diagram of an embodiment of a weight coefficient unit in a clock delay adjustment circuit based on edge addition according to an embodiment of the present invention.
- Figure 6 is a schematic diagram of the drive circuit in the weight coefficient unit of Figure 5.
- FIG. 7 is a schematic diagram of an edge addition unit in a clock delay adjustment circuit based on edge addition according to an embodiment of the present invention.
- Fig. 8c is a comparison diagram of the new clock signal output by the edge addition unit in the case of delay adjustment and without delay adjustment.
- the edge-addition-based clock delay adjustment circuit includes a clock delay unit 1, a weight coefficient unit 2, and The edge addition unit 3, wherein the clock delay unit 1 is configured to perform equal interval delay on the clock signals input from the input terminals thereof to obtain at least three delayed clock signals of equal intervals and output them; the weight coefficient unit 2 is used for Generating a weight signal identical to the number of the delayed clock signals according to the digital code input at the input end thereof, and outputting the same; the edge adding unit 3 is configured to receive the delayed clock signal and the weight signal, and according to the weight signal And performing the weighted summation processing on the delayed clock signal to obtain a new clock having the same continuous clock rising edge as the delayed clock signal/the same continuous clock falling edge as the delayed clock signal signal.
- the amplitudes of the at least three delayed clock signals are correspondingly adjusted by at least three weight signals generated by the weight coefficient unit 2 to ensure the new clock signal output by the edge addition unit 3
- the amplitude is the same as the amplitude of the clock signal input to the clock delay unit 1, and the different weight signals can be obtained by changing the digital code of the input weight coefficient unit 2, and the rising edge of the at least three consecutive clocks can be raised or lowered. Or the amplitude of a segment of the falling edge of three consecutive clocks to change the timing of the transition level, thereby achieving the purpose of clock delay or early adjustment.
- the horizontal axis represents time and the vertical axis represents voltage, where V 0 represents a switching level.
- V 0 represents a switching level.
- the adjustment step size can be much lower than the rising/falling edge of the clock signal, achieving an accuracy of 10 -15 seconds.
- the clock delay adjustment circuit based on the edge addition changes only the rising edge or the falling edge of the clock signal, thereby changing the edge of the rising edge or the falling edge of the clock signal while maintaining the overall amplitude of the clock signal. The overall rise or fall to achieve clock delay adjustment. Therefore, the accuracy of the clock delay adjustment in the present invention is greatly improved as compared with the existing delay unit selection method.
- the technical solution of the edge-added clock delay adjustment circuit will be described in detail below.
- the clock delay unit 1 generates three delayed clock signals and the weight coefficient unit 2 generates three weight signals.
- the edge addition unit 3 will generate Three consecutive clock rising edges, those skilled in the art can implement the description according to the technology, and obtain an implementation scheme with more than three delayed clock signals without any creative work.
- the three delayed clock signals are: a first delayed clock signal, a second delayed clock signal, and a third delayed clock signal; and the three weight signals are: a first weight signal, a second weight signal, and a The three-weight signal; the three-segment continuous clock rising edge includes: the first segment, the second segment, and the third segment.
- FIG. 4 there is shown a schematic diagram of an embodiment of a clock delay unit 1 in an edge-added clock delay adjustment circuit according to the present invention.
- the clock delay unit 1 includes four delay circuits of the same structure.
- the delay circuit 11d is sequentially connected in series in such a manner that the output terminal is connected to the input terminal, that is, the clock signal is input from the input terminal of the first delay circuit 11a, and the output terminal of the first delay circuit 11a outputs the first delayed clock signal and is connected to the second delay circuit 11b.
- the input end of the second delay circuit 11b outputs a second delayed clock signal and is connected to the input end of the third delay circuit 11c.
- the output end of the third delay circuit 11c outputs a third delayed clock signal and is connected to the fourth delay circuit 11d.
- the input terminal, while the output of the fourth delay circuit 11d is left floating, is not processed.
- the fourth delay circuit 11d is equivalent to the load of the third delay circuit 11c, thereby ensuring that the loads of the first delay circuit 11a, the second delay circuit 11b, and the third delay circuit 11c are the same, that is, the first delayed clock signal is secured.
- the second delayed clock signal and the third delayed clock signal are sequentially spaced apart by an equal time delay.
- the four delay circuits in FIG. 4 are implemented by using a differential circuit, and then the clock signal input to the clock delay unit 1 should be a pair of differential signals, and accordingly, the first delayed clock signal and the second delayed clock The signal and the third delayed clock signal are also a pair of differential signals.
- the acquisition of delayed clock signals is a common technique in the prior art
- the differential circuit is also a circuit structure well known in the art.
- the above-mentioned examples can be used to realize the acquisition of three delayed clock signals by using the well-known knowledge and the above technical description, and therefore will not be described again.
- FIG. 5 is a schematic diagram showing an embodiment of a weight coefficient unit 2 in a clock delay adjustment circuit based on edge addition according to an embodiment of the present invention
- the weight coefficient unit 2 including a digital to analog converter 21 (English Digital to The analog converter (referred to as DAC), the amplifier 22, and the driving circuit 23 are three parts, wherein the digital-to-analog converter 21 is configured to convert the digital code input from the input terminal of the self-weighting coefficient unit 2 into a pair of differential analog signals and output the same; 22 is configured to receive the differential analog signal and output the amplified analog signal; the driving circuit 23 is configured to receive the differential analog signal amplified by the amplifier 22 and divide it into three weight signals and output the same.
- DAC American Digital to The analog converter
- the digital-to-analog converter 21 may be a conventional digital-to-analog conversion circuit or a standard digital-to-analog converter 21 chip.
- the amplifier 22 is also the same, as long as it can satisfy the linear amplification of the differential analog signal, for example, a general differential amplifier 22 circuit or the like can be used.
- the driving circuit 23 can adopt two emitter followers and two first resistors having the same resistance (ie, the resistor R1 in the figure, the same below) and the second resistor (ie, the resistor R2 in the figure). Referring to FIG.
- the two emitter followers include a first emitter follower 231 and a second emitter follower 233, a first emitter follower 231 and a second emitter follower 233.
- the emitter is connected in series by a first resistor and a second resistor, and the resistances of the first resistor and the second resistor are equal.
- the bases of the first emitter follower 231 and the second emitter follower 233 are configured to receive the differential analog signal amplified by the amplifier 22, and by the first emitter follower 231 and Outputting the three weight signals between the emitter of the second emitter follower 233 and the first resistor and the second resistor, that is, outputting a second weight signal between the first resistor and the second resistor, the first An emitter follower 231 and a second emitter follower 233 output the first weight signal and the third weight signal, thereby ensuring that the second weight signal is unchanged and averaged for the first weight signal and the third weight signal value.
- the first emitter follower 231 and the second emitter follower 233 may adopt the structure shown in FIG. 6, that is, the first emitter follower 231 is made of a third resistor (ie, the resistor in the figure). R3, the same as below), the first triode (ie, the transistor Q1 in the figure, the same below) and the first DC current source (ie, the DC current source i1 in the figure, the same below) and the source voltage, wherein a base of the first triode is substantially at an input end of the driving circuit 23, an emitter of the first triode is connected to one end of the first direct current source, and a collector of the first triode is connected One end of the three resistors, the other end of the first DC current source is connected to the anode of the source voltage, the other end of the third resistor is connected to the anode of the source voltage; likewise, the second emitter follower 233 is connected to the fourth resistor (ie, the resistor R4 in the figure, the same below), the second
- the digital-to-analog converter 21 (DAC), the amplifier 22 and the driving circuit 23 in the weight coefficient unit 2 are common circuits in the art, and those skilled in the art can perform no creative work through the disclosure of the above technical solutions. The above technical solution is implemented, and therefore will not be described again.
- the adding unit 3 includes a pair of summing the fifth resistor (ie, the resistor R5 in the figure, the same below) and the sixth resistor (ie, the resistor R6 in the figure, the same below), and the third DC current source (ie, the DC in the diagram)
- the current source I the same as the source voltage, and the three differential pair circuits having the same number of the delayed clock signals; wherein the three differential pair circuits are specifically divided into the first differential pair circuit 31a and the second
- the differential pair circuit 31b and the third differential pair circuit 31c, the first differential pair circuit 31a is composed of a third triode (ie, the transistor Q3 in the figure, the same below) and a fourth triode (ie, the transistor Q4 in the diagram) , the same as the ninth transistor (ie, the transistor Q9 in the figure
- the third differential pair circuit 31c is composed of a seventh triode (ie, the transistor Q7 in the figure, the same below), an eighth triode (ie, the transistor Q8 in the figure, the same below), and the eleventh three
- the pole tube ie, the transistor Q11 in the figure, the same below
- the bases of the seventh transistor and the eighth transistor serve as the first input end of the third differential pair circuit 31c
- the collector of the tube and the eighth transistor serves as the output end of the third differential pair circuit 31c
- the emitters of the seventh transistor and the eighth transistor are connected in common to the collector of the eleventh transistor, and the tenth a base of a triode as a second input end of the third differential pair circuit 31c
- the emitters of the ninth triode, the thirteenth pole, and the eleventh transistor are connected to the first One end of the three DC current source, the other end of the third DC current source is connected to the anode of the source voltage; one end of the fifth resistor is commonly connected to the third transistor,
- the first differential pair circuit 31a, the second differential pair circuit 31b, and the third differential pair circuit The first input end of the 31c is configured to respectively receive the first delayed clock signal, the second delayed clock signal, and the third delayed clock signal, and the first differential pair circuit 31a, the second differential pair circuit 31b, and the third The second input end of the differential pair circuit 31c is configured to correspond to the first weight signal, the second weight signal, and the third weight signal, and finally by the first differential pair circuit 31a, the second differential pair circuit 31b, and the third differential pair circuit.
- the output of the 31c is connected in common to output the new clock signal.
- the third DC current source can be realized in the three differential pair circuits by adjusting the base voltages of the ninth transistor, the thirteenth diode, and the first transistor.
- the specific working principle of the edge addition unit 3 is divided into the following two steps: First, the first delayed clock signal, the second delayed clock signal, and the third delayed clock signal are respectively used by the first differential pair circuit 31a, The second differential pair circuit 31b and the third differential pair circuit 31c are enlarged (or reduced), and the multiple (ie, reduced) (i.e., weight) is adjusted by the first weight signal, the second weight signal, and the third weight signal, respectively; In step, the first differential pair circuit 31a, the second differential pair circuit 31b, and the third differential pair circuit 31c output are weighted and summed by summing the fifth resistor and the sixth resistor.
- the first delayed clock signal, the second delayed clock signal, and the third delayed clock respectively input at equal intervals are input to the first input terminals of the first differential pair circuit 31a, the second differential pair circuit 31b, and the third differential pair circuit 31c.
- the signal is known from the later analysis, thereby achieving the addition and adjustment of the rising edge of the clock signal.
- edge addition unit 3 realizes the addition and adjustment of the rising edge of the clock signal, as shown in FIGS. 8a-8b and in conjunction with FIGS. 4-7. Specifically, the operation principle of the edge addition unit 3 can be explained in detail in the case where there is no delay adjustment and in the case of delay adjustment.
- the third DC current source in FIG. 7 flows uniformly through the three differential pair circuits.
- the clock signal k o+ -k outputted from the output of the edge addition unit 3 O- rose from 0 to (the first segment of the new clock signal in Fig.
- the edge addition unit 3 when the rising edge of the delayed clock signal k m+ -k m- (i.e., the second delayed clock signal output from the clock delay unit 1) comes, the edge addition unit 3 The clock signal output from the output is k o+ -k o- up to (the second segment of the new clock signal in Fig. 8b); when the rising edge of the delayed clock signal k r+ -k r- (i.e., the third delayed clock signal output from the clock delay unit 1) comes, the edge addition unit 3 The clock signal output from the output is k o+ -k o- Rise to IR (the third segment of the new clock signal in Figure 8b). That is, the rising edge of the clock of the new clock signal is composed of the first segment, the second segment, and the third segment.
- the weight signal output by the weight coefficient unit 2 is ⁇ v, that is, The tail current of the third DC current source flowing to the left differential pair circuit (ie, the first differential pair circuit 31a) in FIG. 7 will increase. At the same time, the tail current flowing to the right differential pair circuit (ie, the second differential pair circuit 31b) will be reduced.
- g m is the transconductance of the ninth or thirteenth transistor and the eleventh transistor (they have the same size, so the transconductance is the same).
- ⁇ is the second rise time of the new clock signal in Figure 8c, then substituting (2) into the above In, you can get:
- V t is a physical constant proportional to absolute temperature
- N is the digital code of the input weight coefficient unit 2
- L SB is the step size of the DAC circuit
- the clock delay time can be controlled by digital codes, and the above analysis can be seen that the adjustment step is much lower than the rising/falling edge of the clock, which can reach 10 -15 seconds (fs The magnitude of the).
- the present invention can be made into an integrated circuit chip based on the edge addition clock delay adjustment circuit, thereby providing an integrated chip with clock delay adjustment.
- the present invention realizes the advance or delay of the transition level generation time by raising or lowering the rising edge of the clock as a whole, thereby increasing or decreasing the delay of the clock transmission path, and adjusting the precision to 10 -15 (fs). It is an order of magnitude, which solves the problem that the traditional clock delay adjustment method and circuit adjustment are accurate and low, and can not meet the requirements of high-speed, high-precision time-sampling ADC for precise clock delay adjustment. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
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Abstract
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Claims (10)
- 一种基于边沿相加的时钟延迟调节电路,其特征在于,包括:时钟延迟单元,用于对从其输入端输入的时钟信号做相等间隔延迟,以得到至少三个间隔相等时间的延迟时钟信号并予以输出;权系数单元,用于根据其输入端输入的数字码生成与所述延迟时钟信号个数相同的权重信号并予以输出;边沿相加单元,用于接收所述延迟时钟信号和所述权重信号,并依据所述权重信号将所述延迟时钟信号做加权求和处理后予以输出,以得到具有与所述延迟时钟信号个数相同的连续时钟上升沿/与所述延迟时钟信号个数相同的连续时钟下降沿的新时钟信号。
- 根据权利要求1所述的基于边沿相加的时钟延迟调节电路,其特征在于,所述权重信号中的其中一权重信号为其它所有权重信号的平均值。
- 根据权利要求1所述的基于边沿相加的时钟延迟调节电路,其特征在于,所述三个延迟时钟信号包括第一延迟时钟信号、第二延迟时钟信号及第三延迟时钟信号。
- 根据权利要求3所述的基于边沿相加的时钟延迟调节电路,其特征在于,所述时钟延迟单元包括四个具有相同结构的延迟电路,分别为第一延迟电路、第二延迟电路、第三延迟电路及第四延迟电路,所述第一延迟电路的输入端用于接收所述时钟信号,且所述第一延迟电路的输出端输出所述第一延迟时钟信号并连接所述第二延迟电路的输入端,所述第二延迟电路的输出端输出所述第二延迟时钟信号并连接所述第三延迟电路的输入端,所述第三延迟电路的输出端输出所述第三延迟时钟信号并连接所述第四延迟电路的输入端,所述第四延迟电路的输出端悬空。
- 根据权利要求4所述的基于边沿相加的时钟延迟调节电路,其特征在于,所述第一延迟电路、第二延迟电路、第三延迟电路及第四延迟电路分别为一差分电路,且输入所述第一延迟电路的时钟信号为一对差分信号。
- 根据权利要求1或3所述的基于边沿相加的时钟延迟调节电路,其特征在于,所述权系数单元包括:数模转换器,用于将自所述权系数单元的输入端接收的数字码转换成一对差分模拟信 号并予以输出;放大器,用于接收所述差分模拟信号并予以放大后输出;驱动电路,用于接收经所述放大器放大后的差分模拟信号并将其分成与所述延迟时钟信号个数相同的权重信号并予以输出。
- 根据权利要求6所述的基于边沿相加的时钟延迟调节电路,其特征在于,所述驱动电路包括第一射极跟随器、第二射极跟随器、第一电阻及第二电阻,其中,所述第一电阻和第二电阻的阻值相同,并且:所述第一射极跟随器由第三电阻、第一三极管、及第一直流电流源和源电压构成,其中,所述第一三极管的基极为所述驱动电路的输入端,所述第一三极管的发射极连接所述第一直流电流源的一端,所述第一直流电流源的另一端连接源电压的负极,所述第一三极管的集电极连接第三电阻的一端,所述第三电阻的另一端连接源电压的正极;所述第二射极跟随器由第四电阻、第二三极管、及第二直流电流源和源电压构成,其中,所述第二三极管的基极为所述驱动电路的输入端,所述第二三极管的发射极连接所述第二直流电流源的一端,所述第二直流电流源的另一端连接源电压的负极,所述第二三极管的集电极连接第四电阻的一端,所述第四电阻的另一端连接源电压的正极;所述第一电阻的一端连接所述第一三极管的发射极,所述第一电阻的另一端连接所述第二电阻的一端,所述第二电阻的另一端连接所述第二三极管的发射极,所述第一三极管和第二三极管的基极用于接收所述经所述放大器放大后的差分模拟信号,所述第一三极管和第二三极管的发射极、及所述第一电阻和第二电阻之间用于输出所述权重信号。
- 根据权利要求7所述的基于边沿相加的时钟延迟调节电路,其特征在于,所述权重信号依次为第一权重信号、第三权重信号及第二权重信号,且所述第二权重信号为第一权重信号和第三权重信号的平均值。
- 根据权利要求6所述的基于边沿相加的时钟延迟调节电路,其特征在于,所述边沿相加单元由第五电阻、第六电阻、第三直流电流源、源电压以及与所述延迟时钟信号个数相同的差分对电路构成,其中,所述差分对电路分别为第一差分对电路、第二差分对电路、第三差分对电路:所述第一差分对电路由第三三极管、第四三极管、及第九三极管构成,所述第三三极管和所述第四三极管的基极作为第一差分对电路的第一输入端,所述第三三极管和所 述第四三极管的集电极作为所述第一差分对电路的输出端,所述第三三极管和所述第四三极管的发射极共同连接到所述第九三极管的集电极,所述第九三极管的基极作为所述第一差分对电路的第二输入端;所述第二差分对电路由第五三极管、第六三极管、及第十三极管构成,所述第五三极管和所述第六三极管的基极作为第二差分对电路的第一输入端,所述第五三极管和所述第六三极管的集电极作为所述第二差分对电路的输出端,所述第五三极管和所述第六三极管的发射极共同连接到所述第十三极管的集电极,所述第十三极管的基极作为所述第二差分对电路的第二输入端;所述第三差分对电路由第七三极管、第八三极管、及第十一三极管构成,所述第七三极管和所述第八三极管的基极作为所述第三差分对电路的第一输入端,所述第七三极管和所述第八三极管的集电极作为所述第三差分对电路的输出端,所述第七三极管和所述第八三极管的发射极共同连接到所述第十一三极管的集电极,所述第十一三极管的基极作为所述第三差分对电路的第二输入端;所述第九三极管、所述第十三极管及所述第十一三极管的发射极分别共同连接至所述第三直流电流源的一端,所述第三直流电流源的另一端连接至所述源电压的负极;所述第五电阻的一端共同连接至所述第三三极管、第五三极管及第七三极管的集电极,所述第五电阻的另一端连接至所述源电压的正极,所述第六电阻的一端共同连接至所述第四三极管、第六三极管及第八三极管的集电极,所述第六电阻的另一端分别连接至所述源电压的正极。
- 一种基于边沿相加的时钟延迟调节集成芯片,其特征在于,所述集成芯片包括权利要求1-9中任一项所述的基于边沿相加的时钟延迟调节电路。
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