WO2016041229A1 - 基于边沿相加的时钟延迟调节电路及其集成芯片 - Google Patents

基于边沿相加的时钟延迟调节电路及其集成芯片 Download PDF

Info

Publication number
WO2016041229A1
WO2016041229A1 PCT/CN2014/088913 CN2014088913W WO2016041229A1 WO 2016041229 A1 WO2016041229 A1 WO 2016041229A1 CN 2014088913 W CN2014088913 W CN 2014088913W WO 2016041229 A1 WO2016041229 A1 WO 2016041229A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
triode
delay
clock
resistor
Prior art date
Application number
PCT/CN2014/088913
Other languages
English (en)
French (fr)
Inventor
胡蓉彬
朱璨
王永禄
张正平
张磊
高煜寒
叶荣科
陈光炳
王育新
付东兵
Original Assignee
中国电子科技集团公司第二十四研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国电子科技集团公司第二十四研究所 filed Critical 中国电子科技集团公司第二十四研究所
Priority to US15/313,809 priority Critical patent/US10404243B2/en
Publication of WO2016041229A1 publication Critical patent/WO2016041229A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors

Definitions

  • the present invention relates to the field of integrated circuits, and more particularly to an adjustment circuit for clock delay.
  • sampling circuit In time-sampling ADCs, precise timing of sample generation is required.
  • the sampling circuit is controlled by the sampling clock, and the sampling occurrence time can be controlled by adjusting the sampling clock generation time, and the sampling clock generation time can be realized by adjusting the sampling clock transmission path delay.
  • the control of the sampling occurrence timing is mainly realized by using a clock delay adjustment circuit based on the delay unit selection method.
  • a clock delay adjustment circuit based on delay cell selection comprising a plurality of delay cells connected in series and a selection circuit, the outputs of which are respectively connected to the selection Circuit.
  • the clock delay adjustment principle is as follows: the input clock signal K in sequentially passes through a plurality of delay units to obtain a plurality of clock signals K1, K2, K3, K4 having different delays, which sequentially add a delay unit delay with respect to the original input clock signal K in after the clock K1, K2, K3, K4 are fed to the selection circuit for selecting one of the delayed clock signal to be output K out different values of the digital codes S0 and S1.
  • the adjustment accuracy of the conventional clock delay adjustment circuit based on delay cell selection is one delay unit delay time.
  • the delay time of the delay unit can only be on the order of 10 -12 seconds, which is far from meeting the requirements of accurate clock delay adjustment for high speed, high precision time-division sampling ADC.
  • a clock delay adjustment circuit based on edge addition includes: a clock delay unit for performing equal interval delay on a clock signal input from an input terminal thereof to obtain at least three delayed clock signals of equal intervals and outputting the same; a weight coefficient unit, configured to generate a weight signal having the same number of the delayed clock signal according to a digital code input at an input end thereof, and output the same; an edge addition unit configured to receive the delayed clock signal and the weight signal, And based on the weighted letter The delayed clock signal is subjected to weighted summation processing and outputted to obtain a new continuous clock rising edge with the same number of delayed clock signals as the number of the delayed clock signals. Clock signal.
  • one of the three weight signals is an average value of other weight signals.
  • the three delayed clock signals include a first delayed clock signal, a second delayed clock signal, and a third delayed clock signal.
  • the three weight signals are sequentially a first weight signal, a third weight signal, and a second weight signal, and the second weight signal is an average of the first weight signal and the third weight signal. value.
  • the clock delay unit includes four delay circuits having the same structure, which are a first delay circuit, a second delay circuit, a third delay circuit, and a fourth a delay circuit, an input end of the first delay circuit is configured to receive the clock signal, and an output end of the first delay circuit outputs the first delayed clock signal and is connected to an input end of the second delay circuit, An output end of the second delay circuit outputs the second delayed clock signal and is connected to an input end of the third delay circuit, and an output end of the third delay circuit outputs the third delayed clock signal and connects the An input end of the fourth delay circuit, the output of the fourth delay circuit is suspended.
  • the driving circuit includes the driving circuit including a first emitter follower, a second emitter follower, and first and second resistors, wherein the first resistor and The resistance of the second resistor is equal, and: the first emitter follower is composed of a third resistor, a first transistor, and a first DC current source and a source voltage, wherein the base of the first transistor Extremely the input end of the driving circuit, the emitter of the first triode is connected to one end of the first direct current source, and the other end of the first direct current source is connected to the negative pole of the source voltage, the first The collector of the triode is connected to one end of the third resistor, the other end of the third resistor is connected to the anode of the source voltage; the second emitter follower is composed of the fourth resistor, the second triode and the second direct current a source and a source voltage, wherein a base of the second transistor is an input end of the driving circuit, and an emitter of the second transistor is connected to
  • the edge addition unit is composed of a fifth resistor and a sixth resistor, a third DC current source, a source voltage, and a differential pair circuit having the same number of the delayed clock signals.
  • the differential pair circuit includes a first differential pair circuit, a second differential pair circuit, and a third differential pair circuit, and: the first differential pair circuit is composed of a third triode, a fourth triode, and a ninth three-pole a tube, the bases of the third transistor and the fourth transistor being the first input of the first differential pair circuit, and the set of the third transistor and the fourth transistor An electrode is used as an output end of the first differential pair circuit, and emitters of the third transistor and the fourth transistor are commonly connected to a collector of the ninth transistor, the ninth three a base of the pole tube as a second input end of the first differential pair circuit; the second differential pair circuit is composed of a fifth triode, a sixth triode, and a thirteenth pole tube, the The base of the fifth triode and the sixth triode is the first input of the
  • FIG. 1 shows a schematic diagram of a clock delay adjustment circuit based on delay cell selection in the prior art.
  • FIG. 2 is a schematic diagram showing a clock delay adjustment circuit based on edge addition according to the present invention.
  • Fig. 3 is a diagram showing the principle of a clock delay adjustment circuit based on edge addition.
  • FIG. 4 is a schematic diagram of a clock delay unit in a clock delay adjustment circuit based on edge addition in an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an embodiment of a weight coefficient unit in a clock delay adjustment circuit based on edge addition according to an embodiment of the present invention.
  • Figure 6 is a schematic diagram of the drive circuit in the weight coefficient unit of Figure 5.
  • FIG. 7 is a schematic diagram of an edge addition unit in a clock delay adjustment circuit based on edge addition according to an embodiment of the present invention.
  • Fig. 8c is a comparison diagram of the new clock signal output by the edge addition unit in the case of delay adjustment and without delay adjustment.
  • the edge-addition-based clock delay adjustment circuit includes a clock delay unit 1, a weight coefficient unit 2, and The edge addition unit 3, wherein the clock delay unit 1 is configured to perform equal interval delay on the clock signals input from the input terminals thereof to obtain at least three delayed clock signals of equal intervals and output them; the weight coefficient unit 2 is used for Generating a weight signal identical to the number of the delayed clock signals according to the digital code input at the input end thereof, and outputting the same; the edge adding unit 3 is configured to receive the delayed clock signal and the weight signal, and according to the weight signal And performing the weighted summation processing on the delayed clock signal to obtain a new clock having the same continuous clock rising edge as the delayed clock signal/the same continuous clock falling edge as the delayed clock signal signal.
  • the amplitudes of the at least three delayed clock signals are correspondingly adjusted by at least three weight signals generated by the weight coefficient unit 2 to ensure the new clock signal output by the edge addition unit 3
  • the amplitude is the same as the amplitude of the clock signal input to the clock delay unit 1, and the different weight signals can be obtained by changing the digital code of the input weight coefficient unit 2, and the rising edge of the at least three consecutive clocks can be raised or lowered. Or the amplitude of a segment of the falling edge of three consecutive clocks to change the timing of the transition level, thereby achieving the purpose of clock delay or early adjustment.
  • the horizontal axis represents time and the vertical axis represents voltage, where V 0 represents a switching level.
  • V 0 represents a switching level.
  • the adjustment step size can be much lower than the rising/falling edge of the clock signal, achieving an accuracy of 10 -15 seconds.
  • the clock delay adjustment circuit based on the edge addition changes only the rising edge or the falling edge of the clock signal, thereby changing the edge of the rising edge or the falling edge of the clock signal while maintaining the overall amplitude of the clock signal. The overall rise or fall to achieve clock delay adjustment. Therefore, the accuracy of the clock delay adjustment in the present invention is greatly improved as compared with the existing delay unit selection method.
  • the technical solution of the edge-added clock delay adjustment circuit will be described in detail below.
  • the clock delay unit 1 generates three delayed clock signals and the weight coefficient unit 2 generates three weight signals.
  • the edge addition unit 3 will generate Three consecutive clock rising edges, those skilled in the art can implement the description according to the technology, and obtain an implementation scheme with more than three delayed clock signals without any creative work.
  • the three delayed clock signals are: a first delayed clock signal, a second delayed clock signal, and a third delayed clock signal; and the three weight signals are: a first weight signal, a second weight signal, and a The three-weight signal; the three-segment continuous clock rising edge includes: the first segment, the second segment, and the third segment.
  • FIG. 4 there is shown a schematic diagram of an embodiment of a clock delay unit 1 in an edge-added clock delay adjustment circuit according to the present invention.
  • the clock delay unit 1 includes four delay circuits of the same structure.
  • the delay circuit 11d is sequentially connected in series in such a manner that the output terminal is connected to the input terminal, that is, the clock signal is input from the input terminal of the first delay circuit 11a, and the output terminal of the first delay circuit 11a outputs the first delayed clock signal and is connected to the second delay circuit 11b.
  • the input end of the second delay circuit 11b outputs a second delayed clock signal and is connected to the input end of the third delay circuit 11c.
  • the output end of the third delay circuit 11c outputs a third delayed clock signal and is connected to the fourth delay circuit 11d.
  • the input terminal, while the output of the fourth delay circuit 11d is left floating, is not processed.
  • the fourth delay circuit 11d is equivalent to the load of the third delay circuit 11c, thereby ensuring that the loads of the first delay circuit 11a, the second delay circuit 11b, and the third delay circuit 11c are the same, that is, the first delayed clock signal is secured.
  • the second delayed clock signal and the third delayed clock signal are sequentially spaced apart by an equal time delay.
  • the four delay circuits in FIG. 4 are implemented by using a differential circuit, and then the clock signal input to the clock delay unit 1 should be a pair of differential signals, and accordingly, the first delayed clock signal and the second delayed clock The signal and the third delayed clock signal are also a pair of differential signals.
  • the acquisition of delayed clock signals is a common technique in the prior art
  • the differential circuit is also a circuit structure well known in the art.
  • the above-mentioned examples can be used to realize the acquisition of three delayed clock signals by using the well-known knowledge and the above technical description, and therefore will not be described again.
  • FIG. 5 is a schematic diagram showing an embodiment of a weight coefficient unit 2 in a clock delay adjustment circuit based on edge addition according to an embodiment of the present invention
  • the weight coefficient unit 2 including a digital to analog converter 21 (English Digital to The analog converter (referred to as DAC), the amplifier 22, and the driving circuit 23 are three parts, wherein the digital-to-analog converter 21 is configured to convert the digital code input from the input terminal of the self-weighting coefficient unit 2 into a pair of differential analog signals and output the same; 22 is configured to receive the differential analog signal and output the amplified analog signal; the driving circuit 23 is configured to receive the differential analog signal amplified by the amplifier 22 and divide it into three weight signals and output the same.
  • DAC American Digital to The analog converter
  • the digital-to-analog converter 21 may be a conventional digital-to-analog conversion circuit or a standard digital-to-analog converter 21 chip.
  • the amplifier 22 is also the same, as long as it can satisfy the linear amplification of the differential analog signal, for example, a general differential amplifier 22 circuit or the like can be used.
  • the driving circuit 23 can adopt two emitter followers and two first resistors having the same resistance (ie, the resistor R1 in the figure, the same below) and the second resistor (ie, the resistor R2 in the figure). Referring to FIG.
  • the two emitter followers include a first emitter follower 231 and a second emitter follower 233, a first emitter follower 231 and a second emitter follower 233.
  • the emitter is connected in series by a first resistor and a second resistor, and the resistances of the first resistor and the second resistor are equal.
  • the bases of the first emitter follower 231 and the second emitter follower 233 are configured to receive the differential analog signal amplified by the amplifier 22, and by the first emitter follower 231 and Outputting the three weight signals between the emitter of the second emitter follower 233 and the first resistor and the second resistor, that is, outputting a second weight signal between the first resistor and the second resistor, the first An emitter follower 231 and a second emitter follower 233 output the first weight signal and the third weight signal, thereby ensuring that the second weight signal is unchanged and averaged for the first weight signal and the third weight signal value.
  • the first emitter follower 231 and the second emitter follower 233 may adopt the structure shown in FIG. 6, that is, the first emitter follower 231 is made of a third resistor (ie, the resistor in the figure). R3, the same as below), the first triode (ie, the transistor Q1 in the figure, the same below) and the first DC current source (ie, the DC current source i1 in the figure, the same below) and the source voltage, wherein a base of the first triode is substantially at an input end of the driving circuit 23, an emitter of the first triode is connected to one end of the first direct current source, and a collector of the first triode is connected One end of the three resistors, the other end of the first DC current source is connected to the anode of the source voltage, the other end of the third resistor is connected to the anode of the source voltage; likewise, the second emitter follower 233 is connected to the fourth resistor (ie, the resistor R4 in the figure, the same below), the second
  • the digital-to-analog converter 21 (DAC), the amplifier 22 and the driving circuit 23 in the weight coefficient unit 2 are common circuits in the art, and those skilled in the art can perform no creative work through the disclosure of the above technical solutions. The above technical solution is implemented, and therefore will not be described again.
  • the adding unit 3 includes a pair of summing the fifth resistor (ie, the resistor R5 in the figure, the same below) and the sixth resistor (ie, the resistor R6 in the figure, the same below), and the third DC current source (ie, the DC in the diagram)
  • the current source I the same as the source voltage, and the three differential pair circuits having the same number of the delayed clock signals; wherein the three differential pair circuits are specifically divided into the first differential pair circuit 31a and the second
  • the differential pair circuit 31b and the third differential pair circuit 31c, the first differential pair circuit 31a is composed of a third triode (ie, the transistor Q3 in the figure, the same below) and a fourth triode (ie, the transistor Q4 in the diagram) , the same as the ninth transistor (ie, the transistor Q9 in the figure
  • the third differential pair circuit 31c is composed of a seventh triode (ie, the transistor Q7 in the figure, the same below), an eighth triode (ie, the transistor Q8 in the figure, the same below), and the eleventh three
  • the pole tube ie, the transistor Q11 in the figure, the same below
  • the bases of the seventh transistor and the eighth transistor serve as the first input end of the third differential pair circuit 31c
  • the collector of the tube and the eighth transistor serves as the output end of the third differential pair circuit 31c
  • the emitters of the seventh transistor and the eighth transistor are connected in common to the collector of the eleventh transistor, and the tenth a base of a triode as a second input end of the third differential pair circuit 31c
  • the emitters of the ninth triode, the thirteenth pole, and the eleventh transistor are connected to the first One end of the three DC current source, the other end of the third DC current source is connected to the anode of the source voltage; one end of the fifth resistor is commonly connected to the third transistor,
  • the first differential pair circuit 31a, the second differential pair circuit 31b, and the third differential pair circuit The first input end of the 31c is configured to respectively receive the first delayed clock signal, the second delayed clock signal, and the third delayed clock signal, and the first differential pair circuit 31a, the second differential pair circuit 31b, and the third The second input end of the differential pair circuit 31c is configured to correspond to the first weight signal, the second weight signal, and the third weight signal, and finally by the first differential pair circuit 31a, the second differential pair circuit 31b, and the third differential pair circuit.
  • the output of the 31c is connected in common to output the new clock signal.
  • the third DC current source can be realized in the three differential pair circuits by adjusting the base voltages of the ninth transistor, the thirteenth diode, and the first transistor.
  • the specific working principle of the edge addition unit 3 is divided into the following two steps: First, the first delayed clock signal, the second delayed clock signal, and the third delayed clock signal are respectively used by the first differential pair circuit 31a, The second differential pair circuit 31b and the third differential pair circuit 31c are enlarged (or reduced), and the multiple (ie, reduced) (i.e., weight) is adjusted by the first weight signal, the second weight signal, and the third weight signal, respectively; In step, the first differential pair circuit 31a, the second differential pair circuit 31b, and the third differential pair circuit 31c output are weighted and summed by summing the fifth resistor and the sixth resistor.
  • the first delayed clock signal, the second delayed clock signal, and the third delayed clock respectively input at equal intervals are input to the first input terminals of the first differential pair circuit 31a, the second differential pair circuit 31b, and the third differential pair circuit 31c.
  • the signal is known from the later analysis, thereby achieving the addition and adjustment of the rising edge of the clock signal.
  • edge addition unit 3 realizes the addition and adjustment of the rising edge of the clock signal, as shown in FIGS. 8a-8b and in conjunction with FIGS. 4-7. Specifically, the operation principle of the edge addition unit 3 can be explained in detail in the case where there is no delay adjustment and in the case of delay adjustment.
  • the third DC current source in FIG. 7 flows uniformly through the three differential pair circuits.
  • the clock signal k o+ -k outputted from the output of the edge addition unit 3 O- rose from 0 to (the first segment of the new clock signal in Fig.
  • the edge addition unit 3 when the rising edge of the delayed clock signal k m+ -k m- (i.e., the second delayed clock signal output from the clock delay unit 1) comes, the edge addition unit 3 The clock signal output from the output is k o+ -k o- up to (the second segment of the new clock signal in Fig. 8b); when the rising edge of the delayed clock signal k r+ -k r- (i.e., the third delayed clock signal output from the clock delay unit 1) comes, the edge addition unit 3 The clock signal output from the output is k o+ -k o- Rise to IR (the third segment of the new clock signal in Figure 8b). That is, the rising edge of the clock of the new clock signal is composed of the first segment, the second segment, and the third segment.
  • the weight signal output by the weight coefficient unit 2 is ⁇ v, that is, The tail current of the third DC current source flowing to the left differential pair circuit (ie, the first differential pair circuit 31a) in FIG. 7 will increase. At the same time, the tail current flowing to the right differential pair circuit (ie, the second differential pair circuit 31b) will be reduced.
  • g m is the transconductance of the ninth or thirteenth transistor and the eleventh transistor (they have the same size, so the transconductance is the same).
  • ⁇ is the second rise time of the new clock signal in Figure 8c, then substituting (2) into the above In, you can get:
  • V t is a physical constant proportional to absolute temperature
  • N is the digital code of the input weight coefficient unit 2
  • L SB is the step size of the DAC circuit
  • the clock delay time can be controlled by digital codes, and the above analysis can be seen that the adjustment step is much lower than the rising/falling edge of the clock, which can reach 10 -15 seconds (fs The magnitude of the).
  • the present invention can be made into an integrated circuit chip based on the edge addition clock delay adjustment circuit, thereby providing an integrated chip with clock delay adjustment.
  • the present invention realizes the advance or delay of the transition level generation time by raising or lowering the rising edge of the clock as a whole, thereby increasing or decreasing the delay of the clock transmission path, and adjusting the precision to 10 -15 (fs). It is an order of magnitude, which solves the problem that the traditional clock delay adjustment method and circuit adjustment are accurate and low, and can not meet the requirements of high-speed, high-precision time-sampling ADC for precise clock delay adjustment. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

提供一种基于边沿相加的时钟延迟调节电路及其集成芯片，其中，时钟延迟调节电路包括时钟延迟单元（1），用于对从其输入端输入的时钟信号做相等间隔延迟，以得到至少三个间隔相等时间的延迟时钟信号并予以输出；权系数单元（2），用于根据其输入端输入的数字码生成与延迟时钟信号个数相同的权重信号并予以输出；边沿相加单元（3），用于接收延迟时钟信号和权重信号，并依据权重信号将延迟时钟信号做加权求和处理后予以输出，以得到具有与延迟时钟信号个数相同的连续时钟上升沿/连续时钟下降沿的新时钟信号；另外，还可将时钟延迟调节电路做成一种集成芯片。很好地解决了现有时钟延迟调节电路调节精确低而无法满足高精确分时采样要求的问题。

Description

基于边沿相加的时钟延迟调节电路及其集成芯片 技术领域
本发明涉及一种集成电路领域，特别是涉及一种时钟延迟的调节电路。
背景技术
在分时采样ADC中，需要精确控制采样发生时刻。其中，采样电路由采样时钟来控制，通过调节采样时钟发生时间可以来控制采样发生时刻，而采样时钟发生时间可以通过调节采样时钟传输路径延迟来实现。
在现有的采样发生时刻控制技术中，主要是通过采用基于延迟单元选择方法的时钟延迟调节电路来实现对采样发生时刻的控制。例如，参见图1，示出了一种基于延迟单元选择的时钟延迟调节电路，包括多个依次串联连接的延迟单元和一个选择电路，所述多个延迟单元的输出端分别连接至所述选择电路。其时钟延迟调节原理为：输入时钟信号Kin依次经过多个延迟单元后得到多个延迟不同的时钟信号K1、K2、K3、K4，它们相对于原输入时钟信号Kin依次增加一个延迟单元延迟，之后所述时钟K1、K2、K3、K4被送入所述选择电路，根据数字码S0和S1的不同取值选择其中一个延迟时钟信号予以输出Kout。
由上述可知，现有的基于延迟单元选择的时钟延迟调节电路调节精度为一个延迟单元延迟时间。就目前的半导体工艺来说，延迟单元的延迟时间只能达到10-12秒的量级，远远不能满足高速、高精确分时采样ADC对于精确时钟延迟调节的要求。
所以，如何进一步提高时钟传输路径延迟的精度以满足分时采样ADC的要求就成了本技术领域亟待解决的问题。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种基于边沿相加的时钟延迟调节电路，用于解决现有时钟传输路径延迟调节的精确度不高而难以满足高速、高精确分时采样ADC技术要求的问题。
为实现上述目的及其它相关目的，本发明提供以下技术方案：
一种基于边沿相加的时钟延迟调节电路，包括：时钟延迟单元，用于对从其输入端输入的时钟信号做相等间隔延迟，以得到至少三个间隔相等时间的延迟时钟信号并予以输出；权系数单元，用于根据其输入端输入的数字码生成与所述延迟时钟信号个数相同的权重信号并予以输出；边沿相加单元，用于接收所述延迟时钟信号和所述权重信号，并依据所述权重信 号将所述延迟时钟信号做加权求和处理后予以输出，以得到具有与所述延迟时钟信号个数相同的连续时钟上升沿/与所述延迟时钟信号个数相同的连续时钟下降沿的新时钟信号。
优选地，在上述基于边沿相加的时钟延迟调节电路中，所述三个权重信号中的其中一权重信号为其它所有权重信号的平均值。
优选地，在上述基于边沿相加的时钟延迟调节电路中，所述三个延迟时钟信号包括第一延迟时钟信号、第二延迟时钟信号及第三延迟时钟信号。
作为上述优选方案的进一步优化，所述三个权重信号依次为第一权重信号、第三权重信号及第二权重信号，且所述第二权重信号为第一权重信号和第三权重信号的平均值。
优选地，在上述基于边沿相加的时钟延迟调节电路中，所述时钟延迟单元包括四个具有相同结构的延迟电路，分别为第一延迟电路、第二延迟电路、第三延迟电路及第四延迟电路，所述第一延迟电路的输入端用于接收所述时钟信号，且所述第一延迟电路的输出端输出所述第一延迟时钟信号并连接所述第二延迟电路的输入端，所述第二延迟电路的输出端输出所述第二延迟时钟信号并连接所述第三延迟电路的输入端，所述第三延迟电路的输出端输出所述第三延迟时钟信号并连接所述第四延迟电路的输入端，所述第四延迟电路的输出端悬空。
作为上述优选方案的进一步优化，所述权系数单元包括：数模转换器，用于将自权系数单元输入端输入的数字码转换成一对差分模拟信号并予以输出；放大器，用于接收所述差分模拟信号并予以放大后输出；驱动电路，用于接收经所述放大器放大后的差分模拟信号并将其分成三个权重信号并予以输出。
作为上述优选方案的更进一步优化，所述驱动电路包括所述驱动电路包括第一射极跟随器、第二射极跟随器、以及第一电阻和第二电阻，其中，所述第一电阻和第二电阻的阻值相等，并且：所述第一射极跟随器由第三电阻、第一三极管及第一直流电流源和源电压构成，其中，所述第一三极管的基极为所述驱动电路的输入端，所述第一三极管的发射极连接所述第一直流电流源的一端，所述第一直流电流源的另一端连接源电压的负极，所述第一三极管的集电极连接第三电阻的一端，所述第三电阻的另一端连接源电压的正极；所述第二射极跟随器由第四电阻、第二三极管及第二直流电流源和源电压构成，其中，所述第二三极管的基极为所述驱动电路的输入端，所述第二三极管的发射极连接所述第二直流电流源的一端，所述第二直流电流源的另一端连接源电压的负极，所述第二三极管的集电极连接第四电阻的一端，所述第四电阻的另一端连接源电压的正极；所述第一电阻的一端连接所述第一三极管的发射极，所述第一电阻的另一端连接所述第二电阻的一端，所述第二电阻的另一端连接所述 第二三极管的发射极，所述第一三极管和第二三极管的基极用于接收所述经所述放大器放大后的差分模拟信号，所述第一三极管和第二三极管的发射极、及所述第一电阻和第二电阻之间用于输出所述权重信号。
作为上述优选方案的再进一步优化，所述边沿相加单元由第五电阻和第六电阻、第三直流电流源、源电压、以及与所述延迟时钟信号个数相同的差分对电路构成，所述差分对电路包括第一差分对电路、第二差分对电路、第三差分对电路，并且：所述第一差分对电路由第三三极管、第四三极管、及第九三极管构成，所述第三三极管和所述第四三极管的基极作为第一差分对电路的第一输入端，所述第三三极管和所述第四三极管的集电极作为所述第一差分对电路的输出端，所述第三三极管和所述第四三极管的发射极共同连接到所述第九三极管的集电极，所述第九三极管的基极作为所述第一差分对电路的第二输入端；所述第二差分对电路由第五三极管、第六三极管、及第十三极管构成，所述第五三极管和所述第六三极管的基极作为第二差分对电路的第一输入端，所述第五三极管和所述第六三极管的集电极作为所述第二差分对电路的输出端，所述第五三极管和所述第六三极管的发射极共同连接到所述第十三极管的集电极，所述第十三极管的基极作为所述第二差分对电路的第二输入端；所述第三差分对电路由第七三极管、第八三极管、及第十一三极管构成，所述第七三极管和所述第八三极管的基极作为所述第三差分对电路的第一输入端，所述第七三极管和所述第八三极管的集电极作为所述第三差分对电路的输出端，所述第七三极管和所述第八三极管的发射极共同连接到所述第十一三极管的集电极，所述第十一三极管的基极作为所述第三差分对电路的第二输入端；所述第九三极管、所述第十三极管及所述第十一三极管的发射极分别共同连接至所述第三直流电流源的一端，所述第三直流电流源的另一端连接至所述源电压的负极；所述第五电阻的一端共同连接至所述第三三极管、第五三极管及第七三极管的集电极，所述第五电阻的另一端连接至所述源电压的正极，所述第六电阻的一端共同连接至所述第四三极管、第六三极管及第八三极管的集电极，所述第六电阻的另一端分别连接至所述源电压的正极。
优选地，在上述基于边沿相加的时钟延迟调节电路中，所述时钟单元为一差分信号。
如上所述，本发明具有以下有益效果：通过把时钟信号的进行等间隔延得到多个延迟时钟信号，并利用数字码生成与所述多个延迟时钟信号数量相同的权重信号，从而将所述多个延迟时钟信号根据所述权重信号进行加权求和，以得到与时钟信号幅度相同的但具有多段连续的上升沿/下降沿的新时钟信号，那么只需要改变数字码即可实现整体抬升或者下降新时钟信号的上升沿/下降沿，从而来实现转换电平发生时间的提前或者延迟，从而实现时钟传输路 径延迟的增加或减少，本发明相对现有的通过延迟单元选择的方法，其调节精确可达10-15(fs)秒数量级，远远高于现有的延迟调节精度，从而很好地解决了传统时钟延迟调节方法和电路调节精确低而不能满足高速、高精确分时采样ADC对精确时钟延迟调节要求的问题。
附图说明
图1显示为现有技术中一种基于延迟单元选择的时钟延迟调节电路原理图。
图2显示为本发明基于边沿相加的时钟延迟调节电路的原理图。
图3显示为基于边沿相加的时钟延迟调节电路的原理说明图。
图4为本发明基于边沿相加的时钟延迟调节电路中时钟延迟单元在实施例中的原理图。
图5为本发明基于边沿相加的时钟延迟调节电路中权系数单元在一实施例的原理图。
图6为图5权系数单元中的驱动电路的原理图。
图7为本发明基于边沿相加的时钟延迟调节电路中边沿相加单元在一实施例的原理图。
图8a为时钟延迟单元输出的三个延迟时钟信号。
图8b为边沿相加单元在没有延迟调节的情况下所输出的新时钟信号。
图8c为边沿相加单元在延迟调节的情况下和没有延迟调节的情况下输出的新时钟信号对比图。
附图标号说明
1    时钟延迟单元
11a  第一延迟电路
11b  第二延迟电路
11c  第三延迟电路
11d  第四延迟电路
2    权系数单元
21   数模转换器
22   放大器
23   驱动电路
231  第一射极跟随器
233  第二射极跟随器
3    边沿相加单元
31a  第一差分对电路
31b  第二差分对电路
31c  第三差分对电路
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其它优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
请参阅图2，示出了本发明基于边沿相加的时钟延迟调节电路的原理图，在本发明中，所述基于边沿相加的时钟延迟调节电路包括时钟延迟单元1、权系数单元2及边沿相加单元3，其中，时钟延迟单元1用于对从其输入端输入的时钟信号做相等间隔延迟，以得到至少三个间隔相等时间的延迟时钟信号并予以输出；权系数单元2用于根据其输入端输入的数字码生成与所述延迟时钟信号个数相同的权重信号并予以输出；边沿相加单元3用于接收所述延迟时钟信号和所述权重信号，并依据所述权重信号将所述延迟时钟信号做加权求和处理后予以输出，以得到具有与所述延迟时钟信号个数相同的连续时钟上升沿/与所述延迟时钟信号个数相同的连续时钟下降沿的新时钟信号。
在以上所述技术方案中，通过权系数单元2产生的至少三个权重信号来对应调节所述至少三个延迟时钟信号的幅值，以保证边沿相加单元3输出的所述新时钟信号的幅度与输入所述时钟延迟单元1的时钟信号的幅度相同，那么只要改变输入权系数单元2的数字码即可得到不同的权重信号，即可抬高或降低所述至少三段连续时钟上升沿或者三段连续时钟下降沿中某一段的幅度，以改变转换电平的发生时刻，从而达到时钟延迟或提前调节的目的。
进一步地，这里将对上述基于边沿相加的时钟延迟调节电路实现时钟传输路径延迟的增加或减少的原理做详细说明。见图3，图中的横轴表示时间，纵轴表示电压，其中V0表示转换电平。为了说明方便，这里以时钟信号的上升沿调节为例进行说明(本发明对于下降沿也具有同样的调节效果，这对于本领域技术人员是很容易理解的，故下文将默认以时钟信号的 上升沿为例进行说明)。据图3可知，当时钟信号K1整体垂直上升得到时钟信号K1'，转换电平V0的发生时刻由To变成Te，相当于时钟信号K1'相对时钟信号K1提前了To-Te的时间，或者说整个时钟路径延迟减少了To-Te的时间。基于这种方式的时钟延迟调节，调节步长可以远远低于时钟信号上升沿/下降沿，达到10-15秒的精度。而基于边沿相加的时钟延迟调节电路所改变的只是时钟信号的上升沿或下降沿，从而在保持时钟信号整体幅度不变的情况下改变该时钟信号的上升沿或下降沿的部分沿段的整体抬升或下降，以实现时钟的延迟调节。所以，相对于现有的基于延迟单元选择方法，本发明中时钟延迟调节的精度得到很大的提高。
为了使本领域的技术人员更加清楚的了解本发明的技术方案，下面将对所述基于边沿相加的时钟延迟调节电路的技术方案作详细的说明。在下文中，将对所述时钟延迟单元1产生三个延迟时钟信号和所述权系数单元2产生三个权重信号的情况为例进行技术实现说明，对应地，所述边沿相加单元3将生成三段连续时钟上升沿，本领域的技术人员可以依据该技术实现说明，在不付出创造性劳动的情况下而得到大于三个延迟时钟信号的实现方案。另外，为便于叙述，令三个延迟时钟信号为：第一延迟时钟信号、第二延迟时钟信号、第三延迟时钟信号；令三个权重信号为：第一权重信号、第二权重信号、第三权重信号；令三段连续时钟上升沿包括：第一段、第二段、第三段。
具体地，请参见图4，示出了本发明基于边沿相加的时钟延迟调节电路中时钟延迟单元1在一实施例的原理图，所述时钟延迟单元1包括了四个相同结构的延迟电路，分别为：第一延迟电路11a、第二延迟电路11b、第三延迟电路11c及第四延迟电路11d，其中，第一延迟电路11a、第二延迟电路11b、第三延迟电路11c及第四延迟电路11d依次按照输出端连接输入端的方式串联连接，即时钟信号由第一延迟电路11a的输入端输入，第一延迟电路11a的输出端输出第一延迟时钟信号并连接第二延迟电路11b的输入端，第二延迟电路11b的输出端输出第二延迟时钟信号并连接第三延迟电路11c的输入端，第三延迟电路11c的输出端输出第三延迟时钟信号并连接第四延迟电路11d的输入端，而第四延迟电路11d的输出悬空不做处理。这里，第四延迟电路11d相当于第三延迟电路11c的负载，从而保证了第一延迟电路11a、第二延迟电路11b及第三延迟电路11c的负载相同，也即保证了第一延迟时钟信号、第二延迟时钟信号、第三延迟时钟信号依次间隔相等时间延迟。
更具体地，在图4中的四个延迟电路采用差分电路来实现，那么输入时钟延迟单元1的时钟信号应当为一对差分信号，相应地，所述第一延迟时钟信号、第二延迟时钟信号、第三延迟时钟信号也均为一对差分信号。对于延迟时钟信号的获取在现有技术中是常见的技术， 而且差分电路也是本领域公知的电路结构，对于本领域技术人员而言，通过上述示例说明，完全可以利用公知知识和上述技术说明来实现三个延迟时钟信号的获取，故不再赘述。
进一步地，见图5，示出了本发明基于边沿相加的时钟延迟调节电路中权系数单元2在一实施例的原理图，所述权系数单元2包括数模转换器21(英文Digital to analog converter，简称DAC)、放大器22、驱动电路23三部分，其中，数模转换器21用于将自权系数单元2输入端输入的数字码转换成一对差分模拟信号并予以输出；所述放大器22用于接收所述差分模拟信号并予以放大后输出；所述驱动电路23，用于接收经所述放大器22放大后的差分模拟信号并将其分成三个权重信号并予以输出。
具体地，在上述权系数单元2中，所述数模转换器21可以是采用常用的数模转换电路，也可以是各种标准的数模转换器21芯片。同样，放大器22也是一样，只要满足可以对所述差分模拟信号进行线性放大即可，例如可以采用一般差分放大器22电路等。另外，所述驱动电路23可以采用两个射极跟随器及两个阻值相等的第一电阻(即图示中的电阻R1，下同)和第二电阻(即图示中的电阻R2，下同)来予以实现，请参见图6，两个射极跟随器包括第一射极跟随器231和第二射极跟随器233，第一射极跟随器231和第二射极跟随器233的射极通过第一电阻和第二电阻来予以串联连接，所述第一电阻和第二电阻的阻值相等。所述第一射极跟随器231和第二射极跟随器233的基极用于接收所述经所述放大器22放大后的差分模拟信号，并由所述第一射极跟随器231和第二射极跟随器233的射极和所述第一电阻和第二电阻之间输出所述三个权重信号，即所述第一电阻和第二电阻之间输出第二权重信号，所述第一射极跟随器231和第二射极跟随器233输出所述第一权重信号和第三权重信号，从而保证了第二权重信号不变并为所述第一权重信号和第三权重信号平均值。
更具体地，所述第一射极跟随器231和第二射极跟随器233可以采用图6所示结构，即所述第一射极跟随器231由第三电阻(即图示中的电阻R3，下同)、第一三极管(即示图中三极管Q1，下同)及第一直流电流源(即示图中直流电流源i1，下同)和源电压构成，其中，所述第一三极管的基极为所述驱动电路23的输入端，所述第一三极管的发射极连接所述第一直流电流源的一端，所述第一三极管的集电极连接第三电阻的一端，所述第一直流电流源的另一端连接源电压的负极，所述第三电阻的另一端连接源电压的正极；同样，所述第二射极跟随器233由第四电阻(即图示中的电阻R4，下同)、第二三极管(即示图中三极管Q2，下同)及第二直流电流源(即示图中直流电流源i2，下同)和源电压构成，其中，所述第二三极管的基极为所述驱动电路23的输入端，所述第二三极管的发射极连接所述第二直流电流源的一端，所述第二三极管的集电极连接第四电阻的一端，所述直流电流源的另一端连接源 电压的负极，所述第四电阻的另一端连接源电压的正极。
应当理解，权系数单元2中数模转换器21(DAC)、放大器22及驱动电路23是本技术领域的常用电路，通过上述技术方案的公开，本领域的技术人员可以在不付出创造性劳动的情况来实现上述技术方案，故不再赘述。
进一步地，见图7并结合图4和图5，示出了本发明基于边沿相加的时钟延迟调节电路中边沿相加单元3在一实施例的原理图，从图来看，所述边沿相加单元3包括一对求和第五电阻(即示图中电阻R5，下同)和第六电阻(即示图中电阻R6，下同)、第三直流电流源(即示图中直流电流源I，下同)、源电压构成、以及与所述延迟时钟信号个数相同的三个差分对电路；其中，所述三个差分对电路具体分为第一差分对电路31a、第二差分对电路31b及第三差分对电路31c，所述第一差分对电路31a由第三三极管(即示图中三极管Q3，下同)、第四三极管(即示图中三极管Q4，下同)、及第九三极管(即示图中三极管Q9，下同)构成，第三三极管和第四三极管的基极作为第一差分对电路31a的第一输入端，第三三极管和第四三极管的集电极作为第一差分对电路31a的输出端，第三三极管和第四三极管的发射极共同连接到第九三极管的集电极，第九三极管的基极作为第一差分对电路31a的第二输入端；同理，所述第二差分对电路31b由第五三极管(即示图中三极管Q5，下同)、第六三极管(即示图中三极管Q6，下同)、及第十三极管(即示图中三极管Q10，下同)构成，第五三极管和第六三极管的基极作为第二差分对电路31b的第一输入端，第五三极管和第六三极管的集电极作为第二差分对电路31b的输出端，第五三极管和第六三极管的发射极共同连接到第十三极管的集电极，第十三极管的基极作为第二差分对电路31b的第二输入端；所述第三差分对电路31c由第七三极管(即示图中三极管Q7，下同)、第八三极管(即示图中三极管Q8，下同)、及第十一三极管(即示图中三极管Q11，下同)构成，第七三极管和第八三极管的基极作为第三差分对电路31c的第一输入端，第七三极管和第八三极管的集电极作为第三差分对电路31c的输出端，第七三极管和第八三极管的发射极共同连接到第十一三极管的集电极，第十一三极管的基极作为第三差分对电路31c的第二输入端；所述第九三极管、第十三极管及第十一三极管的发射极分别共同连接至所述第三直流电流源的一端，所述第三直流电流源的另一端连接至所述源电压的负极；所述第五电阻的一端共同连接至所述第三三极管、第五三极管及第七三极管的集电极，所述第五电阻的另一端连接至所述源电压的正极，所述第六电阻的一端共同连接至所述第四三极管、第六三极管及第八三极管的集电极，所述第六电阻的另一端分别连接至所述源电压的正极。
具体地，在工作时，所述第一差分对电路31a、第二差分对电路31b及第三差分对电路 31c的第一输入端用于分别对应接收所述第一延迟时钟信号、第二延迟时钟信号及第三延迟时钟信号，而所述第一差分对电路31a、第二差分对电路31b及第三差分对电路31c的第二输入端用于对应所述第一权重信号、第二权重信号及第三权重信号，最后由第一差分对电路31a、第二差分对电路31b及第三差分对电路31c的输出端共同连接后予以输出所述新时钟信号。
更具体地，在上述边沿相加单元3中，通过调节第九三极管、第十三极管及第一三极管的基极电压可实现第三直流电流源在三个差分对电路中的分配比例，所述边沿相加单元3的具体工作原理分以下两步：第一步，第一延迟时钟信号、第二延迟时钟信号及第三延迟时钟信号分别被第一差分对电路31a、第二差分对电路31b、第三差分对电路31c放大(或缩小)，放大(或缩小)倍数(即权重)分别由第一权重信号、第二权重信号、第三权重信号予以调节；第二步，第一差分对电路31a、第二差分对电路31b及第三差分对电路31c输出通过求和第五电阻和第六电阻实现加权求和。由于第一差分对电路31a、第二差分对电路31b及第三差分对电路31c的第一输入端输入的分别为间隔相等时间的第一延迟时钟信号、第二延迟时钟信号及第三延迟时钟信号，由后面的分析可知，从而实现了时钟信号上升沿的相加和调节。
进一步地，下面将对上述边沿相加单元3如何实现时钟信号上升沿的相加和调节进行详细的原理说明，请见图8a-8b并结合图4-7。具体地，可以分在没有延迟调节的情况下和在延迟调节的情况下两种情况来详细说明所述边沿相加单元3的工作原理。
第一，在没有延迟调节的情况下。
在没有延迟调节的情况下，权系数单元2输出的权重信号为cl–cr＝0，cl＝cr＝cm。这时，图7中的第三直流电流源均匀的流过三个差分对电路。如图8a，当延迟时钟信号kl+-kl-的(即时钟延迟单元1输出的第一延迟时钟信号)上升沿到来时，边沿相加单元3的输出端输出的时钟信号ko+-ko-从0上升到
Figure PCTCN2014088913-appb-000001
(图8b中的新时钟信号的第一段)；当延迟时钟信号km+-km-(即时钟延迟单元1输出的第二延迟时钟信号)的上升沿到来时，边沿相加单元3的输出端输出的时钟信号ko+-ko-从
Figure PCTCN2014088913-appb-000002
上升到
Figure PCTCN2014088913-appb-000003
(图8b中的新时钟信号的第二段)；当延迟时钟信号kr+-kr-(即时钟延迟单元1输出的第三延迟时钟信号)的上升沿到来时，边沿相加单元3的输出端输出的时钟信号ko+-ko-从
Figure PCTCN2014088913-appb-000004
上升到IR(图8b中的新时钟信号的第三段)。也即是所述新时钟信号的时钟上升沿是由所述第一段、第二段及第三段组成。
第二，在延迟调节的情况下。
在延迟调节的情况下，假设权系数单元2输出的权重信号为Δv，也就是说
Figure PCTCN2014088913-appb-000005
Figure PCTCN2014088913-appb-000006
图7中第三直流电流源流向左边差分对电路(即第一差分对电路31a)的尾电流将增加
Figure PCTCN2014088913-appb-000007
同时流向右边差分对电路(即第二差分对电路31b)的尾电流将减少
Figure PCTCN2014088913-appb-000008
这里gm是第九三极管或者第十三极管、第十一三极管的跨导(它们具有相同的尺寸，故跨导相同)。在这种情况下，当延迟时钟信号kl+-kl-(即时钟延迟单元1输出的第一延迟时钟信号)的上升沿到来时，边沿相加单元3的输出端输出的时钟信号ko+-ko-从0上升到
Figure PCTCN2014088913-appb-000009
(如图8c中的新时钟信号的第一段)，且上升时间与图8b中的新时钟信号的第一段相同；当延迟时钟信号km+-km-(即时钟延迟单元1输出的第二延迟时钟信号)的上升沿到来时，输出时钟信号ko+-ko-从
Figure PCTCN2014088913-appb-000010
上升到
Figure PCTCN2014088913-appb-000011
(如图8c中新时钟信号的的第二段)，且该段与图8b中新时钟信号的的第二段完全相同，只是整体垂直上升了
Figure PCTCN2014088913-appb-000012
高度，这样转换电平的发生时间提前了
Figure PCTCN2014088913-appb-000013
秒，或者说时钟延迟减少了
Figure PCTCN2014088913-appb-000014
秒，这里a为新时钟信号的第二段的斜率；当延迟时钟信号kr+-kr-(即时钟延迟单元1输出的第三延迟时钟信号)的上升沿到来时，边沿相加单元3的输出端输出的时钟信号ko+-ko-从
Figure PCTCN2014088913-appb-000015
上升到
Figure PCTCN2014088913-appb-000016
(图8c中新时钟信号的的第三段)，同理在延迟调节情况下所述边沿相加单元3所输出的所述第一段、第二段及第三段也是构成了所述新时钟信号的时钟上升沿，从上述整个调节过程来看，在延迟调节情况下输出的新时钟信号和在没有延迟调节的情况下输出的新时钟信号在总高度上是保持不变，即新时钟信号的幅值是保持不变的。
进一步地，在上述延迟调节的情况中，
Figure PCTCN2014088913-appb-000017
上式中τ为图8c中新时钟信号的的第二段上升时间，那么将(2)代入上述
Figure PCTCN2014088913-appb-000018
中，即可得到：
Figure PCTCN2014088913-appb-000019
另外，
Figure PCTCN2014088913-appb-000020
上式中Vt为一正比于绝对温度的物理常数，把(4)代入(3)有
Figure PCTCN2014088913-appb-000021
由于Δv是权系数单元2输出的权重信号，所以
Δv＝N*LSB   (6)
上式中N是输入权系数单元2的数字码，LSB是DAC电路的步长，把(6)代入(5)有
Figure PCTCN2014088913-appb-000022
由上式可以看出时钟延迟时间可以用数字码来控制，而且从上面的分析可以看出这种调节方式，调节步长远远低于时钟的上升/下降沿，可以达到10-15秒(fs)的量级。
另外，在实际应用过程中，可以将本发明基于边沿相加的时钟延迟调节电路做成集成电路芯片，从而提供一种具有时钟延迟调节的集成芯片。
综上所述，本发明通过把时钟上升沿整体抬升或者下降来实现转换电平发生时间的提前或者延迟，从而实现时钟传输路径延迟的增加或减少，且调节精确可达10-15(fs)秒数量级，从而很好地解决了传统时钟延迟调节方法和电路调节精确低而不能满足高速、高精确分时采样ADC对精确时钟延迟调节要求的问题。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种基于边沿相加的时钟延迟调节电路，其特征在于，包括：
    时钟延迟单元，用于对从其输入端输入的时钟信号做相等间隔延迟，以得到至少三个间隔相等时间的延迟时钟信号并予以输出；
    权系数单元，用于根据其输入端输入的数字码生成与所述延迟时钟信号个数相同的权重信号并予以输出；
    边沿相加单元，用于接收所述延迟时钟信号和所述权重信号，并依据所述权重信号将所述延迟时钟信号做加权求和处理后予以输出，以得到具有与所述延迟时钟信号个数相同的连续时钟上升沿/与所述延迟时钟信号个数相同的连续时钟下降沿的新时钟信号。
  2. 根据权利要求1所述的基于边沿相加的时钟延迟调节电路，其特征在于，所述权重信号中的其中一权重信号为其它所有权重信号的平均值。
  3. 根据权利要求1所述的基于边沿相加的时钟延迟调节电路，其特征在于，所述三个延迟时钟信号包括第一延迟时钟信号、第二延迟时钟信号及第三延迟时钟信号。
  4. 根据权利要求3所述的基于边沿相加的时钟延迟调节电路，其特征在于，所述时钟延迟单元包括四个具有相同结构的延迟电路，分别为第一延迟电路、第二延迟电路、第三延迟电路及第四延迟电路，所述第一延迟电路的输入端用于接收所述时钟信号，且所述第一延迟电路的输出端输出所述第一延迟时钟信号并连接所述第二延迟电路的输入端，所述第二延迟电路的输出端输出所述第二延迟时钟信号并连接所述第三延迟电路的输入端，所述第三延迟电路的输出端输出所述第三延迟时钟信号并连接所述第四延迟电路的输入端，所述第四延迟电路的输出端悬空。
  5. 根据权利要求4所述的基于边沿相加的时钟延迟调节电路，其特征在于，所述第一延迟电路、第二延迟电路、第三延迟电路及第四延迟电路分别为一差分电路，且输入所述第一延迟电路的时钟信号为一对差分信号。
  6. 根据权利要求1或3所述的基于边沿相加的时钟延迟调节电路，其特征在于，所述权系数单元包括：
    数模转换器，用于将自所述权系数单元的输入端接收的数字码转换成一对差分模拟信 号并予以输出；
    放大器，用于接收所述差分模拟信号并予以放大后输出；
    驱动电路，用于接收经所述放大器放大后的差分模拟信号并将其分成与所述延迟时钟信号个数相同的权重信号并予以输出。
  7. 根据权利要求6所述的基于边沿相加的时钟延迟调节电路，其特征在于，所述驱动电路包括第一射极跟随器、第二射极跟随器、第一电阻及第二电阻，其中，所述第一电阻和第二电阻的阻值相同，并且：
    所述第一射极跟随器由第三电阻、第一三极管、及第一直流电流源和源电压构成，其中，所述第一三极管的基极为所述驱动电路的输入端，所述第一三极管的发射极连接所述第一直流电流源的一端，所述第一直流电流源的另一端连接源电压的负极，所述第一三极管的集电极连接第三电阻的一端，所述第三电阻的另一端连接源电压的正极；
    所述第二射极跟随器由第四电阻、第二三极管、及第二直流电流源和源电压构成，其中，所述第二三极管的基极为所述驱动电路的输入端，所述第二三极管的发射极连接所述第二直流电流源的一端，所述第二直流电流源的另一端连接源电压的负极，所述第二三极管的集电极连接第四电阻的一端，所述第四电阻的另一端连接源电压的正极；
    所述第一电阻的一端连接所述第一三极管的发射极，所述第一电阻的另一端连接所述第二电阻的一端，所述第二电阻的另一端连接所述第二三极管的发射极，所述第一三极管和第二三极管的基极用于接收所述经所述放大器放大后的差分模拟信号，所述第一三极管和第二三极管的发射极、及所述第一电阻和第二电阻之间用于输出所述权重信号。
  8. 根据权利要求7所述的基于边沿相加的时钟延迟调节电路，其特征在于，所述权重信号依次为第一权重信号、第三权重信号及第二权重信号，且所述第二权重信号为第一权重信号和第三权重信号的平均值。
  9. 根据权利要求6所述的基于边沿相加的时钟延迟调节电路，其特征在于，所述边沿相加单元由第五电阻、第六电阻、第三直流电流源、源电压以及与所述延迟时钟信号个数相同的差分对电路构成，其中，所述差分对电路分别为第一差分对电路、第二差分对电路、第三差分对电路：
    所述第一差分对电路由第三三极管、第四三极管、及第九三极管构成，所述第三三极管和所述第四三极管的基极作为第一差分对电路的第一输入端，所述第三三极管和所 述第四三极管的集电极作为所述第一差分对电路的输出端，所述第三三极管和所述第四三极管的发射极共同连接到所述第九三极管的集电极，所述第九三极管的基极作为所述第一差分对电路的第二输入端；
    所述第二差分对电路由第五三极管、第六三极管、及第十三极管构成，所述第五三极管和所述第六三极管的基极作为第二差分对电路的第一输入端，所述第五三极管和所述第六三极管的集电极作为所述第二差分对电路的输出端，所述第五三极管和所述第六三极管的发射极共同连接到所述第十三极管的集电极，所述第十三极管的基极作为所述第二差分对电路的第二输入端；
    所述第三差分对电路由第七三极管、第八三极管、及第十一三极管构成，所述第七三极管和所述第八三极管的基极作为所述第三差分对电路的第一输入端，所述第七三极管和所述第八三极管的集电极作为所述第三差分对电路的输出端，所述第七三极管和所述第八三极管的发射极共同连接到所述第十一三极管的集电极，所述第十一三极管的基极作为所述第三差分对电路的第二输入端；
    所述第九三极管、所述第十三极管及所述第十一三极管的发射极分别共同连接至所述第三直流电流源的一端，所述第三直流电流源的另一端连接至所述源电压的负极；所述第五电阻的一端共同连接至所述第三三极管、第五三极管及第七三极管的集电极，所述第五电阻的另一端连接至所述源电压的正极，所述第六电阻的一端共同连接至所述第四三极管、第六三极管及第八三极管的集电极，所述第六电阻的另一端分别连接至所述源电压的正极。
  10. 一种基于边沿相加的时钟延迟调节集成芯片，其特征在于，所述集成芯片包括权利要求1-9中任一项所述的基于边沿相加的时钟延迟调节电路。
PCT/CN2014/088913 2014-09-19 2014-10-20 基于边沿相加的时钟延迟调节电路及其集成芯片 WO2016041229A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/313,809 US10404243B2 (en) 2014-09-19 2014-10-20 Clock delay adjusting circuit based on edge addition and integrated chip thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410482378.XA CN104270124B (zh) 2014-09-19 2014-09-19 基于边沿相加的时钟延迟调节电路及其集成芯片
CN201410482378.X 2014-09-19

Publications (1)

Publication Number Publication Date
WO2016041229A1 true WO2016041229A1 (zh) 2016-03-24

Family

ID=52161625

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/088913 WO2016041229A1 (zh) 2014-09-19 2014-10-20 基于边沿相加的时钟延迟调节电路及其集成芯片

Country Status (3)

Country Link
US (1) US10404243B2 (zh)
CN (1) CN104270124B (zh)
WO (1) WO2016041229A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104852692B (zh) * 2015-05-28 2018-03-20 烽火通信科技股份有限公司 限幅放大装置
CN108647422B (zh) * 2018-05-03 2022-05-10 天津芯海创科技有限公司 端口时延约束方法及装置
CN111786663B (zh) * 2020-07-14 2024-05-31 京微齐力(北京)科技有限公司 一种自动调节输入延时、输出延时及输入输出延时的系统

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1192275A (zh) * 1995-08-01 1998-09-02 泰拉丁公司 低成本cmos测试仪
CN1573346A (zh) * 2003-05-09 2005-02-02 特克特朗尼克公司 超精细过采样方法和装置
CN102246415A (zh) * 2008-12-08 2011-11-16 通用电气公司 用于确定信号的频率或周期的方法
CN102420649A (zh) * 2010-06-04 2012-04-18 多伦多大学理事会 光接收机
CN103970180A (zh) * 2013-02-06 2014-08-06 辉达公司 固定频率时钟源的时钟频率调制的方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW483255B (en) * 1999-11-26 2002-04-11 Fujitsu Ltd Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission
KR100554981B1 (ko) * 2003-11-20 2006-03-03 주식회사 하이닉스반도체 지연 고정 루프
US7088163B1 (en) * 2004-09-24 2006-08-08 National Semiconductor Corporation Circuit for multiplexing a tapped differential delay line to a single output
JP2008205749A (ja) * 2007-02-19 2008-09-04 Alpine Electronics Inc パルス信号出力回路
CN101399790B (zh) * 2007-09-30 2012-05-02 华为技术有限公司 一种波形调整装置、波形划分装置及波形调整方法
CN102006033B (zh) * 2010-11-19 2012-01-18 长沙景嘉微电子有限公司 一种基于带权重延迟链的数字50%占空比调节电路
JP6107100B2 (ja) * 2012-12-10 2017-04-05 富士通株式会社 合成回路及びこれを用いた駆動装置
JP6107146B2 (ja) * 2013-01-10 2017-04-05 富士通株式会社 光受信回路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1192275A (zh) * 1995-08-01 1998-09-02 泰拉丁公司 低成本cmos测试仪
CN1573346A (zh) * 2003-05-09 2005-02-02 特克特朗尼克公司 超精细过采样方法和装置
CN102246415A (zh) * 2008-12-08 2011-11-16 通用电气公司 用于确定信号的频率或周期的方法
CN102420649A (zh) * 2010-06-04 2012-04-18 多伦多大学理事会 光接收机
CN103970180A (zh) * 2013-02-06 2014-08-06 辉达公司 固定频率时钟源的时钟频率调制的方法

Also Published As

Publication number Publication date
CN104270124B (zh) 2017-03-29
CN104270124A (zh) 2015-01-07
US10404243B2 (en) 2019-09-03
US20170214397A1 (en) 2017-07-27

Similar Documents

Publication Publication Date Title
US20110133783A1 (en) Signal interpolation methods and circuits
JP2875922B2 (ja) Ａ／ｄ変換器
WO2016041229A1 (zh) 基于边沿相加的时钟延迟调节电路及其集成芯片
CN102545806B (zh) 差动放大器
CN111295840A (zh) 用于模/数转换器的经减小噪声动态比较器
CN105306845A (zh) 一种可消除失调的相关双采样电路
CN104702289A (zh) 逐次逼近型模数转换器及其比较器输入管的电容补偿电路
JP2010258577A (ja) 補間型ａ／ｄ変換器
JP4727511B2 (ja) 高速アナログ／ディジタルコンバータ
US11362669B2 (en) Track and hold circuit
WO2024037157A1 (zh) 可调节延时电路
WO2019223561A1 (zh) 一种带电源抑制的高线性度时间放大器
CN204967796U (zh) 应用于高速模数转换器的高线性度输入信号缓冲器
TW201714402A (zh) 訊號處理電路
RU2439780C1 (ru) Каскодный дифференциальный усилитель
RU2441316C1 (ru) Дифференциальный усилитель с малым напряжением питания
RU2321158C1 (ru) Каскодный дифференциальный усилитель
RU2280318C1 (ru) Операционный усилитель
JP5667613B2 (ja) 演算増幅器及びそれを備えたパイプライン型ａ／ｄコンバータ
RU2432666C1 (ru) Дифференциальный операционный усилитель с малым напряжением питания
TWI477942B (zh) 電壓緩衝裝置
CN211123820U (zh) 一种低电源电压下的基准电路
RU2688223C1 (ru) Дифференциальный операционный усилитель
RU2673003C1 (ru) Буферный усилитель с дифференцирующей цепью коррекции переходного процесса
RU2416147C1 (ru) Дифференциальный усилитель с повышенным коэффициентом усиления

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14902215

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 15313809

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 21.09.2017)

122 Ep: pct application non-entry in european phase

Ref document number: 14902215

Country of ref document: EP

Kind code of ref document: A1