WO2024037157A1 - 可调节延时电路 - Google Patents

可调节延时电路 Download PDF

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Publication number
WO2024037157A1
WO2024037157A1 PCT/CN2023/099786 CN2023099786W WO2024037157A1 WO 2024037157 A1 WO2024037157 A1 WO 2024037157A1 CN 2023099786 W CN2023099786 W CN 2023099786W WO 2024037157 A1 WO2024037157 A1 WO 2024037157A1
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Prior art keywords
terminal
transistor
collector
module
delay
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PCT/CN2023/099786
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English (en)
French (fr)
Inventor
严波
许强
王悦
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普源精电科技股份有限公司
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Publication of WO2024037157A1 publication Critical patent/WO2024037157A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00163—Layout of the delay element using bipolar transistors
    • H03K2005/00176—Layout of the delay element using bipolar transistors using differential stages

Definitions

  • the present application belongs to the field of electronic circuit technology, and relates to, for example, an adjustable delay circuit.
  • delay circuit In circuit design or circuit application, sometimes it is necessary to delay a signal for a period of time before interacting with another signal. Generally, a delay circuit can be used. As a circuit structure that can realize the free movement of signal edges, delay circuits are widely used in a variety of clock, data, calibration and other circuits.
  • phase interpolators or delay lines. Due to structural limitations, it is difficult for these delay circuits to achieve both a large delay range and fine adjustment steps in a limited area. Opposite function.
  • the embodiment of the present application provides an adjustable delay circuit that can simultaneously achieve a large delay range and fine adjustment steps.
  • An embodiment of the present application provides an adjustable delay circuit, which includes a first adjustment module, including a first input terminal and a control output terminal.
  • the first adjustment module is configured to adjust the first input signal from the first input terminal.
  • the adjustment signal is decoded, and a control strobe signal is output from the control output terminal according to the decoding result;
  • the second adjustment module includes a second input end and a first output end, wherein the second adjustment module is configured to control the slave
  • the second adjustment signal input by the second input terminal is differentially processed, and the first pair of differential signals obtained by the differential processing is output through the first output terminal;
  • the third adjustment module includes a third input terminal and a second output terminal. , wherein the third adjustment module is configured to perform differential processing on the third adjustment signal input from the third input terminal, and output the second pair of differential signals obtained through the differential processing through the second output terminal;
  • the delay module includes: a signal input terminal, configured to receive a target differential signal pair; a strobe signal input terminal, connected to the control output terminal, configured to receive the control strobe signal; a first control terminal, configured to receive The first pair of differential signals; the second control terminal is configured to receive the second pair of differential signals; the delay module is configured to respond to the input control strobe signal, the first pair of differential signals and the The second pair of differential signals delays the target differential signal pair; the signal output terminal is set to Output the target differential signal pair delayed by the delay module.
  • Figure 1 is a schematic structural diagram of an adjustable delay circuit according to an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a delay module in an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of the first delay sub-module in an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of the second delay sub-module in an embodiment of the present application.
  • first, second, etc. in the description and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It is to be understood that the figures so used are interchangeable under appropriate circumstances so that the embodiments of the present application can be practiced in orders other than those illustrated or described herein, and that "first,” “second,” etc. are distinguished Objects are usually of one type, and the number of objects is not limited. For example, the first object can be one or multiple.
  • “and/or” in the description and claims indicates at least one of the connected objects, and the character “/" generally indicates that the related objects are in an "or” relationship.
  • FIG. 1 is a schematic structural diagram of an adjustable delay circuit according to an embodiment of the present application.
  • the circuit mainly includes:
  • a first adjustment module includes a first input terminal and a control output terminal.
  • the first adjustment module is configured to decode the first adjustment signal input from the first input terminal, and output the control signal according to the decoding result. terminal output control strobe signal.
  • the first adjustment module can output multiple control strobe signals.
  • the first adjustment module may use a decoder, and generate a control strobe signal through the decoder.
  • the first input A of the first adjustment module can be configured to receive a 3-bit first adjustment signal input by IN3, and the first adjustment module decodes according to the first adjustment signal, It can correspond to the output of 8-bit control strobe signal from the N terminal.
  • the second adjustment module includes a second input end and a first output end, wherein the second adjustment module is configured to differentially process the second adjustment signal input from the second input end, and process the differentially processed first A pair of differential signals is output through the first output terminal.
  • the first output terminal of the second adjustment module includes VOP and VON, wherein one of the first pair of differential signals passes through Through the VOP output, another differential signal is output through VON.
  • the second adjustment module can achieve a delay adjustment step with a certain accuracy.
  • this embodiment of the present application may use a 4-bit Digital to Analog Converter (DAC) as the second adjustment module, and the second adjustment signal input to the second input terminal of the second adjustment module may be a 4-bit signal.
  • DAC Digital to Analog Converter
  • the third adjustment module includes a third input terminal and a second output terminal, wherein the third adjustment module is configured to perform differential processing on the third adjustment signal input from the third input terminal, and perform differential processing on the third adjustment signal obtained by the differential processing.
  • Two pairs of differential signals are output through the second output terminal.
  • the second output terminal of the second adjustment module includes VOP and VON, wherein one differential signal in the second pair of differential signals is output through VOP, Another differential signal is output via VON.
  • the third adjustment module can achieve a delay adjustment step with a certain accuracy.
  • the embodiment of the present application may use a 10-bit digital-to-analog converter DAC as the third adjustment module, and the third adjustment signal input to the third input terminal of the third adjustment module may be a 10-bit signal.
  • the delay module may include: a signal input terminal configured to receive a target differential signal pair.
  • the signal input terminals of the delay module include VIP and VIN, which are respectively configured to receive one differential of the target differential signal pair. signal;
  • the strobe signal input terminal is connected to the control output terminal and is configured to receive the control strobe signal.
  • the strobe signal input terminal is NOE and is configured to receive the output of the first adjustment module. 8-bit control strobe signal; the first control terminal is configured to receive the first pair of differential signals.
  • the first control terminal may include 4bitDAC_VIP and 4bitDAC_VIN; the second control terminal is configured to receive the The second pair of differential signals, for example, in Figure 1, the first control terminal may include 10bitDAC_VIP and 10bitDAC_VIN; the delay module is configured to be based on the input control strobe signal, the first pair of differential signals and the The second pair of differential signals delays the target differential signal pair; the signal output terminal is configured to output the target differential signal pair delayed by the delay module.
  • the signal of the delay module The output terminals include VOP and VON, which are respectively set to output one differential signal of the target differential signal pair after delay.
  • the first adjustment module inputs a control strobe signal to the delay module according to the input first adjustment signal
  • the second adjustment module inputs a first pair of differential signals to the delay module according to the input second adjustment signal
  • the third adjustment module inputs a second pair of differential signals to the delay module according to the input third adjustment signal.
  • the delay module inputs the second pair of differential signals according to the input control strobe signal, the first pair of differential signals and the second pair of differential signals.
  • the differential signal delays the target differential signal pair, so that different levels of adjustment signals can be input through the first adjustment module, the second adjustment module and the third adjustment module, for example, coarse adjustment can be input through the first adjustment module.
  • the adjustment signal of the secondary adjustment is input through the second adjustment module
  • the fine adjustment signal is input through the third adjustment module, thereby not only expanding the delay range of the delay module, but also improving the delay accuracy of the delay module. .
  • Figure 2 shows an optional structural schematic diagram of the delay module in the embodiment of the present application.
  • the delay module mainly includes: a first delay sub-unit. module, N second delay sub-modules, a first load module and a second load module, where N is an integer greater than or equal to 1.
  • N is 7 in an exemplary manner.
  • the first control terminal includes: at least one first control sub-terminal and at least one second control sub-terminal, and the first control sub-terminal is configured to receive one of the first pair of differential signals. one differential signal, and the second control sub-terminal is configured to receive the other differential signal of the first pair of differential signals.
  • the first delay sub-module includes the signal input terminal, the second control terminal, a first differential output terminal, and a first differential output positive terminal.
  • the second control terminal may include two ports, for example, the 10bitDAC_VIP port and the 10bitDAC_VIN port in Figure 2.
  • the first differential output terminal (VOP and VON) is set to output a pair of differential signals to the first second delay sub-module,
  • the first differential output positive terminals (IOP and ION) are connected to the second differential output positive terminals of the N second delay sub-modules and then connected to the first load module.
  • each of the N second delay sub-modules includes: a second differential input terminal, a second differential output terminal, and a second differential output positive terminal.
  • the second differential output terminal of each second delay sub-module except the last second delay sub-module among the N second delay sub-modules is connected to the lower terminal of each second delay sub-module.
  • the second differential input end of a second delay sub-module is connected, and the second differential input end of the first second delay sub-module among the N second delay sub-modules is connected to the first differential output end.
  • the second differential output end of the last second delay sub-module among the N second delay sub-modules is connected to the second load module; the first differential output positive end is connected to the N second delay sub-modules.
  • the second differential output positive terminals of the second delay sub-module are connected together and then connected to the first load module.
  • the first load module includes the signal output end, that is to say, the target differential signal after delay processing is output through the first load module.
  • the first delay sub-module and one of the two adjacent second delay sub-modules among the N second delay sub-modules are also provided with There is the first control sub-terminal, and a second control sub-terminal is also provided on the other second delay sub-module of the two adjacent second delay sub-modules. That is to say, in this embodiment of the present application, one of the first pair of differential signals output by the second adjustment module can be input to the first delay sub-module and the N second delay sub-modules. From one of the two adjacent second delay sub-modules, the other differential signal can be output to the other of the two adjacent second delay sub-modules. , so that the delays of two adjacent second delay sub-modules can be interpolated.
  • the first delay sub-module includes a first control sub-terminal 4bitDAC_VI, which is configured to receive the first pair of differential One differential signal 4bitDAC_VIN in the signal
  • the first second delay sub-module includes a second control sub-terminal 4bitDAC_VI, the second control sub-terminal is configured to receive the other differential signal 4bitDAC_VIP in the first pair of differential signals
  • the second second delay sub-module includes a first control sub-terminal 4bitDAC_VI, which is configured to receive a differential signal 4bitDAC_VIN from the first pair of differential signals.
  • one strobe signal is provided on each second delay sub-module of the first delay sub-module and N second delay sub-modules.
  • Input terminal NOE the strobe signal input terminal NOE is configured to receive a control strobe signal that controls whether the corresponding delay sub-module is connected to the first control sub-terminal or the second control sub-terminal.
  • the control output terminal N of the first adjustment module outputs an 8-bit control strobe signal, of which 1 bit is input to the strobe signal input terminal of a delay sub-module to control whether the delay sub-module is connected. Enter the first control sub-terminal or the second control sub-terminal, that is, whether to access one of the first pair of differential signals.
  • the first delay sub-module may include a first buffer unit, a phase interpolation unit and a first gating unit;
  • the second delay sub-module may include: a second buffer unit and a second gating unit.
  • the input end of the first buffer unit includes the signal input end, and the output end is connected to an input end of the phase interpolation unit; an input end of the phase interpolation unit is connected to The output end of the first buffer unit is connected, and the other input end is configured to input the target differential signal pair.
  • the control end of the phase interpolation unit includes the second control end.
  • the output of the phase interpolation unit The terminal is connected to the first differential output terminal; the input terminal of the first gating unit is connected to the output terminal of the phase interpolation unit, and the control terminal of the first gating unit includes one of the gating signals.
  • Input terminal, the output terminal of the first gating unit includes the first differential output positive terminal, and the first gating unit further includes the first control sub-terminal or the second control sub-terminal.
  • the input end of the second buffer unit may include the second differential input end, and the output end of the second buffer unit is connected to the second differential output end; the second The input end of the strobe unit is connected to the output end of the second buffer unit, the control end includes one of the strobe signal input ends, and the output end of the second strobe unit includes the second differential output positive end,
  • the second gating unit further includes the first control sub-terminal or the second control sub-terminal.
  • the first buffer unit may include: a first transistor Q 1 , the base of which is connected to the first transistor Q 1 The input end of the buffer unit is connected, its collector is connected to one end of the first resistor R 1 , and its emitter is connected to the ground through the current source I 1 ; the base of the second transistor Q 2 is connected to the input end, and its collector is connected to the third One end of the second resistor R 2 has its emitter connected to the ground through the current source I 1 ; one end of the first resistor R 1 is connected to the power supply terminal VCC, and the other end is connected to the collector of the first transistor Q 1 ; the second resistor R 2 One end is connected to the power supply terminal VCC, and the other end is connected to the second transistor Q 2 Collector; the base of the third transistor Q 3 is connected to the collector of the first transistor Q 1 , its collector is connected to the power terminal VCC, and its emitter serves as an output
  • the phase interpolation unit may include: a fifth transistor Q 5 , the base of which is connected to an output end of the first buffer unit. connection, its collector is connected to one end of the third resistor R 3 , and its emitter is connected to the collector of the ninth transistor Q 9 ; the base of the sixth transistor Q 6 is connected to an output of the first buffer unit terminal is connected, its collector is connected to one end of the fourth resistor R 4 , and its emitter is connected to the collector of the ninth transistor Q 9 ; the base of the seventh transistor Q 7 is connected to the signal input terminal, and its base is connected to the signal input terminal.
  • the collector is connected to one end of the third resistor R 3 , and its emitter is connected to the collector of the thirteenth transistor Q 10 ; the base of the eighth transistor Q 8 is connected to the signal input terminal, and its collector is connected to the third transistor Q 10 .
  • One end of the four resistor R 4 has its emitter connected to the collector of the thirteenth transistor Q 10 ; the base of the ninth transistor Q 9 is connected to the third control sub-terminal and its collector is connected to the fifth transistor Q 9 respectively.
  • the emitters of transistor Q5 and the sixth transistor Q6 are grounded through the current source I4 , wherein the second control terminal includes a third control sub-terminal and a fourth control sub-terminal;
  • the base of the thirteenth transistor Q 10 is connected to the fourth control sub-terminal, and its collector is connected to the emitter of the seventh transistor Q 7 and the eighth transistor Q 8 respectively.
  • the emitter is grounded through the current source I 4 ;
  • the third resistor R 3 has one end connected to the collector of the seventh transistor Q 7 and the other end connected to the power supply terminal VCC;
  • the fourth resistor R 4 has one end connected to the eighth transistor
  • the collector of Q 8 is connected to the power supply terminal VCC on the other end.
  • the phase interpolation unit may also include an emitter follower unit.
  • the emitter follower unit may include: an eleventh transistor Q 11 , its base is connected to the collector of the seventh transistor Q 7 , its collector is connected to the power terminal VCC, and its emitter serves as the output end of the phase interpolation unit and is grounded through the current source I 5 ; the twelfth triode The base of tube Q 12 is connected to the collector of the eighth transistor Q 8 , its collector is connected to the power terminal VCC, and its emitter serves as the output terminal of the phase interpolation unit and is grounded through the current source I 6 .
  • the first gating module includes: a thirteenth transistor Q 13 , the base of which serves as an input terminal of the first gating module. , its emitter is connected to the collector of the fifteenth transistor Q 15 ; the base of the fourteenth transistor Q 14 is used as an input terminal of the first strobe module, and its emitter is connected to the fifteenth transistor Q 14
  • the collector of Q 15 ; the collector of the thirteenth transistor Q 13 and the collector of the fourteenth transistor Q 14 are used as output terminals; the base of the fifteenth transistor Q 15 is connected to The source of the Metal Oxide Semiconductor (MOS) tube NM 1 and its collector are respectively connected to the emitter of the thirteenth transistor Q 13 and the emitter of the fourteenth transistor Q 14 . Its emitter is grounded; MOS tube NM 1 has its gate connected to the strobe signal input terminal, its source to the ground and the base of transistor Q 15 , and its drain to the first control sub-terminal or
  • MOS Metal Oxide Semiconductor
  • FIG. 4 shows a schematic structural diagram of the second delay sub-module in an embodiment of the present application.
  • the buffer unit may include: a first transistor Q 1 , the base of which is connected to the input end of the second buffer unit, the collector of which is connected to one end of the first resistor R 1 , and the emitter of which is grounded through the current source I 1 ;
  • the base of transistor Q 2 is connected to the input terminal of the second buffer unit, its collector is connected to one end of second resistor R 2 , and its emitter is connected to ground through current source I 1 ;
  • one end of transistor Q 1 is connected to The power supply terminal VCC, the other end is connected to the collector of the first transistor Q 1 ;
  • the second resistor R 2 one end is connected to the power supply terminal VCC, and the other end is connected to the collector of the second transistor Q 2 ;
  • the third transistor Q 3 its base is connected to the collector of the first transistor Q 1 , its collector is connected to the power terminal VCC, and
  • the second gating unit may include: a thirteenth transistor Q 13 , the base of which serves as an input of the second gating unit. terminal, its emitter is connected to the collector of the fifteenth triode Q 15 ; the base of the fourteenth triode Q 14 is used as an input terminal of the second strobe unit, and its emitter is connected to the fifteenth triode
  • the collector of tube Q 15 ; the collector of the thirteenth triode Q 13 and the collector of the fourteenth triode Q 14 are used as output terminals; the base of the fifteenth triode Q 15 Connect the source of MOS tube NM 1 , its collector is connected to the emitter of the thirteenth triode Q 13 and the fourteenth triode Q 14 respectively, and its emitter is grounded; MOS tube NM 1. Its gate is connected to the strobe signal input terminal, its source is connected to the ground and the base of transistor Q 15 , and its drain is connected to the first control sub-terminal or the second control sub-termin
  • the delay module delays the target differential signal pair according to the input control strobe signal, the first pair of differential signals and the second pair of differential signals, and at the same time Using the first adjustment module, the second adjustment module and the third adjustment module for three-level adjustment can achieve two completely opposite functions of large delay range and fine adjustment steps at the same time, both in terms of delay range and adjustment accuracy. Has great advantages.
  • the embodiment of the present application provides yet another adjustable delay circuit, please refer to Figures 1 to 4.
  • the embodiment of the present application consists of a 10bit_DAC (10-bit digital-to-analog converter), a 4bit_DAC (4-bit digital-to-analog converter), a decoder, and a delay module.
  • the input terminal DI ⁇ 9:0> of the 10bit_DAC is used as the input terminal of the three-level adjustment IN1 ⁇ 9:0>;
  • the input terminal DI ⁇ 3:0> of the 4bit_DAC is used as the input terminal of the second-level adjustment IN2 ⁇ 3 :0> input terminal;
  • the decoder input terminal A ⁇ 2:0> is used as the input terminal of the first-level adjustment IN3 ⁇ 2:0>;
  • the differential input terminal VIP/VIN of the delay module is connected to the differential input signal VIP/ VIN, differential output terminal VOP/VON are connected to differential output signal VOP/VON.
  • the differential output terminal VOP/VON of the 10bit_DAC is connected to the 10bitDAC_VIP/10bitDAC_VIN port of the delay module;
  • the differential output terminal VOP/VON of the 4bit_DAC is connected to the 4bitDAC_VIP/4bitDAC_VIN port of the delay module;
  • the output terminal N of the decoder ⁇ 7:0> is connected to the delay module NOE ⁇ 7:0> port.
  • the delay module is composed of a first delay sub-module, seven second delay sub-modules, a first load module and a second load module.
  • the differential input terminal VIP/VIN of the first delay sub-module is connected to the external differential input signal VIP/VIN; the 10bitDAC_VIP/10bitDAC_VIN terminal of the first delay sub-module is connected to the external third-level adjustment signal 10bitDAC_VIP/10bitDAC_VIN; the first delay The 4bitDAC_VI terminal of the submodule is connected to the external 4bitDAC_VIN signal, which serves as a control terminal for the second-level adjustment; the NOE of the first delay submodule is connected to the control strobe signal NOE ⁇ 0>; the differential output terminal VOP of the first delay submodule /VON is used as a differential output terminal to output a differential signal; the IOP terminal of the first delay sub-module is connected with the IOPs of the other six second delay sub-modules and connected to the emitter of transistor Q 1 ; the first delay sub-module The ION end of the first delay sub-module is connected to the ION of the other six second delay sub-modules and connected to
  • the differential input terminal VIP/VIN of the first second delay sub-module (can be numbered B_1) is connected to the differential output terminal VIP/VIN of the first delay sub-module; the 4bitDAC_VI terminal of the second delay sub-module (B_1) is connected The external 4bitDAC_VIP signal serves as a control end for the second-level adjustment; the NOE of the second delay sub-module (B-_1) is connected to the control strobe signal NOE ⁇ 1>; the differential output of the second delay sub-module (B_1)
  • the terminal VOP/VON is used as a differential output terminal to output a differential signal.
  • the differential input terminal VIP/VIN of the second second delay sub-module (can be numbered B_2) is connected to the differential output terminal VIP/VIN of the second delay sub-module (B_1); the second delay sub-module (B_2)
  • the 4bitDAC_VI terminal is connected to the external 4bitDAC_VIN signal as a control terminal for the second-level adjustment; the NOE of the second delay sub-module (B_2) is connected to the control strobe signal NOE ⁇ 2>; the differential of the second delay sub-module (B_2)
  • the output terminal VOP/VON is used as a differential output terminal to output differential signals.
  • the differential input terminal VIP/VIN of the third second delay sub-module (can be numbered as B_3) is connected to the differential output terminal VIP/VIN of the second delay sub-module (B_2); the second delay sub-module (B_3)
  • the 4bitDAC_VI terminal is connected to the external 4bitDAC_VIP signal as a control terminal for the second-level adjustment;
  • the NOE of the second delay sub-module (B_3) is connected to the control strobe signal NOE ⁇ 3>;
  • the output terminal VOP/VON is used as a differential output terminal to output differential signals.
  • the differential input terminal VIP/VIN of the fourth second delay sub-module (can be numbered B_4) is connected to the differential output terminal VIP/VIN of the second delay sub-module (B_3); the second delay sub-module (B_4)
  • the 4bitDAC_VI terminal is connected to the external 4bitDAC_VIN signal as a control terminal for the second-level adjustment;
  • the NOE of the second delay sub-module (B_4) is connected to the control strobe signal NOE ⁇ 4>;
  • the output terminal VOP/VON is used as a differential output terminal to output differential signals.
  • the differential input terminal VIP/VIN of the fifth second delay sub-module (can be numbered B_5) is connected to the second delay sub-module.
  • the differential output terminal VIP/VIN of the time sub-module (B_4); the 4bitDAC_VI terminal of the second delay sub-module (B_5) is connected to the external 4bitDAC_VIP signal as a control terminal for the second-level adjustment;
  • the second delay sub-module (B_5 ) is connected to the control strobe signal NOE ⁇ 5>;
  • the differential output terminal VOP/VON of the second delay sub-module (B_5) is used as a differential output terminal to output a differential signal.
  • the differential input terminal VIP/VIN of the sixth second delay sub-module (can be numbered as B_6) is connected to the differential output terminal VIP/VIN of the second delay sub-module (B_5); the second delay sub-module (B_6)
  • the 4bitDAC_VI terminal is connected to the external 4bitDAC_VIN signal as a control terminal for the second-level adjustment;
  • the NOE of the second delay sub-module (B_6) is connected to the control strobe signal NOE ⁇ 6>;
  • the output terminal VOP/VON is used as a differential output terminal to output differential signals.
  • the differential input terminal VIP/VIN of the seventh second delay sub-module (can be numbered as B_7) is connected to the differential output terminal VIP/VIN of the second delay sub-module (B_6); the second delay sub-module (B_7)
  • the 4bitDAC_VI terminal is connected to the external 4bitDAC_VIP signal as a control terminal for the second-level adjustment;
  • the NOE of the second delay sub-module (B_7) is connected to the control strobe signal NOE ⁇ 7>;
  • the output terminal VOP/VON is used as a differential output terminal to output differential signals.
  • the base of the transistor Q 5 is connected to the output terminal VOP of the second delay sub-module (B_7); the base of the transistor Q 6 is connected to the second delay sub-module (B_7)
  • the output terminal VON; the emitters of Q 5 and Q 6 are connected together to the current source I 04 to ground; the collector of Q 5 is connected to the lower end of the resistor R 4 ; the collector of Q 6 is connected to the lower end of the resistor R 5 ;
  • the upper ends of R 4 and R 5 are connected to VCC at the same time.
  • the bases of transistor Q 1 and transistor Q 2 are connected together to the lower end of resistor R 3 , and the current source I 01 is connected to ground.
  • the upper end of R 3 is connected to VCC; the collector of Q 1 is connected to the lower end of resistor R 1 . ;
  • the collector of Q 2 is connected to the lower end of resistor R 2 ; the upper ends of R 1 and R 2 are connected to VCC;
  • the base of transistor Q 3 is connected to the lower end of R 1 ;
  • the collectors of transistor Q 3 and transistor Q 4 are connected Connected to VCC, the emitter of Q 4 is connected from current source I 03 to ground, while the emitters of Q 3 and Q 4 serve as the differential output VOP/VON of the circuit.
  • the first delay sub-module includes: the bases of transistors Q 1 and Q 2 are connected to the differential input terminals VIP/VIN to the external differential input signal, and the emitters of Q 1 and Q 2 Connect together to the current source I 1 to ground, the collector of Q 1 is connected to the lower end of the resistor R 1 , the collector of Q 2 is connected to the lower end of the resistor R 2 , and the upper ends of R 1 and R 2 are connected to VCC; At the same time, the lower end of R 1 is connected to the base of transistor Q 3 , the lower end of R 2 is connected to the base of transistor Q 4 , the bases of Q 3 and Q 4 are connected to VCC at the same time, and the emitter of Q 3 is connected to the current source I 2 to ground, and the emitter of Q 4 is connected to current source I 3 to ground.
  • the base of transistor Q 5 is connected to the emitter of Q 3 , the base of transistor Q 6 is connected to the emitter of Q 4 , the emitters of Q 5 and Q 6 are connected together to the collector of transistor Q 9 ;
  • Q 5 The collector of Q 6 is connected to the collector of triode Q 7 and connected to the lower end of resistor R 3 ; the collector of Q 6 is connected to the collector of triode Q 7 and connected to the lower end of resistor R 4 ;
  • the upper ends of R 3 and R 4 are connected to VCC; the bases of Q 8 and Q 7 are connected to the differential input terminal VIP/VIN to the external differential input signal, and the emitters of Q 7 and Q 8 are connected together to The collector of transistor Q 10 ;
  • the bases of Q 10 and Q 9 are connected to the external first-stage adjustment signal 10bitDAC_VIP/10bitDAC_VIN; the emitters of Q 9 and Q 10 are connected together to the current source I 4 to ground;
  • the transistor Q The base of 11 is connected to the lower end of R 3 ,
  • the base of transistor Q 13 is connected to the emitter of Q 11 , the base of transistor Q 14 is connected to the emitter of Q 12 , the emitters of Q 13 and Q 14 are connected together to the collector of transistor Q 15 , Q 14 and
  • the collector of Q 13 is used as the current differential output terminal IOP/ION of the circuit to output a current differential signal;
  • the base of Q 15 is connected to the source of NMOS tube NM1, and the emitter of Q 15 is used as the current output terminal IF;
  • the gate of NM1 is used as the selector
  • the pass control NOE is connected to the external strobe signal, and the drain end of NM 1 is used as one end of the second-level adjustment signal 4bitDAC_VI, which is connected to the external signal.
  • the second delay sub-module includes: the bases of transistor Q1 and transistor Q2 are connected to the differential input terminal VIP/VIN to the external differential input signal, and the emitters of Q1 and Q2 are connected to the differential input terminal VIP/VIN.
  • the collector of Q 1 is connected to the lower end of the resistor R 1
  • the collector of Q 2 is connected to the lower end of the resistor R 2
  • the upper ends of R 1 and R 2 are connected to VCC;
  • the lower end of R 1 is connected to the base of transistor Q 3
  • the lower end of R 2 is connected to the base of transistor Q 4
  • the bases of Q 3 and Q 4 are connected to VCC at the same time
  • the emitter of Q 3 is connected to the current source I 2 to ground
  • the emitter of Q 4 is connected to current source I 3 to ground.
  • the emitters of Q 3 and Q 4 serve as the voltage differential output terminal VOP/VON of the circuit to output a voltage differential signal.
  • the base of transistor Q 13 is connected to the emitter of Q 3 , the base of transistor Q 14 is connected to the emitter of Q 4 , the emitters of Q 13 and Q 14 are connected together to the collector of transistor Q 15 , Q 14 and
  • the collector of Q 13 is used as the current differential output terminal IOP/ION of the circuit to output a current differential signal;
  • the base of Q 15 is connected to the source of NMOS tube NM 1 , and the emitter of Q 15 is used as the current output terminal IF;
  • the gate of NM 1 As the strobe control NOE, it is connected to the external strobe signal, and the drain end of NM 1 is used as one end of the second-level adjustment signal 4bitDAC_VI, which is connected to the external signal.
  • a first delay sub-module can provide a fixed delay X (different processes have different values of X), and each second delay sub-module can provide a fixed delay Y (different values process, the value of Y is different), therefore the maximum delay range of the circuit structure of this embodiment is approximately Delay range;
  • two adjacent second delay sub-modules are gated among the seven second delay sub-modules, so the accuracy of the first-level adjustment is Y; again, in the two gated
  • the adjacent second delay sub-module performs phase interpolation, and its adjustment accuracy is (The accuracy is determined by the 4-bit DAC, and bits can be added or subtracted according to actual needs), thereby achieving the second level of adjustment;
  • the first delay sub-module is a phase interpolator module, and its adjustment accuracy is (The accuracy is determined by the 10-bit DAC, and bits can be added or subtracted according to actual needs).
  • the value of X is generally about 2 times that of Y. From this rough estimate, Than Small 32 times, that is, the adjustment accuracy of the third pole is 32 times higher than that of the second level, thereby achieving high-precision adjustment; therefore, the circuit structure of this embodiment can achieve an adjustment range of X+7Y, Precision three-pole adjustment, Second-level adjustment of accuracy, first-level adjustment of Y accuracy.
  • the delay circuit has a three-level adjustment function.
  • the first level adjustment is first used to perform a rough adjustment, and the adjacent control strobe signal is gated through the control gating signal output by the first adjustment module.
  • the two second delay sub-modules perform a secondary adjustment using the second-level adjustment, and control whether the two gated second delay sub-modules are connected to the first control according to the second adjustment signal input by the second adjustment module.
  • the sub-terminal or the second control sub-terminal realizes interpolation of the delays of two adjacent second delay sub-modules to achieve secondary adjustment.
  • the third-level adjustment is used to perform a fine adjustment and is output through the third scheduling module.
  • the second pair of differential signals controls whether the first delay sub-module is connected to the first control sub-terminal or the second control sub-terminal to interpolate the delay of the first delay sub-module to achieve fine adjustment. Therefore, It can achieve two contradictory indicators of large delay range and fine adjustment at the same time.
  • the decoder only gates two adjacent delay sub-modules, such as the second delay sub-module B_1 and the second delay sub-module B_2, or the second delay sub-module B_6 and the second delay sub-module B_7 , thus performing a rough adjustment of the delay.
  • the adjusted delay accuracy is equivalent to the delay of a Current Mode logic (CML) buffer.
  • CML Current Mode logic
  • the delay of a CML buffer is T; the first level After the adjustment is set, use these two gated modules to perform a 4-bit precision phase interpolation.
  • the adjustment accuracy is equivalent to From this, the second level of adjustment is carried out; finally, the third level of fine adjustment is carried out, and the adjustment accuracy is equivalent to
  • the maximum delay range of the embodiment of this application is approximately: T ⁇ 10; the minimum adjustment accuracy is approximately:
  • adjustable delay circuit provided by the embodiment of the present application can perform the above three levels of delay adjustment, in application, one or two levels of delay can also be achieved through the adjustable delay circuit.
  • time adjustment For example, delay adjustment with a narrow range but high accuracy can be achieved through the above-mentioned adjustable delay circuit.
  • a fixed high level can be input at the input terminals of the first adjustment module and the second adjustment module, and a fixed high level can be input at the input terminals of the third scheduling module. The input terminal inputs the corresponding adjustment signal, so that the delay only needs to be performed through the first delay sub-module in the delay module to achieve fine adjustment of the delay.
  • the above-mentioned adjustable delay circuit can also be used to achieve delay adjustment with a wide range but slightly lower accuracy.
  • a fixed high level can be input at the input end of the third adjustment module, and a fixed high level can be input at the input end of the first adjustment module.
  • the input end of the first adjustment signal and the second adjustment module inputs the second adjustment signal, so that the delay module can delay according to the first adjustment signal and the second adjustment signal to achieve secondary adjustment of the delay.
  • the adjustable delay circuit in this application uses the first adjustment module, the second adjustment module and the third adjustment module to perform three-level adjustments, thereby enabling multi-level adjustment of the delay to meet the requirements on the delay range and adjustment accuracy. need.

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Abstract

一种可调节延时电路。所述电路包括：第一调节模块，包括第一输入端和控制输出端；第二调节模块，包括第二输入端和第一输出端；第三调节模块，包括第三输入端和第二输出端；延时模块，包括：信号输入端，设置为接收目标差分信号对；选通信号输入端，与所述控制输出端连接，设置为接收所述控制选通信号；第一控制端，设置为接收所述第一对差分信号；第二控制端，设置为接收所述第二对差分信号；所述延时模块设置为根据输入的所述控制选通信号、所述第一对差分信号和所述第二对差分信号对所述目标差分信号对进行延时；信号输出端，设置为输出经所述延时模块延时后的目标差分信号对。

Description

可调节延时电路
本申请要求在2022年08月19日提交中国专利局、申请号为202211003512.4的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请属于电子电路技术领域，例如涉及一种可调节延时电路。
背景技术
在电路设计或电路应用中，有时需要把一个信号延迟一段时间再和另一个信号作用，一般可以采用延时电路。延时电路作为一种可实现信号边沿自由移动的电路结构，广泛的应用于多种时钟、数据、校准等电路。
延时电路最常用的实现方式是相位内插器或者延时线，由于结构的限制，这些延时电路很难在有限的面积下同时实现大的延时范围和精细的调节步进两个截然相反的功能。
发明内容
本申请实施例提供了一种可调节延时电路，能够同时实现大的延时范围和精细的调节步进。
本申请实施例提供了一种可调节延时电路，包括第一调节模块，包括第一输入端和控制输出端，所述第一调节模块设置为对从所述第一输入端输入的第一调节信号进行译码，根据译码结果从所述控制输出端输出控制选通信号；第二调节模块，包括第二输入端和第一输出端，其中，所述第二调节模块设置为对从所述第二输入端输入的第二调节信号进行差分处理，将差分处理得到的第一对差分信号通过所述第一输出端输出；第三调节模块，包括第三输入端和第二输出端，其中，所述第三调节模块设置为对从所述第三输入端输入的第三调节信号进行差分处理，将差分处理得到的第二对差分信号通过所述第二输出端输出；
延时模块，包括：信号输入端，设置为接收目标差分信号对；选通信号输入端，与所述控制输出端连接，设置为接收所述控制选通信号；第一控制端，设置为接收所述第一对差分信号；第二控制端，设置为接收所述第二对差分信号；所述延时模块设置为根据输入的所述控制选通信号、所述第一对差分信号和所述第二对差分信号对所述目标差分信号对进行延时；信号输出端，设置为 输出经所述延时模块延时后的目标差分信号对。
附图说明
图1为本申请中一个实施例可调节延时电路的结构示意图；
图2为本申请一个实施例中延时模块的结构示意图；
图3为本申请一个实施例中第一延时子模块的结构示意图；
图4为本申请一个实施例中第二延时子模块的结构示意图。
具体实施方式
下面将结合本申请实施例及相应的附图对本申请技术方案进行描述。显然，所描述的实施例仅是本申请一部分实施例。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
以下结合附图，说明本申请多个实施例提供的技术方案。
本申请实施例提供了一种可调节延时电路，如图1所示。图1为本申请中一个实施例可调节延时电路的结构示意图，所述电路主要包括：
第一调节模块，包括第一输入端和控制输出端，所述第一调节模块设置为对从所述第一输入端输入的第一调节信号进行译码，根据译码结果从所述控制输出端输出控制选通信号。在本申请实施例中，根据延时电路的实际需求，所述第一调节模块可以输出多路控制选通信号。示意性的，本申请实施例中第一调节模块可以采用译码器，通过译码器产生控制选通信号。例如，在图1中，第一调节模块的第一输入端A可以设置为接收IN3输入的一个3比特(bit的)第一调节信号，第一调节模块根据该第一调节信号进行译码，可以对应从N端输出8bit的控制选通信号。
第二调节模块，包括第二输入端和第一输出端，其中，所述第二调节模块设置为对从所述第二输入端输入的第二调节信号进行差分处理，将差分处理得到的第一对差分信号通过所述第一输出端输出，例如，在图1中，第二调节模块的第一输出端包括VOP和VON，其中，第一对差分信号中的一个差分信号通 过VOP输出，另一个差分信号通过VON输出。在本申请实施例中，根据延时电路的实际需求，所述第二调节模块可以实现一定精度的延时调节步长。例如，本申请实施例可以采用4位的数字模拟转换器(Digital to Analog Converter，DAC)作为第二调节模块，第二调节模块的第二输入端输入的第二调节信号可以为4bit的信号。
第三调节模块，包括第三输入端和第二输出端，其中，所述第三调节模块设置为对从所述第三输入端输入的第三调节信号进行差分处理，将差分处理得到的第二对差分信号通过所述第二输出端输出，例如，在图1中，第二调节模块的第二输出端包括VOP和VON，其中，第二对差分信号中的一个差分信号通过VOP输出，另一个差分信号通过VON输出。在本申请实施例中，根据延时电路的实际需求，所述第三调节模块可以实现一定精度的延时调节步长。例如，本申请实施例可以采用10位的数字模拟转换器DAC作为第三调节模块，第三调节模块的第三输入端输入的第三调节信号可以为10bit的信号。
延时模块，可以包括：信号输入端，设置为接收目标差分信号对，例如，在图1中，延时模块的信号输入端包括VIP和VIN，分别设置为接收目标差分信号对中的一个差分信号；选通信号输入端，与所述控制输出端连接，设置为接收所述控制选通信号，例如，在图1中，选通信号输入端为NOE，设置为接收第一调节模块输出的8bit的控制选通信号；第一控制端，设置为接收所述第一对差分信号，例如，在图1中，第一控制端可以包括4bitDAC_VIP和4bitDAC_VIN；第二控制端，设置为接收所述第二对差分信号，例如，在图1中，第一控制端可以包括10bitDAC_VIP和10bitDAC_VIN；所述延时模块设置为根据输入的所述控制选通信号、所述第一对差分信号和所述第二对差分信号对所述目标差分信号对进行延时；信号输出端，设置为输出经所述延时模块延时后的目标差分信号对，例如，在图1中，延时模块的信号输出端包括VOP和VON，分别设置为输出延时后的目标差分信号对中的一个差分信号。
在本申请实施例中，第一调节模块根据输入的第一调节信号向延时模块输入控制选通信号，第二调节模块根据输入的第二调节信号向延时模块输入第一对差分信号，第三调节模块根据输入的第三调节信号向延时模块输入第二对差分信号，所述延时模块根据输入的所述控制选通信号、所述第一对差分信号和所述第二对差分信号对所述目标差分信号对进行延时，从而使得可以通过第一调节模块、第二调节模块和第三调节模块，输入不同的级别的调节信号，例如，通过第一调节模块输入粗调的调节信号，通过第二调节模块输入次调的调节信号，通过第三调节模块输入精调的调节信号，从而既可以扩大延时模块的延时范围，又可以提高延时模块的延时精度。
图2示出了本申请实施例中的延时模块的一种可选结构示意图，如图2所示，在该可选的实现方式中，所述延时模块主要包括：第一延时子模块、N个第二延时子模块、第一负载模块和第二负载模块，其中，N为大于等于1的整数，例如，在图2中，示例性的，N为7。
在该可能的实现方式中，所述第一控制端包括：至少一个第一控制子端和至少一个第二控制子端，所述第一控制子端设置为接收所述第一对差分信号中的一个差分信号，第二控制子端设置为接收所述第一对差分信号中的另一个差分信号。
该可能的实现方式中，所述第一延时子模块包括所述信号输入端、所述第二控制端、第一差分输出端、以及第一差分输出正端。第二控制端可以包括两个端口，例如，图2中的10bitDAC_VIP端口和10bitDAC_VIN端口，第一差分输出端(VOP和VON)设置为向第一个第二延时子模块输出一对差分信号，而第一差分输出正端(IOP和ION)与N个第二延时子模块的第二差分输出正端连接后与第一负载模块连接。
在本申请实施例中，N个所述第二延时子模块中的每个所述第二延时子模块包括：第二差分输入端、第二差分输出端以及第二差分输出正端。，N个所述第二延时子模块中除最后一个第二延时子模块中的每个第二延时子模块的第二差分输出端与所述每个第二延时子模块的下一个第二延时子模块的第二差分输入端连接，N个所述第二延时子模块中的第一个第二延时子模块的第二差分输入端与所述第一差分输出端连接，N个所述第二延时子模块中的最后一个第二延时子模块的第二差分输出端与所述第二负载模块连接；所述第一差分输出正端与N个所述第二延时子模块的第二差分输出正端连接在一起后与所述第一负载模块连接。
在本申请实施例中，所述第一负载模块包括所述信号输出端，也就是说，延时处理后的目标差分信号通过第一负载模块输出。
在本申请实施例中，所述第一延时子模块和N个所述第二延时子模块中相邻的两个第二延时子模块中一个第二延时子模块上还均设置有所述第一控制子端，相邻的两个第二延时子模块中的另一个第二延时子模块上还设置第二控制子端。也就是说，在本申请实施例中，第二调节模块输出的第一对差分信号中的一个差分信号可以输入到所述第一延时子模块和N个所述第二延时子模块中相邻的两个第二延时子模块中的其中一个第二延时子模块，另一个差分信号可以输出到相邻的两个第二延时子模块中的另一个第二延时子模块，从而可以对两个相邻的第二延时子模块的延时进行插值。例如，在图2中，第一延时子模块包括一个第一控制子端4bitDAC_VI，该第一控制子端设置为接收第一对差分 信号中的一个差分信号4bitDAC_VIN，而第一个第二延时子模块包括一个第二控制子端4bitDAC_VI，该第二控制子端设置为接收第一对差分信号中的另一个差分信号4bitDAC_VIP，而第二个第二延时子模块包括一个第一控制子端4bitDAC_VI，该第一控制子端设置为接收第一对差分信号中的一个差分信号4bitDAC_VIN。
在本申请实施例中，如图2所示，所述第一延时子模块和N个所述第二延时子模块中每个第二延时子模块上均设置一个所述选通信号输入端NOE，所述选通信号输入端NOE设置为接收控制对应的延时子模块是否接入所述第一控制子端或所述第二控制子端的控制选通信号。例如，在图2中，第一调节模块的控制输出端N输出8bit的控制选通信号，其中1bit输入到一个延时子模块的选通信号输入端，用于控制该延时子模块是否接入所述第一控制子端或所述第二控制子端，即是否接入第一对差分信号中的一个差分信号。
在本申请实施例的一个可能的实现方式中，如图3和4所示，所述第一延时子模块可以包括第一缓冲单元、相位内插单元和第一选通单元；所述第二延时子模块可以包括：第二缓冲单元和第二选通单元。
在上述可能的实现方式中，所述第一缓冲单元的输入端包括所述信号输入端，输出端与所述相位内插单元的一个输入端连接；所述相位内插单元的一输入端与所述第一缓冲单元的输出端连接，另一个输入端设置为输入所述目标差分信号对，所述相位内插单元的控制端包括所述第二控制端，所述相位内插单元的输出端与所述第一差分输出端连接；所述第一选通单元的输入端与所述相位内插单元的输出端连接，所述第一选通单元的控制端包括一个所述选通信号输入端，所述第一选通单元的输出端包括所述第一差分输出正端，所述第一选通单元上还包括所述第一控制子端或所述第二控制子端。
在上述可能的实现方式中，所述第二缓冲单元的输入端可以包括所述第二差分输入端，所述第二缓冲单元的输出端与所述第二差分输出端连接；所述第二选通单元的输入端与所述第二缓冲单元的输出端连接，控制端包括一个所述选通信号输入端，所述第二选通单元的输出端包括所述第二差分输出正端，所述第二选通单元上还包括所述第一控制子端或所述第二控制子端。
图3示出了本申请一个实施例中第一延时子模块的结构示意图，如图3所示，所述第一缓冲单元可以包括：第一三极管Q1，其基极与第一缓冲单元的输入端连接，其集电极接第一电阻R1的一端，其发射极通过电流源I1接地；第二三极管Q2，其基极与输入端连接，其集电极接第二电阻R2的一端，其发射极通过电流源I1接地；第一电阻R1，其一端接电源端VCC，另一端接第一三极管Q1的集电极；第二电阻R2，其一端接电源端VCC，另一端接第二三极管Q2的 集电极；第三三极管Q3，其基极接所述第一三极管Q1的集电极，其集电极接电源端VCC，其发射极作为第一缓冲单元的一个输出端并通过电流源I2接地；第四三极管Q4，其基极接所述第二三极管Q2的集电极，其集电极接电源端VCC，其发射极作为第一缓冲单元的一个输出端并通过电流源I3接地。
在本申请实施例一种可能的实现方式中，如图3所示，所述相位内插单元可以包括：第五三极管Q5，其基极与所述第一缓冲单元的一个输出端连接，其集电极接第三电阻R3的一端，其发射极接第九三极管Q9的集电极；第六三极管Q6，其基极与所述第一缓冲单元的一个输出端连接，其集电极接第四电阻R4的一端，其发射极接第九三极管Q9的集电极；第七三极管Q7，其基极与所述信号输入端连接，其集电极接第三电阻R3的一端，其发射极接第十三极管Q10的集电极；第八三极管Q8，其基极与所述信号输入端连接，其集电极接第四电阻R4的一端，其发射极接第十三极管Q10的集电极；第九三极管Q9，其基极与第三控制子端连接，其集电极分别接所述第五三极管Q5和所述第六三极管Q6的发射极，其发射极通过电流源I4接地，其中，所述第二控制端包括第三控制子端和第四控制子端；第十三极管Q10，其基极与所述第四控制子端连接，其集电极分别接所述第七三极管Q7和所述第八三极管Q8的发射极，其发射极通过电流源I4接地；第三电阻R3，其一端接第七三极管Q7的集电极，另一端接电源端VCC；第四电阻R4，其一端接第八三极管Q8的集电极，另一端接电源端VCC。
在本申请实施例一种可能的实现方式中，所述相位内插单元还可以包括射极跟随单元，如图3所示，所述射极跟随单元可以包括：第十一三极管Q11，其基极接所述第七三极管Q7的集电极，其集电极接电源端VCC，其发射极作为相位内插单元的输出端并通过电流源I5接地；第十二三极管Q12，其基极接所述第八三极管Q8的集电极，其集电极接电源端VCC，其发射极作为相位内插单元的输出端并通过电流源I6接地。
在本申请实施例一种可能的实现方式中，如图3所示，所述第一选通模块包括：第十三三极管Q13，其基极作为第一选通模块的一输入端，其发射极接第十五三极管Q15的集电极；第十四三极管Q14，其基极作为第一选通模块的一输入端，其发射极接第十五三极管Q15的集电极；所述第十三三极管Q13的集电极和所述第十四三极管Q14的集电极作为输出端；第十五三极管Q15，其基极接金属氧化物半导体(Metal Oxide Semiconductor，MOS)管NM1的源极，其集电极分别与所述第十三三极管Q13的发射极和第十四三极管Q14的发射极连接，其发射极接地；MOS管NM1，其栅极与所述选通信号输入端连接，其源极接地十五三极管Q15的基极，其漏极与所述第一控制子端或所述第二控制子端连接。
图4示出了本申请一个实施例中第二延时子模块的结构示意图，所述第二 缓冲单元可以包括：第一三极管Q1，其基极与第二缓冲单元的输入端连接，其集电极接第一电阻R1的一端，其发射极通过电流源I1接地；第二三极管Q2，其基极与第二缓冲单元的输入端连接，其集电极接第二电阻R2的一端，其发射极通过电流源I1接地；第一电阻R1，其一端接电源端VCC，另一端接第一三极管Q1的集电极；第二电阻R2，其一端接电源端VCC，另一端接第二三极管Q2的集电极；第三三极管Q3，其基极接所述第一三极管Q1的集电极，其集电极接电源端VCC，其发射极作为第二缓冲单元的一个输出端并通过电流源I2接地；第四三极管Q4，其基极接所述第二三极管Q2的集电极，其集电极接电源端VCC，其发射极作为第二缓冲单元的一个输出端并通过电流源I3接地。
在本申请实施例一种可能的实现方式中，如图4所示，所述第二选通单元可以包括：第十三三极管Q13，其基极作为第二选通单元的一输入端，其发射极接第十五三极管Q15的集电极；第十四三极管Q14，其基极作为第二选通单元的一输入端，其发射极接第十五三极管Q15的集电极；所述第十三三极管Q13的集电极和所述第十四三极管Q14的集电极作为输出端；第十五三极管Q15，其基极接MOS管NM1的源极，其集电极与分别与所述第十三三极管Q13的发射极和第十四三极管Q14的发射极连接，其发射极接地；MOS管NM1，其栅极与所述选通信号输入端连接，其源极接地十五三极管Q15的基极，其漏极与所述第一控制子端或所述第二控制子端连接。
在本申请实施例中，通过所述延时模块根据输入的所述控制选通信号、所述第一对差分信号和所述第二对差分信号对所述目标差分信号对进行延时，同时采用第一调节模块、第二调节模块和第三调节模块进行三级调节，可同时实现大的延时范围和精细的调节步进两个截然相反的功能，在延时范围和调节精度上都具有很大优势。
本申请实施例提供了又一种可调节延时电路，可以参考图1至图4。本申请实施例由10bit_DAC(10位的数字模拟转换器)、4bit_DAC(4位的数字模拟转换器)、译码器和延时模块构成。
在本申请实施例中，10bit_DAC的输入端DI<9:0>作为三级调节的IN1<9:0>的输入端；4bit_DAC的输入端DI<3:0>作为二级调节的IN2<3:0>的输入端；译码器的输入端A<2:0>作为一级调节的IN3<2:0>的输入端；延时模块的差分输入端VIP/VIN接差分输入信号VIP/VIN，差分输出端VOP/VON接差分输出信号VOP/VON。
在本申请实施例中，10bit_DAC的差分输出端VOP/VON接延时模块的10bitDAC_VIP/10bitDAC_VIN端口；4bit_DAC的差分输出端VOP/VON接延时模块的4bitDAC_VIP/4bitDAC_VIN端口；译码器的输出端N<7:0>接延时模块的 NOE<7:0>端口。
在本申请实施例中，所述延时模块由一个第一延时子模块、7个第二延时子模块、第一负载模块和第二负载模块组成。
第一延时子模块的差分输入端VIP/VIN接外部的差分输入信号VIP/VIN；第一延时子模块的10bitDAC_VIP/10bitDAC_VIN端接外部的第三级调节信号10bitDAC_VIP/10bitDAC_VIN；第一延时子模块的4bitDAC_VI端接外部的4bitDAC_VIN信号，作为第二级调节的一个控制端；第一延时子模块的NOE接控制选通信号NOE<0>；第一延时子模块的差分输出端VOP/VON作为差分输出端输出差分信号；第一延时子模块的IOP端同其他6个第二延时子模块的IOP连在一起，并接三极管Q1的发射极；第一延时子模块的ION端同其他6个第二延时子模块的ION连在一起，并接三极管Q2的发射极；第一延时子模块的IF端同其他6个第二延时子模块的IF连在一起，并接电流源I5到地。
第一个第二延时子模块(可编号为B_1)的差分输入端VIP/VIN接第一延时子模块的差分输出端VIP/VIN；第二延时子模块(B_1)的4bitDAC_VI端接外部的4bitDAC_VIP信号，作为第二级调节的一个控制端；第二延时子模块(B-_1)的NOE接控制选通信号NOE<1>；第二延时子模块(B_1)的差分输出端VOP/VON作为差分输出端输出差分信号。
第二个第二延时子模块(可编号为B_2)的差分输入端VIP/VIN接第二延时子模块(B_1)的差分输出端VIP/VIN；第二延时子模块(B_2)的4bitDAC_VI端接外部的4bitDAC_VIN信号，作为第二级调节的一个控制端；第二延时子模块(B_2)的NOE接控制选通信号NOE<2>；第二延时子模块(B_2)的差分输出端VOP/VON作为差分输出端输出差分信号。
第三个第二延时子模块(可编号为B_3)的差分输入端VIP/VIN接第二延时子模块(B_2)的差分输出端VIP/VIN；第二延时子模块(B_3)的4bitDAC_VI端接外部的4bitDAC_VIP信号，作为第二级调节的一个控制端；第二延时子模块(B_3)的NOE接控制选通信号NOE<3>；第二延时子模块(B_3)的差分输出端VOP/VON作为差分输出端输出差分信号。
第四个第二延时子模块(可编号为B_4)的差分输入端VIP/VIN接第二延时子模块(B_3)的差分输出端VIP/VIN；第二延时子模块(B_4)的4bitDAC_VI端接外部的4bitDAC_VIN信号，作为第二级调节的一个控制端；第二延时子模块(B_4)的NOE接控制选通信号NOE<4>；第二延时子模块(B_4)的差分输出端VOP/VON作为差分输出端输出差分信号。
第五个第二延时子模块(可编号为B_5)的差分输入端VIP/VIN接第二延 时子模块(B_4)的差分输出端VIP/VIN；第二延时子模块(B_5)的4bitDAC_VI端接外部的4bitDAC_VIP信号，作为第二级调节的一个控制端；第二延时子模块(B_5)的NOE接控制选通信号NOE<5>；第二延时子模块(B_5)的差分输出端VOP/VON作为差分输出端输出差分信号。
第六个第二延时子模块(可编号为B_6)的差分输入端VIP/VIN接第二延时子模块(B_5)的差分输出端VIP/VIN；第二延时子模块(B_6)的4bitDAC_VI端接外部的4bitDAC_VIN信号，作为第二级调节的一个控制端；第二延时子模块(B_6)的NOE接控制选通信号NOE<6>；第二延时子模块(B_6)的差分输出端VOP/VON作为差分输出端输出差分信号。
第七个第二延时子模块(可编号为B_7)的差分输入端VIP/VIN接第二延时子模块(B_6)的差分输出端VIP/VIN；第二延时子模块(B_7)的4bitDAC_VI端接外部的4bitDAC_VIP信号，作为第二级调节的一个控制端；第二延时子模块(B_7)的NOE接控制选通信号NOE<7>；第二延时子模块(B_5)的差分输出端VOP/VON作为差分输出端输出差分信号。
作为第二延时子模块(B_7)的负载，三极管Q5的基极接第二延时子模块(B_7)的输出端VOP；三极管Q6的基极第二接延时子模块(B_7)的输出端VON；Q5和Q6的发射极连在一起接到电流源I04到地；Q5的集电极接到电阻R4的下端；Q6的集电极接到电阻R5的下端；R4和R5的上端同时连接到VCC。
三极管Q1和三极管Q2的基极连在一起接到电阻R3的下端，同时连接电流源I01到地，R3的上端接到VCC；Q1的集电极接到电阻R1的下端；Q2的集电极接到电阻R2的下端；R1和R2的上端接到VCC；三极管Q3的基极接到R1的下端；三极管Q3和三极管Q4的集电极连都接到VCC，Q4的发射极连接到电流源I03到地，同时Q3和Q4的发射极作为电路的差分输出端VOP/VON。
在本申请实施例中，所述第一延时子模块包括：三极管Q1和三极管Q2的基极连接差分输入端VIP/VIN接到外部的差分输入信号，Q1和Q2的发射极连到一起接到电流源I1到地，Q1的集电极接到电阻R1的下端，Q2的集电极接到电阻R2的下端，R1和R2的上端都接到VCC；同时R1的下端接到三极管Q3的基极，R2的下端接到三极管Q4的基极，Q3和Q4的基极同时连接到VCC，Q3的发射极接到电流源I2到地，Q4的发射极接到电流源I3到地。
三极管Q5的基极接到Q3的发射极，三极管Q6的基极接到Q4的发射极，Q5和Q6的发射极连到一起接到三极管Q9的集电极；Q5的集电极和三级管Q7的集电极连在一起，接到电阻R3的下端；Q6的集电极和三级管Q7的集电极连在一起，接到电阻R4的下端；R3和R4的上端都接到VCC；Q8和Q7的基极连接差分输入端VIP/VIN接到外部的差分输入信号，Q7和Q8的发射极连在一起接到 三极管Q10的集电极；Q10和Q9的基极连接到外部的第一级调节信号10bitDAC_VIP/10bitDAC_VIN；Q9和Q10的发射极连在一起接到电流源I4到地；三极管Q11的基极接到R3的下端，三极管Q12的基极接到R4的下端，Q11和Q12的集电极都接到VCC，Q11的发射极接到电流源I5到地，Q12的发射极接到电流源I6到地，同时Q11和Q12的发射极作为电路的电压差分输出端VOP/VON输出电压差分信号。
三极管Q13的基极接到Q11的发射极，三极管Q14的基极接到Q12的发射极，Q13和Q14的发射极连一起接到三极管Q15的集电极，Q14和Q13的集电极作为电路的电流差分输出端IOP/ION输出电流差分信号；Q15的基极接NMOS管NM1的源极，Q15的发射极作为电流输出端IF；NM1的栅极作为选通控制NOE接外部选通信号，NM1的漏端作为第二级调节信号的一端4bitDAC_VI，接外部信号。
在本申请实施例中，所述第二延时子模块包括：三极管Q1和三极管Q2的基极连接差分输入端VIP/VIN接到外部的差分输入信号，Q1和Q2的发射极连到一起接到电流源I1到地，Q1的集电极接到电阻R1的下端，Q2的集电极接到电阻R2的下端，R1和R2的上端都接到VCC；同时R1的下端接到三极管Q3的基极，R2的下端接到三极管Q4的基极，Q3和Q4的基极同时连接到VCC，Q3的发射极接到电流源I2到地，Q4的发射极接到电流源I3到地。同时Q3和Q4的发射极作为电路的电压差分输出端VOP/VON输出电压差分信号。
三极管Q13的基极接到Q3的发射极，三极管Q14的基极接到Q4的发射极，Q13和Q14的发射极连一起接到三极管Q15的集电极，Q14和Q13的集电极作为电路的电流差分输出端IOP/ION输出电流差分信号；Q15的基极接NMOS管NM1的源极，Q15的发射极作为电流输出端IF；NM1的栅极作为选通控制NOE接外部选通信号，NM1的漏端作为第二级调节信号的一端4bitDAC_VI，接外部信号。
在本申请实施例中，首先，一个第一延时子模块可提供一个固定延时X(不同工艺，X的值不同)，每一个第二延时子模块可提供一个固定延时Y(不同工艺，Y的值不同)，由此本实施例电路结构的最大延时范围约为X+7Y；此外，还可根据需求适当增加或删减第二延时子模块的个数，实现宽的延时范围；其次，根据延时需要在7个第二延时子模块中选通两个相邻的第二延时子模块，因此一级调节的精度为Y；再次，在选通的两个相邻的第二延时子模块进行相位内插，其调节精度为(其精度由4bit DAC决定，可根据实际需求进行bit位的加减)，由此实现第二级调节；最后，第一延时子模块是一个相位内插器模块，其调节精度为(其精度由10bit DAC决定，可根据实际需求进行bit位的加减)，X的值一般是Y的2倍左右，由此粗略估计，要比小32 倍，也就是第三极调节的精度比第二级高32倍，由此实现高精度调节；因此，本实施例电路结构可实现X+7Y的调节范围，精度的三极调节，精度的二级调节，Y精度的一级调节。
在本申请实施例中，所述延时电路具有三级调节的功能，在使用时首先使用第一级调节进行一个粗调，通过第一调节模块输出的控制选通信号，选通相邻的两个第二延时子模块，在使用第二级调节进行一个次调，根据第二调节模块输入的第二调节信号，控制两个选通的第二延时子模块是否接入第一控制子端或第二控制子端，实现对两个相邻的第二延时子模块的延时进行插值，从而实现次调，最后使用第三级调节进行一个精调，通过第三调度模块输出的第二对差分信号，控制第一延时子模块是否接入第一控制子端或第二控制子端，实现对第一延时子模块的延时进行插值，从而实现精调，因此，可同时实现大的延时范围和精细的调节两个矛盾的指标。译码器只选通相邻的两个延时子模块，例如第二延时子模块B_1和第二延时子模块B_2，又或者第二延时子模块B_6和第二延时子模块B_7，由此进行延时的粗调，调节的延时精度相当于1个电流模式逻辑(Current Mode logic，CML)缓冲器的延时，若1个CML缓冲器的延时为T；第一级调节设置好后，用这两个选通的模块进行一个4bit精度的相位内插，调节精度相当于由此进行第二级调节；最后在进行第三级精调，调节精度相当于本申请实施例最大的延时范围约为：T×10；最小调节精度约为：
需要说明的是，虽然本申请实施例提供的可调节延时电路可以进行以上三级的延时调节，但在应用中，也可以通过所述可调节延时电路实现一级或二级的延时调节。例如，可以通过上述可调节延时电路实现范围窄但精度高的延时调节，例如，可以在第一调节模块和第二调节模块的输入端输入固定的高电平，在第三调度模块的输入端输入对应的调节信号，从而可以使得只需通过延时模块中的第一延时子模块进行延时，实现延时的精调。或者，也可以通过上述可调节延时电路实现范围宽但精度稍微低一些的延时调节，例如，可以在第三调节模块的输入端输入固定的高电平，在第一调节模块的输入端输入第一调节信号和第二调节模块的输入端输入第二调节信号，从而使得延时模块可以根据第一调节信号和第二调节信号进行延时，实现延时的次调。
本申请中的可调节延时电路采用第一调节模块、第二调节模块和第三调节模块进行三级调节，从而可以实现对延时进行多级调节，以满足对延时范围和调节精度的需求。
需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非 排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。

Claims (9)

  1. 一种可调节延时电路，包括：
    第一调节模块，包括第一输入端和控制输出端，所述第一调节模块设置为对从所述第一输入端输入的第一调节信号进行译码，根据译码结果从所述控制输出端输出控制选通信号；
    第二调节模块，包括第二输入端和第一输出端，其中，所述第二调节模块设置为对从所述第二输入端输入的第二调节信号进行差分处理，将差分处理得到的第一对差分信号通过所述第一输出端输出；
    第三调节模块，包括第三输入端和第二输出端，其中，所述第三调节模块设置为对从所述第三输入端输入的第三调节信号进行差分处理，将差分处理得到的第二对差分信号通过所述第二输出端输出；
    延时模块，包括：
    信号输入端，设置为接收目标差分信号对；
    选通信号输入端，与所述控制输出端连接，设置为接收所述控制选通信号；
    第一控制端，设置为接收所述第一对差分信号；
    第二控制端，设置为接收所述第二对差分信号；
    所述延时模块设置为根据输入的所述控制选通信号、所述第一对差分信号和所述第二对差分信号对所述目标差分信号对进行延时；
    信号输出端，设置为输出经所述延时模块延时后的目标差分信号对。
  2. 根据权利要求1所述的电路，其中，所述延时模块包括第一延时子模块、N个第二延时子模块、第一负载模块和第二负载模块，其中，
    所述第一控制端包括：至少一个第一控制子端和至少一个第二控制子端，所述至少一个第一控制子端设置为接收所述第一对差分信号中的一个差分信号，所述至少一个第二控制子端设置为接收所述第一对差分信号中的另一个差分信号；
    所述第一延时子模块包括所述信号输入端、所述第二控制端、第一差分输出端、以及第一差分输出正端；
    所述N个第二延时子模块中的每个第二延时子模块包括：第二差分输入端、第二差分输出端以及第二差分输出正端；
    所述N个第二延时子模块中除最后一个第二延时子模块中的每个第二延时子模块的第二差分输出端与所述每个第二延时子模块的下一个第二延时子模块的第二差分输入端连接，所述N个第二延时子模块中的第一个第二延时子模块 的第二差分输入端与所述第一差分输出端连接，所述N个第二延时子模块中的所述最后一个第二延时子模块的第二差分输出端与所述第二负载模块连接；
    所述第一差分输出正端与所述N个第二延时子模块的第二差分输出正端连接在一起后与所述第一负载模块连接；
    所述第一负载模块包括所述信号输出端；
    所述第一延时子模块和所述N个第二延时子模块中相邻的两个第二延时子模块中一个第二延时子模块上还均设置有第一控制子端，所述相邻的两个第二延时子模块中另一个第二延时子模块上还设置第二控制子端；
    所述第一延时子模块和所述N个第二延时子模块中的每个第二延时子模块上均设置一个选通信号输入端，所述一个选通信号输入端设置为接收控制所述一个选通信号输入端对应的延时子模块是否接入所述第一控制子端或所述第二控制子端的控制选通信号；
    N为大于等于1的整数。
  3. 根据权利要求2所述的电路，其中，所述第一延时子模块包括第一缓冲单元、相位内插单元和第一选通单元；
    所述第一缓冲单元的输入端包括所述信号输入端，所述第一缓冲单元的输出端与所述相位内插单元的一个输入端连接；
    所述相位内插单元的一个输入端与所述第一缓冲单元的输出端连接，所述相位内插单元的另一个输入端设置为输入所述目标差分信号对，所述相位内插单元的控制端包括所述第二控制端，所述相位内插单元的输出端与所述第一差分输出端连接；
    所述第一选通单元的输入端与所述相位内插单元的输出端连接，所述第一选通单元的控制端包括一个选通信号输入端，所述第一选通单元的输出端包括所述第一差分输出正端，所述第一选通单元上还包括第一控制子端或第二控制子端；
    所述第二延时子模块包括：第二缓冲单元和第二选通单元；
    所述第二缓冲单元的输入端包括所述第二差分输入端，所述第二缓冲单元的输出端与所述第二差分输出端连接；
    所述第二选通单元的输入端与所述第二缓冲单元的输出端连接，所述第二选通单元的控制端包括一个选通信号输入端，所述第二选通单元的输出端包括所述第二差分输出正端，所述第二选通单元上还包括第一控制子端或第二控制子端。
  4. 根据权利要求3所述的电路，其中，所述第一缓冲单元包括：
    第一三极管Q1，其基极与所述第一缓冲单元的一个输入端连接，其集电极接第一电阻R1的一端，其发射极通过电流源I1接地；
    第二三极管Q2，其基极与所述第一缓冲单元的另一个输入端连接，其集电极接第二电阻R2的一端，其发射极通过所述电流源I1接地；
    所述第一电阻R1，其一端接电源端VCC，另一端接所述第一三极管Q1的集电极；
    所述第二电阻R2，其一端接所述电源端VCC，另一端接所述第二三极管Q2的集电极；
    第三三极管Q3，其基极接所述第一三极管Q1的集电极，其集电极接所述电源端VCC，其发射极作为所述第一缓冲单元的一个输出端并通过电流源I2接地；
    第四三极管Q4，其基极接所述第二三极管Q2的集电极，其集电极接所述电源端VCC，其发射极作为所述第一缓冲单元的另一个输出端并通过电流源I3接地；
    所述第二缓冲单元包括：
    第一三极管Q1，其基极与所述第二缓冲单元的一个输入端连接，其集电极接第一电阻R1的一端，其发射极通过电流源I1接地；
    第二三极管Q2，其基极与所述第二缓冲单元的另一个输入端连接，其集电极接第二电阻R2的一端，其发射极通过所述电流源I1接地；
    所述第一电阻R1，其一端接电源端VCC，另一端接所述第一三极管Q1的集电极；
    所述第二电阻R2，其一端接所述电源端VCC，另一端接所述第二三极管Q2的集电极；
    第三三极管Q3，其基极接所述第一三极管Q1的集电极，其集电极接所述电源端VCC，其发射极作为所述第二缓冲单元的一个输出端并通过电流源I2接地；
    第四三极管Q4，其基极接所述第二三极管Q2的集电极，其集电极接所述电源端VCC，其发射极作为所述第二缓冲单元的另一个输出端并通过电流源I3接地。
  5. 根据权利要求3所述的电路，其中，所述相位内插单元包括：
    第五三极管Q5，其基极与所述第一缓冲单元的一个输出端连接，其集电极 接第三电阻R3的一端，其发射极接第九三极管Q9的集电极；
    第六三极管Q6，其基极与所述第一缓冲单元的另一个输出端连接，其集电极接第四电阻R4的一端，其发射极接第所述九三极管Q9的集电极；
    第七三极管Q7，其基极与所述信号输入端连接，其集电极接所述第三电阻R3的一端，其发射极接第十三极管Q10的集电极；
    第八三极管Q8，其基极与所述信号输入端连接，其集电极接所述第四电阻R4的一端，其发射极接所述第十三极管Q10的集电极；
    所述第九三极管Q9，其基极与第三控制子端连接，其集电极分别接所述第五三极管Q5的发射极和所述第六三极管Q6的发射极，其发射极通过电流源I4接地，其中，所述第二控制端包括第三控制子端和第四控制子端；
    所述第十三极管Q10，其基极与所述第四控制子端连接，其集电极分别接所述第七三极管Q7的发射极和所述第八三极管Q8的发射极，其发射极通过所述电流源I4接地；
    所述第三电阻R3，其一端接所述第七三极管Q7的集电极，另一端接电源端VCC；
    所述第四电阻R4，其一端接所述第八三极管Q8的集电极，另一端接所述电源端VCC。
  6. 根据权利要求5所述的电路，其中，所述相位内插单元还包括射极跟随单元，所述射极跟随单元包括：
    第十一三极管Q11，其基极接所述第七三极管Q7的集电极，其集电极接所述电源端VCC，其发射极作为所述相位内插单元的一个输出端并通过电流源I5接地；
    第十二三极管Q12，其基极接所述第八三极管Q8的集电极，其集电极接所述电源端VCC，其发射极作为所述相位内插单元的另一个输出端并通过电流源I6接地。
  7. 根据权利要求3所述的电路，其中，所述第一选通单元包括：
    第十三三极管Q13，其基极作为所述第一选通单元的一个输入端，其发射极接第十五三极管Q15的集电极；
    第十四三极管Q14，其基极作为所述第一选通单元的另一个输入端，其发射极接所述第十五三极管Q15的集电极；
    所述第十三三极管Q13的集电极和所述第十四三极管Q14的集电极作为所述第一选通单元的输出端；
    所述第十五三极管Q15，其基极接金属氧化物半导体MOS管NM1的源极，其集电极分别与所述第十三三极管Q13的发射极和第十四三极管Q14的发射极连接，其发射极接地；
    所述MOS管NM1，其栅极与所述选通信号输入端连接，其源极接所述第十五三极管Q15的基极，其漏极与第一控制子端或第二控制子端连接
    所述第二选通单元包括：
    第十三三极管Q13，其基极作为所述第二选通单元的一个输入端，其发射极接第十五三极管Q15的集电极；
    第十四三极管Q14，其基极作为所述第二选通单元的另一个输入端，其发射极接所述第十五三极管Q15的集电极；
    所述第十三三极管Q13的集电极和所述第十四三极管Q14的集电极作为所述第一选通单元的输出端；
    所述第十五三极管Q15，其基极接金属氧化物半导体MOS管NM1的源极，其集电极分别与所述第十三三极管Q13的发射极和第十四三极管Q14的发射极连接，其发射极接地；
    所述MOS管NM1，其栅极与所述选通信号输入端连接，其源极接所述第十五三极管Q15的基极，其漏极与第一控制子端或第二控制子端连接。
  8. 根据权利要求1至7任一项所述的电路，其中，所述第一调节模块包括译码器，所述第二调节模块包括4位的数字模拟转换器DAC，所述第三调节模块包括10位的数字模拟转换器DAC。
  9. 根据权利要求2至7任一项所述的电路，其中，N＝7。
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CN115378406A (zh) * 2022-08-19 2022-11-22 普源精电科技股份有限公司 一种可调节延时电路和电子设备

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