WO2016008099A1 - 检测基板裂缝的方法、基板和检测电路 - Google Patents

检测基板裂缝的方法、基板和检测电路 Download PDF

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Publication number
WO2016008099A1
WO2016008099A1 PCT/CN2014/082254 CN2014082254W WO2016008099A1 WO 2016008099 A1 WO2016008099 A1 WO 2016008099A1 CN 2014082254 W CN2014082254 W CN 2014082254W WO 2016008099 A1 WO2016008099 A1 WO 2016008099A1
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WIPO (PCT)
Prior art keywords
test line
tft substrate
edge
crack
conductive layer
Prior art date
Application number
PCT/CN2014/082254
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English (en)
French (fr)
Inventor
贾彦峰
唐磊
谢鹏飞
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华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to US15/326,308 priority Critical patent/US9983452B2/en
Priority to PCT/CN2014/082254 priority patent/WO2016008099A1/zh
Priority to CN201480041262.0A priority patent/CN105393165B/zh
Publication of WO2016008099A1 publication Critical patent/WO2016008099A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133302—Rigid substrates, e.g. inorganic substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • Embodiments of the present invention relate to the field of manufacturing liquid crystal panels, and in particular, to a method for detecting cracks in a substrate, a substrate, and a detecting circuit. Background technique
  • a TFT (Thin Film Transistor) substrate (or TFT glass) is a basic component of an LCD (Liquid Crystal Display) and is one of the key basic materials.
  • the TFT substrate is a glass substrate which is a thin glass sheet with an extremely flat surface.
  • a transparent conductive layer ie, IT0 (indium tin oxide)
  • IT0 indium tin oxide
  • the film layer is photolithographically processed to form transparent conductive patterns, and the patterns are composed of a pixel pattern and an outer lead pattern.
  • the detection of the TFT substrate is mainly performed after cutting, and generally the inspection personnel perform detection by an AOI (Automatic Optic Inspection) optical device (such as a microscope). By this method, it is possible to detect small cracks or collapses occurring at the cutting edge of the TFT substrate during the cutting process.
  • AOI Automatic Optic Inspection
  • the above detection method mainly relies on manual detection in implementation, not only the detection efficiency is low, but also the occurrence of missed detection, and the above detection method can only detect small cracks or collapses occurring during the cutting process, and the TFT substrate is The process of assembling into an LCM (LCD Module) and the cracks or collapses generated during transportation cannot be detected, and the cracks generated by the LCM during assembly into a complete machine (such as assembly into a TV or mobile phone) Or a collapse is also undetectable.
  • LCM LCD Module
  • the embodiment of the invention provides a method for detecting a crack of a substrate, a substrate and a detecting circuit, which can improve the detection efficiency, avoid the occurrence of the missed detection, and can detect the TFT substrate after the TFT substrate is assembled into the LCM and the LCM is assembled into the whole machine.
  • a TFT substrate is provided, the TFT substrate comprising:
  • the glass substrate is provided with a non-closed test line having an opening along the edge of the glass substrate;
  • the opening is composed of two end points of the test line, wherein a test point is set at a set distance from each end point on the test line, and the test point is used for connecting to determine that the test line is on and off A measuring tool for determining whether the edge of the TFT substrate has a crack or a collapse; one of the two end points is grounded.
  • the opening is located in a conjugate FOG Bonding region of the flexible printed circuit board and the glass substrate;
  • the two ends of the opening are electrically connected to the first connector interface through a flexible printed circuit board, the first connector interface is used for electrically connecting with a connector interface of the detecting circuit, and the detecting circuit is used for measuring The continuity of the test line is performed to determine whether the edge of the TFT substrate has a crack or a chip.
  • the conductive layer of the test line is fabricated as any conductive layer in the TFT substrate process, and the test line It is produced together with the conductive pattern of the conductive layer in a patterning process of the conductive layer.
  • the conductive layer includes: any one of a gate metal layer, a source drain metal layer, and a transparent conductive film;
  • the conductive layer for fabricating the test line is any conductive layer in the TFT substrate process, and the test line is produced together with the conductive pattern of the conductive layer in a patterning process of the conductive layer, including:
  • the conductive layer for forming the test line is the gate metal layer, and the test line is fabricated together with the gate metal line in a patterning process for the gate metal layer;
  • the conductive layer forming the test line is the source drain metal layer, and the test line is fabricated together with the source drain metal line in a patterning process of the source drain metal layer; Or,
  • the conductive layer on which the test line is formed is the transparent conductive film, and the test line is in the
  • the transparent conductive film is fabricated together with the pixel electrode in a single patterning process.
  • the method includes:
  • the distance between the test line and the edge of the glass substrate is 150 ⁇ to 200 ⁇ ;
  • the distance between the test line and the edge of the glass substrate is 100 ⁇ m.
  • a second aspect provides a TFT substrate, where the TFT substrate includes:
  • the glass substrate is provided with a non-closed test line having an opening along the edge of the glass substrate;
  • the opening is composed of two end points of the test line; one of the two end points is grounded;
  • the opening is located in a mating FOG Bonding region of the flexible printed circuit board and the glass substrate, and the two end points of the opening are electrically connected to the first connector interface through the flexible printed circuit board, and the first connector interface is used And electrically connected to the connector interface of the detecting circuit, wherein the detecting circuit is configured to measure the continuity of the test line to determine whether the edge of the TFT substrate has cracks or collapse.
  • the conductive layer of the test line is fabricated as any conductive layer in the TFT substrate process, and the test line is in a patterning process on the conductive layer. Made with the conductive pattern of the conductive layer.
  • the conductive layer includes: any one of a gate metal layer, a source drain metal layer, and a transparent conductive film;
  • the conductive layer for fabricating the test line is any conductive layer in the TFT substrate process, and the test line is produced together with the conductive pattern of the conductive layer in a patterning process of the conductive layer, including:
  • the conductive layer for forming the test line is the gate metal layer, and the test line is fabricated together with the gate metal line in a patterning process for the gate metal layer;
  • the conductive layer forming the test line is the source drain metal layer, and the test line is in the opposite
  • the source-drain metal layer is fabricated together with the source-drain metal line in a single patterning process; or
  • the conductive layer on which the test line is formed is the transparent conductive film, and the test line is formed together with the pixel electrode in a patterning process of the transparent conductive film.
  • the method includes:
  • the distance between the test line and the edge of the glass substrate is 150 ⁇ to 200 ⁇ ;
  • the distance between the test line and the edge of the glass substrate is 100 ⁇ m.
  • a detection circuit in a third aspect, includes: an analog to digital conversion interface, a power source, a resistor, a second connector interface, and a test platform;
  • the power source is electrically connected to the first end of the resistor, the second end of the resistor is electrically connected to the second connector interface, and the first end of the analog-to-digital conversion interface and the resistor
  • the second end is electrically connected, the second end of the analog-to-digital conversion interface is electrically connected to the test platform, and the first possible implementation of the first aspect of the claim to the third possibility of the second aspect
  • the test platform is configured to measure an electrical parameter of the resistor of the series circuit and a connection point of the second connector interface, and determine, according to the electrical parameter, whether an edge of the TFT substrate has Crack or collapse.
  • the first connector interface and the second connector interface are BTB (Board to Board) interfaces
  • the first connector interface is a BTB interface female
  • the second connector interface is a BTB interface male
  • a fourth aspect a liquid crystal display comprising: the TFT substrate according to any one of the first aspect to the third possible implementation of the second aspect.
  • an electronic terminal comprising the liquid crystal display of the fourth aspect.
  • a method for detecting a crack in a substrate comprising:
  • test line Acquiring electrical parameters of the test line on the TFT substrate by using a measurement tool; wherein the test line a non-closed test line having an opening along the edge of the glass substrate of the TFT substrate, the opening being composed of two end points of the test line, wherein the test line is at a set distance from each end point Providing a test point for connecting the measuring tool;
  • the test line is turned on and off according to the electrical parameter to determine whether the edge of the TFT substrate has a crack or a chip.
  • the obtaining, by the measuring tool, the electrical parameters of the test line on the TFT substrate includes:
  • the resistance value of the test line is obtained by a multimeter.
  • the determining, according to the electrical parameter, whether an edge of the TFT substrate has a crack or a collapse comprises: determining the test Whether the resistance value of the line is infinite, if the resistance value is infinite, determining that the edge of the TFT substrate has cracks or collapse; if the resistance value is not infinite, determining that there is no crack at the edge of the TFT substrate Or collapse.
  • the measuring tool includes a multimeter, an external power source, the multimeter, the external power source, and the test line forming a loop;
  • the obtaining, by the measuring tool, the electrical parameters of the test line on the TFT substrate includes:
  • the current value on the test line is obtained by the multimeter.
  • the determining, according to the electrical parameter, whether the edge of the TFT substrate has a crack or a collapse comprises: determining the test Whether the current value on the line is zero, if the current value is zero, determining that the edge of the TFT substrate has a crack or a collapse; if the current value is not zero, determining the edge of the TFT substrate There are no cracks or collapses.
  • the measuring tool includes an indicator light, an external power source, and the indicator light, the external power source, and the test line form a loop;
  • the obtaining, by the measuring tool, the electrical parameters of the test line on the TFT substrate includes:
  • the test line is obtained to be disconnected or turned on by the indicator light.
  • the determining, according to the electrical parameter, whether an edge of the TFT substrate has a crack or a collapse includes: If the line is disconnected, it is determined that the edge of the TFT substrate has a crack or a collapse; if the test line is turned on, it is determined that there is no crack or chipping at the edge of the TFT substrate.
  • the method further includes: the opening is located in a mating FOG Bonding region of the flexible printed circuit board and the glass substrate;
  • the printed circuit board is electrically connected to the first connector interface, and the first connector interface is electrically connected to a connector interface of the detecting circuit capable of determining that the test line of the TFT substrate is turned on and off.
  • the detection circuit detects whether the edge of the TFT substrate in the liquid crystal module has a crack or a chip.
  • the method further includes: after the liquid crystal module is assembled into a terminal, detecting, by the detecting circuit Whether the edge of the TFT substrate in the liquid crystal module has cracks or collapses.
  • the detecting, by the detecting circuit, detecting whether an edge of the TFT substrate in the liquid crystal module has a crack Or the collapse includes:
  • the electrical parameter includes a voltage value or a current value
  • Determining, according to the electrical parameter, whether an edge of the TFT substrate in the liquid crystal module has a crack or a collapse comprises:
  • a method for detecting a crack in a substrate comprising:
  • the detecting circuit obtains, by the detecting circuit, an electrical parameter of the connection between the TFT substrate and the detecting circuit;
  • the TFT substrate is provided with a non-closed test line having an opening along an edge of the glass substrate; the opening is The two endpoints of the test line are composed; one of the two endpoints is connected The opening is located in a mating FOG Bonding region of the flexible printed circuit board and the glass substrate, and the two ends of the opening are electrically connected to the first connector interface through the flexible printed circuit board, the first connector The interface is used for electrically connecting to a connector interface of the detecting circuit;
  • the on/off of the test line is judged based on the electrical parameter to determine whether the edge of the TFT substrate has a crack or a collapse.
  • Embodiments of the present invention provide a method for detecting a crack of a substrate, a substrate, and a detecting circuit.
  • a non-closed test line having an opening on one edge of the glass substrate of the TFT substrate, it is possible to measure the conduction or disconnection of the test line. Judging whether the edge of the TFT substrate has cracks or collapses, compared with the prior art, the visual measurement can avoid the missed detection and improve the detection efficiency, and assemble the TFT substrate into a liquid crystal module or assemble the liquid crystal module into a complete machine. After that, it is still possible to detect whether there is a crack or a chipping in the edge of the TFT substrate in the liquid crystal module.
  • FIG. 1 is a schematic structural diagram of a TFT substrate according to an embodiment of the present invention.
  • FIG. 2 is another schematic structural diagram of a TFT substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a detection circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of connection between a TFT substrate and a detection circuit according to an embodiment of the present invention
  • FIG. 5 is a schematic flow chart of a method for detecting a crack of a substrate according to an embodiment of the present invention
  • FIG. 6 is another schematic flowchart of a method for detecting a crack of a substrate according to an embodiment of the present invention.
  • the technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention.
  • the embodiments are a part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.
  • the embodiment of the present invention provides a TFT substrate 1.
  • the TFT substrate 1 includes: a glass substrate 11;
  • the glass substrate 11 is provided with a non-closed test line 12 along the edge of the glass substrate and having an opening 121;
  • the opening 121 is composed of two end points A and B of the test line 12, wherein test points are set within a set distance of each end point, for example, the test point A1 and the test point B1 shown in FIG. 1 are respectively located at the end point A and the end point.
  • test points A1 and B1 are used to connect a measuring tool capable of determining the continuity of the test line; one of the two end points is grounded (exemplary, in Figure 1, the end point B is grounded, typically connected to the TFT substrate 1) GND terminal).
  • the set distance is not limited in the embodiment of the present invention, and the preferred set distance is selected such that two test points are close to the two end points.
  • the opening 121 is located on a embossed area of an FPC (Flexible Printed Circuit) and a glass substrate on a glass substrate, and the area may be referred to as FOG (FPC on Glass, flexible circuit board). Attached to the glass circuit board) FOG Bonding area 13.
  • FPC Flexible Printed Circuit
  • FOG FOG on Glass, flexible circuit board
  • Attached to the glass circuit board FOG Bonding area 13.
  • the position of the opening 121 is exemplary, including but not limited thereto, and in other possible embodiments, the opening 121 may be located at other positions.
  • the test line 12 can be fabricated by using an existing TFT substrate process.
  • the conductive layer of the test line 12 can be any conductive layer in the existing TFT substrate process, and the test line 12 is a patterned layer on the conductive layer. The process is produced together with the conductive pattern of the conductive layer.
  • the test point A1 and the test point B1 on the test line 12 are produced together with the test line 12.
  • an insulating layer is further disposed on the test line 12, and other metal layers or insulating layers may be disposed on the insulating layer to complete the subsequent TFT substrate process on the other layers covered on the test line 12.
  • a via hole penetrating the layers is left at the test point A1 and the test point B1 to leak out the test point A1 and the test point B1 so that the test point A1 and the test point B1 can be connected to the measuring tool.
  • the conductive layer may be any one of a gate metal layer, a source/drain metal layer, and a transparent conductive film.
  • test line is formed together with the gate metal line in a patterning process for the gate metal layer.
  • the conductive layer for the test line is the source drain metal layer, and the test line is the source drain metal layer. In a patterning process, it is fabricated together with the source drain metal line.
  • the conductive layer for the test line is a transparent conductive film, and the test line is formed together with the pixel electrode in a patterning process for the transparent conductive film.
  • the conductive layer may be formed by magnetron sputtering or other film forming method to deposit a metal layer of a certain thickness. If the gate metal layer and the source drain metal layer are formed, molybdenum, aluminum, aluminum-nickel alloy, or the like may be used. For metals such as molybdenum-tungsten alloy, chromium or copper, a combination of the above materials may be used; if a transparent conductive film is formed, indium tin oxide (ITO), indium zinc oxide (IZO) or other transparent electrode materials may be used.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the above-mentioned one-time patterning process may include: after the metal layer is formed, the test line 12 and other conductive patterns of the conductive layer are obtained by a process of development, etching, etc., and it can be seen that the test line 12 is fabricated by using an existing process. No increase in process complexity.
  • the distance between the test line 12 and the edge of the glass substrate 11 is determined by the process capability.
  • the distance between the test line 12 and the edge of the glass substrate 11 is different in different metal layers, such as:
  • test line 12 is formed in the first patterning process of forming the gate metal layer or the source/drain metal layer, together with the gate metal layer or the source drain metal layer, the distance between the test line 12 and the edge of the glass substrate 11 It is 150 ⁇ (nano) ⁇ 200 ⁇ .
  • test line 12 is formed together with the transparent conductive film in a patterning process for producing a transparent conductive film, the distance between the test line 12 and the edge of the glass substrate 11 is about ⁇ .
  • the electrical parameters of the test line 12 can be measured by using a measuring tool such as a multimeter (also called a jig).
  • a measuring tool such as a multimeter (also called a jig).
  • two measuring pens of the multimeter can be respectively connected to the two measuring points of the test line 12, A1 and On B1, the resistance value of the test line 12 is obtained by a multimeter.
  • the resistance value of the test line 12 is infinite, it indicates that the test line 12 has been disconnected, and it can be determined that the edge of the TFT substrate has cracks or chipping. If the resistance value of the test line 12 is not infinite, it indicates that the test line 12 is intact, and it can be determined that there is no crack or chipping at the edge of the TFT substrate.
  • the multimeter, the external power supply, and the test line 12 can be connected in series to form a loop, and the current value on the test line 12 can be obtained by the multimeter.
  • the test line 12 has been disconnected, and the TFT can be determined.
  • the edge of the substrate has cracks or chipping; otherwise, it indicates that the test line 12 is intact, and it can be determined that there is no crack or chipping at the edge of the TFT substrate.
  • the indicator light, external power supply, and test line 12 are connected in series to form a loop, and the indicator line 12 is used to indicate that the test line 12 is disconnected or turned on.
  • test line 12 If the test line 12 is disconnected, it can be determined that the edge of the TFT substrate has a crack or a collapse; if the test line is turned on, it can be determined that there is no crack or chipping at the edge of the TFT substrate.
  • test line 12 is turned on or off.
  • the two terminals A and B of the test line 12 can also be electrically connected to the first connector interface 14 through the FPC, and the first connector interface 14 is used for electrical connection with the connector interface of the detection circuit.
  • the detection circuit is any detection circuit capable of detecting that the test line 12 on the TFT substrate 1 is turned on or off.
  • the timing of detecting the TFT substrate 1 by the detecting circuit may be after the substrate is cut, or after the TFT substrate 1 is assembled into the LCM, or after the LCM including the TFT substrate 1 is assembled into a terminal.
  • the detecting circuit can be an independent detecting circuit, and the detecting circuit can be detected by externally connecting the detecting circuit; or the detecting circuit can be integrated in the liquid crystal module or the terminal, and the terminal is used as a detecting platform, and the software for controlling the detecting circuit is controlled. It is possible to test the terminal's own liquid crystal module.
  • the detection circuit can be the detection circuit 3 provided in the following embodiments.
  • the connector interface of the first connector interface 14 and the detecting circuit may be a BTB interface (or a B2B interface).
  • the first connector interface 14 is a female base of the BTB interface
  • the connector interface of the detecting circuit is The public seat of the BTB interface.
  • the connector interface uses the BTB interface only for the sake of example, and other interfaces besides the BTB interface.
  • a non-closed test line having an opening is formed by one edge on the edge of the glass substrate of the TFT substrate, and the opening is composed of two end points of the test line, wherein test points are disposed at each end point.
  • the test point is used for connecting a measuring tool capable of determining the continuity of the test line, and the measuring tool can be used to measure whether the edge of the TFT substrate has cracks or collapses by measuring the conduction or disconnection of the test line, and the visual measurement is compared with the prior art.
  • the embodiment of the present invention provides a TFT substrate 2, as shown in FIG. 2, the TFT substrate 2 includes: a glass substrate 21;
  • the glass substrate 21 is provided with a non-closed test line 22 along the edge of the glass substrate 21 and having an opening 221;
  • the opening 221 is composed of two end points C and D of the test line 22, and one of the two end points is grounded (exemplary, the end point D is grounded in FIG. 2, generally connected to the GND 3 ⁇ 4 of the TFT substrate 2);
  • the opening 221 is located in the FOG Bonding area 23, and the two ends A and B of the opening 221 are electrically connected to the first connector interface 24 through a flexible printed circuit board, and the first connector interface 24 is used to interface with the connector of the detecting circuit.
  • the connection, detection circuit is used to measure the on and off of the test line 22 to judge whether the edge of the TFT substrate 2 has cracks or chipping.
  • the test line 22 can be fabricated by using an existing TFT substrate process.
  • the conductive layer of the test line 22 can be any conductive layer in the existing TFT substrate process, and the test line 22 is once in the pair of conductive layers.
  • the patterning process is produced together with the conductive pattern of the conductive layer.
  • the specific fabrication process is identical to the process of the test line 12 in the TFT substrate 1, and will not be described again.
  • the detection circuit is any type of detection circuit capable of detecting that the test line 22 on the TFT substrate 2 is turned on or off.
  • the timing of detecting the TFT substrate 2 by the detecting circuit may be after the substrate is cut, or after the TFT substrate 2 is assembled into the LCM, or after the LCM including the TFT substrate 2 is assembled into a terminal.
  • the detecting circuit can be an independent detecting circuit, and the detecting circuit can be detected by externally connecting the detecting circuit; or the detecting circuit can be integrated in the liquid crystal module or the terminal, and the terminal is used as a detecting platform, and the software for controlling the detecting circuit is controlled. It is possible to test the terminal's own liquid crystal module.
  • the detection circuit can be the detection circuit 3 provided in the following embodiments.
  • the TFT substrate provided by the embodiment of the present invention is provided with a non-closed test line having an opening on the edge of the glass substrate of the TFT substrate, the opening being composed of two end points of the test line, two end points of the opening and passing through the flexible printed circuit
  • the board is electrically connected to the first connector interface, and the first connector interface is electrically connected to the connector interface of the detecting circuit, so that the detecting circuit can measure the continuity of the test line to determine whether the edge of the TFT substrate has a crack or
  • the collapse compared with the prior art using visual measurement, can avoid miss detection and improve detection efficiency, and assemble the TFT substrate into a liquid crystal mode.
  • the group can still detect whether there is crack or collapse of the edge of the TFT substrate in the liquid crystal module after the liquid crystal module is assembled into a whole machine.
  • the embodiment of the present invention further provides a detecting circuit 3.
  • the detecting circuit 3 includes: an analog-to-digital conversion interface 31, a power source 32, a resistor 33, a second connector interface 34, and a test platform 35.
  • the first end of the resistor 33 is electrically connected to the second end of the resistor 33, and the first end of the analog-to-digital converter interface 31 is electrically connected to the second end of the resistor 33.
  • the second end of the conversion interface 31 is electrically connected to the test platform 35, when the first connector interface 14 of the TFT substrate 1 (or the first connector interface 24 of the TFT substrate 2) and the second connector interface 34 Electrically connected, forming a series circuit including a power source 32, a resistor 33, a TFT substrate 1 (or a TFT substrate 2) (actual connection diagram can be as shown in FIG. 4), and a test platform 35 for measuring resistance
  • the detection circuit 3 is connected to the TFT substrate 1 as an example (the embodiment in which the TFT substrate 2 is used in FIG. 3 is not shown). Since the test line 12 in the TFT substrate 1 has an internal resistance, the power source 32, the resistor 33, The test line 12 and the GND terminal on the TFT substrate 1 constitute a series circuit. According to the map
  • the voltage at point C that is, the voltage divided by the internal resistance of the test line 12 is known from the voltage division formula of the series circuit:
  • the voltage is:
  • V c represents the voltage at point C
  • V represents the voltage of the power source 23
  • R T represents the resistance of the test line 12
  • R represents the resistance of the resistor 33
  • the power source 32 can be 1.8 V (volts) and the resistor 33 can be 1 ⁇ ⁇ ( Mega ohms).
  • the timing of detecting the TFT substrate by the detecting circuit 3 may be after the substrate is cut, or after the TFT substrate is assembled into the LCM, or after the LCM including the TFT substrate is assembled into the terminal.
  • the detecting circuit 3 can be an independent detecting circuit, and the detecting circuit 3 can be detected by externally connecting the detecting circuit 3; or the detecting circuit 3 can be integrated in the liquid crystal module or the terminal, and the terminal is used as a detecting platform, and the detecting circuit is controlled.
  • Software can test the terminal's own liquid crystal mode Piece.
  • the detection circuit provided by the embodiment of the invention can determine whether the edge of the TFT substrate has cracks or collapses by measuring the conduction or disconnection of the test line, which can avoid missed detection and improve compared with the prior art by using visual measurement. Detecting efficiency, and whether the TFT substrate is assembled into a liquid crystal module or after the liquid crystal module is assembled into a whole machine, whether the edge of the TFT substrate in the liquid crystal module has cracks or chipping can be realized.
  • the embodiment of the invention further provides a liquid crystal display.
  • the liquid crystal display comprises: the TFT substrate 1 (or the TFT substrate 2) provided by the foregoing embodiment, and a liquid crystal, a color filter substrate, a polarizer, a backlight, and a light guide plate.
  • the backlight and the light guide plate provide a light source for the liquid crystal display, and the TFT substrate 1 (or the TFT substrate 2) is disposed above the backlight and the light guide plate, and the liquid crystal is disposed between the TFT substrate 1 (or the TFT substrate 2) and the color filter substrate.
  • the liquid crystal is disposed in the sealant between the TFT substrate 1 (or the TFT substrate 2) and the color filter substrate, and the polarizer is disposed above the color filter substrate.
  • the embodiment of the invention further provides an electronic terminal, comprising: the liquid crystal display.
  • the above liquid crystal display may further include the detecting circuit 3 described in the foregoing embodiment.
  • Embodiments of the present invention provide a method for detecting a crack in a substrate. As shown in FIG. 5, the method includes:
  • the TFT substrate may be the TFT substrate 1 provided in the foregoing embodiment.
  • the TFT substrate 1 has a test line 12 on the edge of the glass substrate 11 of the TFT substrate 1 and having an opening 121 .
  • the non-closed test line, the opening 121 is composed of two end points A and B of the test line 12, wherein test points are set within a set distance of each end point, such as A1 and B1 shown in Fig. 1, test points A1 and B1 Used to connect measurement tools that can measure the continuity of test line 12.
  • the electrical parameter may be a resistance value, a current value, a voltage value, and the like.
  • the electrical parameter of the test line of the TFT substrate is measured by a measuring tool, and whether the test line is turned on according to the electrical parameter of the test line, thereby determining whether the edge of the TFT substrate has a crack.
  • collapse compared with the prior art by visual measurement, it can avoid missed detection and improve detection efficiency, and can still realize the liquid crystal mode after the TFT substrate is assembled into a liquid crystal module or after the liquid crystal module is assembled into a whole machine. Whether the edge of the TFT substrate in the group has cracks Or the detection of a collapse.
  • the TFT substrate may be the TFT substrate 1 provided in the foregoing embodiment.
  • FIG. 1 reference may be made to S101 , and details are not described herein again.
  • the measuring tool is used to test the test line 12 is turned on or off, so the electrical parameters can usually be parameters such as resistance value, current value, voltage value, etc., so a measuring instrument such as a multimeter can be used.
  • two measuring pens of the multimeter can be connected to two measuring points of the test line 12, respectively.
  • the resistance value of the test line 12 is obtained by a multimeter.
  • the measuring tool can also be a multimeter, an external power supply, and the multimeter, the external power supply, and the test line 12 can be connected in series to form a loop, and the current value on the test line 12 can be obtained by a multimeter.
  • the measuring tool can also be an indicator light, an external power supply, and the indicator light, the external power supply, and the test line 12 are connected in series to form a loop, and the indicator light 12 is used to obtain an indication that the test line 12 is disconnected or turned on.
  • test line 12 If the resistance value of the test line 12 is infinite, the test line 12 has been disconnected, and it can be determined.
  • the edge of the TFT substrate has cracks or chipping. If the resistance value of the test line 12 is not infinite, it indicates that the test line 12 is intact, and it can be determined that there is no crack or chipping at the edge of the TFT substrate.
  • test line 12 If the current value on the test line 12 is zero, it indicates that the test line 12 has been disconnected, and it can be determined that the edge of the TFT substrate has a crack or a collapse; otherwise, the test line 12 is complete, and it can be determined that the edge of the TFT substrate does not exist. Crack or collapse.
  • the indicator light indicates that the test line 12 is disconnected, it may be determined that the edge of the TFT substrate has a crack or a collapse; if the indicator light indicates that the test line is conductive, it may be determined that there is no crack or chipping at the edge of the TFT substrate.
  • the above several measurement methods are merely exemplary, and other detection methods may be used to detect whether the test line 12 is turned on or off to determine whether there is a crack or a chipping at the edge of the TFT substrate.
  • the detection circuit detects whether the edge of the TFT substrate in the liquid crystal module has cracks or collapse.
  • the detection circuit detects whether the edge of the TFT substrate in the liquid crystal module has cracks or collapse.
  • the detecting circuit may be the detecting circuit 3 provided by the foregoing embodiment, and the detecting circuit 3 is connected to the TFT substrate 1.
  • the detecting circuit 3 may be connected to the TFT substrate 1 through a connector, wherein the TFT substrate 1 having a connector first interface 14 (for example, a female base of a BTB interface), the detection circuit 3 having a connector second interface 34 (for example, a male seat of the BTB interface), and the middle connector of the detection circuit is obtained by the detection circuit 3 (ie The electrical parameter of the connection point of the resistor 33 and the second connector interface 34, point C in Fig. 3, here taking the voltage as an example.
  • the power supply 32, the resistor 33, the test line 12, and the GND terminal on the TFT substrate 1 in the detecting circuit 3 constitute a series circuit.
  • the voltage at point C that is, the voltage divided by the internal resistance of the test line 12, is known from the voltage division formula of the series circuit: The voltage is:
  • V c represents the voltage at point C
  • V represents the voltage of the power source 32
  • R T represents the resistance of the test line 12
  • R represents the resistance of the resistor 33.
  • the test platform 35 can perform voltage collection on the voltage of the C point through the analog-to-digital conversion interface 31 (ADC). If the collected voltage value is equal to the voltage of the power source 32, it is determined that there is a crack or a collapse of the edge of the TFT substrate 1. .
  • ADC analog-to-digital conversion interface 31
  • the timing of detecting the TFT substrate by the detecting circuit 3 may be after the substrate is cut, or after the TFT substrate is assembled into the LCM, or the LCM including the TFT substrate is assembled into a terminal.
  • the detecting circuit 3 can be an independent detecting circuit, and the detecting circuit 3 can be detected by externally connecting the detecting circuit 3; or the detecting circuit 3 can be integrated in the liquid crystal module or the terminal, and the terminal is used as a detecting platform, and the detecting circuit is controlled.
  • Software can test the terminal's own liquid Crystal module.
  • the TFT substrate 2 since the measurement points are not provided, the TFT substrate 2 is required after the substrate is cut, or after the TFT substrate 2 is assembled into the LCM, or the LCM including the TFT substrate 2 is assembled into a terminal.
  • the crack or chipping of the edge of the substrate is measured by the measuring circuit.
  • the test circuit 3 can also be used for measurement, and the method of measuring the test line 22 in the TFT substrate 2 by the test circuit 3 is the same as the method of measuring the test line 12 in the TFT substrate 1 by using the test circuit 3, and will not be described again. .
  • the electrical parameter of the test line of the TFT substrate is measured by a measuring tool, and whether the test line is turned on according to the electrical parameter of the test line, thereby determining whether the edge of the TFT substrate has a crack. Or collapse, compared with the prior art by visual measurement, it can avoid missed detection and improve detection efficiency, and can still realize the liquid crystal mode after the TFT substrate is assembled into a liquid crystal module or after the liquid crystal module is assembled into a whole machine. Whether the edge of the TFT substrate in the group has crack or chipping detection.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be electrical, mechanical or otherwise.
  • the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solution of the embodiment.

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Abstract

一种检测基板裂缝的方法、基板和检测电路，包括：在TFT基板（1、2）的玻璃基板（11、21）上的边缘一周设置具有开口（121、221）的非闭合测试线（12、22），通过测量测试线（12、22）的导通或断开就能够判断TFT基板（1、2）边缘是否具有裂缝或崩块，从而能够避免漏检并提高检测效率，并且在TFT基板（1、2）组装成液晶模组或在液晶模组组装成整机后依然能够实现对液晶模组中TFT基板（1、2）边缘是否具有裂缝或崩块的检测。

Description

检测基板裂缝的方法、 基板和检测电路 技术领域
本发明实施例涉及液晶面板制造领域， 尤其涉及一种检测基板裂缝的方 法、 基板和检测电路。 背景技术
TFT (Thin Film Transistor, 薄膜晶体管） 基板 （或者叫做 TFT玻璃） 是 构成 LCD (Liquid Crystal Display, 液晶显示器） 的一个基本部件， 也是关键 基础材料之一。 TFT基板是一种玻璃基板， 该玻璃基板是一种表面极其平整 的薄玻璃片， 在 LCD面板的制造过程中， 会在玻璃基板的表面蒸镀一层透明 导电层， 即 IT0 (氧化铟锡） 膜层， 经光刻加工制成透明导电图形， 这些图 形由像素图形和外引线图形组成。
在现有的制程中， 在一个整块 TFT基板制作完成后， 会切割成多个规定 尺寸的 TFT 基板。 比如， 现在现有的 5 代线最高阶段的基板尺寸是 1200*1300mm， 可以切割 6片 27英寸宽屏电视用的基板。而目前， 对于 TFT 基板的检测， 主要是在切割后进行的， 一般是检测人员通过 AOI (Automatic Optic Inspection, 自动光学检测）光学设备（比如显微镜）进行检测。 通过该 方法， 能够检测出切割过程中 TFT基板切割边沿出现的细小裂缝或崩块。
但是， 上述检测方法在在实现时主要依靠人工检测， 不但检测效率低， 还可能会出现漏检的情况， 并且上述检测方法只能检测切割过程中出现的细 小裂缝或崩块， 而 TFT基板在组装成 LCM (LCD Module,液晶模组） 的过程 以及运输过程中产生的裂缝或崩块是无法检测的， 而且 LCM在组装成整机 (比如组装成电视或手机） 的过程中产生的沿裂或崩块是也无法检测的。 发明内容
本发明实施例提供一种检测基板裂缝的方法、 基板和检测电路， 能够提 高检测效率， 避免出现漏检， 并且能够在 TFT基板在组装成 LCM以及 LCM 在组装成整机后对 TFT基板进行检测。 第一方面， 提供一种 TFT基板， 所述 TFT基板包括：
玻璃基板；
所述玻璃基板上设置有沿所述玻璃基板边缘一周且具有开口的非闭合测 试线；
所述开口由所述测试线的两个端点组成， 其中在所述测试线上距每个端 点的设定距离处设置有测试点， 所述测试点用于连接能够判断所述测试线通 断以判断所述 TFT基板的边缘是否具有裂缝或崩块的测量工具； 所述两个端 点中的一个端点接地。
结合第一方面， 在第一种可能的实现方式中， 所述开口位于柔性印刷电 路板与所述玻璃基板的圧合 FOG Bonding区域；
所述开口的两个端点通过柔性印刷电路板与第一连接器接口电性连接， 所述第一连接器接口用于与检测电路的连接器接口电性连接， 所述检测电路 用于测量所述测试线的通断以判断所述 TFT 基板的边缘是否具有裂缝或崩 块。
结合第一方面或第一方面的第一种可能的实现方式， 在第二种可能的实 现方式中， 制作所述测试线的导电层为 TFT基板制程中的任一导电层， 所述 测试线是在对所述导电层的一次构图工艺中与所述导电层的导电图案一同制 作出来的。
结合第一方面的第二种可能的实现方式， 在第三种可能的实现方式中， 所述导电层包括： 栅金属层、 源极漏极金属层、 透明导电薄膜中的任意一种； 所述制作所述测试线的导电层为 TFT基板制程中的任一导电层， 所述测试线 是在对所述导电层的一次构图工艺中与所述导电层的导电图案一同制作出来 的包括：
制作所述测试线的导电层为所述栅金属层， 所述测试线是在对所述栅金 属层的一次构图工艺中与栅金属线一同制作出来的；
或者，
制作所述测试线的导电层为所述源极漏极金属层， 所述测试线是在对所 述源极漏极金属层的一次构图工艺中与源极漏极金属线一同制作出来的； 或者，
制作所述测试线的导电层为所述透明导电薄膜， 所述测试线是在对所述 透明导电薄膜的一次构图工艺中与像素电极一同制作出来的。
结合第一方面的第三种可能的实现方式， 在第四种可能的实现方式中， 包括：
若制作所述测试线的导电层为所述栅金属层或所述源极漏极金属层， 所 述测试线与所述玻璃基板的边缘的距离为 150μπι ~200μπΐ;
若制作所述测试线的导电层为所述透明导电薄膜， 所述测试线与所述玻 璃基板的边缘的距离为 100μπι。
第二方面， 提供一种 TFT基板， 所述 TFT基板包括：
玻璃基板；
所述玻璃基板上设置有沿所述玻璃基板边缘一周且具有开口的非闭合测 试线；
所述开口由所述测试线的两个端点组成； 所述两个端点中的一个端点接 地；
所述开口位于柔性印刷电路板与所述玻璃基板的圧合 FOG Bonding 区 域， 所述开口的两个端点通过柔性印刷电路板与第一连接器接口电性连接， 所述第一连接器接口用于与检测电路的连接器接口电性连接， 所述检测电路 用于测量所述测试线的通断以判断所述 TFT 基板的边缘是否具有裂缝或崩 块。
结合第二方面， 在第一种可能的实现方式中， 制作所述测试线的导电层 为 TFT基板制程中的任一导电层， 所述测试线是在对所述导电层的一次构图 工艺中与所述导电层的导电图案一同制作出来的。
结合第二方面的第一种可能的实现方式， 在第二种可能的实现方式中， 所述导电层包括： 栅金属层、 源极漏极金属层、 透明导电薄膜中的任意一种； 所述制作所述测试线的导电层为 TFT基板制程中的任一导电层， 所述测试线 是在对所述导电层的一次构图工艺中与所述导电层的导电图案一同制作出来 的包括：
制作所述测试线的导电层为所述栅金属层， 所述测试线是在对所述栅金 属层的一次构图工艺中与栅金属线一同制作出来的；
或者，
制作所述测试线的导电层为所述源极漏极金属层， 所述测试线是在对所 述源极漏极金属层的一次构图工艺中与源极漏极金属线一同制作出来的； 或者，
制作所述测试线的导电层为所述透明导电薄膜， 所述测试线是在对所述 透明导电薄膜的一次构图工艺中与像素电极一同制作出来的。
结合第二方面的第二种可能的实现方式， 在第三种可能的实现方式中， 包括：
若制作所述测试线的导电层为所述栅金属层或所述源极漏极金属层， 所 述测试线与所述玻璃基板的边缘的距离为 150μπι ~200μπΐ;
若制作所述测试线的导电层为所述透明导电薄膜， 所述测试线与所述玻 璃基板的边缘的距离为 100μπι。
第三方面， 提供一种检测电路， 所述检测电路包括： 模数转换接口、 电 源、 电阻、 第二连接器接口、 测试平台；
其中， 所述电源与所述电阻的第一端电性连接， 所述电阻的第二端与所 述第二连接器接口电性连接， 所述模数转换接口的第一端与所述电阻的第二 端电性连接， 所述模数转换接口的第二端与所述测试平台电性连接， 当权利 要求第一方面的第一种可能的实现方式至第二方面的第三种可能的实现方式 中的任意一种所述的 TFT基板的中的第一连接器接口与所述第二连接器接口 电性连接时， 形成包括所述电源、 所述电阻、 所述 TFT基板的串联电路， 所 述测试平台用于测量所述串联电路的所述电阻、 所述第二连接器接口的连接 点处的电性参数， 并根据所述电性参数判断所述 TFT基板的边缘是否具有裂 缝或崩块。
结合第三方面， 在第一种可能的实现方式中， 所述第一连接器接口和所 述第二连接器接口为 BTB (Board to Board, 板对板） 接口；
其中， 所述第一连接器接口为 BTB 接口母座， 所述第二连接器接口为 BTB接口公座。
第四方面， 提供一种液晶显示器， 包括： 第一方面至第二方面的第三种 可能的实现方式中的任意一种所述的 TFT基板。
第五方面， 提供一种电子终端， 包括第四方面所述的液晶显示器。
第六方面， 提供一种检测基板裂缝的方法， 所述方法包括：
通过测量工具获取 TFT基板上的测试线的电性参数； 其中， 所述测试线 为沿所述 TFT基板的玻璃基板边缘一周且具有开口的非闭合测试线， 所述开 口由所述测试线的两个端点组成， 其中在所述测试线上距每个端点的设定距 离处设置有测试点， 所述测试点用于连接所述测量工具；
根据所述电性参数判断所述测试线通断以判断所述 TFT基板的边缘是否 具有裂缝或崩块。
结合第六方面，在第一种可能的实现方式中，所述通过测量工具获取 TFT 基板上的测试线的电性参数包括：
通过万用表获取所述测试线的电阻值。
结合第六方面的第一种可能的实现方式， 在第二种可能的实现方式中， 所述根据所述电性参数判断所述 TFT基板的边缘是否具有裂缝或崩块包括： 判断所述测试线的电阻值是否为无穷大， 若所述电阻值为无穷大， 则确 定所述 TFT基板的边缘具有裂缝或崩块； 若所述电阻值为不是无穷大， 则确 定所述 TFT基板的边缘不存在裂缝或崩块。
结合第六方面， 在第三种可能的实现方式中， 所述测量工具包括万用表、 外接电源， 所述万用表、 所述外接电源和所述测试线形成回路；
所述通过测量工具获取 TFT基板上的测试线的电性参数包括：
通过所述万用表获取所述测试线上的电流值。
结合第六方面的第三种可能的实现方式， 在第四种可能的实现方式中， 所述根据所述电性参数判断所述 TFT基板的边缘是否具有裂缝或崩块包括： 判断所述测试线上的所述电流值是否为零， 若所述电流值为零， 则确定 所述 TFT基板的边缘具有裂缝或崩块;若所述电流值不为零，则确定所述 TFT 基板的边缘不存在裂缝或崩块。
结合第六方面， 在第五种可能的实现方式中， 所述测量工具包括指示灯、 外接电源， 所述指示灯、 所述外接电源和所述测试线形成回路；
所述通过测量工具获取 TFT基板上的测试线的电性参数包括：
通过所述指示灯获取所述测试线为断开或导通。
结合第六方面的第五种可能的实现方式， 在第六种可能的实现方式中， 所述根据所述电性参数判断所述 TFT基板的边缘是否具有裂缝或崩块包括： 若所述测试线为断开， 则确定所述 TFT基板的边缘具有裂缝或崩块； 若 所述测试线为导通， 则确定所述 TFT基板的边缘不存在裂缝或崩块。 结合第六方面， 在第七种可能的实现方式中， 所述方法还包括： 所述开 口位于柔性印刷电路板与所述玻璃基板的圧合 FOG Bonding区域； 所述开口 的两个端点通过柔性印刷电路板与第一连接器接口电性连接， 所述第一连接 器接口用于与能够判断所述 TFT基板的所述测试线通断的检测电路的连接器 接口电性连接， 在所述 TFT基板组装成液晶模组后， 通过所述检测电路检测 所述液晶模组中的所述 TFT基板的边缘是否具有裂缝或崩块。
结合第六方面的第七种可能的实现方式， 在第八种可能的实现方式中， 所述方法还包括： 在所述液晶模组装成终端整机后， 通过所述检测电路检测 所述液晶模组中的所述 TFT基板的边缘是否具有裂缝或崩块。
结合第六方面的第七或第八种可能的实现方式， 在第九种可能的实现方 式中， 所述通过所述检测电路检测所述液晶模组中的所述 TFT基板的边缘是 否具有裂缝或崩块包括：
通过所述检测电路获取所述检测电路的中连接器处的电性参数； 根据所述电性参数判断所述液晶模组中的所述 TFT基板的边缘是否具有 裂缝或崩块。
结合第六方面的第九种可能的实现方式， 在第十种可能的实现方式中， 所述电性参数包括电压值或电流值；
所述根据所述电性参数判断所述液晶模组中的所述 TFT基板的边缘是否 具有裂缝或崩块包括：
判断所述电压值是否等于所述检测电路的电源电压， 若所述电压值等于 所述电源电压， 则确定所述液晶模组中的所述 TFT基板的边缘具有裂缝或崩 块； 否则， 确定所述液晶模组中的所述 TFT基板的边缘不存在裂缝或崩块； 或者，
判断所述电流值是否等于零， 若所述电压值等于零， 则确定所述液晶模 组中的所述 TFT基板的边缘具有裂缝或崩块； 否则， 确定所述液晶模组中的 所述 TFT基板的边缘不存在裂缝或崩块。
第七方面， 提供一种检测基板裂缝的方法， 所述方法包括：
通过检测电路获取 TFT基板与所述检测电路连接处的电性参数； 其中， 所述 TFT基板上设置有有沿所述玻璃基板边缘一周且具有开口的非闭合测试 线； 所述开口由所述测试线的两个端点组成； 所述两个端点中的一个端点接 地;所述开口位于柔性印刷电路板与所述玻璃基板的圧合 FOG Bonding区域， 所述开口的两个端点通过柔性印刷电路板与第一连接器接口电性连接， 所述 第一连接器接口用于与检测电路的连接器接口电性连接；
根据所述电性参数判断所述测试线的通断以判断所述 TFT基板的边缘是 否具有裂缝或崩块。
本发明实施例提供一种检测基板裂缝的方法、 基板和检测电路， 通过在 TFT基板的玻璃基板上的边缘一周设置具有开口的非闭合测试线， 通过测量 测试线的导通或断开就能够判断 TFT基板边缘是否具有裂缝或崩块， 相比现 有技术采用目视测量而言， 能够避免漏检并提高检测效率， 并且在 TFT基板 组装成液晶模组或在液晶模组组装成整机后依然能够实现对液晶模组中 TFT 基板边缘是否具有裂缝或崩块的检测。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作一简单地介绍， 显而易见地， 下 面描述中的附图是本发明的一些实施例， 对于本领域普通技术人员来讲， 在 不付出创造性劳动性的前提下， 还可以根据这些附图获得其他的附图。
图 1为本发明实施例提供的 TFT基板的结构示意图；
图 2为本发明实施例提供的 TFT基板的另一结构示意图；
图 3为本发明实施例提供的检测电路的结构示意图；
图 4为本发明实施例提供的 TFT基板与检测电路连接示意图；
图 5为本发明实施例提供的检测基板裂缝的方法的流程示意图； 图 6为本发明实施例提供的检测基板裂缝的方法的另一流程示意图。 具体实施方式 为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例中的附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例是本发明一部分实施例， 而不是全部的实施例。 基于 本发明中的实施例， 本领域普通技术人员在没有作出创造性劳动前提下所获 得的所有其他实施例， 都属于本发明保护的范围。 本发明实施例提供 TFT基板 1， 如图 1所示， 该 TFT基板 1包括： 玻璃基板 11 ;
玻璃基板 11上设置有沿玻璃基板边缘一周且具有开口 121的非闭合测试 线 12;
开口 121 由测试线 12的两个端点 A和 B组成， 其中在每个端点的设定 距离内设置有测试点， 例如图 1中所示的测试点 A1和测试点 B1分别位于端 点 A和端点 B附近， 测试点 A1和 B1用于连接能够判断测试线通断的测量 工具； 两个端点中的一个端点接地 （示例性的， 图 1中是端点 B接地， 一般 是接在 TFT基板 1的 GND端） 。 容易理解的是， 设定的距离大小本发明实 施例并不限定， 优选设定的距离选择为使得两个测试点靠近上述两个端点。
可选的， 如图 1所示， 开口 121位于玻璃基板上的 FPC (Flexible Printed Circuit，柔性印刷电路板）与玻璃基板的压合区域，该区域可以称为 FOG (FPC on Glass, 柔性线路板与玻璃电路板接装） 绑定 （FOG Bonding) 区域 13。 其 中， 上述开口 121 的位置为示例性的， 包括但不限于此， 在其他可能的实施 例中， 开口 121也可能位于其他位置。
可选的， 上述测试线 12可以利用现有的 TFT基板制程制作， 制作测试 线 12的导电层可以为现有 TFT基板制程中的任一导电层， 测试线 12是在对 导电层的一次构图工艺中与导电层的导电图案一同制作出来的。 其中， 值得 一提的是， 测试线 12上的测试点 A1和测试点 B1是与测试线 12—起制作出 来的。 在测试线 12制作完成后， 测试线 12上还会设置绝缘层， 其绝缘层上 可能还会设置其他金属层或绝缘层， 以便完成后续 TFT基板制程， 在测试线 12上覆盖的其它层上位于测试点 A1和测试点 B1处留有贯穿这些层的过孔， 以便漏出测试点 A1和测试点 B1 ,使得测试点 A1和测试点 B1能够与测量工 具连接。
其中， 这一导电层可以为栅金属层、 源极漏极金属层、 透明导电薄膜中 任意一种。
若制作测试线的导电层为栅金属层， 测试线是在对栅金属层的一次构图 工艺中与栅金属线一同制作出来的。
或者，
制作测试线的导电层为源极漏极金属层， 测试线是在对源极漏极金属层 的一次构图工艺中与源极漏极金属线一同制作出来的。
或者，
制作测试线的导电层为透明导电薄膜， 测试线是在对透明导电薄膜的一 次构图工艺中与像素电极一同制作出来的。
上述导电层的制作可以采用磁控溅射或其他成膜方法， 沉积一定厚度的 金属层， 其中， 若是制作栅金属层、 源极漏极金属层， 则可以使用钼、 铝、 铝镍合金、 钼钨合金、 铬或铜等金属， 也可使用上述几种材料的组合； 若是 制作透明导电薄膜， 则可以采用氧化铟锡 （ITO) 、 氧化铟锌 （IZO) 或其他 透明电极材料。
上述的一次构图工艺可以包括： 在制作好金属层后， 通过显影、 刻蚀等 工艺得到该测试线 12以及该导电层的其他导电图案， 可见该测试线 12是利 用现有的制程制作的， 并未增加工艺复杂度。
另外， 测试线 12与玻璃基板 11的边缘的距离是由工艺能力决定的， 在 不同的金属层中制作， 测试线 12与玻璃基板 11的边缘的距离也是不同的， 比如：
若测试线 12是在制作栅金属层或源极漏极金属层的一次构图工艺中，与 栅金属层或源极漏极金属层一同制作出来的， 测试线 12与玻璃基板 11的边 缘的距离为 150μπι (纳米） ~200μπι。
若测试线 12是在制作透明导电薄膜的一次构图工艺中，与透明导电薄膜 一同制作出来的， 测试线 12与玻璃基板 11的边缘的距离为 ΙΟΟμπι左右。
在检测时， 可以采用万用表等测量工具（也称治具）对测试线 12的电性 参数进行测量， 比如可以将万用表的两只测量笔分别连接在测试线 12的两个 测量点上 A1和 B1上， 通过万用表获取测试线 12的电阻值。
若测试线 12的电阻值为无穷大， 则说明测试线 12已经断开， 可以确定 TFT基板的边缘具有裂缝或崩块。若测试线 12的电阻值不是无穷大， 则说明 测试线 12是完整的， 可以确定 TFT基板的边缘不存在裂缝或崩块。
或者，
可以将万用表、 外接电源、 测试线 12串联连接形成回路， 通过万用表获 取测试线 12上的电流值。
若测试线 12上的电流值为零，则说明测试线 12已经断开，可以确定 TFT 基板的边缘具有裂缝或崩块； 否则， 说明测试线 12是完整的， 可以确定 TFT 基板的边缘不存在裂缝或崩块。
又或者，
指示灯、 外接电源、 测试线 12串联连接形成回路， 通过指示灯获取测试 线 12为断开或导通的指示。
若测试线 12为断开， 则可以确定 TFT基板的边缘具有裂缝或崩块； 若 测试线为导通， 则可以确定 TFT基板的边缘不存在裂缝或崩块。
当然， 上述的几种测量方法仅仅为示例性的， 还可以采用其他检测方法 检测测试线 12导通或断开。
可选的， 测试线 12的两个端点 A和 B还可以通过 FPC与第一连接器接 口 14电性连接，第一连接器接口 14用于与检测电路的连接器接口电性连接。 其中， 该检测电路为能够检测出 TFT基板 1上的测试线 12导通或断开的任 意一种检测电路。 通过该检测电路检测 TFT基板 1的时机可以为在完成基板 切割后， 或者该 TFT基板 1被组装到 LCM中之后， 或者包括 TFT基板 1的 LCM被组装成终端后。 该检测电路， 可以为独立的检测电路， TFT基板 1的 通过外接该检测电路进行检测； 或者该检测电路也可以集成在液晶模组或终 端中， 将终端作为检测平台， 通过控制检测电路的软件就可以测试该终端自 己的液晶模块。 示例性的， 该检测电路可以为下文实施例提供的检测电路 3。
其中， 上述第一连接器接口 14和检测电路的连接器接口可以采用 BTB 接口 （或称为 B2B接口） ， 例如， 第一连接器接口 14为 BTB接口的母座， 检测电路的连接器接口为 BTB接口的公座。
当然， 连接器接口采用 BTB接口仅仅为示例性的， 除了 BTB接口之外 也可以采用其他接口。
本发明实施例提供的 TFT基板，通过在 TFT基板的玻璃基板上的边缘一 周设置具有开口的非闭合测试线， 该开口由测试线的两个端点组成， 其中在 每个端点设置有测试点，该测试点用于连接能够判断测试线通断的测量工具， 通过测量工具测量测试线的导通或断开就能够判断 TFT基板边缘是否具有裂 缝或崩块， 相比现有技术采用目视测量而言， 能够避免漏检并提高检测效率， 并且在 TFT基板组装成液晶模组或在液晶模组组装成整机后依然能够实现对 液晶模组中 TFT基板边缘是否具有裂缝或崩块的检测。 本发明实施例提供 TFT基板 2， 如图 2所示， 该 TFT基板 2包括： 玻璃基板 21 ;
玻璃基板 21上设置有沿玻璃基板 21边缘一周且具有开口 221的非闭合 测试线 22;
开口 221由所述测试线 22的两个端点 C和 D组成， 两个端点中的一个 端点接地（示例性的， 图 2中是端点 D接地，一般是接在 TFT基板 2的 GND ¾ ) ；
开口 221位于 FOG Bonding区域 23， 开口 221的两个端点 A和 B通过 柔性印刷电路板与第一连接器接口 24电性连接， 第一连接器接口 24用于与 检测电路的连接器接口电性连接，检测电路用于测量测试线 22的通断以判断 TFT基板 2的边缘是否具有裂缝或崩块。
可选的， 上述测试线 22可以利用现有的 TFT基板制程制作， 制作测试 线 22的导电层可以为现有 TFT基板制程中的任一导电层， 测试线 22是在该 对导电层的一次构图工艺中与该导电层的导电图案一同制作出来的。 具体的 制作工艺与 TFT基板 1中的测试线 12的工艺完全一致， 不再赘述。
在检测时，通过 TFT基板 2外接的上述检测电路来检测 TFT基板 2的边 缘是否具有裂缝或崩块。 其中， 该检测电路为能够检测出 TFT基板 2上的测 试线 22导通或断开的任意一种检测电路。 通过该检测电路检测 TFT基板 2 的时机可以为在完成基板切割后，或者该 TFT基板 2被组装到 LCM中之后， 或者包括 TFT基板 2的 LCM被组装成终端后。 该检测电路， 可以为独立的 检测电路， TFT基板 2的通过外接该检测电路进行检测； 或者该检测电路也 可以集成在液晶模组或终端中， 将终端作为检测平台， 通过控制检测电路的 软件就可以测试该终端自己的液晶模块。 示例性的， 该检测电路可以为下文 实施例提供的检测电路 3。
本发明实施例提供的 TFT基板，通过在 TFT基板的玻璃基板上的边缘一 周设置具有开口的非闭合测试线， 该开口由测试线的两个端点组成， 开口的 两个端点和通过柔性印刷电路板与第一连接器接口电性连接， 第一连接器接 口用于与检测电路的连接器接口电性连接， 从而可以通过检测电路测量测试 线的通断以判断 TFT基板的边缘是否具有裂缝或崩块， 相比现有技术采用目 视测量而言， 能够避免漏检并提高检测效率， 并且在 TFT基板组装成液晶模 组或在液晶模组组装成整机后依然能够实现对液晶模组中 TFT基板边缘是否 具有裂缝或崩块的检测。
本发明实施例还提供一种检测电路 3， 如图 3所示， 检测电路 3包括： 模数转换接口 31、 电源 32、 电阻 33、第二连接器接口 34、 测试平台 35 ; 其中， 电源 32与电阻 33的第一端电性连接， 电阻 33的第二端与第二连接器 接口 34电性连接， 模数转换接口 31的第一端与电阻 33的第二端电性连接， 模数转换接口 31的第二端与测试平台 35电性连接， 当 TFT基板 1的中的第 一连接器接口 14 (或者 TFT基板 2的中的第一连接器接口 24 ) 与第二连接 器接口 34电性连接， 形成包括电源 32、 电阻 33、 TFT基板 1 (或 TFT基板 2) 的串联电路 （实际连接图可以如图 4所示） ， 测试平台 35用于测量电阻
33、第二连接器接口 34的连接点 C处的电性参数，并根据电性参数判断 TFT 基板 1 (或者 TFT基板 2 ) 的边缘是否具有裂缝或崩块。
示例性的， 以检测电路 3连接 TFT基板 1为例 （图 3中采用 TFT基板 2 的实施方式未示出） ， 由于 TFT基板 1中的测试线 12具有内阻， 因此电源 32、 电阻 33、测试线 12和 TFT基板 1上的 GND端组成了串联电路。根据图
3所示， C点的电压即测试线 12内阻所分的电压， 由串联电路的分压公式可 知： 该电压为：
R + RT
其中， Vc表示 C点的电压， V表示电源 23 的电压， RT表示测试线 12 的电阻， R表示电阻 33 的电阻， 其中电源 32可以为 1.8V (伏） ， 电阻 33 可以为 1ΜΩ (兆欧姆） 。
由于， 当 TFT基板 1的边缘存在裂缝或崩块时， 裂缝或崩块处的测试线 12会断开， 此时测试线 12的电阻 RT为无穷大， 则 Vc会等于 V。
因此，只需要测量出 C点的电压等于电源 32的电压时，就可以确定 TFT 基板 1的边缘存在裂缝或崩块。
通过该检测电路 3检测 TFT基板的时机可以为在完成基板切割后， 或者 该 TFT基板被组装到 LCM中之后， 或者包括 TFT基板的 LCM被组装成终 端后。 该检测电路 3， 可以为独立的检测电路， TFT基板的通过外接该检测 电路 3进行检测； 或者该检测电路 3也可以集成在液晶模组或终端中， 将终 端作为检测平台， 通过控制检测电路的软件就可以测试该终端自己的液晶模 块。
本发明实施例提供的检测电路， 能够通过测量测试线的导通或断开来判 断 TFT基板边缘是否具有裂缝或崩块， 相比现有技术采用目视测量而言， 能 够避免漏检并提高检测效率， 并且在 TFT基板组装成液晶模组或在液晶模组 组装成整机后依然能够实现对液晶模组中 TFT基板边缘是否具有裂缝或崩块 本发明实施例还提供一种液晶显示器， 该液晶显示器包括： 前述实施例 提供的 TFT基板 1 (或 TFT基板 2) ， 以及液晶、 彩膜基板、 偏光片、 背光 和导光板。
其中， 背光和导光板为液晶显示器提供光源， 在背光和导光板的上方为 该 TFT基板 1 (或 TFT基板 2) ， 该 TFT基板 1 (或 TFT基板 2) 和彩膜基 板之间设置有液晶， 液晶设置在 TFT基板 1 (或 TFT基板 2) 和彩膜基板之 间的封框胶内， 偏光片设置在彩膜基板的上方。
本发明实施例还提供一种电子终端， 该电子终端包括： 上述液晶显示器。 可选的， 上述液晶显示器还可以包括前述实施例所述的检测电路 3。 本发明实施例提供一种检测基板裂缝的方法， 如图 5所示， 该方法包括：
5101、 通过测量工具获取 TFT基板上的测试线的电性参数。
其中， 该 TFT基板可以为前述实施例提供的 TFT基板 1， 如图 1所示， TFT基板 1上具有测试线 12，测试线 12为沿 TFT基板 1的玻璃基板 11边缘 一周且具有开口 121 的非闭合测试线， 开口 121 由测试线 12的两个端点 A 和 B组成， 其中在每个端点的设定距离内设置有测试点， 如图 1所示的 A1 和 B1 , 测试点 A1和 B1用于连接能够测量测试线 12通断的测量工具。
5102、 根据电性参数判断测试线的通断以判断 TFT基板的边缘是否具有 裂缝或崩块。
其中， 电性参数可以是电阻值、 电流值、 电压值等参数。
本发明实施例提供的检测基板裂缝的方法， 通过测量工具测量 TFT基板 的测试线的电性参数， 根据测试线的电性参数判断该测试线是否导通， 从而 能够判断 TFT基板边缘是否具有裂缝或崩块， 相比现有技术采用目视测量而 言， 能够避免漏检并提高检测效率， 并且在 TFT基板组装成液晶模组或在液 晶模组组装成整机后依然能够实现对液晶模组中 TFT基板边缘是否具有裂缝 或崩块的检测。
为了使本领域技术人员能够更清楚地理解本发明实施例提供的技术方 案， 下面通过具体的实施例， 对本发明的实施例提供的检测基板裂缝的方法 进行详细说明， 如图 6所示， 该方法包括：
S201、 通过测量工具获取 TFT基板上的测试线的电性参数。
示例性的， TFT基板可以是前述实施例提供的 TFT基板 1， 如图 1所示， 具体可参照 S101 , 不再赘述。
测量工具用于测试测试线 12是导通或断开，故电性参数通常可以为电阻 值、 电流值、 电压值等参数， 因此可以采用万用表等测量工具。
例如，可以将万用表的两只测量笔分别连接在测试线 12的两个测量点上
A1和 B1上， 通过万用表获取测试线 12的电阻值。
或者，
测量工具还可以为万用表、 外接电源， 可以将万用表、 外接电源、 测试 线 12串联连接形成回路， 通过万用表获取测试线 12上的电流值。
又或者，
测量工具还可以为指示灯、 外接电源， 将指示灯、 外接电源、 测试线 12 串联连接形成回路， 通过指示灯获取测试线 12为断开或导通的指示。
S202、根据电性参数判断 TFT基板的边缘是否具有裂缝或崩块。具体的， 根据 S201中获取的电性参数：
若测试线 12的电阻值为无穷大， 则说明测试线 12已经断开， 可以确定
TFT基板的边缘具有裂缝或崩块。若测试线 12的电阻值不是无穷大， 则说明 测试线 12是完整的， 可以确定 TFT基板的边缘不存在裂缝或崩块。
或者，
若测试线 12上的电流值为零，则说明测试线 12已经断开，可以确定 TFT 基板的边缘具有裂缝或崩块； 否则， 说明测试线 12是完整的， 可以确定 TFT 基板的边缘不存在裂缝或崩块。
或者，
若指示灯指示测试线 12为断开， 则可以确定 TFT基板的边缘具有裂缝 或崩块； 若指示灯指示测试线为导通， 则可以确定 TFT基板的边缘不存在裂 缝或崩块。 当然， 上述的几种测量方法仅仅为示例性的， 还可以采用其他检测方法 检测测试线 12导通或断开以判断 TFT基板的边缘是否存在裂缝或崩块。
S203、 在 TFT基板组装成液晶模组后， 通过检测电路检测液晶模组中的 TFT基板的边缘是否具有裂缝或崩块。
S204、在液晶模组装成终端整机后，通过检测电路检测液晶模组中的 TFT 基板的边缘是否具有裂缝或崩块。
例如， 上述检测电路可以为前述实施例提供的检测电路 3， 以检测电路 3 与 TFT基板 1连接为例， 如图 4所示， 检测电路 3可以通过连接器与 TFT基 板 1连接，其中 TFT基板 1具有连接器第一接口 14 (例如 BTB接口的母座）， 检测电路 3具有连接器第二接口 34 (例如 BTB接口的公座）， 通过检测电路 3获取检测电路的中连接器处 （即电阻 33与第二连接器接口 34的连接点， 图 3中 C点） 的电性参数， 此处以电压为例。
由于检测电路 3中的电源 32、 电阻 33、 测试线 12和 TFT基板 1上的 GND端组成了串联电路。 根据图 3所示， C点的电压即测试线 12内阻所分 的电压， 由串联电路的分压公式可知： 该电压为：
R + RT
其中， Vc表示 C点的电压， V表示电源 32的电压， RT表示测试线 12 的电阻， R表示电阻 33的电阻。
由于， 当 TFT基板 1的边缘存在裂缝或崩块时， 裂缝或崩块处的测试线 12会断开， 此时测试线 12的电阻 RT为无穷大， 则 Vc会等于 V。
因此，只需要测量出 C点的电压等于电源 32的电压时，就可以确定 TFT 基板 1的边缘存在裂缝或崩块。
示例性的， 测试平台 35可以通过模数转换接口 31 (ADC) 对 C点的电 压进行电压采集， 若采集到的电压值等于电源 32的电压时， 确定 TFT基板 1 的边缘存在裂缝或崩块。
其中，通过该检测电路 3检测 TFT基板的时机可以为在完成基板切割后， 或者该 TFT基板被组装到 LCM中之后， 或者包括 TFT基板的 LCM被组装 成终端后。 该检测电路 3， 可以为独立的检测电路， TFT基板的通过外接该 检测电路 3进行检测； 或者该检测电路 3也可以集成在液晶模组或终端中， 将终端作为检测平台， 通过控制检测电路的软件就可以测试该终端自己的液 晶模块。
另外， 对于 TFT基板 2， 由于未设置测量点， 因此 TFT基板 2在完成基 板切割后， 或者该 TFT基板 2被组装到 LCM中之后， 或者包括 TFT基板 2 的 LCM被组装成终端后， 都需要通过测量电路来测量基板边缘的裂缝或崩 块。 具体的， 也可以采用测试电路 3进行测量， 且 用测试电路 3测量 TFT 基板 2中的测试线 22的方法与上述采用测试电路 3测量 TFT基板 1中的测 试线 12的方法相同， 不再赘述。
本发明实施例提供的检测基板裂缝的方法， 通过测量工具测量 TFT基板 的测试线的电性参数， 根据测试线的电性参数判断该测试线是否导通， 从而 能够判断 TFT基板边缘是否具有裂缝或崩块， 相比现有技术采用目视测量而 言， 能够避免漏检并提高检测效率， 并且在 TFT基板组装成液晶模组或在液 晶模组组装成整机后依然能够实现对液晶模组中 TFT基板边缘是否具有裂缝 或崩块的检测。
在本发明所提供的几个实施例中， 应该理解到， 所揭露的装置和方法， 可以通过其它的方式实现。例如， 以上所描述的装置实施例仅仅是示意性的， 例如， 所述单元的划分， 仅仅为一种逻辑功能划分， 实际实现时可以有另外 的划分方式， 例如多个单元或组件可以结合或者可以集成到另一个系统， 或 一些特征可以忽略， 或不执行。 另一点， 所显示或讨论的相互之间的耦合或 直接耦合或通信连接可以是通过一些接口， 装置或单元的间接耦合或通信连 接， 可以是电性， 机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的， 作 为单元显示的部件可以是或者也可以不是物理单元。 可以根据实际的需要选 择其中的部分或者全部单元来实现本实施例方案的目的。
本领域技术人员可以清楚地了解到， 为描述的方便和简洁， 仅以上述各 功能模块的划分进行举例说明， 实际应用中， 可以根据需要而将上述功能分 配由不同的功能模块完成， 即将装置的内部结构划分成不同的功能模块， 以 完成以上描述的全部或者部分功能。 上述描述的装置的具体工作过程， 可以 参考前述方法实施例中的对应过程， 在此不再赘述。

Claims

权 利 要 求 书
1、 一种薄膜晶体管 TFT基板， 其特征在于， 所述 TFT基板包括： 玻璃基板；
所述玻璃基板上设置有沿所述玻璃基板边缘一周且具有开口的非闭合测 试线；
所述开口由所述测试线的两个端点组成，其中在所述测试线上距每个端 点的设定距离处设置有测试点， 所述测试点用于连接能够判断所述测试线通 断以判断所述 TFT基板的边缘是否具有裂缝或崩块的测量工具； 所述两个端 点中的一个端点接地。
2、 根据权利要求 1所述的 TFT基板， 其特征在于， 所述开口位于柔性 印刷电路板与所述玻璃基板的圧合 FOG Bonding区域；
所述开口的两个端点通过柔性印刷电路板与第一连接器接口电性连接， 所述第一连接器接口用于与检测电路的连接器接口电性连接， 所述检测电路 用于测量所述测试线的通断以判断所述 TFT基板的边缘是否具有裂缝或崩 块。
3、 根据权利要求 1或 2所述的 TFT基板， 其特征在于， 制作所述测试 线的导电层为 TFT基板制程中的任一导电层， 所述测试线是在对所述导电层 的一次构图工艺中与所述导电层的导电图案一同制作出来的。
4、 根据权利要求 3所述的 TFT基板， 其特征在于， 所述导电层包括： 栅金属层、 源极漏极金属层、 透明导电薄膜中的任意一种； 所述制作所述测 试线的导电层为 TFT基板制程中的任一导电层， 所述测试线是在对所述导电 层的一次构图工艺中与所述导电层的导电图案一同制作出来的包括：
制作所述测试线的导电层为所述栅金属层， 所述测试线是在对所述栅金 属层的一次构图工艺中与栅金属线一同制作出来的；
或者，
制作所述测试线的导电层为所述源极漏极金属层， 所述测试线是在对所 述源极漏极金属层的一次构图工艺中与源极漏极金属线一同制作出来的； 或者，
制作所述测试线的导电层为所述透明导电薄膜， 所述测试线是在对所述 透明导电薄膜的一次构图工艺中与像素电极一同制作出来的。
5、 根据权利要求 4所述的 TFT基板， 其特征在于， 包括： 若制作所述测试线的导电层为所述栅金属层或所述源极漏极金属层， 所 述测试线与所述玻璃基板的边缘的距离为 150μπι ~200μπΐ;
若制作所述测试线的导电层为所述透明导电薄膜， 所述测试线与所述玻 璃基板的边缘的距离为 100μπι。
6、 一种 TFT基板， 其特征在于， 所述 TFT基板包括：
玻璃基板；
所述玻璃基板上设置有沿所述玻璃基板边缘一周且具有开口的非闭合测 试线；
所述开口由所述测试线的两个端点组成； 所述两个端点中的一个端点接 地；
所述开口位于柔性印刷电路板与所述玻璃基板的圧合 FOG Bonding区 域， 所述开口的两个端点通过柔性印刷电路板与第一连接器接口电性连接， 所述第一连接器接口用于与检测电路的连接器接口电性连接， 所述检测电路 用于测量所述测试线的通断以判断所述 TFT基板的边缘是否具有裂缝或崩 块。
7、 根据权利要求 6所述的 TFT基板， 其特征在于， 制作所述测试线的 导电层为 TFT基板制程中的任一导电层， 所述测试线是在对所述导电层的一 次构图工艺中与所述导电层的导电图案一同制作出来的。
8、 根据权利要求 7所述的 TFT基板， 其特征在于， 所述导电层包括： 栅金属层、 源极漏极金属层、 透明导电薄膜中的任意一种； 所述制作所述测 试线的导电层为 TFT基板制程中的任一导电层， 所述测试线是在对所述导电 层的一次构图工艺中与所述导电层的导电图案一同制作出来的包括：
制作所述测试线的导电层为所述栅金属层， 所述测试线是在对所述栅金 属层的一次构图工艺中与栅金属线一同制作出来的；
或者，
制作所述测试线的导电层为所述源极漏极金属层， 所述测试线是在对所 述源极漏极金属层的一次构图工艺中与源极漏极金属线一同制作出来的； 或者，
制作所述测试线的导电层为所述透明导电薄膜， 所述测试线是在对所述 透明导电薄膜的一次构图工艺中与像素电极一同制作出来的。
9、 根据权利要求 8所述的 TFT基板， 其特征在于， 包括：
若制作所述测试线的导电层为所述栅金属层或所述源极漏极金属层， 所 述测试线与所述玻璃基板的边缘的距离为 150μπι ~200μπΐ;
若制作所述测试线的导电层为所述透明导电薄膜， 所述测试线与所述玻 璃基板的边缘的距离为 100μπι。
10、 一种检测电路， 其特征在于， 所述检测电路包括： 模数转换接口、 电源、 电阻、 第二连接器接口、 测试平台；
其中， 所述电源与所述电阻的第一端电性连接， 所述电阻的第二端与所 述第二连接器接口电性连接， 所述模数转换接口的第一端与所述电阻的第二 端电性连接， 所述模数转换接口的第二端与所述测试平台电性连接， 当权利 要求 2至 9任意一种 TFT基板的中的第一连接器接口与所述第二连接器接口 电性连接时， 形成包括所述电源、 所述电阻、 所述 TFT基板的串联电路； 所 述测试平台用于测量所述串联电路的所述电阻、 所述第二连接器接口的连接 点处的电性参数， 并根据所述电性参数判断所述 TFT基板的边缘是否具有裂 缝或崩块。
11、 根据权利要求 10所述的检测电路， 其特征在于， 所述第一连接器接 口和所述第二连接器接口为板对板 ΒΤΒ接口；
其中， 所述第一连接器接口为 ΒΤΒ接口母座， 所述第二连接器接口为 ΒΤΒ接口公座。
12、 一种液晶显示器， 其特征在于， 包括： 权利要求 1至 9任意一种所 述的薄膜晶体管 TFT基板。
13、一种电子终端， 其特征在于，包括：权利要求 12所述的液晶显示器。
14、 一种检测基板裂缝的方法， 其特征在于， 所述方法包括：
通过测量工具获取 TFT基板上的测试线的电性参数； 其中， 所述测试线 为沿所述 TFT基板的玻璃基板边缘一周且具有开口的非闭合测试线， 所述开 口由所述测试线的两个端点组成， 其中在所述测试线上距每个端点的设定距 离处设置有测试点， 所述测试点用于连接所述测量工具；
根据所述电性参数判断所述测试线的通断以判断所述 TFT基板的边缘是 否具有裂缝或崩块。
15、 根据权利要求 14所述的方法， 其特征在于， 所述通过测量工具获取 TFT基板上的测试线的电性参数包括：
通过万用表获取所述测试线的电阻值。
16、 根据权利要求 15所述的方法， 其特征在于， 所述根据所述电性参数 判断所述 TFT基板的边缘是否具有裂缝或崩块包括：
判断所述测试线的电阻值是否为无穷大， 若所述电阻值为无穷大， 则确 定所述 TFT基板的边缘具有裂缝或崩块； 若所述电阻值为不是无穷大， 则确 定所述 TFT基板的边缘不存在裂缝或崩块。
17、 根据权利要求 14所述的方法， 其特征在于， 所述测量工具包括万用 表、 外接电源， 所述万用表、 所述外接电源和所述测试线形成回路；
所述通过测量工具获取 TFT基板上的测试线的电性参数包括：
通过所述万用表获取所述测试线上的电流值。
18、 根据权利要求 17所述的方法， 其特征在于， 所述根据所述电性参数 判断所述 TFT基板的边缘是否具有裂缝或崩块包括：
判断所述测试线上的所述电流值是否为零， 若所述电流值为零， 则确定 所述 TFT基板的边缘具有裂缝或崩块;若所述电流值不为零，则确定所述 TFT 基板的边缘不存在裂缝或崩块。
19、 根据权利要求 14所述的方法， 其特征在于， 所述测量工具包括指示 灯、 外接电源， 所述指示灯、 所述外接电源和所述测试线形成回路；
所述通过测量工具获取 TFT基板上的测试线的电性参数包括：
通过所述指示灯获取所述测试线为断开或导通。
20、 根据权利要求 19所述的方法， 其特征在于， 所述根据所述电性参数 判断所述 TFT基板的边缘是否具有裂缝或崩块包括：
若所述测试线为断开， 则确定所述 TFT基板的边缘具有裂缝或崩块； 若 所述测试线为导通， 则确定所述 TFT基板的边缘不存在裂缝或崩块。
21、 根据权利要求 14所述的方法， 其特征在于， 所述方法还包括： 所述 开口位于柔性印刷电路板与所述玻璃基板的圧合 FOG Bonding区域； 所述开 口的两个端点通过柔性印刷电路板与第一连接器接口电性连接， 所述第一连 接器接口用于与能够判断所述 TFT基板的所述测试线通断的检测电路的连接 器接口电性连接， 在所述 TFT基板组装成液晶模组后， 通过所述检测电路检 测所述液晶模组中的所述 TFT基板的边缘是否具有裂缝或崩块。
22、 根据权利要求 21所述的方法， 其特征在于， 所述方法还包括： 在所 述液晶模组装成终端整机后， 通过所述检测电路检测所述液晶模组中的所述 TFT基板的边缘是否具有裂缝或崩块。
23、 根据权利要求 21或 22所述的方法， 其特征在于， 所述通过所述检 测电路检测所述液晶模组中的所述 TFT基板的边缘是否具有裂缝或崩块包 括：
通过所述检测电路获取所述检测电路的中连接器处的电性参数； 根据所述电性参数判断所述液晶模组中的所述 TFT基板的边缘是否具有 裂缝或崩块。
24、 根据权利要求 23所述的方法， 其特征在于， 所述电性参数包括电压 值或电流值；
所述根据所述电性参数判断所述液晶模组中的所述 TFT基板的边缘是否 具有裂缝或崩块包括：
判断所述电压值是否等于所述检测电路的电源电压， 若所述电压值等于 所述电源电压， 则确定所述液晶模组中的所述 TFT基板的边缘具有裂缝或崩 块； 否则， 确定所述液晶模组中的所述 TFT基板的边缘不存在裂缝或崩块； 或者，
判断所述电流值是否等于零， 若所述电压值等于零， 则确定所述液晶模 组中的所述 TFT基板的边缘具有裂缝或崩块； 否则， 确定所述液晶模组中的 所述 TFT基板的边缘不存在裂缝或崩块。
25、 一种检测基板裂缝的方法， 其特征在于， 所述方法包括：
通过检测电路获取 TFT基板与所述检测电路连接处的电性参数； 其中， 所述 TFT基板上设置有沿所述玻璃基板边缘一周且具有开口的非闭合测试 线； 所述开口由所述测试线的两个端点组成； 所述两个端点中的一个端点接 地;所述开口位于柔性印刷电路板与所述玻璃基板的圧合 FOG Bonding区域， 所述开口的两个端点通过柔性印刷电路板与第一连接器接口电性连接， 所述 第一连接器接口用于与检测电路的连接器接口电性连接；
根据所述电性参数判断所述测试线的通断以判断所述 TFT基板的边缘是 否具有裂缝或崩块。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105976744A (zh) * 2016-06-24 2016-09-28 上海与德科技有限公司 一种屏模组、电子设备及屏模组的微裂纹检测方法
US10267844B2 (en) 2016-06-27 2019-04-23 Au Optronics Corporation Panel structure with detecting circuit and detecting circuit for panel
CN111508401A (zh) * 2020-06-12 2020-08-07 京东方科技集团股份有限公司 裂纹检测电路、显示面板及裂纹检测方法
CN112230487A (zh) * 2020-09-22 2021-01-15 江西兴泰科技有限公司 电子纸模组及检测其崩边暗裂的方法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102454188B1 (ko) * 2016-04-18 2022-10-13 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 검사 방법
US10643511B2 (en) * 2016-08-19 2020-05-05 Apple Inc. Electronic device display with monitoring circuitry
KR102631799B1 (ko) 2016-11-11 2024-02-02 삼성디스플레이 주식회사 표시장치 및 그의 검사방법
WO2018138105A1 (en) * 2017-01-27 2018-08-02 Merck Patent Gmbh Method for detecting breakage of a substrate of a switchable optical element and switchable optical device
CN106681075B (zh) * 2017-03-23 2019-05-28 京东方科技集团股份有限公司 显示面板、阵列基板及其制造方法、检测电路
CN107863055B (zh) * 2017-11-29 2021-06-22 武汉天马微电子有限公司 一种柔性基板及其状态检测方法、显示装置
CN110211517B (zh) * 2018-03-27 2021-03-16 京东方科技集团股份有限公司 显示基板及其检测方法、显示装置
EP3651304B1 (en) * 2018-11-07 2021-04-07 Siemens Gamesa Renewable Energy Innovation & Technology, S.L. Method for performing a testing procedure of an electrical power system for a wind turbine and an electrical power system
KR102572345B1 (ko) 2018-11-15 2023-08-29 삼성디스플레이 주식회사 표시 장치 및 그 검사 방법
CN110264891B (zh) * 2019-07-18 2022-02-01 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
CN110608871B (zh) * 2019-09-20 2021-05-25 京东方科技集团股份有限公司 像素检测电路、显示装置及检测方法
KR20210044356A (ko) * 2019-10-14 2021-04-23 삼성디스플레이 주식회사 표시 장치
CN110957329B (zh) * 2019-11-29 2022-04-26 武汉华星光电技术有限公司 显示模组及显示模组的制作方法
KR20210090752A (ko) * 2020-01-10 2021-07-21 삼성디스플레이 주식회사 표시패널 및 이의 제조 방법
CN112309880B (zh) * 2020-02-17 2023-05-19 成都华微电子科技股份有限公司 芯片边缘损坏检测方法和电路
CN112259587B (zh) * 2020-10-21 2024-02-20 京东方科技集团股份有限公司 一种显示面板、制作方法、检测方法和显示装置
CN113205758A (zh) * 2021-04-29 2021-08-03 京东方科技集团股份有限公司 显示模组、裂纹检测方法及显示装置
CN113889013B (zh) * 2021-11-17 2024-05-17 合肥京东方光电科技有限公司 面板裂纹检测电路、方法、显示模组及装置
CN115078469A (zh) * 2022-06-17 2022-09-20 福建华佳彩有限公司 一种玻璃基板缺陷检测方法及装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1619299A (zh) * 2003-11-21 2005-05-25 布鲁克斯自动化机械亚洲株式会社 玻璃基板边缘部分的破损检测装置及方法
CN201007763Y (zh) * 2007-03-01 2008-01-16 北京京东方光电科技有限公司 一种lcd玻璃基板破碎检测电路
JP2009085925A (ja) * 2007-10-03 2009-04-23 Seiko Epson Corp リーク欠陥検出方法
JP2009093132A (ja) * 2007-09-21 2009-04-30 Mitsubishi Electric Corp 液晶表示装置用セル及びその製造方法、並びに液晶表示装置の製造方法
KR20090078566A (ko) * 2008-01-15 2009-07-20 주식회사 디쌤 기판 에지 검사장치 및 방법
CN101652705A (zh) * 2007-04-25 2010-02-17 夏普株式会社 液晶显示面板及其检查方法
CN102338943A (zh) * 2010-07-27 2012-02-01 北京京东方光电科技有限公司 阵列基板、液晶面板和液晶显示器以及制造和检测方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070112644A (ko) * 2006-05-22 2007-11-27 삼성전자주식회사 어레이 기판, 이를 갖는 액정표시장치, 및 이의 검사 방법
US20090079928A1 (en) 2007-09-21 2009-03-26 Mitsubishi Electric Corporation Cell for liquid crystal display devices and method of manufacturing same, and method of manufacturing liquid crystal display device
TWI480655B (zh) * 2011-04-14 2015-04-11 Au Optronics Corp 顯示面板及其測試方法
CN103680384B (zh) * 2012-09-26 2016-05-11 乐金显示有限公司 具有柔性膜线缆的显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1619299A (zh) * 2003-11-21 2005-05-25 布鲁克斯自动化机械亚洲株式会社 玻璃基板边缘部分的破损检测装置及方法
CN201007763Y (zh) * 2007-03-01 2008-01-16 北京京东方光电科技有限公司 一种lcd玻璃基板破碎检测电路
CN101652705A (zh) * 2007-04-25 2010-02-17 夏普株式会社 液晶显示面板及其检查方法
JP2009093132A (ja) * 2007-09-21 2009-04-30 Mitsubishi Electric Corp 液晶表示装置用セル及びその製造方法、並びに液晶表示装置の製造方法
JP2009085925A (ja) * 2007-10-03 2009-04-23 Seiko Epson Corp リーク欠陥検出方法
KR20090078566A (ko) * 2008-01-15 2009-07-20 주식회사 디쌤 기판 에지 검사장치 및 방법
CN102338943A (zh) * 2010-07-27 2012-02-01 北京京东方光电科技有限公司 阵列基板、液晶面板和液晶显示器以及制造和检测方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105976744A (zh) * 2016-06-24 2016-09-28 上海与德科技有限公司 一种屏模组、电子设备及屏模组的微裂纹检测方法
US10267844B2 (en) 2016-06-27 2019-04-23 Au Optronics Corporation Panel structure with detecting circuit and detecting circuit for panel
CN111508401A (zh) * 2020-06-12 2020-08-07 京东方科技集团股份有限公司 裂纹检测电路、显示面板及裂纹检测方法
CN112230487A (zh) * 2020-09-22 2021-01-15 江西兴泰科技有限公司 电子纸模组及检测其崩边暗裂的方法

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