WO2016004633A1 - 阵列基板的制作方法、阵列基板及液晶显示装置 - Google Patents

阵列基板的制作方法、阵列基板及液晶显示装置 Download PDF

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Publication number
WO2016004633A1
WO2016004633A1 PCT/CN2014/082089 CN2014082089W WO2016004633A1 WO 2016004633 A1 WO2016004633 A1 WO 2016004633A1 CN 2014082089 W CN2014082089 W CN 2014082089W WO 2016004633 A1 WO2016004633 A1 WO 2016004633A1
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Prior art keywords
array substrate
insulating layer
liquid crystal
crystal display
thin film
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Ceased
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PCT/CN2014/082089
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English (en)
French (fr)
Inventor
柴立
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/390,656 priority Critical patent/US9733536B2/en
Publication of WO2016004633A1 publication Critical patent/WO2016004633A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D86/01—Manufacture or treatment
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    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
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    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10P50/00—Etching of wafers, substrates or parts of devices
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    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1362—Active matrix addressed cells
    • G02F1/13625—Patterning using multi-mask exposure

Definitions

  • the present invention relates to the field of liquid crystal technology, and in particular, to a method for fabricating an array substrate, an array substrate, and a liquid crystal display device.
  • the display brightness of the display screen in the relatively severe area is attenuated, and the display brightness of the display screen in the lighter area is lower.
  • the display images on both sides are higher than the display brightness in the middle display screen (the attenuation of the scanning drive signals on both sides is small).
  • An object of the present invention is to provide a method for fabricating an array substrate, an array substrate, and a liquid crystal display device, which solve the technical problem of uneven display brightness, low aperture ratio, or high manufacturing cost of a display screen of a conventional liquid crystal display device. .
  • the embodiment of the present invention provides a method for fabricating an array substrate.
  • the array substrate is disposed in a corresponding liquid crystal display panel, and includes:
  • a transparent electrode layer is deposited, and the pixel electrode is formed by a patterning process, wherein the pixel electrode is connected to the thin film field effect transistor through the contact hole.
  • the cross-sectional shape of the patterned first insulating layer of the entire array substrate is a curved quadrilateral having a curved side, and the curved edge is concavely curved. .
  • the step of performing the patterning process on the first insulating layer comprises:
  • the first insulating layer coated with the photoresist having a curved surface is dry etched to form the patterned first insulating layer.
  • the step of dry etching the first insulating layer coated with the photoresist having a curved surface includes:
  • a light blocking ratio of a middle portion of the grading mask is smaller than a light blocking ratio of both side portions of the grading mask.
  • the step of depositing the semiconductor layer and the second metal layer comprises:
  • the thin film field effect transistor includes a source, a drain, and a gate, and a channel is disposed between the source and the drain, and the source is The data lines are connected, the gate is connected to the scan line, and the drain is connected to the pixel electrode.
  • the source is connected to the channel through an ohmic contact layer.
  • the drain is connected to the channel through an ohmic contact layer.
  • the embodiment of the present invention further provides an array substrate disposed in a corresponding liquid crystal display panel, wherein the array substrate includes:
  • a plurality of thin film field effect transistors for transmitting the data signal to the pixel electrode according to the scan signal to display the data signal
  • a first insulating layer disposed between the thin film field effect transistor and the scan line;
  • a second insulating layer disposed between the pixel electrode and the thin film field effect transistor
  • the thickness of the first insulating layer corresponding to the array substrate on the two sides of the liquid crystal display panel is greater than the thickness of the first insulating layer corresponding to the array substrate in the middle of the liquid crystal display panel.
  • the cross-sectional shape of the first insulating layer of the entire array substrate is a curved quadrilateral having a curved side, and the curved side is concavely curved.
  • the thin film field effect transistor includes a source, a drain, and a gate, and a channel is disposed between the source and the drain, the source and the data A line is connected, the gate is connected to the scan line, and the drain is connected to the pixel electrode.
  • the source is connected to the channel through an ohmic contact layer.
  • the drain is connected to the channel through an ohmic contact layer.
  • the embodiment of the invention further provides a liquid crystal display device, comprising: a liquid crystal display panel having a color film substrate and an array substrate;
  • the array substrate comprises:
  • a plurality of thin film field effect transistors for transmitting the data signal to the pixel electrode according to the scan signal to display the data signal
  • a first insulating layer disposed between the thin film field effect transistor and the scan line;
  • a second insulating layer disposed between the pixel electrode and the thin film field effect transistor
  • the thickness of the first insulating layer corresponding to the array substrate on the two sides of the liquid crystal display panel is greater than the thickness of the first insulating layer corresponding to the array substrate in the middle of the liquid crystal display panel.
  • the cross-sectional shape of the first insulating layer of the entire array substrate is a curved quadrilateral having a curved side, and the curved side is concavely curved.
  • the thin film field effect transistor includes a source, a drain, and a gate, and a channel is disposed between the source and the drain, the source and the source The data lines are connected, the gate is connected to the scan line, and the drain is connected to the pixel electrode.
  • the source is connected to the channel through an ohmic contact layer.
  • the drain is connected to the channel through an ohmic contact layer.
  • the method for fabricating the array substrate, the array substrate, and the liquid crystal display device of the present invention provide uniform display brightness of the display screen of the liquid crystal display device by providing the first insulating layer having different thicknesses;
  • the display screen has uneven display brightness, a low aperture ratio, or a high manufacturing cost.
  • FIG. 1 is a flow chart of a preferred embodiment of a method of fabricating an array substrate of the present invention
  • step S102 is a specific flowchart of step S102 of the method for fabricating the array substrate of the present invention
  • FIG. 3 is a schematic structural view of a gradation mask used in the method for fabricating an array substrate of the present invention
  • FIG. 4 is a cross-sectional view showing a first insulating layer of the entire array substrate of the liquid crystal display device of the present invention.
  • FIG. 5 is a schematic structural view of an array substrate of one pixel unit of the liquid crystal display device of the present invention.
  • Figure 6 is a cross-sectional view taken along line A-A' of Figure 5;
  • FIG. 1 is a flow chart of a preferred embodiment of a method for fabricating an array substrate according to the present invention.
  • the method for fabricating the array substrate of the preferred embodiment includes:
  • Step S101 depositing a first metal layer on the substrate, and forming a scan line by a patterning process
  • Step S102 depositing a first insulating layer, and patterning the first insulating layer
  • Step S103 depositing a semiconductor layer and a second metal layer, and forming a data line and a thin film field effect transistor by a patterning process;
  • Step S104 depositing a second insulating layer, and forming a contact hole by patterning
  • step S105 a transparent electrode layer is deposited, and a pixel electrode is formed by a patterning process.
  • step S105 The method of fabricating the array substrate of the preferred embodiment ends in step S105.
  • step S101 a base substrate is provided, and then a first metal layer is deposited on the base substrate, and the material of the first metal layer may be tantalum, molybdenum, aluminum, copper, titanium, tantalum or tungsten, etc., and a photomask is used.
  • the first metal layer is patterned to form a scan line on the base substrate; then, the process proceeds to step S102.
  • step S102 a first insulating layer is deposited, the material of the first insulating layer may be a silicon nitride layer or the like, and the first insulating layer is patterned by using a grading mask.
  • FIG. 2 is A specific flowchart of step S102 of the method for fabricating the array substrate of the invention. Step S102 includes:
  • Step S1021 performing a photoresist coating operation on the first insulating layer, and uniformly coating the photoresist on the surface of the first insulating layer;
  • step S1022 the photoresist is exposed by using a grading mask, and the light blocking ratio of the middle portion of the grading mask is smaller than the light blocking ratio of the two sides of the grading mask.
  • FIG. 3 is an array substrate of the present invention. Schematic diagram of the gradient mask used in the manufacturing method. The two sides of the gradient mask are the areas with the highest light blocking rate, and the middle of the gradient mask is the area with the lowest light blocking rate, and the other areas of the gradient light gradually change gently.
  • the light-shielding rate of the middle portion of the gradation mask in FIG. 3 is 0%, and the light-shielding ratio of the two sides of the gradual mask is 50%-100%, and the specific setting of the light-shielding ratio of the both sides can be set according to the needs of the user. set.
  • Step S1023 performing a developing operation on the photoresist after the exposure operation, since the degree of exposure of the photoresist at different positions is different, a photoresist having a curved surface is formed after the developing operation, and the photoresist having a higher exposure degree (positive direction) The more the photoresist is melted in the developer, the light resistance of the arc having the intermediate depression is formed.
  • Step S1024 performing dry etching on the first insulating layer coated with the photoresist of the screen, and the dry etching oxidizing gas may completely ash the photoresist having the curved surface, and continue to dry the first insulating layer. Etching operation. Since the photoresist of different regions is completely ashed, the cross-sectional shape of the first insulating layer after the dry etching (or the patterned first insulating layer) is a curved quadrilateral having a curved edge. The curved side is concavely curved.
  • FIG. 4 is a cross-sectional view showing a first insulating layer of the entire array substrate of the liquid crystal display device of the present invention. The thickness of the first insulating layer of the array substrate on both sides of the liquid crystal display panel is greater than the thickness of the first insulating layer of the array substrate in the middle of the liquid crystal display panel. Then it proceeds to step S103.
  • step S103 a semiconductor layer ohmic contact layer and a second metal layer are deposited on the patterned first insulating layer, the semiconductor layer is an amorphous silicon layer, and the ohmic contact layer is an amorphous silicon layer doped with phosphorus ions.
  • the material of the second metal layer may be tantalum, molybdenum, aluminum, copper, titanium, tantalum or tungsten.
  • the semiconductor layer and the second metal layer are then patterned using a photomask to form data lines and thin film field effect transistors. Then it proceeds to step S104.
  • step S104 a second insulating layer is deposited, and then the second insulating layer is patterned using a photomask to form a contact hole on the second insulating layer. Then it proceeds to step S105.
  • a transparent electrode layer is deposited on the second insulating layer, and then the transparent electrode layer is patterned using a photomask to form a pixel electrode.
  • the pixel electrode is connected to the drain of the thin film field effect transistor through a contact hole on the second insulating layer.
  • the thickness of the first insulating layer of the array substrate is inversely proportional to the opening efficiency of the channel of the corresponding thin film field effect transistor, that is, the larger the thickness of the first insulating layer of the array substrate, the corresponding
  • the lower the channel opening efficiency of the thin film field effect transistor the lower the display brightness of the display area of the liquid crystal display panel corresponding to the thin film field effect transistor driven by the same data signal.
  • the thickness of the first insulating layer of the array substrate is smaller, the channel opening effect of the corresponding thin film field effect transistor is higher, so that the display area of the liquid crystal display panel corresponding to the thin film field effect transistor is driven by the same data signal. The lower the display brightness.
  • the thickness of the first insulating layer corresponding to the array substrate on both sides of the liquid crystal display panel is greater than the thickness of the first insulating layer of the array substrate in the middle of the liquid crystal display panel. Therefore, under the driving of the same data signal, the display brightness of the display area on both sides of the liquid crystal display panel should be smaller than the display brightness of the display area in the middle of the liquid crystal display panel. In this way, the attenuation of the scan driving signal can be effectively compensated, so that the display screen of the entire display screen of the compensated liquid crystal display device is uniform.
  • the method for fabricating the array substrate of the preferred embodiment has uniform display brightness of the display screen of the liquid crystal display device by providing the first insulating layer of different thickness, and at the same time, ensures a high aperture ratio and a low manufacturing cost of the liquid crystal display device.
  • FIG. 5 is a schematic structural diagram of an array substrate of a pixel unit of the liquid crystal display device of the present invention
  • FIG. 6 is a A-A of FIG. 'A cross-sectional view of the section line.
  • the liquid crystal display device includes a liquid crystal display panel having a color filter substrate (not shown) and an array substrate.
  • the array substrate 50 includes a plurality of scan lines 51, a plurality of data lines 52, a plurality of thin film field effect transistors 53, a first insulating layer 54, and a second insulating layer 55.
  • the scan line 51 is used for transmitting the scan signal;
  • the data line 52 is used for transmitting the data signal;
  • the thin film field effect crystal 53 is used for transmitting the data signal to the pixel electrode according to the scan signal to display the data signal;
  • the first insulating layer 54 is disposed at
  • the thin film field effect transistor 53 is interposed between the scan lines 51;
  • the second insulating layer 55 is disposed between the pixel electrode 56 and the thin film field effect transistor 53.
  • the thickness of the first insulating layer 54 corresponding to the array substrate 50 on both sides of the liquid crystal display panel of the liquid crystal display device of the preferred embodiment is greater than the thickness of the first insulating layer 54 of the array substrate 50 in the middle of the liquid crystal display panel.
  • the cross-sectional shape of the first insulating layer 54 of the entire array substrate is a curved quadrilateral having a curved side, and the curved side is concavely curved.
  • the thin film field effect transistor 53 includes a source 531, a drain 532, and a gate 533.
  • a channel 534 is disposed between the source 531 and the drain 532.
  • the source 531 is connected to the data line 52, and the gate 533 is connected to the scan line 51.
  • the drain 532 is connected to the pixel electrode 56.
  • the thickness of the first insulating layer 54 of the array substrate 50 is inversely proportional to the opening efficiency of the channel of the corresponding thin film field effect transistor 53, that is, the first insulating layer 54 of the array substrate 50.
  • the thickness of the first insulating layer 54 of the array substrate 50 is smaller, the channel opening effect of the corresponding thin film field effect transistor 53 is higher, so that the display area of the liquid crystal display panel corresponding to the thin film field effect transistor 53 is the same.
  • the display brightness driven by the data signal is higher.
  • the thickness of the first insulating layer 54 corresponding to the array substrate 50 on both sides of the liquid crystal display panel is greater than the thickness of the first insulating layer 54 of the array substrate 50 in the middle of the liquid crystal display panel. Therefore, under the driving of the same data signal, the display brightness of the display area on both sides of the liquid crystal display panel should be smaller than the display brightness of the display area in the middle of the liquid crystal display panel. In this way, the attenuation of the scan driving signal can be effectively compensated, so that the display screen of the entire display screen of the compensated liquid crystal display device is uniform.
  • the method for fabricating the array substrate, the array substrate, and the liquid crystal display device of the present invention provide uniform display brightness of the display screen of the liquid crystal display device by providing the first insulating layer having different thicknesses; and the display of the display screen of the conventional liquid crystal display device is solved.
  • Technical problems of uneven brightness, low aperture ratio, or high manufacturing cost are also known.

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Abstract

一种阵列基板的制作方法、阵列基板及液晶显示装置，该阵列基板的制作方法包括如下步骤：S101，在衬底基板上沉积第一金属层，并形成扫描线；S102，沉积第一绝缘层，并对第一绝缘层进行图形化处理；其中液晶显示面板两侧的阵列基板的第一绝缘层的厚度大于液晶显示面板中间的阵列基板的第一绝缘层的厚度；S103，沉积半导体层以及第二金属层，并形成数据线以及薄膜场效应晶体管；S104，沉积第二绝缘层，并形成接触孔；S105，沉积透明电极层，并形成像素电极。由此解决了显示画面的显示亮度不均的技术问题。

Description

阵列基板的制作方法、阵列基板及液晶显示装置 技术领域
本发明涉及液晶技术领域，特别是涉及一种阵列基板的制作方法、阵列基板及液晶显示装置。
 背景技术
随着信息社会的发展，人们对液晶显示设备的需求越来越高，因而推动了液晶显示面板行业的快速发展，液晶显示面板的尺寸也越做越大，客户对液晶显示面板的品质要求也越来越高。
目前由于扫描驱动信号在扫描线上的衰减，导致衰减比较严重区域的显示画面的显示亮度，比衰减较轻区域的显示画面的显示亮度要低。对于大尺寸的液晶显示面板，表现出来即为，在同一灰阶画面下，两侧的显示画面会比中间的显示画面的显示亮度要高（两侧的扫描驱动信号的衰减较小）。
对于上述的问题，目前有两种改善方案：
一、减少扫描线的阻抗，可以增加扫描线的线宽，但是增加扫描线的线宽会减小像素单元的开口率。
二、对扫描驱动信号进行波形消角处理，这样导致液晶显示装置整体的亮度变低，需要通过增加背光源的功率，来加大液晶显示装置的显示亮度，从而增加了液晶显示装置的功耗。
故，有必要提供一种阵列基板的制作方法及阵列基板，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种阵列基板的制作方法、阵列基板及液晶显示装置，以解决现有的液晶显示装置的显示画面的显示亮度不均、开口率较低或制作成本较高的技术问题。
 技术解决方案
本发明实施例提供一种阵列基板的制作方法，所述阵列基板设置在相应的液晶显示面板中，其包括：
在所述衬底基板上沉积第一金属层，并通过图形化处理形成扫描线；
沉积第一绝缘层，并对所述第一绝缘层进行图形化处理；其中所述液晶显示面板两侧的所述阵列基板的所述第一绝缘层的厚度大于所述液晶显示面板中间的所述阵列基板的所述第一绝缘层的厚度；
沉积半导体层以及第二金属层，并通过图形化处理形成数据线以及薄膜场效应晶体管；
沉积第二绝缘层，并通过图形化处理形成接触孔；以及
沉积透明电极层，并通过图形化处理形成所述像素电极，其中所述像素电极通过所述接触孔与所述薄膜场效应晶体管连接。
在本发明所述的阵列基板的制作方法中，整个所述阵列基板的所述图形化处理后的第一绝缘层的截面形状为具有一条曲边的曲边四边形，所述曲边为凹弧状。
在本发明所述的阵列基板的制作方法中，所述对所述第一绝缘层进行图形化处理的步骤包括：
在所述第一绝缘层上进行光阻涂布操作；
使用渐变光罩对所述光阻进行曝光操作；
对所述曝光操作后的光阻进行显影操作，以形成具有弧面的光阻；以及
对涂布所述具有弧面的光阻的第一绝缘层进行干法刻蚀，以形成所述图形化处理后的第一绝缘层。
在本发明所述的阵列基板的制作方法中，所述对涂布所述具有弧面的光阻的第一绝缘层进行干法刻蚀的步骤包括：
将所有所述具有弧面的光阻进行灰化操作；以及
对所述第一绝缘层进行干法刻蚀操作，以形成所述图形化处理后的第一绝缘层
在本发明所述的阵列基板的制作方法中，所述渐变光罩的中间部分的遮光率小于所述渐变光罩的两侧部分的遮光率。
在本发明所述的阵列基板的制作方法中，所述沉积半导体层以及第二金属层的步骤包括：
在所述半导体层上形成欧姆接触层；以及
在所述欧姆接触层上沉积所述第二金属层。
在本发明所述的阵列基板的制作方法中，所述薄膜场效应晶体管包括源极、漏极以及栅极，所述源极和所述漏极之间设置有沟道，所述源极与所述数据线连接，所述栅极与所述扫描线连接，所述漏极与所述像素电极连接。
在本发明所述的阵列基板的制作方法中，所述源极通过欧姆接触层与所述沟道连接。
在本发明所述的阵列基板的制作方法中，所述漏极通过欧姆接触层与所述沟道连接。
本发明实施例还提供一种阵列基板，设置在相应的液晶显示面板中，其中所述阵列基板包括：
多个扫描线，用于传输扫描信号；
多个数据线，用于传输数据信号；
多个薄膜场效应晶体管，用于根据所述扫描信号，将所述数据信号传输给像素电极，以显示所述数据信号；
第一绝缘层，设置在所述薄膜场效应晶体管与所述扫描线之间；以及
第二绝缘层，设置在所述像素电极与所述薄膜场效应晶体管之间；
其中所述液晶显示面板两侧的所述阵列基板对应的所述第一绝缘层的厚度大于所述液晶显示面板中间的所述阵列基板对应的所述第一绝缘层的厚度。
在本发明所述的阵列基板中，整个所述阵列基板的所述第一绝缘层的截面形状为具有一条曲边的曲边四边形，所述曲边为凹弧状。
在本发明所述的阵列基板中，所述薄膜场效应晶体管包括源极、漏极以及栅极，所述源极和所述漏极之间设置有沟道，所述源极与所述数据线连接，所述栅极与所述扫描线连接，所述漏极与所述像素电极连接。
在本发明所述的阵列基板中，所述源极通过欧姆接触层与所述沟道连接。
在本发明所述的阵列基板中，所述漏极通过欧姆接触层与所述沟道连接。
本发明实施例还提供一种液晶显示装置，其包括：具有彩膜基板以及阵列基板的液晶显示面板；
其中所述阵列基板包括：
多个扫描线，用于传输扫描信号；
多个数据线，用于传输数据信号；
多个薄膜场效应晶体管，用于根据所述扫描信号，将所述数据信号传输给像素电极，以显示所述数据信号；
第一绝缘层，设置在所述薄膜场效应晶体管与所述扫描线之间；以及
第二绝缘层，设置在所述像素电极与所述薄膜场效应晶体管之间；
其中所述液晶显示面板两侧的所述阵列基板对应的所述第一绝缘层的厚度大于所述液晶显示面板中间的所述阵列基板对应的所述第一绝缘层的厚度。
在本发明所述的液晶显示装置中，整个所述阵列基板的所述第一绝缘层的截面形状为具有一条曲边的曲边四边形，所述曲边为凹弧状。
在本发明所述的液晶显示装置中，所述薄膜场效应晶体管包括源极、漏极以及栅极，所述源极和所述漏极之间设置有沟道，所述源极与所述数据线连接，所述栅极与所述扫描线连接，所述漏极与所述像素电极连接。
在本发明所述的液晶显示装置中，所述源极通过欧姆接触层与所述沟道连接。
在本发明所述的液晶显示装置中，所述漏极通过欧姆接触层与所述沟道连接。
 有益效果
相较于现有的液晶显示装置，本发明的阵列基板的制作方法、阵列基板及液晶显示装置通过设置不同厚度的第一绝缘层，使液晶显示装置的显示画面的显示亮度均匀；解决了现有的液晶显示装置的显示画面的显示亮度不均、开口率较低或制作成本较高的技术问题。
 附图说明
图1为本发明的阵列基板的制作方法的优选实施例的流程图；
图2为本发明的阵列基板的制作方法的步骤S102的具体流程图；
图3为本发明的阵列基板的制作方法中使用的渐变光罩的结构示意图；
图4为本发明的液晶显示装置的整个阵列基板的第一绝缘层的截面图；
图5为本发明的液晶显示装置的一个像素单元的阵列基板的结构示意图；
图6为图5的按A-A’截面线的截面图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
本发明实施例提供一种阵列基板的制作方法，请参照图1，图1为本发明的阵列基板的制作方法的优选实施例的流程图。本优选实施例的阵列基板的制作方法包括：
步骤S101，在衬底基板上沉积第一金属层，并通过图形化处理形成扫描线；
步骤S102，沉积第一绝缘层，并对第一绝缘层进行图形化处理；
步骤S103，沉积半导体层以及第二金属层，并通过图形化处理形成数据线以及薄膜场效应晶体管；
步骤S104，沉积第二绝缘层，并通过图形化处理形成接触孔；
步骤S105，沉积透明电极层，并通过图形化处理形成像素电极。
本优选实施例的阵列基板的制作方法结束于步骤S105。
下面详细说明本优选实施例的阵列基板的制作方法的各步骤的具体流程。
在步骤S101中，提供衬底基板，然后在该衬底基板上沉积第一金属层，第一金属层的材料可为锘、钼、铝、铜、钛、钽或钨等，并使用光罩对第一金属层进行图形化处理在衬底基板上形成扫描线；随后转到步骤S102。
在步骤S102中，沉积第一绝缘层，第一绝缘层的材料可为氮化硅层等，并使用渐变光罩对第一绝缘层进行图形化处理，具体可参见图2，图2为本发明的阵列基板的制作方法的步骤S102的具体流程图。步骤S102包括：
步骤S1021，在第一绝缘层上进行光阻涂布操作，将光阻均匀的涂布在第一绝缘层的表面；
步骤S1022，使用渐变光罩对光阻进行曝光操作，该渐变光罩的中间部分的遮光率小于渐变光罩的两侧部分的遮光率；具体请参照图3，图3为本发明的阵列基板的制作方法中使用的渐变光罩的结构示意图。该渐变光罩的两侧为遮光率最高的区域，渐变光罩的中间为遮光率最低的区域，渐变光照的其他区域的遮光率逐渐平缓变化。图3中的渐变光罩的中间部分的遮光率为0%，渐变光罩的两侧部分的遮光率为50%-100%，两侧部分的遮光率的具体设置可以根据用户的需要进行设定。
步骤S1023，对曝光操作后的光阻进行显影操作，由于不同位置的光阻接收曝光的程度不同，因此显影操作后形成一具有弧面的光阻，其中曝光程度越高的光阻（正向光阻）融于显影液中的越多，因此形成一具有中间凹陷的弧面的光阻。
步骤S1024，对涂布具有画面的光阻的第一绝缘层进行干法刻蚀，干法刻蚀的氧化气体可以全部灰化具有弧面的光阻，并且继续对第一绝缘层进行干法刻蚀操作。由于不同区域的光阻被完全灰化的时间不同，因此干法刻蚀后的第一绝缘层（或图形化处理后的第一绝缘层）的截面形状为具有一条曲边的曲边四边形，该曲边为凹弧状。具体请参见图4，图4为本发明的液晶显示装置的整个阵列基板的第一绝缘层的截面图。液晶显示面板两侧的阵列基板的第一绝缘层的厚度大于液晶显示面板中间的阵列基板的第一绝缘层的厚度。随后转到步骤S103。
在步骤S103中，在图形化处理后的第一绝缘层上沉积半导体层欧姆接触层以及第二金属层，半导体层为非晶硅层，欧姆接触层为掺杂磷离子的非晶硅层，第二金属层的材料可为锘、钼、铝、铜、钛、钽或钨等。然后使用光罩对对半导体层以及第二金属层进行图形化处理，以形成数据线以及薄膜场效应晶体管。随后转到步骤S104。
在步骤S104中，沉积第二绝缘层，然后使用光罩对第二绝缘层进行图形化处理，在第二绝缘层上形成接触孔。随后转到步骤S105。
在步骤S105中，在第二绝缘层上沉积透明电极层，然后使用光罩对透明电极层进行图形化处理，以形成像素电极。该像素电极通过第二绝缘层上的接触孔与薄膜场效应晶体管的漏极连接。
这样即完成了本优选实施例的阵列基板的制作过程。
本优选实施例的阵列基板使用时，阵列基板的第一绝缘层的厚度与相应的薄膜场效应晶体管的沟道的开启效率成反比，即阵列基板的第一绝缘层的厚度越大，则对应的薄膜场效应晶体管的沟道开启效率越低，这样该薄膜场效应晶体管对应的液晶显示面板的显示区域，在相同数据信号的驱动下的显示亮度就越低。同时如阵列基板的第一绝缘层的厚度越小，则对应的薄膜场效应晶体管的沟道开启效率越高，这样该薄膜场效应晶体管对应的液晶显示面板的显示区域，在相同数据信号的驱动下的显示亮度就越高。
由于液晶显示面板两侧的阵列基板对应的第一绝缘层的厚度大于液晶显示面板中间的阵列基板的第一绝缘层的厚度。因此在相同数据信号的驱动下，液晶显示面板两侧的显示区域的显示亮度应小于液晶显示面板中间的显示区域的显示亮度。这样可以有效的对扫描驱动信号的衰减进行补偿，使得补偿后的液晶显示装置的整个显示画面的显示画面均匀。
本优选实施例的阵列基板的制作方法通过设置不同厚度的第一绝缘层，使液晶显示装置的显示画面的显示亮度均匀，同时保证了液晶显示装置较高的开口率以及较低的制作成本。
本发明实施例还提供一种液晶显示装置，请参照图5和图6，图5为本发明的液晶显示装置的一个像素单元的阵列基板的结构示意图；图6为图5的按A-A’截面线的截面图。
该液晶显示装置包括具有彩膜基板（图中未示出）以及阵列基板的液晶显示面板。该阵列基板50包括多个扫描线51、多个数据线52、多个薄膜场效应晶体管53、第一绝缘层54以及第二绝缘层55。其中扫描线51用于传输扫描信号；数据线52用于传输数据信号；薄膜场效应晶体53管用于根据扫描信号，将数据信号传输给像素电极，以显示数据信号；第一绝缘层54设置在薄膜场效应晶体管53与扫描线51之间；第二绝缘层55设置在像素电极56与薄膜场效应晶体管53之间。
本优选实施例的液晶显示装置的液晶显示面板两侧的阵列基板50对应的第一绝缘层54的厚度大于液晶显示面板中间的阵列基板50的第一绝缘层54的厚度。整个阵列基板的第一绝缘层54的截面形状为具有一条曲边的曲边四边形，该曲边为凹弧状。
薄膜场效应晶体管53包括源极531、漏极532以及栅极533，源极531和漏极532之间设置有沟道534，源极531与数据线52连接，栅极533与扫描线51连接，漏极532与像素电极56连接。
本优选实施例的液晶显示装置使用时，阵列基板50的第一绝缘层54的厚度与相应的薄膜场效应晶体管53的沟道的开启效率成反比，即阵列基板50的第一绝缘层54的厚度越大，则对应的薄膜场效应晶体管53的沟道开启效率越低，这样该薄膜场效应晶体管53对应的液晶显示面板的显示区域，在相同数据信号的驱动下的显示亮度就越低。同时如阵列基板50的第一绝缘层54的厚度越小，则对应的薄膜场效应晶体管53的沟道开启效率越高，这样该薄膜场效应晶体管53对应的液晶显示面板的显示区域，在相同数据信号的驱动下的显示亮度就越高。
由于液晶显示面板两侧的阵列基板50对应的第一绝缘层54的厚度大于液晶显示面板中间的阵列基板50的第一绝缘层54的厚度。因此在相同数据信号的驱动下，液晶显示面板两侧的显示区域的显示亮度应小于液晶显示面板中间的显示区域的显示亮度。这样可以有效的对扫描驱动信号的衰减进行补偿，使得补偿后的液晶显示装置的整个显示画面的显示画面均匀。
本发明的阵列基板的制作方法、阵列基板及液晶显示装置通过设置不同厚度的第一绝缘层，使液晶显示装置的显示画面的显示亮度均匀；解决了现有的液晶显示装置的显示画面的显示亮度不均、开口率较低或制作成本较高的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种阵列基板的制作方法，所述阵列基板设置在相应的液晶显示面板中，其包括：
    在所述衬底基板上沉积第一金属层，并通过图形化处理形成扫描线；
    沉积第一绝缘层，并对所述第一绝缘层进行图形化处理；其中所述液晶显示面板两侧的所述阵列基板的所述第一绝缘层的厚度大于所述液晶显示面板中间的所述阵列基板的所述第一绝缘层的厚度；
    沉积半导体层以及第二金属层，并通过图形化处理形成数据线以及薄膜场效应晶体管；
    沉积第二绝缘层，并通过图形化处理形成接触孔；以及
    沉积透明电极层，并通过图形化处理形成所述像素电极，其中所述像素电极通过所述接触孔与所述薄膜场效应晶体管连接。
  2. 根据权利要求1所述的阵列基板的制作方法，其中整个所述阵列基板的所述图形化处理后的第一绝缘层的截面形状为具有一条曲边的曲边四边形，所述曲边为凹弧状。
  3. 根据权利要求2所述的阵列基板的制作方法，其中所述对所述第一绝缘层进行图形化处理的步骤包括：
    在所述第一绝缘层上进行光阻涂布操作；
    使用渐变光罩对所述光阻进行曝光操作；
    对所述曝光操作后的光阻进行显影操作，以形成具有弧面的光阻；以及
    对涂布所述具有弧面的光阻的第一绝缘层进行干法刻蚀，以形成所述图形化处理后的第一绝缘层。
  4. 根据权利要求3所述的阵列基板的制作方法，其中所述对涂布所述具有弧面的光阻的第一绝缘层进行干法刻蚀的步骤包括：
    将所有所述具有弧面的光阻进行灰化操作；以及
    对所述第一绝缘层进行干法刻蚀操作，以形成所述图形化处理后的第一绝缘层。
  5. 根据权利要求3所述的阵列基板的制作方法，其中所述渐变光罩的中间部分的遮光率小于所述渐变光罩的两侧部分的遮光率。
  6. 根据权利要求1所述的阵列基板的制作方法，其中所述沉积半导体层以及第二金属层的步骤包括：
    在所述半导体层上形成欧姆接触层；以及
    在所述欧姆接触层上沉积所述第二金属层。
  7. 根据权利要求1所述的阵列基板的制作方法，其中所述薄膜场效应晶体管包括源极、漏极以及栅极，所述源极和所述漏极之间设置有沟道，所述源极与所述数据线连接，所述栅极与所述扫描线连接，所述漏极与所述像素电极连接。
  8. 根据权利要求1所述的阵列基板的制作方法，其中所述源极通过欧姆接触层与所述沟道连接。
  9. 根据权利要求1所述的阵列基板的制作方法，其中所述漏极通过欧姆接触层与所述沟道连接。
  10. 一种阵列基板，设置在相应的液晶显示面板中，其中所述阵列基板包括：
    多个扫描线，用于传输扫描信号；
    多个数据线，用于传输数据信号；
    多个薄膜场效应晶体管，用于根据所述扫描信号，将所述数据信号传输给像素电极，以显示所述数据信号；
    第一绝缘层，设置在所述薄膜场效应晶体管与所述扫描线之间；以及
    第二绝缘层，设置在所述像素电极与所述薄膜场效应晶体管之间；
    其中所述液晶显示面板两侧的所述阵列基板对应的所述第一绝缘层的厚度大于所述液晶显示面板中间的所述阵列基板对应的所述第一绝缘层的厚度。
  11. 根据权利要求10所述的阵列基板，其中整个所述阵列基板的所述第一绝缘层的截面形状为具有一条曲边的曲边四边形，所述曲边为凹弧状。
  12. 根据权利要求10所述的阵列基板，其中所述薄膜场效应晶体管包括源极、漏极以及栅极，所述源极和所述漏极之间设置有沟道，所述源极与所述数据线连接，所述栅极与所述扫描线连接，所述漏极与所述像素电极连接。
  13. 根据权利要求12所述的阵列基板，其中所述源极通过欧姆接触层与所述沟道连接。
  14. 根据权利要求12所述的阵列基板，其中所述漏极通过欧姆接触层与所述沟道连接。
  15. 一种液晶显示装置，其包括具有彩膜基板以及阵列基板的液晶显示面板；
    其中所述阵列基板包括：
    多个扫描线，用于传输扫描信号；
    多个数据线，用于传输数据信号；
    多个薄膜场效应晶体管，用于根据所述扫描信号，将所述数据信号传输给像素电极，以显示所述数据信号；
    第一绝缘层，设置在所述薄膜场效应晶体管与所述扫描线之间；以及
    第二绝缘层，设置在所述像素电极与所述薄膜场效应晶体管之间；
    其中所述液晶显示面板两侧的所述阵列基板对应的所述第一绝缘层的厚度大于所述液晶显示面板中间的所述阵列基板对应的所述第一绝缘层的厚度。
  16. 根据权利要求15所述的液晶显示装置，其中整个所述阵列基板的所述第一绝缘层的截面形状为具有一条曲边的曲边四边形，所述曲边为凹弧状。
  17. 根据权利要求15所述的液晶显示装置，其中所述薄膜场效应晶体管包括源极、漏极以及栅极，所述源极和所述漏极之间设置有沟道，所述源极与所述数据线连接，所述栅极与所述扫描线连接，所述漏极与所述像素电极连接。
  18. 根据权利要求17所述的液晶显示装置，其中所述源极通过欧姆接触层与所述沟道连接。
  19. 根据权利要求17所述的液晶显示装置，其中所述漏极通过欧姆接触层与所述沟道连接。
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CN103413813A (zh) * 2013-07-31 2013-11-27 北京京东方光电科技有限公司 一种阵列基板及其制作方法、显示装置

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