WO2015198978A1 - Dispositif de conversion photoélectrique et son procédé de fabrication - Google Patents

Dispositif de conversion photoélectrique et son procédé de fabrication Download PDF

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WO2015198978A1
WO2015198978A1 PCT/JP2015/067694 JP2015067694W WO2015198978A1 WO 2015198978 A1 WO2015198978 A1 WO 2015198978A1 JP 2015067694 W JP2015067694 W JP 2015067694W WO 2015198978 A1 WO2015198978 A1 WO 2015198978A1
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semiconductor layer
type semiconductor
photoelectric conversion
layer
silicon substrate
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PCT/JP2015/067694
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English (en)
Japanese (ja)
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神川　剛
真臣 原田
和也 辻埜
親扶 岡本
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シャープ株式会社
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Priority claimed from JP2014132665A external-priority patent/JP5913446B2/ja
Priority claimed from JP2014132666A external-priority patent/JP5871996B2/ja
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Publication of WO2015198978A1 publication Critical patent/WO2015198978A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a photoelectric conversion device that converts light into electricity and a method for manufacturing the photoelectric conversion device.
  • intrinsic (i-type) amorphous silicon is interposed between an n-type crystalline silicon substrate and a p-type amorphous silicon layer to reduce defects at the interface, and characteristics at the heterojunction interface.
  • a photoelectric conversion device with improved characteristics.
  • Japanese Unexamined Patent Application Publication No. 2010-283408 discloses a pair of second semiconductor layers disposed on both sides of a first semiconductor layer, and an insulating layer formed from one second semiconductor layer to the first semiconductor layer. And an insulating layer formed from the other second semiconductor layer to the first semiconductor layer is disclosed.
  • the transparent electrode layer and the collecting electrode layer are separated by a pair of separation grooves formed along the first direction on the insulating layer.
  • a surface passivation layer of a semiconductor material is locally opened on a surface-passivated semiconductor material through a tensioned foil opening by a plasma etching method.
  • Tensioned foil is then used as a mask for a heterocontact, TCO (Transparent Conductive Oxide) or further deposition process of metal and / or further plasma process.
  • the first semiconductor layer and the second semiconductor layer may be in contact with each other between the insulating layer and the substrate. Therefore, a leak current may occur between them. Even if the i layer is formed between the first semiconductor layer and the second semiconductor layer, defects are introduced into the i layer due to thermal or physical damage when the insulating layer is formed, There is a possibility that sufficient electrical separation cannot be performed.
  • the adhesion between the mask and the substrate is improved by applying tension to the foil (mask).
  • the mask and the substrate may not be sufficiently adhered.
  • a p-type semiconductor layer and an n-type semiconductor layer are formed on one surface of a substrate, if the adhesion between the mask and the substrate is poor, the p-type semiconductor layer and the n-type semiconductor layer can be sufficiently electrically separated. There is a possibility of disappearing.
  • An object of the present invention is to effectively separate an n-type semiconductor layer (first conductive semiconductor layer) and a p-type semiconductor layer (second conductive semiconductor layer) formed on one surface of a silicon substrate. It is obtaining the structure of the photoelectric conversion apparatus which can be obtained, and the manufacturing method of a photoelectric conversion apparatus.
  • the photoelectric conversion device disclosed herein includes a silicon substrate, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer formed on one surface of the silicon substrate and having opposite conductivity types, and the silicon substrate.
  • An insulating layer is provided on the one surface and insulates the first conductive semiconductor layer from the second conductive semiconductor layer.
  • the first conductive semiconductor layer and the second conductive semiconductor layer are adjacent to each other across the insulating layer in the in-plane direction of the silicon substrate. Neither the first conductive semiconductor layer nor the second conductive semiconductor layer is formed between the silicon substrate and the insulating layer.
  • Another photoelectric conversion device disclosed herein includes a silicon substrate, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer formed on one surface of the silicon substrate and having opposite conductivity types, and the silicon
  • An insulating layer is provided on the one surface of the substrate and insulates the first conductive semiconductor layer from the second conductive semiconductor layer.
  • the first conductive semiconductor layer and the second conductive semiconductor layer are adjacent to each other across the insulating layer in the in-plane direction of the silicon substrate.
  • the thickness of the insulating layer is larger than the height difference of the irregularities on the one surface of the silicon substrate.
  • the manufacturing method of the photoelectric conversion device disclosed herein includes a step of preparing a silicon substrate, a step of forming an insulating layer on one surface of the silicon substrate, and a part of a region sandwiched between the insulating layers. Forming a first conductivity type semiconductor layer; forming a second conductivity type semiconductor layer of a conductivity type opposite to the first conductivity type semiconductor layer in another part of the region sandwiched between the insulating layers; Is provided.
  • a step of preparing a silicon substrate, and an insulating layer on one surface of the silicon substrate are thicker than a difference in height of the unevenness of the one surface of the silicon substrate.
  • a configuration of a photoelectric conversion device that can effectively separate the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and a method for manufacturing the photoelectric conversion device are obtained.
  • FIG. 1 is a cross-sectional view schematically showing the configuration of the photoelectric conversion element according to the first embodiment of the present invention.
  • FIG. 2A is a diagram for explaining an example of a method for manufacturing a photoelectric conversion element.
  • FIG. 2B is a diagram for explaining an example of a method for manufacturing a photoelectric conversion element.
  • FIG. 2C is a diagram for explaining an example of a method for manufacturing a photoelectric conversion element.
  • FIG. 2D is a diagram for explaining an example of a method for manufacturing a photoelectric conversion element.
  • FIG. 2E is a diagram for describing an example of a method of manufacturing a photoelectric conversion element.
  • FIG. 2F is a diagram for describing an example of a method for manufacturing a photoelectric conversion element.
  • FIG. 2A is a diagram for explaining an example of a method for manufacturing a photoelectric conversion element.
  • FIG. 2B is a diagram for explaining an example of a method for manufacturing a photoelectric conversion element.
  • FIG. 2G is a diagram for explaining an example of a method for manufacturing a photoelectric conversion element.
  • FIG. 3A is a surface micrograph of a silicon substrate.
  • FIG. 3B is an uneven profile of the silicon substrate.
  • FIG. 3C is a cross-sectional view showing a state in which an insulating layer is formed on an uneven surface.
  • FIG. 4A is a schematic diagram showing a state in which an n-type semiconductor layer is formed on a surface where an insulating layer is not formed.
  • FIG. 4B is a schematic diagram showing a state in which a p-type semiconductor layer is further formed from FIG. 4A.
  • FIG. 5A is a cross-sectional view schematically showing the shape of a mask suitably used in this embodiment.
  • FIG. 5A is a cross-sectional view schematically showing the shape of a mask suitably used in this embodiment.
  • FIG. 5B is a cross-sectional view schematically showing the shape of a mask which is another example of a mask suitably used in the present embodiment.
  • FIG. 6 is a cross-sectional view schematically showing a configuration of a photoelectric conversion element according to a modification of the first embodiment of the present invention.
  • FIG. 7A is a diagram for explaining an example of a method for manufacturing a photoelectric conversion element.
  • FIG. 7B is a diagram for explaining an example of a method for manufacturing a photoelectric conversion element.
  • FIG. 7C is a diagram for explaining an example of a method for manufacturing a photoelectric conversion element.
  • FIG. 8 is a cross-sectional view schematically showing a configuration of a photoelectric conversion element according to the second embodiment of the present invention.
  • FIG. 10A is a diagram for explaining an example of a method for manufacturing a photoelectric conversion element.
  • FIG. 10B is a diagram for explaining an example of a method of manufacturing a photoelectric conversion element.
  • FIG. 10C is a diagram for describing an example of a method of manufacturing a photoelectric conversion element.
  • FIG. 10D is a diagram for describing an example of a method of manufacturing a photoelectric conversion element.
  • FIG. 11A is a schematic diagram illustrating a state where an i-type semiconductor layer and an n-type semiconductor layer are formed on a surface where an insulating layer is not formed.
  • FIG. 11B is a schematic diagram showing a state in which an i-type semiconductor layer and a p-type semiconductor layer are further formed from FIG. 11A.
  • FIG. 12 is sectional drawing which shows typically the structure of the photoelectric conversion element concerning the modification of the 3rd Embodiment of this invention.
  • FIG. 13A is a diagram for explaining an example of a method of manufacturing a photoelectric conversion element.
  • FIG. 13B is a diagram for describing an example of a method of manufacturing a photoelectric conversion element.
  • FIG. 14 is sectional drawing which shows typically the structure of the photoelectric conversion element concerning the 4th Embodiment of this invention.
  • FIG. 15A is a diagram for explaining an example of a method of manufacturing a photoelectric conversion element.
  • FIG. 12 is sectional drawing which shows typically the structure of the photoelectric conversion element concerning the modification of the 3rd Embodiment of this invention.
  • FIG. 13A is a diagram for explaining an example of a method of manufacturing a photoelectric conversion element.
  • FIG. 15B is a diagram for explaining an example of a method of manufacturing a photoelectric conversion element.
  • FIG. 15C is a diagram for describing an example of a method of manufacturing a photoelectric conversion element.
  • FIG. 15D is a diagram for describing an example of a method of manufacturing a photoelectric conversion element.
  • FIG. 16 is a schematic diagram illustrating an example of the configuration of the photoelectric conversion module according to the present embodiment.
  • FIG. 17 is a schematic diagram illustrating an example of the configuration of the photovoltaic power generation system according to the present embodiment.
  • FIG. 18 is a schematic diagram illustrating an example of the configuration of the photoelectric conversion module array illustrated in FIG.
  • FIG. 19 is a schematic diagram illustrating another example of the configuration of the solar power generation system according to the present embodiment.
  • FIG. 20 is a schematic diagram illustrating another example of the configuration of the photovoltaic power generation system according to the present embodiment.
  • FIG. 21 is a schematic diagram illustrating another example of the configuration of the photovoltaic
  • FIG. 1 is a cross-sectional view schematically showing the configuration of the photoelectric conversion element 1 according to the first embodiment of the present invention.
  • the photoelectric conversion element 1 includes a substrate 10 (silicon substrate), an ARC (Anti Reflection Coat) 11, a passivation layer 12, an insulating layer 13, an n-type semiconductor layer (first conductive semiconductor layer) 14, a p-type semiconductor layer (second semiconductor layer). Conductive semiconductor layer) 15, n-type electrode 16, and p-type electrode 17.
  • the substrate 10 is a single crystal silicon substrate having an n-type conductivity.
  • the thickness of the silicon substrate 10 is, for example, 100 to 150 ⁇ m.
  • a pyramid-shaped texture is formed on one surface of the substrate 10. The texture decreases the surface reflectance of the substrate 10 and increases the short-circuit current Jsc.
  • the photoelectric conversion element 1 is a so-called back junction type photoelectric conversion element in which both the n-type semiconductor layer 14 and the p-type semiconductor layer 15 are formed on the back surface.
  • the ARC 11 is formed so as to cover the light receiving surface of the substrate 10.
  • the ARC 11 decreases the surface reflectance of the substrate 10 and increases the short-circuit current Jsc.
  • the ARC 11 is formed by laminating a silicon oxide film having a thickness of about 20 nm and a silicon nitride film having a thickness of about 60 nm in this order.
  • the passivation layer 12 is formed so as to cover the back surface of the substrate 10.
  • the passivation layer 12 may be, for example, silicon oxide, silicon nitride, or silicon oxynitride, polycrystalline silicon, aluminum oxide, aluminum nitride, or aluminum oxynitride, phosphorous nitride, or titanium. Nitride and the like.
  • the passivation layer 12 is preferably an oxide of silicon.
  • the passivation layer 12 may be formed by oxidizing the substrate 10.
  • the thickness of the passivation layer 12 is, for example, 0.5 to 3 nm.
  • the insulating layer 13, the n-type semiconductor layer 14, and the p-type semiconductor layer 15 are formed on the passivation layer 12.
  • the n-type semiconductor layer 14 and the p-type semiconductor layer 15 are disposed adjacent to each other across the insulating layer 13 in the in-plane direction of the substrate 10.
  • the insulating layer 13 insulates the n-type semiconductor layer 14 from the p-type semiconductor layer 15.
  • the insulating layer 13 is formed in contact with the passivation layer 12. Neither the n-type semiconductor layer 14 nor the p-type semiconductor layer 15 is formed between the substrate 10 and the insulating layer 13.
  • the width L of the insulating layer 13 is preferably 2 to 800 ⁇ m. If the width L is smaller than 2 ⁇ m, depending on the manufacturing method, the n-type semiconductor layer 14 and the p-type semiconductor layer 15 may be in contact with each other, and the leakage current may increase. On the other hand, when the width L is wider than 800 ⁇ m, the areas of the n-type semiconductor layer 14 and the p-type semiconductor layer 15 are relatively small, and the series resistance is high.
  • the width L of the insulating layer 13 is more preferably 20 to 500 ⁇ m.
  • the layer thickness d of the insulating layer 13 is preferably 0.3 to 300 ⁇ m. In the present embodiment, the layer thickness d is larger than the height difference of the unevenness on the back surface of the substrate 10. This point will be described later.
  • the insulating layer 13 may be, for example, an inorganic material or an organic material.
  • the inorganic substance include silicon oxide, silicon nitride, or silicon oxynitride, polycrystalline silicon, aluminum oxide, aluminum nitride, or aluminum oxynitride.
  • organic substances include imide resins, epoxy resins, fluororesins, polycarbonates, and liquid crystal polymers.
  • the imide resin is, for example, polyimide.
  • the fluororesin is, for example, polytetrafluoroethylene (PTFE).
  • the n-type semiconductor layer 14 is an amorphous semiconductor layer having an n-type conductivity and containing hydrogen.
  • the n-type semiconductor layer 14 contains, for example, phosphorus (P) as a dopant.
  • the n-type semiconductor layer 14 is, for example, n-type amorphous silicon, n-type amorphous silicon germanium, n-type amorphous germanium, n-type amorphous silicon carbide, n-type amorphous silicon nitride, n-type non-crystalline. Examples thereof include crystalline silicon oxide, n-type amorphous silicon oxynitride, and n-type amorphous silicon carbon oxide.
  • the thickness of the n-type semiconductor layer 14 is, for example, 3 to 50 nm.
  • the p-type semiconductor layer 15 is an amorphous semiconductor layer having a p-type conductivity and containing hydrogen.
  • the p-type semiconductor layer 15 contains, for example, boron (B) as a dopant.
  • the p-type semiconductor layer 15 may be, for example, p-type amorphous silicon, p-type amorphous silicon germanium, p-type amorphous germanium, p-type amorphous silicon carbide, p-type amorphous silicon nitride, p-type non-crystalline. Examples thereof include crystalline silicon oxide, p-type amorphous silicon oxynitride, and p-type amorphous silicon carbon oxide.
  • the thickness of the p-type semiconductor layer 15 is, for example, 5 to 50 nm.
  • the amorphous semiconductor may include a microcrystalline phase.
  • the microcrystalline phase includes crystals having an average particle size of 1 to 50 nm.
  • the n-type electrode 16 is formed in contact with the n-type semiconductor layer 14, and the p-type electrode 17 is formed in contact with the p-type semiconductor layer 15.
  • the n-type electrode 16 includes a conductive layer 161 and a conductive layer 162.
  • the p-type electrode 17 includes a conductive layer 171 and a conductive layer 172.
  • Each of the conductive layers 161, 162, 171, and 172 is, for example, TCO, metal, or the like.
  • TCO is, for example, ITO (Indium Tin Oxide), ZnO, or the like.
  • the metal is, for example, Ag, Ni, Al, Cu, Sn, Pt, Au, or an alloy thereof.
  • each of the conductive layers 161 and 171 is, for example, 3 to 100 nm, and the thickness of each of the conductive layers 162 and 172 is, for example, about 2 ⁇ m.
  • a substrate 10 having a texture formed on one side is prepared (FIG. 2A).
  • the substrate 10 is manufactured as follows.
  • a wafer having a thickness of 100 to 300 ⁇ m is cut out from the bulk silicon by a wire saw. Etching for removing the damaged layer on the surface of the wafer and etching for adjusting the thickness are performed.
  • a protective film is formed on one surface of the etched wafer.
  • the protective film is, for example, silicon oxide, silicon nitride or the like.
  • the wafer on which the protective film is formed is etched using an alkaline solution such as NaOH or KOH (for example, an aqueous solution of KOH: 1 to 5 wt%, isopropyl alcohol: 1 to 10 wt%).
  • a pyramidal texture is formed on the surface where the protective film is not formed by anisotropic etching.
  • the substrate 10 is obtained by removing the protective film after the etching.
  • the ARC 11 and the passivation layer 12 are formed on the substrate 10 (FIG. 2B).
  • the ARC 11 is formed by laminating a silicon oxide film and a silicon nitride film
  • the passivation layer 12 is a silicon oxide film.
  • the surface of the substrate 10 is oxidized to form an oxide film on the light receiving surface and a passivation layer 12 on the back surface.
  • a silicon nitride film is formed on the oxide film on the light receiving surface to form ARC11.
  • the substrate 10 may be oxidized by either wet treatment or thermal oxidation.
  • wet processing for example, the substrate 10 is immersed in hydrogen peroxide, nitric acid, ozone water, etc., and then heated to 800 to 1000 ° C. in a dry atmosphere.
  • thermal oxidation for example, the substrate 10 is heated to 900 to 1000 ° C. in an atmosphere of oxygen or water vapor.
  • the silicon nitride film can be formed by sputtering, EB (Electron Beam) vapor deposition, TEOS method, or the like.
  • the SiON film can be formed by nitriding with nitrogen plasma by PECVD (Plasma Enhanced Chemical Vapor Deposition) and further annealing at 500 ° C. or higher.
  • PECVD Pulsma Enhanced Chemical Vapor Deposition
  • the passivation film with SiON it is possible to suppress the diffusion of dopants such as boron contained in the p-type layer formed on the passivation film into the silicon substrate. By doing so, even when a passivation film having a thickness capable of flowing a tunnel current or the like is formed, it is more preferable because diffusion of boron can be effectively suppressed.
  • the insulating layer 13 is formed on the passivation layer 12 to be thicker than the unevenness on the back surface of the substrate 10 (FIG. 2C).
  • the insulating layer 13 is formed using silicon oxide, silicon nitride, silicon oxynitride, polycrystalline silicon, aluminum oxide, aluminum nitride, aluminum oxynitride, or the like, for example, vapor deposition Or by sputtering.
  • silicon oxide, silicon nitride, or silicon oxynitride is used as the insulating layer 13, a printing method or a film formation method using an inkjet may be used.
  • the printing method is, for example, a screen printing method. Even when an organic material is used for the insulating layer 13, a printing method or a film forming method using an ink jet can be used.
  • n-type semiconductor layer 14 is formed in a part of the region sandwiched between the insulating layers 13 on the back surface of the substrate 10 (FIG. 2D).
  • the n-type semiconductor layer 14 can be formed by, for example, PECVD (Plasma Enhanced Chemical Vapor Deposition).
  • substrate temperature 130 to 180 ° C.
  • hydrogen gas flow rate 0 to 100 sccm
  • silane gas flow rate 40 sccm
  • mixed gas of phosphine and hydrogen phosphine concentration with respect to hydrogen: 1%
  • flow rate 40 sccm
  • pressure 40 to 120 Pa
  • a mask MA is arranged in a region where the n-type semiconductor layer 14 is not formed.
  • the n-type semiconductor layer 14 can be formed only in a part of the region sandwiched between the insulating layers 13 on the back surface of the substrate 10 (region A in FIG. 2D).
  • a p-type semiconductor layer 15 is formed in another part of the region sandwiched between the insulating layers 13 on the back surface of the substrate 10 (FIG. 2E).
  • the p-type semiconductor layer 15 can be formed by PECVD, for example.
  • substrate temperature 130-180 ° C.
  • hydrogen gas flow rate 0-100 sccm
  • silane gas flow rate 40 sccm
  • pressure 40-120 Pa
  • the p-type semiconductor layer 15 is formed only in a part of the region sandwiched between the insulating layers 13 on the back surface of the substrate 10 (region B in FIG. 2E) using the mask MB. To do.
  • the n-type semiconductor layer 14 is washed with hydrofluoric acid or the like. Then, it is preferable to remove the natural oxide film.
  • the insulating layer 13 When the insulating layer 13 is formed of an organic material, there is no problem with the insulating layer 13 even if it is washed with hydrofluoric acid or the like. However, when an oxide film such as SiO 2, a nitride film, or an oxynitride film is formed, it is etched with hydrofluoric acid or the like, so that the insulating layer 13 is not etched away. It is necessary to adjust time etc.
  • a conductive layer 191 and a conductive layer 192 are formed to cover the insulating layer 13, the n-type semiconductor layer 14, and the p-type semiconductor layer 15 (FIG. 2F). As will be described later, the conductive layer 191 and the conductive layer 192 are layers that are separated in the next step and become the n-type electrode 16 and the p-type electrode 17.
  • the conductive layers 191 and 192 can be formed by a sputtering method, a vapor deposition method, an ion plating method, a thermal CVD method, an MOCVD method, a sol-gel method, a method of spraying and heating a liquefied raw material, an ink jet method, or the like.
  • a sputtering method a vapor deposition method, an ion plating method, a thermal CVD method, an MOCVD method, a sol-gel method, a method of spraying and heating a liquefied raw material, an ink jet method, or the like.
  • ITO for example, an ITO target having a SnO 2 was 0.5 ⁇ 4 wt% dope, flowing a mixed gas of argon gas or argon gas and oxygen gas, substrate temperature: 25 ⁇ 250 ° C., Pressure: 0.1-1.
  • It can be formed by performing a sputtering process under conditions of 5 Pa and power: 0.01 to 2 kW.
  • ZnO it can be formed by the same sputtering using a ZnO target doped with 0.5 to 4 wt% of Al instead of the ITO target.
  • Al can be formed by EB vapor deposition.
  • the conductive layer 192 may be formed by plating using the conductive layer 191 as a seed electrode.
  • the conductive layer 191 for example, Ni, W, Co, Ti, or an alloy thereof, or an alloy of these metals and P, B can be used as the conductive layer 191.
  • Cu, Al, Sn, or the like can be used as the conductive layer 192.
  • Grooves are formed in the conductive layers 191 and 192 that overlap with the insulating layer 13 in plan view (FIG. 2G). More specifically, the conductive layer 191 is separated into conductive layers 161 and 171, and the conductive layer 192 is separated into conductive layers 162 and 172. Thereby, the n-type electrode 16 and the p-type electrode 17 are formed.
  • the groove is preferably formed by laser ablation.
  • the laser used for laser ablation is, for example, an ArF excimer laser (wavelength: 193 nm).
  • substrate 10 can be suppressed by utilizing ultrashort pulse laser (femtosecond order) and UV light of a short wavelength.
  • the configuration and manufacturing method of the photoelectric conversion element 1 according to the first embodiment of the present invention have been described above.
  • the p-type semiconductor layer 15 and the substrate 10 form a pn junction with the passivation layer 12 interposed therebetween.
  • Electrons and holes move to the n-type semiconductor layer 14 and the p-type semiconductor layer 15 by tunneling the passivation layer 12, respectively, and are taken out as current through the n-type electrode 16 and the p-type electrode 17.
  • the passivation layer 12 reduces defects at the interface between the substrate 10 and the n-type semiconductor layer 14 and at the interface between the substrate 10 and the p-type semiconductor layer 15.
  • the n-type semiconductor layer 14 and the p-type semiconductor layer 15 are adjacent to each other with the insulating layer 13 interposed therebetween in the in-plane direction of the substrate 10.
  • the insulating layer 13 is formed before the n-type semiconductor layer 14 and the p-type semiconductor layer 15 are formed. Therefore, neither the n-type semiconductor layer 14 nor the p-type semiconductor layer 15 is formed between the substrate 10 and the insulating layer 13.
  • the n-type semiconductor layer 14 and the p-type semiconductor layer 15 are reliably separated by the insulating layer 13. As a result, leakage between the n-type semiconductor layer 14 and the p-type semiconductor layer 15 can be suppressed, and a high shunt resistance can be obtained.
  • the layer thickness d of the insulating layer 13 is larger than the height difference of the unevenness on the back surface of the substrate 10. This effect will be described with reference to FIGS. 3A to 3C.
  • FIG. 3A is a surface micrograph of the silicon substrate.
  • FIG. 3B is an uneven profile of the silicon substrate.
  • the substrate 10 may have irregularities of about 1 ⁇ m on the surface where no texture is formed due to the influence of etching performed to remove the damaged layer.
  • the layer thickness d of the insulating layer 13 is made larger than the height difference ⁇ of the unevenness on the back surface of the substrate 10. Note that the height difference ⁇ indicates the maximum height difference of the unevenness on the back surface of the substrate 10.
  • the insulating layer 13 protrudes from the back surface of the substrate 10 even when the insulating layer 13 is formed in the deepest part of the recess on the back surface of the substrate 10. Therefore, when the n-type semiconductor layer 14 and the p-type semiconductor layer 15 are formed in the same plane, the n-type semiconductor layer 14 and the p-type semiconductor layer 15 can be prevented from contacting each other. As a result, leakage between the n-type semiconductor layer 14 and the p-type semiconductor layer 15 can be suppressed, and a high shunt resistance can be obtained.
  • the n-type semiconductor layer 14 and the p-type semiconductor layer 15 can be more reliably separated if the thickness d of the insulating layer 13 is larger than the height difference of the irregularities on the back surface of the substrate 10.
  • the n-type semiconductor layer 14 and the p-type semiconductor layer 15 can be separated to some extent even if the layer thickness d of the insulating layer 13 is equal to or less than the height difference of the unevenness on the back surface of the substrate 10. Therefore, it is not essential that the layer thickness d of the insulating layer 13 is larger than the height difference of the unevenness on the back surface of the substrate 10.
  • the layer thickness d is preferably 3 ⁇ m or more. However, if the substrate 10 is flat like a mirror substrate, the layer thickness d may be less than 3 ⁇ m. Even when the substrate 10 is flat like a mirror substrate, the layer thickness d is preferably 0.3 ⁇ m or more. If the layer thickness d is 0.3 ⁇ m or more, the substrate 10 can be effectively protected from damage due to laser ablation when laser ablation is used in the manufacturing process.
  • the layer thickness d is greater than 300 ⁇ m, peeling or cracking is likely to occur due to stress or the like. Therefore, the layer thickness d is preferably 300 ⁇ m or less from the viewpoint of the upper limit.
  • FIG. 4A is a schematic diagram showing a state in which an n-type semiconductor layer 94 is formed on the surface where the insulating layer 13 is not formed.
  • the n-type semiconductor layer 94 is formed using a mask MC having an opening at a portion facing the region A.
  • active species (radicals) generated by the decomposition of the source gas enter between the mask MC and the substrate 10, and the n-type semiconductor layer 94 is also formed in the region C.
  • FIG. 4B is a schematic diagram showing a state in which the p-type semiconductor layer 95 is further formed from FIG. 4A.
  • the p-type semiconductor layer 95 is formed using a mask MD having an opening at a portion facing the region B.
  • the active species enter between the mask MD and the substrate 10, and the p-type semiconductor layer 95 is also formed in the region D. Therefore, in this comparative example, the n-type semiconductor layer 94 and the p-type semiconductor layer 95 are in contact with each other.
  • the active species are blocked by the insulating layer 13, and therefore, between the mask MA and the substrate 10 or between the mask MB and the substrate 10. Do not intrude in between. Therefore, the n-type semiconductor layer 14 and the p-type semiconductor layer 15 can be reliably separated.
  • the mask MA or MB and the insulating layer 13 can be more easily adhered as the layer thickness d (FIG. 1) of the insulating layer 13 is larger. Further, the greater the layer thickness d, the more active species can be prevented from wrapping around. Therefore, the layer thickness d is preferably as thick as possible within a range not exceeding 300 ⁇ m.
  • FIG. 5A is a cross-sectional view schematically showing the shape of the mask MA preferably used in the present embodiment.
  • a recess MAa is formed on the lower surface of the mask MA.
  • the recesses MAa are formed so as to correspond to the interval and width of the insulating layer 13.
  • the alignment between the mask Ma and the substrate 10 can be performed accurately and easily.
  • the area where the mask MA and the insulating layer 13 face each other is increased by the concave portion MAa, the wraparound of the active species can be effectively suppressed.
  • FIG. 5B is a cross-sectional view schematically showing the shape of a mask ME which is another example of a mask suitably used in the present embodiment.
  • a recess MEa is formed instead of the recess MAa of the mask MA.
  • the recess MEa is formed so as to straddle the insulating layer 13. Also with the mask ME, alignment can be performed accurately and easily, and the wraparound of active species can be effectively suppressed.
  • a metal mask such as stainless steel, copper, nickel, nickel alloy (42 alloy, invar material, etc.), molybdenum, or the like, or a glass mask, a ceramic mask, an organic film, or the like may be used. May be.
  • FIG. 6 is a cross-sectional view schematically showing a configuration of a photoelectric conversion element 1A according to a modification of the first embodiment of the present invention.
  • the photoelectric conversion element 1 ⁇ / b> A includes an n-type semiconductor layer 14 ⁇ / b> A instead of the n-type semiconductor layer 14 of the photoelectric conversion element 1.
  • the layer thickness d of the insulating layer 13 is larger than the height difference of the unevenness on the back surface of the substrate 10.
  • the photoelectric conversion element 1 and the photoelectric conversion element 1A are different in the stacking order of the n-type semiconductor layer 14 (n-type semiconductor layer 14A) and the insulating layer 13.
  • the insulating layer 13 is formed so as to straddle the passivation film 12 and the n-type semiconductor layer 14A.
  • the n-type semiconductor layer 14 ⁇ / b> A exists in a part between the insulating layer 13 and the substrate 10.
  • an n-type semiconductor layer 14A is formed on the passivation layer 12 (FIG. 7A).
  • the n-type semiconductor layer 14A is formed using a mask MC having an opening in a portion facing the region A.
  • active species radicals
  • An insulating layer 13 is formed in a portion straddling the passivation layer 12 and the n-type semiconductor layer 14A (FIG. 7B). Note that the insulating layer 13 may be formed outside the n-type semiconductor layer 14A. In other words, the insulating layer 13 may be formed so as to sandwich the n-type semiconductor layer 14A. If the distance between the insulating layers 13 is increased, the n-type semiconductor layer 14 ⁇ / b> A will not be outside the insulating layer 13.
  • a p-type semiconductor layer 15 is formed in a region between the insulating layers 13 where the n-type semiconductor layer 14A is not formed (FIG. 7C). As in the case of the photoelectric conversion element 1, the p-type semiconductor layer 15 is formed only in a part of the region sandwiched between the insulating layers 13 on the back surface of the substrate 10 (region B in FIG. 7C) using the mask MB. .
  • the n-type electrode 16 and the p-type electrode 17 are formed in the same manner as the photoelectric conversion element 1. Thereby, the photoelectric conversion element 1A is manufactured.
  • the n-type semiconductor layer 14A, the insulating layer 13, and the p-type semiconductor layer 15 are formed in this order.
  • the p-type semiconductor layer, the insulating layer, and the n-type semiconductor layer are formed in this order. Also good. That is, at least one of the step of forming the n-type semiconductor layer and the step of forming the p-type semiconductor layer may be performed after the step of forming the insulating layer.
  • FIG. 8 is a cross-sectional view schematically showing the configuration of the photoelectric conversion element 2 according to the second embodiment of the present invention.
  • the photoelectric conversion element 2 includes an i-type semiconductor layer 22 in place of the passivation layer 12 of the photoelectric conversion element 1.
  • the i-type semiconductor layer 22 is a layer of an amorphous semiconductor that is substantially intrinsic and contains hydrogen.
  • the i-type semiconductor layer 22 includes, for example, i-type amorphous silicon, i-type amorphous silicon germanium, i-type amorphous germanium, i-type amorphous silicon carbide, i-type amorphous silicon nitride, i-type non-crystalline. It consists of crystalline silicon oxide, i-type amorphous silicon oxynitride, i-type amorphous silicon carbon oxide, and the like.
  • the i-type semiconductor layer 22 has a thickness of 1 to 10 nm, for example.
  • a dopant such as boron contained in the p-type semiconductor layer 15 formed on the i-type semiconductor layer 22 is added to the substrate 10. Can be prevented from diffusing. This is more preferable because boron diffusion can be effectively suppressed.
  • the i-type semiconductor layer 22 reduces defects at the interface between the substrate 10 and the n-type semiconductor layer 14 and at the interface between the substrate 10 and the p-type semiconductor layer 15.
  • the photoelectric conversion element 2 can be manufactured by forming the i-type semiconductor layer 22 instead of the passivation film 12 of the photoelectric conversion element 1.
  • the i-type semiconductor layer 22 may be formed before the ARC 11 is formed, or may be formed after the ARC 11 is formed.
  • the i-type semiconductor layer 22 can be formed by PECVD, for example. For example, by performing PECVD under conditions of substrate temperature: 130 to 180 ° C., hydrogen gas flow rate: 0 to 100 sccm, silane gas flow rate: 40 sccm, pressure: 40 to 120 Pa, RF power density: 5 to 15 mW / cm 2 , Type amorphous silicon can be formed.
  • FIG. 9 is a cross-sectional view schematically showing the configuration of the photoelectric conversion element 3 according to the third embodiment of the present invention.
  • the photoelectric conversion element 3 includes an i-type semiconductor layer (first i-type semiconductor layer) 321 and an i-type semiconductor layer (second i-type semiconductor layer) 322 instead of the passivation layer 12 of the photoelectric conversion element 1.
  • the i-type semiconductor layer 321 is formed between the substrate 10 and the n-type semiconductor layer 14, and the i-type semiconductor layer 322 is formed between the substrate 10 and the p-type semiconductor layer 15.
  • the insulating layer 13 is in contact with the back surface of the substrate 10. That is, none of the i-type semiconductor layers 321 and 322, the n-type semiconductor layer 14, and the p-type semiconductor layer 15 are formed between the substrate 10 and the insulating layer 13.
  • I-type semiconductor layers 321 and 322 reduce defects at the interface between substrate 10 and n-type semiconductor layer 14 and at the interface between substrate 10 and p-type semiconductor layer 15.
  • a substrate 10 having a texture formed on one side is prepared.
  • An ARC 11 is formed on the light receiving surface of the substrate 10 (FIG. 10A).
  • An insulating layer 13 is formed on the back surface of the substrate 10 (FIG. 10B).
  • the i-type semiconductor layer 321 and the n-type semiconductor layer 14 are formed in this order in a part of the region sandwiched between the insulating layers 13 on the back surface of the substrate 10 (FIG. 10C).
  • the i-type semiconductor layer 321 and the n-type semiconductor layer 14 can be formed by PECVD, for example. Similar to the first embodiment, by using the mask MA, the i-type semiconductor layer 321 and the n-type semiconductor layer 321 and the n-type semiconductor layer only in a part of the region sandwiched between the insulating layers 13 on the back surface of the substrate 10 (region A in FIG. 10C).
  • the semiconductor layer 14 can be formed.
  • the i-type semiconductor layer 322 and the p-type semiconductor layer 15 are formed in this order in the other part of the region sandwiched between the insulating layers 13 on the back surface of the substrate 10 (FIG. 10D).
  • the i-type semiconductor layer 322 and the p-type semiconductor layer 15 can be formed by PECVD, for example. Similar to the first embodiment, by using the mask MB, the i-type semiconductor layer 322 and the p-type are formed only in a part of the region sandwiched between the insulating layers 13 on the back surface of the substrate 10 (region B in FIG. 10D).
  • the semiconductor layer 15 can be formed.
  • the n-type electrode 16 and the p-type electrode 17 are formed. Thereby, the photoelectric conversion element 3 is manufactured.
  • FIG. 11A is a schematic diagram showing a state in which the i-type semiconductor layer 921 and the n-type semiconductor layer 94 are formed on the surface where the insulating layer 13 is not formed. At this time, the i-type semiconductor layer 921 and the n-type semiconductor layer 94 are also formed in the region C due to the wraparound of the active species.
  • the i-type semiconductor layer 921 and the n-type semiconductor layer 94 become thinner toward the ends.
  • the passivation property of the i-type semiconductor layer 921 is lowered in the region C. This shortens the lifetime of minority carriers.
  • FIG. 11B is a schematic diagram showing a state in which an i-type semiconductor layer 922 and a p-type semiconductor layer 95 are further formed from FIG. 11A. Also in this case, the i-type semiconductor layer 922 and the p-type semiconductor layer 95 are formed also in the region D by the wraparound of the active species. Then, the i-type semiconductor layer 922 and the p-type semiconductor layer 95 become thinner toward the end portions. When the i-type semiconductor layer 922 is thinned, the passivation property of the i-type semiconductor layer 922 is lowered in the region D. This shortens the lifetime of minority carriers.
  • the insulating layer 13 by forming the insulating layer 13, it is possible to prevent a region such as the region C or the region D from being present. Therefore, the lifetime of the minority carrier can be suppressed from being shortened.
  • FIG. 12 is a cross-sectional view schematically showing the configuration of a photoelectric conversion element 3A according to a modification of the third embodiment of the present invention.
  • the photoelectric conversion element 3 ⁇ / b> A further includes a passivation layer 323 formed between the substrate 10 and the insulating layer 13 in addition to the configuration of the photoelectric conversion element 3.
  • the passivation layer 323 may be, for example, silicon oxide, silicon nitride, or silicon oxynitride, polycrystalline silicon, aluminum oxide, aluminum nitride, or aluminum oxynitride, phosphorous nitride, or titanium. Nitride and the like.
  • the passivation layer 323 is preferably an oxide of silicon.
  • the passivation layer 323 may be formed by oxidizing the substrate 10. The thickness of the passivation layer 323 is, for example, 0.5 to 3 nm.
  • a substrate 10 having a texture formed on one side is prepared.
  • the ARC 11 and the passivation layer 12 are formed.
  • the insulating layer 13 is formed on the passivation layer 12 (FIG. 13A).
  • the passivation layer 12 is etched (FIG. 13B). As a result, the passivation layer 12 between the substrate 10 and the insulating layer 13 remains as the passivation layer 323, and the other portion of the passivation layer 12 is removed.
  • the i-type semiconductor layer 321 and the n-type semiconductor layer 14, the i-type semiconductor layer 322 and the p-type semiconductor layer 15, and the n-type electrode 16 and the p-type electrode 17 are formed. Thereby, the photoelectric conversion element 3A is manufactured.
  • the photoelectric conversion element 3 ⁇ / b> A includes a passivation layer 323 between the substrate 10 and the insulating layer 13. With the passivation layer 323, the passivation property in the lower portion of the insulating layer 13 can be further enhanced as compared with the photoelectric conversion element 3.
  • FIG. 14 is a cross-sectional view schematically showing the configuration of the photoelectric conversion element 4 according to the fourth embodiment of the present invention.
  • the photoelectric conversion element 4 includes an n-type semiconductor layer 441 and an n-type dopant source 442 instead of the n-type semiconductor layer 14 of the photoelectric conversion element 1, and replaces the p-type semiconductor layer 15 with a p-type semiconductor layer 451 and a p-type dopant.
  • a source 452 is provided.
  • the n-type semiconductor layer 441 and the p-type semiconductor layer 451 are formed on the passivation layer 12.
  • the n-type semiconductor layer 441 and the p-type semiconductor layer 451 are disposed adjacent to each other across the insulating layer 13 in the in-plane direction of the substrate 10.
  • the n-type dopant source 442 is formed on the n-type semiconductor layer 441, and the p-type dopant source 452 is formed on the p-type semiconductor layer 451.
  • the n-type semiconductor layer 441 and the p-type semiconductor layer 451 are disposed adjacent to each other across the insulating layer 13 in the in-plane direction of the substrate 10.
  • the n-type semiconductor layer 441 is polycrystalline silicon in which an n-type dopant is diffused.
  • the n-type dopant source 442 is, for example, phosphorus-doped silicate glass (PSG).
  • the p-type semiconductor layer 451 is polycrystalline silicon in which a p-type dopant is diffused.
  • the p-type dopant source 452 is, for example, boron-doped silicate glass (BSG).
  • a substrate 10 having a texture formed on one side is prepared.
  • the ARC 11 and the passivation layer 12 are formed.
  • the insulating layer 13 is formed on the passivation layer 12 (FIG. 15A).
  • a polycrystalline silicon layer 440 is formed on the passivation layer 12 (FIG. 15B).
  • the polycrystalline silicon layer 440 can be formed by, for example, LPCVD (Low Pressure CVD).
  • n-type dopant source 442 and a p-type dopant source 452 are formed on the polycrystalline silicon layer 440 (FIG. 15C).
  • the n-type dopant source 442 and the p-type dopant source 452 can be formed by, for example, a screen printing method.
  • the substrate 10 is heat-treated to diffuse the dopants of the n-type dopant source 442 and the p-type dopant source 452 into the polycrystalline silicon layer 440 (FIG. 15D).
  • the heat treatment temperature is 600 to 1100 ° C., for example.
  • the n-type semiconductor layer 441 is formed in a part of the region sandwiched between the insulating layers 13 on the back surface of the substrate 10, and the p-type is formed on another part of the region sandwiched between the insulating layers 13 on the back surface of the substrate 10.
  • a semiconductor layer 451 is formed.
  • n-type dopant source 442 and the p-type dopant source 452 may be removed after the n-type semiconductor layer 441 and the p-type semiconductor layer 451 are formed.
  • the n-type electrode 16 and the p-type electrode 17 are formed in the same manner as in the first embodiment. Thereby, the photoelectric conversion element 4 is manufactured.
  • the case where the conductivity type of the substrate 10 is n-type has been described, but the conductivity type of the substrate 10 may be p-type.
  • the case where the ARC 11 is formed on the light receiving surface has been described. However, the ARC 11 may not be formed. Instead of the ARC 11, or between the light receiving surface and the ARC 11, an n + layer in which a high concentration n-type dopant is diffused may be formed.
  • each of the n-type electrode 16 and the p-type electrode 17 may be composed of one conductive layer or may be composed of three or more conductive layers.
  • the first layer may be TCO
  • the second layer may be Ni
  • the third layer may be Cu formed by plating.
  • an amorphous semiconductor layer may be formed by CatCVD instead of PECVD.
  • the film formation conditions are, for example, substrate temperature: 100 to 300 ° C., pressure: 10 to 500 Pa, temperature of the thermal catalyst (when tungsten is used as the thermal catalyst): 1500 to 2000 ° C., RF power density : 0.01 to 1 W / cm 2 . Accordingly, a high-quality amorphous semiconductor layer can be formed at a relatively low temperature and in a short time.
  • the photoelectric conversion device in this specification is a device based on a wide concept including a photoelectric conversion element, a photoelectric conversion module using the photoelectric conversion element, and a photovoltaic power generation system including the photoelectric conversion module.
  • a photoelectric conversion module (fifth embodiment) including at least one of the photoelectric conversion elements of the first to fourth embodiments and a photovoltaic power generation system (sixth embodiment, seventh embodiment). Mode) will be described.
  • the photoelectric conversion module and the photovoltaic power generation system including the photoelectric conversion elements can also have high conversion efficiency.
  • the fifth embodiment is a photoelectric conversion module including at least one of the photoelectric conversion elements of the first to fourth embodiments.
  • FIG. 16 is a schematic diagram illustrating an example of the configuration of the photoelectric conversion module according to the present embodiment.
  • the photoelectric conversion module 1000 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1013 and 1014.
  • a plurality of photoelectric conversion elements 1001 are arranged in an array and connected in series.
  • FIG. 16 illustrates an arrangement in which the photoelectric conversion elements 1001 are connected in series.
  • the arrangement and connection method are not limited to this, and the photoelectric conversion elements 1001 may be connected in parallel or may be combined in series and parallel. It may be an array.
  • any one of the photoelectric conversion elements of the first to fourth embodiments is used.
  • the photoelectric conversion module 1000 is not limited to the above description as long as at least one of the plurality of photoelectric conversion elements 1001 includes any one of the photoelectric conversion elements of the first to fourth embodiments, and can take any configuration. To do. Further, the number of photoelectric conversion elements 1001 included in the photoelectric conversion module 1000 can be any integer of 2 or more.
  • the cover 1002 is composed of a weatherproof cover and covers the plurality of photoelectric conversion elements 1001.
  • the cover 1002 includes, for example, a transparent base material (for example, glass) provided on the light receiving surface side of the photoelectric conversion element 1001 and a back surface base material provided on the back surface side opposite to the light receiving surface side of the photoelectric conversion element 1001. (For example, glass, a resin sheet etc.) and the sealing material (for example, EVA etc.) which fills the clearance gap between the said transparent base material and the said resin base material.
  • a transparent base material for example, glass
  • a back surface base material provided on the back surface side opposite to the light receiving surface side of the photoelectric conversion element 1001.
  • the sealing material for example, EVA etc.
  • the output terminal 1013 is connected to a photoelectric conversion element 1001 arranged at one end of a plurality of photoelectric conversion elements 1001 connected in series.
  • the output terminal 1014 is connected to the photoelectric conversion element 1001 arranged at the other end of the plurality of photoelectric conversion elements 1001 connected in series.
  • the sixth embodiment is a photovoltaic power generation system including at least one of the photoelectric conversion elements of the first to fourth embodiments. Since the photoelectric conversion element of the present invention has high conversion efficiency, the photovoltaic power generation system of the present invention including the photoelectric conversion element can also have high conversion efficiency. Note that the solar power generation system is a device that appropriately converts the power output from the photoelectric conversion module and supplies the converted power to a commercial power system or an electric device.
  • FIG. 17 is a schematic diagram illustrating an example of the configuration of the photovoltaic power generation system according to the present embodiment.
  • the photovoltaic power generation system 2000 includes a photoelectric conversion module array 2001, a connection box 2002, a power conditioner 2003, a distribution board 2004, and a power meter 2005.
  • the photoelectric conversion module array 2001 includes a plurality of photoelectric conversion modules 1000 (fifth embodiment). Since the photoelectric conversion element of the present invention has high conversion efficiency, the photovoltaic power generation system of the present invention including the photoelectric conversion element can also have high conversion efficiency.
  • the solar power generation system 2000 is added with a function generally called “Home Energy Management System (HEMS)”, “Building Energy Management System (BEMS)”, or the like. can do. Accordingly, the energy consumption can be reduced by monitoring the power generation amount of the solar power generation system 2000, monitoring / controlling the power consumption amount of each electrical device connected to the solar power generation system 2000, and the like.
  • HEMS Home Energy Management System
  • BEMS Building Energy Management System
  • connection box 2002 is connected to the photoelectric conversion module array 2001.
  • the power conditioner 2003 is connected to the connection box 2002.
  • the distribution board 2004 is connected to the power conditioner 2003 and the electrical equipment 2011.
  • the power meter 2005 is connected to the distribution board 2004 and the commercial power system.
  • a storage battery 2100 may be connected to the power conditioner 2003 as shown in FIG. In this case, output fluctuation due to fluctuations in the amount of sunlight can be suppressed, and power stored in the storage battery 2100 can be supplied even in a time zone without sunlight.
  • the storage battery 2100 may be built in the power conditioner 2003.
  • the photoelectric conversion module array 2001 converts sunlight into electricity to generate DC power and supplies the DC power to the connection box 2002.
  • the power conditioner 2003 converts the DC power received from the connection box 2002 into AC power and supplies it to the distribution board 2004. Note that part or all of the DC power received from the connection box 2002 may be supplied to the distribution board 2004 as it is without being converted to AC power.
  • the power conditioner 2003 receives the direct current received from the connection box 2002. A part or all of the electric power can be appropriately converted into electric power and stored in the storage battery 2100.
  • the power stored in the storage battery 2100 is appropriately supplied to the power conditioner 2003 according to the amount of power generated by the photoelectric conversion module and the power consumption of the electrical equipment 2011, and is appropriately converted to the distribution board 2004. Supplied.
  • the distribution board 2004 supplies the electric equipment 2011 with at least one of the electric power received from the power conditioner 2003 and the commercial electric power received via the electric power meter 2005.
  • the distribution board 2004 supplies the AC power received from the power conditioner 2003 to the electrical equipment 2011 when the AC power received from the power conditioner 2003 is larger than the power consumption of the electrical equipment 2011.
  • the surplus AC power is supplied to the commercial power system via the power meter 2005.
  • the distribution board 2004 receives the AC power received from the commercial power system and the AC power received from the power conditioner 2003 in the electrical equipment. To 2011.
  • the power meter 2005 measures the power in the direction from the commercial power system to the distribution board 2004 and measures the power in the direction from the distribution board 2004 to the commercial power system.
  • the photoelectric conversion module array 2001 will be described.
  • FIG. 18 is a schematic diagram showing an example of the configuration of the photoelectric conversion module array 2001 shown in FIG. Referring to FIG. 18, photoelectric conversion module array 2001 includes a plurality of photoelectric conversion modules 1000 and output terminals 2013 and 2014.
  • a plurality of photoelectric conversion modules 1000 are arranged in an array and connected in series.
  • FIG. 18 illustrates an arrangement in which the photoelectric conversion modules 1000 are connected in series.
  • the arrangement and connection method are not limited to this, and the photoelectric conversion modules 1000 may be connected in parallel or may be combined in series and parallel. It is good also as an arrangement.
  • the number of photoelectric conversion modules 1000 included in the photoelectric conversion module array 2001 can be any integer of 2 or more.
  • the output terminal 2013 is connected to the photoelectric conversion module 1000 located at one end of the plurality of photoelectric conversion modules 1000 connected in series.
  • the output terminal 2014 is connected to the photoelectric conversion module 1000 located at the other end of the plurality of photoelectric conversion modules 1000 connected in series.
  • the photovoltaic power generation system of this embodiment is such that at least one of the plurality of photoelectric conversion elements 1001 includes any one of the photoelectric conversion elements of the first to fourth embodiments.
  • the present invention is not limited to the above description, and any configuration can be taken.
  • the seventh embodiment is a photovoltaic power generation system that is larger than the photovoltaic power generation system described as the sixth embodiment.
  • the solar power generation system according to the seventh embodiment also includes at least one of the photoelectric conversion elements of the first to fourth embodiments. Since the photoelectric conversion element of the present invention has high conversion efficiency, the photovoltaic power generation system of the present invention including the photoelectric conversion element can also have high conversion efficiency.
  • FIG. 19 is a schematic diagram illustrating another example of the configuration of the solar power generation system according to the present embodiment.
  • solar power generation system 4000 includes a plurality of subsystems 4001, a plurality of power conditioners 4003, and a transformer 4004.
  • the photovoltaic power generation system 4000 is a larger scale photovoltaic power generation system than the photovoltaic power generation system 2000 shown in FIG. Since the photoelectric conversion element of the present invention has high conversion efficiency, the photovoltaic power generation system of the present invention including the photoelectric conversion element can also have high conversion efficiency.
  • the plurality of power conditioners 4003 are each connected to the subsystem 4001.
  • the number of the power conditioners 4003 and the subsystems 4001 connected thereto can be any integer of 2 or more.
  • a storage battery 4100 may be connected to the power conditioner 4003 as shown in FIG. In this case, output fluctuation due to fluctuations in the amount of sunshine can be suppressed, and power stored in the storage battery 4100 can be supplied even in a time zone without sunshine.
  • the storage battery 4100 may be built in the power conditioner 4003.
  • the transformer 4004 is connected to a plurality of power conditioners 4003 and a commercial power system.
  • Each of the plurality of subsystems 4001 includes a plurality of module systems 3000.
  • the number of module systems 3000 in the subsystem 4001 can be any integer greater than or equal to two.
  • Each of the plurality of module systems 3000 includes a plurality of photoelectric conversion module arrays 2001, a plurality of connection boxes 3002, and a current collection box 3004.
  • the number of the junction box 3002 in the module system 3000 and the photoelectric conversion module array 2001 connected to the junction box 3002 can be any integer of 2 or more.
  • the current collection box 3004 is connected to a plurality of connection boxes 3002.
  • the power conditioner 4003 is connected to a plurality of current collection boxes 3004 in the subsystem 4001.
  • the plurality of photoelectric conversion module arrays 2001 of the module system 3000 convert sunlight into electricity to generate DC power, and supply the DC power to the current collection box 3004 via the connection box 3002.
  • a plurality of current collection boxes 3004 in the subsystem 4001 supplies DC power to the power conditioner 4003.
  • the plurality of power conditioners 4003 convert DC power into AC power and supply the AC power to the transformer 4004.
  • the power conditioner 4003 when the storage battery 4100 is connected to the power conditioner 4003 (or when the storage battery 4100 is built in the power conditioner 4003), the power conditioner 4003 is received from the current collection box 3004. A part or all of the DC power can be appropriately converted into power and stored in the storage battery 4100.
  • the electric power stored in the storage battery 4100 is appropriately supplied to the power conditioner 4003 side according to the power generation amount of the subsystem 4001, appropriately converted into electric power, and supplied to the transformer 4004.
  • the transformer 4004 converts the voltage level of AC power received from a plurality of power conditioners 4003 and supplies it to the commercial power system.
  • the solar power generation system 4000 only needs to have at least one of the photoelectric conversion elements of the first to fourth embodiments, and all the photoelectric conversion elements included in the solar power generation system 4000 are the first to fourth. It is not necessary to be the photoelectric conversion element of the embodiment.
  • all of the photoelectric conversion elements included in one subsystem 4001 are any of the photoelectric conversion elements of the first to fourth embodiments, and a part or all of the photoelectric conversion elements included in another subsystem 4001 are There may be cases where the photoelectric conversion elements of the first to fourth embodiments are not used.
  • a photoelectric conversion device includes a silicon substrate, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer which are formed on one surface of the silicon substrate and have opposite conductivity types, silicon An insulating layer is formed on one surface of the substrate and insulates the first conductive semiconductor layer from the second conductive semiconductor layer.
  • the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are adjacent to each other with the insulating layer interposed therebetween in the in-plane direction of the silicon substrate. Neither the first conductive semiconductor layer nor the second conductive semiconductor layer is formed between the silicon substrate and the insulating layer (first configuration).
  • the first conductive type semiconductor layer and the second conductive type semiconductor layer are adjacent to each other with the insulating layer interposed therebetween in the in-plane direction of the silicon substrate. Neither the first conductive semiconductor layer nor the second conductive semiconductor layer is formed between the silicon substrate and the insulating layer. Therefore, the first conductive type semiconductor layer and the second conductive type semiconductor layer are reliably separated by the insulating layer.
  • the thickness of the insulating layer is larger than the height difference of the unevenness on one surface of the silicon substrate (second configuration).
  • a photoelectric conversion device includes a silicon substrate, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer which are formed on one surface of the silicon substrate and have opposite conductivity types, An insulating layer is provided on one surface of the silicon substrate and insulates the first conductive semiconductor layer from the second conductive semiconductor layer.
  • the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are adjacent to each other with the insulating layer interposed therebetween in the in-plane direction of the silicon substrate.
  • the thickness of the insulating layer is larger than the level difference of the irregularities on one surface of the silicon substrate (third configuration).
  • the first conductive type semiconductor layer and the second conductive type semiconductor layer are adjacent to each other with the insulating layer interposed therebetween in the in-plane direction of the silicon substrate.
  • the thickness of the insulating layer is larger than the height difference of the irregularities on one surface of the silicon substrate.
  • the insulating layer protrudes from one surface of the silicon substrate. Therefore, the first conductive semiconductor layer and the second conductive semiconductor layer can be prevented from contacting each other. Thereby, the first conductive semiconductor layer and the second conductive semiconductor layer are reliably separated by the insulating layer.
  • the width of the insulating layer is preferably 20 to 500 ⁇ m (fourth configuration).
  • the insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, polycrystalline silicon, aluminum oxide, aluminum nitride, aluminum It may be one kind selected from the group consisting of oxynitrides, imide resins, epoxy resins, fluororesins, polycarbonates, and liquid crystal polymers (fifth configuration).
  • Any of the first to fifth configurations may further include a passivation layer formed at least between the silicon substrate and the insulating layer (sixth configuration).
  • the passivation property in the lower part of the insulating layer can be further enhanced.
  • the first i-type semiconductor layer formed between the silicon substrate and the first conductivity type semiconductor layer and the silicon substrate and the second conductivity type semiconductor layer are formed.
  • the second i-type semiconductor layer may be further provided (seventh configuration).
  • defects at the interface between the silicon substrate and the first conductivity type semiconductor layer and the interface between the silicon substrate and the second conductivity type semiconductor layer can be reduced.
  • a method for manufacturing a photoelectric conversion device includes a step of preparing a silicon substrate, a step of forming an insulating layer on one surface of the silicon substrate, and a part of a region sandwiched between the insulating layers.
  • the insulating layer is formed before forming the first conductive type semiconductor layer and the second conductive type semiconductor layer. For this reason, neither the first conductive semiconductor layer nor the second conductive semiconductor layer is formed between the silicon substrate and the insulating layer. Therefore, the first conductive type semiconductor layer and the second conductive type semiconductor layer are reliably separated by the insulating layer.
  • a method for manufacturing a photoelectric conversion device comprising: preparing a silicon substrate; and forming an insulating layer on one surface of the silicon substrate thicker than a difference in height of one surface of the silicon substrate. Forming a first conductive semiconductor layer on one surface of the silicon substrate; and forming a second conductive semiconductor layer of a conductivity type opposite to the first conductive semiconductor layer on one surface of the silicon substrate. Forming. At least one of the process of forming a 1st conductivity type semiconductor layer and the process of forming a 2nd conductivity type semiconductor layer is performed after the process of forming an insulating layer (2nd aspect).
  • the layer thickness of the insulating layer is larger than the height difference of the irregularities on one surface of the silicon substrate. Therefore, the insulating layer protrudes from one surface of the silicon substrate. At least one of the step of forming the first conductive type semiconductor layer and the step of forming the second conductive type semiconductor layer is performed after the step of forming the insulating layer. Therefore, at least one of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer is blocked by the insulating layer. Thereby, the first conductive semiconductor layer and the second conductive semiconductor layer can be reliably separated.
  • the passivation layer is formed on one surface of the silicon substrate before the earlier step of forming the first conductivity type semiconductor layer and the step of forming the second conductivity type semiconductor layer. You may further provide the process to form (3rd aspect).
  • the step of forming the first i-type semiconductor layer on one surface of the silicon substrate before the step of forming the first conductivity type semiconductor layer, and the second conductivity type semiconductor Before the step of forming the layer, a step of forming the second i-type semiconductor layer on one surface of the silicon substrate may be further provided (fourth aspect).
  • the step of forming a conductive layer covering the first conductive type semiconductor layer, the second conductive type semiconductor layer, and the insulating layer, and a portion overlapping the insulating layer in plan view And a step of forming a groove in the conductive layer (fifth aspect).
  • an electrode electrically connected to the first semiconductor layer and an electrode electrically connected to the second semiconductor layer can be manufactured. Further, by forming a groove in a portion of the conductive layer that overlaps with the insulating layer in plan view, damage to the silicon substrate can be suppressed.
  • the method may further include a step of plating the conductive layer (sixth aspect).
  • the electrode can be formed at low cost.

Abstract

Cette invention concerne une configuration d'un dispositif de conversion photoélectrique, qui est capable de séparer efficacement l'une de l'autre une couche de semi-conducteur d'un premier type de conductivité et une couche de semi-conducteur d'un second type de conductivité, lesdites couches de semi-conducteur étant formées sur une surface d'un substrat de silicium. Un dispositif de conversion photoélectrique (1) selon l'invention comprend : un substrat de silicium (10) ; une couche de semi-conducteur d'un premier type de conductivité (14) et une couche de semi-conducteur d'un second type de conductivité (15), qui sont formées sur une surface du substrat de silicium (10) et présentent des types de conductivité opposés ; et une couche isolante (13) qui est formée sur ladite surface du substrat de silicium (10) qui et isole l'une de l'autre la couche de semi-conducteur d'un premier type de conductivité (14) et la couche de semi-conducteur d'un second type de conductivité (15). La couche de semi-conducteur d'un premier type de conductivité (14) et la couche de semi-conducteur d'un second type de conductivité (15) sont disposées de manière adjacente dans la direction du plan du substrat de silicium (10), la couche isolante (13) étant interposée entre celles-ci. Ni la couche de semi-conducteur d'un premier type de conductivité (14) ni la couche de semi-conducteur d'un second type de conductivité (15) n'est formée entre le substrat de silicium (10) et la couche isolante (13).
PCT/JP2015/067694 2014-06-27 2015-06-19 Dispositif de conversion photoélectrique et son procédé de fabrication WO2015198978A1 (fr)

Applications Claiming Priority (4)

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JP2014132665A JP5913446B2 (ja) 2014-06-27 2014-06-27 光電変換装置およびその製造方法
JP2014-132665 2014-06-27
JP2014132666A JP5871996B2 (ja) 2014-06-27 2014-06-27 光電変換装置およびその製造方法
JP2014-132666 2014-06-27

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WO2017056378A1 (fr) * 2015-09-30 2017-04-06 パナソニックＩｐマネジメント株式会社 Procédé de fabrication de cellule solaire

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JP2005101240A (ja) * 2003-09-24 2005-04-14 Sanyo Electric Co Ltd 光起電力素子およびその製造方法
JP2008021993A (ja) * 2006-06-30 2008-01-31 General Electric Co <Ge> 全背面接点構成を含む光起電力デバイス及び関連する方法
JP2008529265A (ja) * 2005-01-20 2008-07-31 コミツサリア タ レネルジー アトミーク へテロ接合およびインターフィンガ構造を有する半導体デバイス
JP2012164961A (ja) * 2011-02-08 2012-08-30 Samsung Sdi Co Ltd 太陽電池およびその製造方法

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Publication number Priority date Publication date Assignee Title
JP2005101240A (ja) * 2003-09-24 2005-04-14 Sanyo Electric Co Ltd 光起電力素子およびその製造方法
JP2008529265A (ja) * 2005-01-20 2008-07-31 コミツサリア タ レネルジー アトミーク へテロ接合およびインターフィンガ構造を有する半導体デバイス
JP2008021993A (ja) * 2006-06-30 2008-01-31 General Electric Co <Ge> 全背面接点構成を含む光起電力デバイス及び関連する方法
JP2012164961A (ja) * 2011-02-08 2012-08-30 Samsung Sdi Co Ltd 太陽電池およびその製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017056378A1 (fr) * 2015-09-30 2017-04-06 パナソニックＩｐマネジメント株式会社 Procédé de fabrication de cellule solaire

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