WO2015177164A1 - Verfahren zur herstellung eines optoelektronischen halbleiterchips sowie optoelektronischer halbleiterchip - Google Patents
Verfahren zur herstellung eines optoelektronischen halbleiterchips sowie optoelektronischer halbleiterchip Download PDFInfo
- Publication number
- WO2015177164A1 WO2015177164A1 PCT/EP2015/061015 EP2015061015W WO2015177164A1 WO 2015177164 A1 WO2015177164 A1 WO 2015177164A1 EP 2015061015 W EP2015061015 W EP 2015061015W WO 2015177164 A1 WO2015177164 A1 WO 2015177164A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- mesa
- semiconductor chip
- sequence
- aluminum
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 166
- 230000005693 optoelectronics Effects 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title description 20
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 84
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000000463 material Substances 0.000 claims abstract description 34
- 230000005855 radiation Effects 0.000 claims abstract description 15
- 230000005670 electromagnetic radiation Effects 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 396
- 239000011241 protective layer Substances 0.000 claims description 85
- 238000000034 method Methods 0.000 claims description 79
- 238000002161 passivation Methods 0.000 claims description 46
- 238000000151 deposition Methods 0.000 claims description 25
- 230000008569 process Effects 0.000 claims description 25
- 230000008021 deposition Effects 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 238000003631 wet chemical etching Methods 0.000 claims description 12
- -1 nitride compound Chemical class 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 230000003746 surface roughness Effects 0.000 claims description 6
- 238000007740 vapor deposition Methods 0.000 claims description 6
- 238000007704 wet chemistry method Methods 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 abstract 3
- 230000035515 penetration Effects 0.000 abstract 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 14
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 12
- 238000002310 reflectometry Methods 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 7
- 229910052709 silver Inorganic materials 0.000 description 7
- 239000004332 silver Substances 0.000 description 7
- 239000011787 zinc oxide Substances 0.000 description 7
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 6
- 238000003486 chemical etching Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 230000000087 stabilizing effect Effects 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000032683 aging Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 229910052703 rhodium Inorganic materials 0.000 description 3
- 239000010948 rhodium Substances 0.000 description 3
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 101100434911 Mus musculus Angpt1 gene Proteins 0.000 description 1
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000012080 ambient air Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 229910052700 potassium Inorganic materials 0.000 description 1
- 239000011591 potassium Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0232—Optical elements or arrangements associated with the device
- H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02366—Special surface textures of the substrate or of a layer on the substrate, e.g. textured ITO/glass substrate or superstrate, textured polymer layer on glass substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/0304—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L31/03044—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds comprising a nitride compounds, e.g. GaN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1892—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/405—Reflective materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
- H01S5/0217—Removal of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/028—Coatings ; Treatment of the laser facets, e.g. etching, passivation layers or reflecting layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
- H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
- H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/32308—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm
- H01S5/32341—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm blue laser based on GaN or GaP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
Definitions
- Optoelectronic semiconductor chip can be, for example, a light-emitting diode chip or a laser diode chip, which are each provided for the emission of electromagnetic radiation. Furthermore, it may be in the
- Optoelectronic semiconductor chip to a photodiode chip which is provided for the detection of electromagnetic radiation act.
- a growth substrate is first provided.
- the growth substrate may be a temporary carrier that is removed during the process or after completion of the process.
- the growth substrate may be a semiconductor body, on which subsequent layers of the semiconductor chip can be epitaxially deposited, for example.
- a semiconductor layer sequence having a p-type layer, an active zone and an n-type layer is grown on the growth substrate.
- the growth of the n-type layer occurs before the growth of the active region and the p-type layer.
- the n-type layer is thus arranged in a stacking direction between the growth substrate and the p-type layer.
- a top surface of the p-type layer then forms a top surface of the
- the semiconductor layer sequence has a
- Main extension plane in which it extends in lateral directions. Perpendicular to the main extension plane, for example in the stacking direction, ie in a vertical direction
- the semiconductor layer sequence has a thickness.
- the thickness of the semiconductor layer sequence is small compared to the maximum extent of the semiconductor layer sequence in a lateral direction.
- the active zone is particularly for emission or for
- the semiconductor layer sequence may comprise a nitride compound semiconductor material or be formed of a nitride compound semiconductor material.
- the semiconductor layer sequence becomes at its the growth substrate away side by area removed. As a result, an opening is formed which extends through the p-conducting layer and the active zone into the n-conducting layer of the semiconductor layer sequence.
- the breakthrough completely penetrates the p-type layer and the active region.
- the n-type layer is not completely broken by the breakdown. That is, the breakdown ends in the n-type layer and
- At least one top surface of the p-type layer is no longer simply contiguous after the area-wise removal, while at least one top surface of the n-type layer is simply coherent after the area-wise removal.
- the breakthrough allows electrical contacting of the n-type layer.
- Photographic technique done. For this purpose, a photoresist is first applied as a mask and then the to be removed
- a protective layer is deposited on a side of the semiconductor layer sequence facing away from the growth substrate. At least one top surface of the protective layer is contiguous
- the protective layer surrounds the opening in the manner of a frame, the opening remaining free of the protective layer.
- the protective layer can be constructed in the stacking direction from one or more layers.
- the protective layer may be a metal such as
- titanium, chromium, silver, rhodium, tungsten, nickel or a transparent conductive oxide such as ITO include.
- the active zone which generates red and / or infrared light the
- Protective layer further gold include.
- the layer sequence of the protective layer can be constructed as follows: Ti-Ag-TiWN or ITO-Ag-TiWN.
- the specified order of the materials is observed in the stacking direction.
- the protective layer may be formed electrically conductive.
- the multi-layered design can ensure the simultaneous fulfillment of different requirements.
- a high reflectivity can be ensured by the choice of, for example, silver, rhodium and / or gold as the middle layer of the layer sequence of the protective layer.
- an outer layer that allows titanium, chromium, tungsten, nickel, ITO and / or combinations of these
- a "high reflectivity" of a layer and / or layer sequence can be given here and below if the reflectivity of the layer and / or the
- Layer sequence for an electromagnetic radiation emitted by the active zone is at least 80%, preferably at least 90%.
- the geometric shape of the Protective layer is produced for example by means of a lift-off process.
- an aluminum layer is deposited over the whole area on the side of the semiconductor layer sequence facing away from the growth substrate.
- the deposition can be done, for example, by vapor deposition of the aluminum layer.
- the aluminum layer in particular contains aluminum or may be used in the context of
- Manufacturing tolerances consist of aluminum. "In the context of manufacturing tolerances” can here and below
- Aluminum layer may be present.
- the aluminum layer may in particular be designed to be electrically conductive. It is possible that the aluminum layer of the electric
- the aluminum layer may at least in places be in direct contact with the aluminum layer.
- the aluminum layer may further be formed in the stacking direction of a plurality of layers, wherein at least one of the layers may comprise a compound of aluminum and titanium.
- the aluminum layer covers a the
- the aluminum layer completely covers a side of the protective layer facing away from the growth substrate.
- the deposition of the aluminum layer can in particular
- the aluminum layer directly adjoins the
- the aluminum layer is therefore in direct contact with the protective layer and may be electrically conductively connected to the protective layer.
- the growth substrate is removed.
- Semiconductor chip is thus free of a growth substrate after its completion.
- the growth substrate can
- a mesa is formed. This is a mesa
- the p-type layer, the n-type layer and the active region at the regions of the protective layer are completely removed.
- Protective layer done. In other words, it is possible that the semiconductor layer sequence is removed only in areas that are covered by the protective layer.
- the protective layer is at least partially freely accessible from the outside.
- the mesa also includes a p conductive layer, an active zone and an n-type
- the mesa may take the form of a
- this comprises the following steps:
- Aluminum layer as n-contact layer provides.
- Such a layer has the particular advantage that the threshold voltage of the semiconductor chip is reduced due to reduced ohmic losses and the n-contact region has a high reflectivity.
- values of a threshold voltage of less than 3 V, with a starting current of approximately 350 mA can be achieved.
- Aluminum has a higher aging stability and does not tarnish strongly in comparison to silver during oxidation.
- Dielectric relatively strong compared to a also offering as n-contacting material silver.
- the semiconductor layer sequence on a nitride compound semiconductor material In accordance with at least one embodiment of the method for producing an optoelectronic semiconductor chip the semiconductor layer sequence on a nitride compound semiconductor material.
- nitride compound semiconductor based means that the epitaxial epitaxial layer sequence, or at least one layer thereof, comprises a nitride III / V compound semiconductor material, preferably Al n Ga m In ] ⁇ n m where 0 ⁇ n ⁇ 1, 0 ⁇ m ⁇ 1 and n + m ⁇ 1. This material does not necessarily have to be mathematically exact
- composition according to the above formula may contain one or more dopants as well as additional
- the formation of the mesa in step F) takes place with a wet-chemical etching method.
- a wet-chemical etching method Preferably, hot phosphoric acid is used for this purpose.
- hot potassium liquor it is also possible to use hot potassium liquor for the wet-chemical etching process.
- dry chemical etching process is cheaper to use, has a higher accuracy of the etched structures result and the resulting component may have, for example, a better small-current behavior.
- wet chemistry which is used to etch a
- Nitride compound semiconductor material particularly of GaN, such as hot phosphoric acid, however, there is a problem that aluminum passes through them
- the protective layer that seals against the hot phosphoric acid provided.
- the protective layer can be constructed in the stacking direction of several layers.
- the protective layer is formed from a material which is etched by the wet chemistry used at an etching rate which is at least a factor of 100, preferably a factor of 1000, particularly preferably a factor of 10000, lower than the etching rate for the nitride compound semiconductor material.
- the protective layer is thus hardly or not etched by the hot phosphoric acid and / or the hot potassium hydroxide. In particular, the etching can thus be stopped before it can lead to material changes or material removal on the protective layer.
- the deposition of the protective layer in step D) takes place by means of a deposition method which conforms conformally. Especially become during the deposition of the protective layer corners and / or
- Edges of previously grown layers conformally covered by the protective layer conformally covered by the protective layer.
- a conformal deposition for example, sputtering or vapor deposition with a planetary gear is suitable.
- vapor deposition in which no conforming
- edges or corners results, thus a complete or conformal deformation of the corners and / or edges can be achieved.
- steep edges grain boundaries at the edges and / or corners and / or incomplete over-shaping of the previously grown layers can thus be avoided.
- the mirror layer deposited on a the growth substrate facing away from the top surface of the semiconductor layer sequence.
- the deposition can be done for example by vapor deposition.
- the mirror layer may in particular be an electrically conductive layer, which is provided for contacting the p-type layer.
- the mirror layer can be in direct contact with the p-type
- the mirror layer stand.
- the mirror layer is in a top view
- a "top view” is here and below by a supervision of a
- the mirror layer is in particular designed to be reflective for electromagnetic radiation generated by the active zone.
- the mirror layer may comprise silver, gold, rhodium, aluminum and / or platinum.
- the top surface of the semiconductor layer sequence remains free at least in places in the areas in which the formation of the openings in step B), at least in places free of the mirror layer. For this purpose, for example, find a photo technique application.
- a contacting layer is deposited on a side of the mirror layer facing away from the semiconductor layer sequence.
- the contacting layer is electrically conductively connected to the mirror layer.
- the contacting layer covers the mirror layer at least in places. However, it is also possible that the contacting layer the
- the contacting layer may be formed, for example, with gold and / or platinum.
- the contacting layer is partially adjacent directly to the top surface of the semiconductor layer sequence.
- facing contact surface of the contacting layer is in a plane with the top surface of the semiconductor layer sequence.
- a first passivation layer is formed over the whole area of the substrate
- the first passivation layer is in particular formed electrically insulating.
- Passivation layer may consist of several layers in the stacking direction, but it is also possible that the first passivation layer is composed of only a single layer.
- the first passivation layer comprises a dielectric, electrically insulating material, such as
- silicon oxide for example, silicon oxide
- the first passivation layer is in the region of the breakdown
- the first passivation layer is removed in the region in which the at least one breakdown adjoins the n-conducting layer. This allows in particular an electrical contacting of the n-type layer from the outside.
- Passivation layer remains in particular in the areas of the breakthrough, in which the breakthrough adjacent to the p-type layer and the active zone. This is to avoid a short circuit.
- the first passivation layer extends into the aperture.
- regions of the aluminum layer at least fill the at least one breakthrough after the application of the aluminum layer
- the breakthrough except for the areas where the first passivation layer is present, completely filled by the aluminum layer.
- the aluminum layer is electrically conductively connected to the n-type layer.
- connection carrier may include a Lotsystem and a Lotsperre.
- the Lotsperre can be, for example, surface applied TiWN layers.
- connection carrier is in particular for electrical
- connection carrier can be contacted from the outside.
- the connection carrier can, for example, be placed on another carrier and connected to it by means of soldering, gluing and / or sintering.
- Connection carrier can do this on his the
- the other carrier such as a printed circuit board
- the component resulting from the connection of the optoelectronic semiconductor chip and the further carrier can be, for example, SMD-mountable.
- connection carrier can in particular mechanically
- Connection carrier a mechanically stabilizing
- Decoupling structure formed on a side facing away from the connection carrier outer surface of the mesa.
- the coupling-out structure can be any suitable coupling-out structure.
- the coupling-out structure can be any suitable coupling-out structure.
- the coupling-out structure serves for improved decoupling of the generated electromagnetic radiation.
- the coupling-out structure the transmission of the electromagnetic radiation which is on the the
- connection carrier facing away from the outer surface of the mesa, increased by said outer surface.
- a second passivation layer is deposited over the whole area on all the exposed outer surfaces of the mesa facing away from the connection carrier.
- the second passivation layer covers all the exposed outer surfaces of the protective layer and / or the contacting layer facing away from the connection carrier.
- Optoelectronic semiconductor chip is thus at this stage of the manufacturing process thus electrically insulated on its sides facing away from the connection carrier surfaces to the outside.
- the second passivation layer is in particular of a
- the second Passivation layer is formed electrically insulating.
- Silica be formed.
- the second passivation layer is removed in places, wherein the contacting layer is subsequently freely accessible from outside at locations. At these points, a contact pad is then vapor-deposited. This contact pad is used for
- the optoelectronic semiconductor chip is
- the optoelectronic semiconductor chip has a mesa.
- the mesa comprises a semiconductor layer sequence with a p-type layer, an active zone and an n-type layer.
- the active zone is for generating or detecting
- the optoelectronic semiconductor chip comprises a via which extends through the p-conducting layer and the active zone into the n-conducting layer.
- the Through-connection comprises an electrically conductive material, which is electrically conductively connected to the n-conductive layer.
- the via breaks through the p-type
- the optoelectronic semiconductor chip comprises a connection carrier with a connection substrate which is attached to one of the
- the optoelectronic semiconductor chip can, for example, by means of the connection carrier on a
- Printed circuit board are applied and contacted electrically.
- the latter comprises a full-surface aluminum layer containing aluminum.
- the aluminum layer is arranged in particular between the mesa and the connection carrier.
- the aluminum layer is electrically conductively connected to the n-type layer.
- the aluminum layer reflects the electromagnetic energy emitted or absorbed by the active zone
- Aluminum layer for the radiation emitted by the active zone at least 80%, preferably at least 90%.
- the aluminum layer can directly adjoin the n-type layer.
- a further layer applied over the entire surface which are formed with a transparent conductive oxide, such as, for example, with ITO can, is upset.
- This further layer may, for example, have a thickness of at most 100 nm, preferably at most 50 nm. Such a further layer serves for improved electrical contacting of the n-conducting layer of the semiconductor layer sequence.
- the mesa is lateral of a trench
- the mesa is characterized by the fact that it is bounded by a frame-like trench.
- the at least one via is at least partially formed by the material of the aluminum layer.
- the aluminum layer extends through the p-conducting layer and the active zone into the n-conducting layer.
- the material of the aluminum layer may in particular be the only electrically conductive material of the plated through hole.
- the material of the aluminum layer may in particular be the only electrically conductive material of the plated through hole.
- Aluminum layer may be the only layer of the optoelectronic semiconductor chip, which is provided for electrically contacting the n-type layer.
- the aluminum layer is formed in a top view, that is, in a plan view from a direction which is perpendicular to the main plane of extension, simply connected.
- the base of the mesa is completely covered by the aluminum layer in a top view, with the aluminum layer forming the mesa laterally
- the aluminum layer is thus over the entire surface formed and has along the main extension plane to a greater extent than the mesa.
- the latter comprises a contacting layer, which is connected in an electrically conductive manner to the p-conducting layer.
- the contacting layer is at least in places in the region of the trench lateral to the mesa
- the contact surface of the contacting layer has no depressions and / or roughness which exceeds the usual uniformity or unevenness of the surface roughness of a vapor-deposited layer.
- the roughness of the contact surface can thus be used to detect the wet-chemical etching process used.
- this comprises a second one Passivation layer, which is connected to the connection carrier
- the second passivation layer envelops the mesa in a form-fitting manner.
- Passivation layer of the trench which encloses the mesa - with the exception of areas where a contact pad
- the second passivation layer is thus formed almost completely over the entire surface.
- a cover surface of the second passivation layer facing away from the connection carrier has the same vertical distance, that is to say an equal distance in the vertical direction, to the connection substrate of the connection carrier.
- the second passivation layer is planar
- wet chemical etching can be detected. This is explained as follows. As already described, in the case of using a dry chemical etching process, the contacting layer would also be easily etched. In this case, the contact surface of the contacting layer with the top surface of the semiconductor layer sequence would no longer lie in one plane. Thus, on one side of the mesa, where the contacting layer is present, a deeper trench would form than on the other side of the mesa. This would then lead to a non-planar implementation of the second passivation layer. Thus, the top surface of the second passivation layer would not be planar in the region of the trench when using a dry chemical etching process.
- the optoelectronic semiconductor chip all side surfaces of the mesa are free of the material of the contacting layer. In particular, in the method for producing such an optoelectronic semiconductor chip described above, it is not necessary to remove the material of the contacting layer from the side surfaces of the mesa. In the case of using a
- Semiconductor chip can be detected.
- the latter comprises a protective layer whose at least one cover surface is designed to be continuous.
- the protective layer surrounds the mesa like a frame and is arranged at least in places between the contacting layer and the aluminum layer.
- the protective layer is in the regions of the trench of the mesa
- the latter further comprises a mirror layer whose one cover surface is designed to be continuous.
- the mirror layer is electrically conductively connected to the p-type layer and the contacting layer.
- the mirror layer almost completely covers the p-type layer of the mesa.
- the mirror layer surrounds the via-like frame-like.
- the mirror layer and / or the protective layer are identical to each other.
- Radiation is reflected by the mirror layer and / or the protective layer.
- the reflectivity of the protective layer and / or the mirror layer is for the electromagnetic radiation emitted by the active zone
- a cover surface of the protective layer facing away from the mesa does not form a planar surface and / or the surface
- Protective layer does not have a uniform thickness.
- the "thickness" of a layer here and hereinafter is the extent of the layer along the stacking direction. This uneven thickness of the protective layer points to the one used
- the protective layer is deposited with a conformal covering deposition process.
- the protective layer is sputtered
- the Use double-lacquer system provided for the deposition by sputtering. This creates a non-uniformly thick protective layer. In particular, due to the uneven thickness of the protective layer, the
- the cover surface of the protective layer has, in at least one cross section perpendicular to the connection carrier, a shape which can be approximated by a curve which has a local maximum at the edges of the protective layer, at least one between the two local maxima local minimum is present.
- the curve it is possible for the curve to run along a lateral direction.
- the shape of this cross section can therefore correspond to a curve which has horns or points on the sides. These horns or tips are formed in the areas where the masking layers were deposited by deposition by the conformally depositing deposition method.
- the manufacturing process of the protective layer can be detected at this form of the protective layer.
- the top surface of the protective layer along a lateral direction at the edges of the protective layer may be spaced a greater distance from the connection carrier than away from the edges.
- the protective layer can therefore be a
- FIG. 1 shows an exemplary embodiment of one here
- Figures 2 to 4 show embodiments of a
- a growth substrate 1 having a cover surface 1a is provided on the growth substrate 1 .
- a growth substrate 1 having a cover surface 1a is provided on the growth substrate 1 .
- a mirror layer 31 is further applied, which is electrically conductively connected to the p-type layer 23 of the semiconductor layer sequence 2.
- a top surface 31a of the mirror layer 31 is formed in particular continuous.
- a cover surface 2a of the semiconductor layer sequence 2 remains partially free of the mirror layer 31. In these areas, in later Process steps a breakthrough 70 (not shown here) formed.
- the contacting layer 4 is in particular electrically conductively connected to the mirror layer 31.
- the contacting layer 4 covers the mirror layer 31 at least partially.
- the semiconductor layer sequence 2 is removed in regions, whereby an opening 70, which extends through the p-conducting layer 21 and the active zone 22 into the n-conducting layer 23 of the semiconductor layer sequence 2,
- the breakdown thus completely penetrates the p-type layer 21 and the active region 22, the n-type layer 23 being only partially penetrated by the aperture 70.
- a bottom surface 23a of the n-type layer 23 after the formation of the aperture 70 is further formed simply continuous.
- the first passivation layer 51 completely covers the mirror layer 31 and the contacting layer 4.
- Semiconductor layer sequence 2 becomes a protective layer 32 after the application of the first passivation layer 51
- Protective layer 32 is formed simply connected.
- the protective layer 32 encloses the opening 70 like a frame.
- the protective layer 32 directly adjoins the first one
- the aluminum layer 33 becomes
- the aluminum layer 33 thus completely covers all previously grown layers. In particular, the aluminum layer 33 extends into the aperture 70. In the region of the aperture, the aluminum layer 33 then forms together with the first
- connection carrier 6 is attached to the side of the aluminum layer 33 facing away from the growth substrate 1.
- the connection carrier 6 comprises a solder barrier 61, a solder system 62 and a connection substrate 63
- Substrate 63 is formed in particular mechanically stabilizing.
- the growth substrate 1 was removed in this process step.
- a mesa 72 is formed. This is done by removing the
- Semiconductor layer sequence 2 at the areas of the protective layer 32.
- the removal is preferably carried out by wet chemical etching. At the areas where the
- the mesa has a base surface 72 a, which on the side facing the connection carrier 6 side
- Semiconductor layer sequence 2 is located.
- outgoing coupling structures 24 are attached to the outer surface of the mesa 72 facing away from the connection carrier 6.
- the n-conductive layer 23 is at least partially removed, resulting in recesses 24.
- Connection carrier 6 facing away from outer surface 24a of the mesa then forms a radiation exit surface of the optoelectronic semiconductor chip. According to the schematic sectional illustration of FIG. 1C, a further method step is one described here
- the process step shows already a finished optoelectronic semiconductor chip.
- a second passivation layer 52 is applied to exposed outer surfaces of the mesa 72 and the trench facing away from the connection carrier 6. This second passivation layer 52 is subsequently removed in regions. At the areas where the second passivation layer 52 has been removed, a contact pad 41 is applied. A cover surface 6 facing away from the top surface in the region of the trench 52a of the second passivation layer 52 is formed in particular planar. In other words, the top surface in the region of the trench 52a of the second passivation layer 52 has an equal distance in the vertical direction to the terminal substrate 63 of the connection carrier 6. The wet-chemical etching process used to fabricate the mesa 72 is detectable in this planar design.
- the contacting layer 4 is designed in such a way that it almost nearly reaches the mirror layer 31 on the cover surface of the mirror layer 31 facing away from the semiconductor layer sequence 2
- FIG. 3 A further exemplary embodiment of an optoelectronic semiconductor chip described here is explained in greater detail in accordance with the schematic sectional representation of FIG. In the embodiment shown here is instead of a Aluminum layer 33, a second mirror layer 34 is attached. As a result, for the production of the optoelectronic semiconductor chip according to the exemplary embodiment of FIG. 3, a further photographic technique is compared to the previous ones
- the second mirror layer 34 used in the embodiment may be formed with AgPt, for example.
- the via 71 in the illustrated embodiment includes an additional contact material 35, which may be formed with ZnO, for example.
- ZnO has the disadvantage that it has a
- the second mirror layer 34 may start because silver is susceptible to the ingress of moisture, and thus the reflectivity of the second mirror layer 34
- Top view is taken from above, that is, from a direction perpendicular to the main plane of extension of the
- FIG. 4A The plan view of Figure 4A corresponds to the sectional view of Figure 3, while the top view of Figure 4B corresponds to the sectional views of Figures IE and / or 2.
- Main extension plane laterally spaced from each other.
- the plated-through holes 71 of the embodiment of FIG. 4A are formed, for example, with ZnO. This material reflects those emitted by the active zone
- the plated-through holes 71 in the supervision are no longer recognizable. Accordingly, the electromagnetic radiation emitted by the active zone appears spatially more homogeneous and results in an aesthetic
- the embodiment of Figure 4B also has a higher efficiency, since due to the higher reflectivity of the aluminum layer 33 compared to ZnO more light from the active zone 22 can be coupled.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Led Devices (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/309,260 US9806225B2 (en) | 2014-05-20 | 2015-05-19 | Method of producing an optoelectronic semiconductor chip and an optoelectronic semiconductor chip |
DE112015002379.8T DE112015002379B4 (de) | 2014-05-20 | 2015-05-19 | Verfahren zur Herstellung eines optoelektronischen Halbleiterchips sowie optoelektronischer Halbleiterchip |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102014107123.9 | 2014-05-20 | ||
DE102014107123.9A DE102014107123A1 (de) | 2014-05-20 | 2014-05-20 | Verfahren zur Herstellung eines optoelektronischen Halbleiterchips sowie optoelektronischer Halbleiterchip |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015177164A1 true WO2015177164A1 (de) | 2015-11-26 |
Family
ID=53181299
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2015/061015 WO2015177164A1 (de) | 2014-05-20 | 2015-05-19 | Verfahren zur herstellung eines optoelektronischen halbleiterchips sowie optoelektronischer halbleiterchip |
Country Status (3)
Country | Link |
---|---|
US (1) | US9806225B2 (de) |
DE (2) | DE102014107123A1 (de) |
WO (1) | WO2015177164A1 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102014116935A1 (de) * | 2014-11-19 | 2016-05-19 | Osram Opto Semiconductors Gmbh | Bauelement und Verfahren zur Herstellung eines Bauelements |
US10461218B2 (en) * | 2015-11-03 | 2019-10-29 | Lg Innotek Co., Ltd. | Semiconductor device |
DE102016114550B4 (de) | 2016-08-05 | 2021-10-21 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Bauelement und Verfahren zur Herstellung von Bauelementen |
DE102017113407A1 (de) * | 2017-06-19 | 2018-12-20 | Osram Opto Semiconductors Gmbh | Strahlungsemittierender Halbleiterchip, Verfahren zur Herstellung eines strahlungsemittierenden Halbleiterchips und ein Verfahren zur Herstellung einer strahlungsemittierenden Anordnung |
DE102020104372A1 (de) * | 2020-01-15 | 2021-07-15 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronischer Halbleiterchip |
DE102021124129A1 (de) | 2021-09-17 | 2023-03-23 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronisches halbleiterbauelement und optoelektronisches modul |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102010009717A1 (de) * | 2010-03-01 | 2011-09-01 | Osram Opto Semiconductors Gmbh | Leuchtdiodenchip |
EP2402995A2 (de) * | 2010-07-01 | 2012-01-04 | LG Innotek Co., Ltd. | Lichtemittierende Vorrichtung und Beleuchtungseinheit |
EP2408030A2 (de) * | 2010-07-12 | 2012-01-18 | LG Innotek Co., Ltd. | Elektrodenanordnung für eine lichtemittierende Vorrichtung |
US20120138969A1 (en) * | 2010-12-20 | 2012-06-07 | Lg Innotek Co., Ltd. | Light emitting device, light emitting device package, and lighting device with the same |
DE102011016302A1 (de) * | 2011-04-07 | 2012-10-11 | Osram Opto Semiconductors Gmbh | Optoelektronischer Halbleiterchip |
US20130062657A1 (en) * | 2011-09-14 | 2013-03-14 | Lextar Electronics Corporation | Light emitting diode structure and manufacturing method thereof |
DE102012108879A1 (de) * | 2012-09-20 | 2014-03-20 | Osram Opto Semiconductors Gmbh | Optoelektronischer Halbleiterchip mit mehreren nebeneinander angeordneten aktiven Bereichen |
EP2725629A2 (de) * | 2012-10-24 | 2014-04-30 | Nichia Corporation | Lichtemittierendes Element |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102007022947B4 (de) | 2007-04-26 | 2022-05-05 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronischer Halbleiterkörper und Verfahren zur Herstellung eines solchen |
DE102010025320B4 (de) * | 2010-06-28 | 2021-11-11 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronisches Bauelement und Verfahren zu dessen Herstellung |
DE102012108883A1 (de) | 2012-09-20 | 2014-03-20 | Osram Opto Semiconductors Gmbh | Optoelektronischer Halbleiterchip und Verfahren zur Herstellung von optoelektronischen Halbleiterchips |
DE102012217533A1 (de) * | 2012-09-27 | 2014-03-27 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines optoelektronischen Bauelements |
DE102012110775A1 (de) * | 2012-11-09 | 2014-05-15 | Osram Opto Semiconductors Gmbh | Optoelektronischer Halbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips |
-
2014
- 2014-05-20 DE DE102014107123.9A patent/DE102014107123A1/de not_active Withdrawn
-
2015
- 2015-05-19 US US15/309,260 patent/US9806225B2/en active Active
- 2015-05-19 WO PCT/EP2015/061015 patent/WO2015177164A1/de active Application Filing
- 2015-05-19 DE DE112015002379.8T patent/DE112015002379B4/de active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102010009717A1 (de) * | 2010-03-01 | 2011-09-01 | Osram Opto Semiconductors Gmbh | Leuchtdiodenchip |
EP2402995A2 (de) * | 2010-07-01 | 2012-01-04 | LG Innotek Co., Ltd. | Lichtemittierende Vorrichtung und Beleuchtungseinheit |
EP2408030A2 (de) * | 2010-07-12 | 2012-01-18 | LG Innotek Co., Ltd. | Elektrodenanordnung für eine lichtemittierende Vorrichtung |
US20120138969A1 (en) * | 2010-12-20 | 2012-06-07 | Lg Innotek Co., Ltd. | Light emitting device, light emitting device package, and lighting device with the same |
DE102011016302A1 (de) * | 2011-04-07 | 2012-10-11 | Osram Opto Semiconductors Gmbh | Optoelektronischer Halbleiterchip |
US20130062657A1 (en) * | 2011-09-14 | 2013-03-14 | Lextar Electronics Corporation | Light emitting diode structure and manufacturing method thereof |
DE102012108879A1 (de) * | 2012-09-20 | 2014-03-20 | Osram Opto Semiconductors Gmbh | Optoelektronischer Halbleiterchip mit mehreren nebeneinander angeordneten aktiven Bereichen |
EP2725629A2 (de) * | 2012-10-24 | 2014-04-30 | Nichia Corporation | Lichtemittierendes Element |
Also Published As
Publication number | Publication date |
---|---|
US9806225B2 (en) | 2017-10-31 |
DE112015002379A5 (de) | 2017-02-23 |
DE112015002379B4 (de) | 2021-08-05 |
US20170084777A1 (en) | 2017-03-23 |
DE102014107123A1 (de) | 2015-11-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2351079B1 (de) | Strahlungsemittierender halbleiterchip | |
DE112015005964B4 (de) | Bauelement und Verfahren zur Herstellung eines Bauelements | |
DE112015002379B4 (de) | Verfahren zur Herstellung eines optoelektronischen Halbleiterchips sowie optoelektronischer Halbleiterchip | |
DE102010034665B4 (de) | Optoelektronischer Halbleiterchip und Verfahren zur Herstellung von optoelektronischen Halbleiterchips | |
DE102012108879B4 (de) | Optoelektronischer Halbleiterchip mit mehreren nebeneinander angeordneten aktiven Bereichen | |
WO2015121062A1 (de) | Verfahren zur herstellung eines optoelektronischen halbleiterbauteils sowie optoelektronisches halbleiterbauteil | |
WO2014095556A1 (de) | Verfahren zum herstellen von optoelektronischen halbleiterchips und optoelektronischer halbleiterchip | |
WO2012110364A1 (de) | Optoelektronischer halbleiterchip und verfahren zur herstellung von optoelektronischen halbleiterchips | |
EP2057696B1 (de) | Optoelektronischer halbleiterchip und verfahren zur dessen herstellung | |
EP2340568A1 (de) | Optoelektronischer halbleiterkörper | |
WO2014154503A1 (de) | Optoelektronischer halbleiterchip mit einer ald-schicht verkapselt und entsprechendes verfahren zur herstellung | |
WO2012013523A1 (de) | Strahlungsemittierender halbleiterchip und verfahren zur herstellung eines strahlungsemittierenden halbleiterchips | |
DE102016100317A1 (de) | Optoelektronisches Bauelement und Verfahren zur Herstellung eines optoelektronischen Bauelements | |
EP3259783B1 (de) | Verfahren zur herstellung eines halbleiterkörpers | |
WO2016135024A1 (de) | Optoelektronisches halbleiterbauelement, verfahren zur herstellung eines elektrischen kontakts und verfahren zur herstellung eines halbleiterbauelements | |
WO2017158046A1 (de) | Lichtemittierender halbleiterchip und verfahren zur herstellung eines lichtemittierenden halbleiterchips | |
WO2017178627A1 (de) | Optoelektronischer halbleiterchip | |
DE102016124860A1 (de) | Optoelektronischer Halbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips | |
DE102015102378B4 (de) | Verfahren zur Herstellung eines Halbleiterkörpers | |
WO2014072410A1 (de) | Optoelektronischer halbleiterchip und verfahren zur herstellung eines optoelektronischen halbleiterchips | |
WO2020182621A1 (de) | Verfahren zur herstellung von optoelektronischen halbleiterbauteilen und optoelektronisches halbleiterbauteil | |
WO2021043901A1 (de) | Optoelektronisches bauelement und verfahren zur herstellung eines optoelektronischen bauelements | |
WO2019025206A1 (de) | Optoelektronischer halbleiterchip und verfahren zur herstellung eines optoelektronischen halbleiterchips | |
DE102019220215A1 (de) | Verfahren zur Herstellung von Halbleiterbauelementen und Halbleiterbauelement | |
WO2018215265A1 (de) | Optoelektronischer halbleiterchip und verfahren zur herstellung eines optoelektronischen halbleiterchips |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 15723029 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 15309260 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 112015002379 Country of ref document: DE |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: R225 Ref document number: 112015002379 Country of ref document: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 15723029 Country of ref document: EP Kind code of ref document: A1 |