WO2015174296A1 - 固体撮像素子および固体撮像素子の製造方法、並びに電子機器 - Google Patents
固体撮像素子および固体撮像素子の製造方法、並びに電子機器 Download PDFInfo
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Definitions
- the present technology relates to a solid-state imaging device, a manufacturing method of the solid-state imaging device, and an electronic device, and in particular, a solid-state imaging device and a manufacturing method of the solid-state imaging device that can suppress a decrease in charge transfer characteristics from a photodiode, and an electronic device Regarding equipment.
- CMOS Complementary Metal Oxide Semiconductor
- pixel sharing technology pixel sharing technology
- This pixel sharing technique is a technique for securing an opening area of a photodiode by sharing a transistor between a plurality of pixels and minimizing the area occupied by elements other than the photodiode in the pixel portion.
- This pixel sharing technique it is possible to improve characteristics such as saturation signal amount and sensitivity of the photodiode (see Patent Documents 1 to 4).
- the layer in which the transistor is formed is formed as an epitaxial layer on the layer in which the photodiode is formed.
- a charge transfer method from the photodiode to the floating diffusion a method using a vertical transistor or a II plug method using II (Ion Implant) is adopted.
- the photodiode and the floating diffusion are stacked in a direction perpendicular to the pixel plane.
- the path for transferring charges from the photodiode to the floating diffusion needs to form a transfer path in the direction perpendicular to the pixel plane, such as a vertical transistor or II ⁇ plug connected by II.
- the transfer path becomes longer as a whole, and the transfer characteristics of the charge that becomes the pixel signal may deteriorate.
- it is necessary to form a buried photodiode after securing a region for forming a II plug for securing a transfer path which may restrict the layout pattern in a layer for forming the photodiode.
- self-alignment II Ion Implant
- the vertically stacked photodiode and floating diffusion are aligned. In some cases, the robustness with respect to the resistance is lowered.
- the present technology has been made in view of such a situation, and in particular, by forming the floating diffusion at the same depth as the photodiode, the direction in which the transfer path is parallel to the pixel plane (horizontal direction). ) To suppress a decrease in transfer characteristics.
- a back-illuminated solid-state imaging device includes a pixel transistor formed in a first layer, and a photodiode formed in a second layer separated from the first layer in a depth direction. And a transfer transistor for controlling charge transfer of the photodiode, and the transfer transistor is formed to be embedded in the first layer.
- the gate of the transfer transistor can be formed in the second layer.
- a floating diffusion for detecting the charge transferred from the photodiode can be further included, and the floating diffusion can be formed at a position including the second layer.
- a part of the floating diffusion is configured to have the same depth as that of a part of the photodiode with respect to an incident direction of light, a part of the floating diffusion having the same depth, and the photo diffusion.
- a channel whose opening / closing is controlled by the transfer transistor may be formed between a part of the diodes.
- the floating diffusion may be integrated as a whole, and may be formed at a position including the second layer through the first layer.
- the floating diffusion may be formed separately for each of the first layer and the second layer.
- the floating diffusion may be formed in the second layer, and a contact for electrically connecting the floating diffusion may be formed by being engraved so as to penetrate the first layer.
- an oxide film can be formed at positions adjacent to the drain and source of the pixel transistor so as to sandwich the pixel transistor.
- a buried oxide film can be formed as a continuous structure at a position corresponding to the oxide film of the first layer.
- the surface-side pinning layer of the photodiode which is an interface between the first layer and the second layer and on the second layer, is formed by p-type epitaxial growth. Can do.
- the surface pinning layer can be formed by in-site doped Eu growth.
- An oxide film having a thickness greater than or equal to a gate oxide film can be formed between the floating diffusion and the gate of the transfer transistor.
- the floating diffusion may be formed in the second layer, and a metal wiring that electrically connects the floating diffusion may be formed by being engraved so as to penetrate the first layer.
- An oxide film having a thickness greater than that of the gate oxide film can be formed so as to surround the gate of the transfer transistor.
- Only the bottom part of the gate of the transfer transistor may be formed so as to straddle the floating diffusion and the photodiode, and the other part may be formed to have a smaller diameter than the bottom part. Can be.
- a backside illumination type solid-state imaging device includes a pixel transistor formed in a first layer and a second layer separated from the first layer in a depth direction.
- a back-illuminated solid-state imaging device wherein the transfer transistor is embedded in the first layer, and the transfer transistor controls the charge transfer of the photodiode.
- an engraving is formed in the first layer such that the gate of the transfer transistor is formed in the second layer, and the gate is formed in the second layer.
- the transfer transistor is formed in the engraving to be formed.
- An electronic apparatus including a back-illuminated solid-state imaging device includes a pixel transistor formed in a first layer and a second layer separated from the first layer in a depth direction.
- a pixel transistor is formed in a first layer, a photodiode is formed in a second layer that is separated from the first layer in a depth direction, and the photodiode is formed by a transfer transistor. Charge transfer is controlled, and the transfer transistor is formed to be embedded in the first layer.
- First Embodiment Example in which floating diffusion is formed by engraving up to a layer where a photodiode is formed
- Second Embodiment Example in which floating diffusion is formed separately in a layer in which a photodiode is formed and a layer in which a pixel transistor is formed
- Third Embodiment Example in which a floating diffusion is formed in a layer where a photodiode is formed and a contact is engraved in the epitaxial layer
- Fourth Embodiment Example in which an oxide film is formed so as to sandwich a pixel transistor
- FIG. 1 is a diagram illustrating a configuration example of a first embodiment of a solid-state imaging device to which the present technology is applied.
- the solid-state imaging device in FIG. 1 is a back-illuminated solid-state imaging device.
- the traveling direction (depth direction) of incident light with respect to the solid-state imaging element is from the lower direction to the upper direction in the figure, and thereafter, the upper surface in each layer in the figure is the surface, and the lower side. Is the back side. Therefore, the lower part in the figure is a deep position, while the upper part in the figure is a shallow position.
- FIG. 1 is a side sectional view of one pixel of the solid-state imaging device.
- an on-chip lens 21 is provided at the head position in the traveling direction of the incident light, and the incident light is condensed so as to be received by the photodiode 42.
- a color filter (Color Filter) 22 is provided, and light having a specific wavelength out of light incident through the on-chip lens 21 is transmitted to the photodiode 42. .
- a light shielding metal 23 is provided around the color filter 22 so that the light transmitted through the on-chip lens 21 and the color filter 22 does not enter the photodiode 42 of another adjacent pixel. Shaded.
- a backside pinning layer 24 is provided above the color filter 22 in the figure, and is formed as an element isolation layer between the silicon (Si) substrate 25 and the color filter 22.
- the silicon substrate 25 is provided with a photodiode (photo-diode: PD) 42 formed of an N-type region in the center of the figure, and a separation layer 41 is provided around the photodiode.
- the photodiode 42 is thus configured to be embedded, generates charges according to the amount of incident light by the photoelectric effect, and enters the floating diffusion 56 via the channel 44 whose opening / closing is controlled by the gate 55 of the transfer transistor. Output.
- a surface pinning layer 43 composed of a P-type region is provided above the silicon substrate 25 in the figure, and an element isolation layer between the silicon (Si) substrate 25 and the epitaxial layer (P-Epi) 26 is provided. It is formed as.
- An epitaxial layer (P-Epi) 26 is formed on a silicon substrate 25, on which a gate of a pixel transistor such as an amplification transistor (AMP), a reset transistor (RST), or a selection transistor (SEL).
- AMP amplification transistor
- RST reset transistor
- SEL selection transistor
- AMP or RST or SEL 51 is provided below the gate 51. Further, below the gate 51, opening and closing is controlled by the gate 51, and a channel 52 that connects the drain 53 and the source 54 is provided.
- SEL selection transistor
- a transfer transistor gate (TRG) 55 for controlling the opening and closing of the channel 44 is formed so as to penetrate the epitaxial layer 26 above the channel 44 in the silicon substrate 25. Further, a floating diffusion 56 is provided so as to penetrate the epitaxial layer 26 so as to be in contact with the side surface of the channel 44.
- the bottom of the floating diffusion 56 in the drawing is positioned at the same position as the top of the photodiode 42 in the drawing in the incident light traveling direction (depth direction).
- the structure is provided so as to penetrate through the epitaxial layer 26.
- the channel 44 is configured as a transfer path for transferring the charge accumulated by the photodiode 42 to the floating diffusion 56, and its opening / closing is controlled by the gate 55 of the transfer transistor.
- a transfer path is formed in the direction perpendicular to the traveling direction (depth direction) of incident light (the direction parallel to the pixel plane) via the channel 44 so that the transfer distance is not increased. It is configured.
- the transfer distance does not become long, it is possible to reduce the deterioration of transfer characteristics.
- it is not necessary to provide the II type plug required for securing the transfer path in the embedded photodiode 42 it is possible to eliminate the pattern restriction such as securing an area for the II type plug on the silicon substrate 25. It becomes possible.
- the separation layer 41, the photodiode 42, and the surface pinning layer 43 are formed on the n-type silicon substrate (n-Si) 25. That is, a silicon substrate (n-Si) 25 as shown in the upper part of FIG. 3 is applied to a separation layer (p) 41, a photodiode 42, and a surface pinning layer (p +) as shown in the lower part of FIG. 43 is formed. As shown in the lower part of FIG. 3, the photodiode 42 includes an n + layer (n +) 42a and an n layer (n) 42b.
- a p-type epitaxial layer (P-Epi) 26 is formed on the silicon substrate 25 in the drawing. That is, as shown in FIG. 4, the epitaxial layer is formed on the upper portion of the silicon substrate 25 in which the separation layer (p) 41, the photodiode 42, and the surface pinning layer (p +) 43 are formed by the process of step S11. (P-Epi) 26 is formed. As shown in FIG. 4, the photodiode 42 is formed in a buried manner in a state surrounded by the isolation layer 41 and the epitaxial layer 26.
- step S13 engravings for forming the gate 55 and the channel 44 of the embedded transfer transistor (TRG) are formed. That is, as shown in FIG. 5, the engraving 61 to the depth at which the gate (TRG) 55 and the channel 44 of the transfer transistor in the epitaxial layer 26 are formed to reach the silicon substrate 25 through the epitaxial layer 26. Is formed. At this time, the engraving 61 is at a position at least in contact with the n + layer 42a which is the upper portion of the photodiode 42 and has a depth thereof.
- an n-type channel (n) 52 of a pixel transistor such as an amplification transistor (AMP), a reset transistor (RST), or a selection transistor (SEL), and an n-type transistor provided below the gate 55 of the transfer transistor.
- a channel (n) 44 is formed.
- an oxide film 71 is formed on the epitaxial layer 26 in the drawing. That is, as shown in FIG. 6, an n-type channel (n) 52 is formed in the upper portion of the epitaxial layer 26, and a channel (n) 44 is formed in the bottom portion of the engraving 61. Further, an oxide film 71 is formed on the entire channel (n) 52 and channel (n) 44 from the top in the drawing. In FIG. 1, the oxide film 71 is formed although not shown.
- a gate 51 of a pixel transistor such as an amplification transistor (AMP), a reset transistor (RST), or a selection transistor (SEL), and a gate (TRG) 55 of a transfer transistor are formed. That is, as shown in FIG. 7, the gate (AMP / RST / SEL) 51 is formed on the channel (n) 52, and the gate 55 of the transfer transistor is formed at a position corresponding to the engraving 61.
- step S16 the drain (N ++) 53, the source (N ++) 54, and the floating diffusion (N ++) 56 of the pixel transistor such as the amplification transistor (AMP), the reset transistor (RST), or the selection transistor (SEL) are It is formed. That is, as shown in FIG. 8, the drain (N ++) 53 and the source (N ++) 54 are formed at both ends of the channel 52. Further, as shown in FIG. 8, the floating diffusion (N ++) is formed so as to be in contact with at least the channel 44.
- the drain (N ++) 53 and the source (N ++) 54 are formed at both ends of the channel 52.
- the floating diffusion (N ++) is formed so as to be in contact with at least the channel 44.
- the back surface pinning layer 24, the light shielding metal 23, the color filter 22, and the on-chip lens 21 are provided in the lower part of the figure of the silicon substrate 25, so that a solid-state imaging device as shown in FIG. Is done.
- the floating diffusion 56 up to the depth reaching the upper part of the photodiode 42 is formed, and the channel 44 connecting them is formed. It is possible to secure the charge transfer path in the direction (horizontal direction in the figure) perpendicular to the depth direction (vertical direction in the figure).
- the surface pinning layer 43 as an element isolation layer between the epitaxial layer 26 and the silicon substrate 25 is formed by impurity implantation.
- the epitaxial layer 26 is of a P-type (P-Epi) as shown in FIG. 1
- the P-type concentration of the epitaxial layer is such that the photodiode 42 and (gate 51, channel 52, drain 53, If the concentration is sufficiently separable from the pixel transistor (consisting of the source 54 and the source 54), it is not necessary to implant the P-type impurity to form the surface pinning layer 43. In this case, the surface pinning layer 43 is formed. It is also possible to reduce the number of processes.
- a P-type impurity is implanted to form the photodiode 42 (the gate 51, the channel 52, the drain 53, and the source 54). It is necessary to form a surface pinning layer (well) 43 that separates the transistor.
- the gate 55 of the transfer transistor may be dug after the epitaxial layer 26 is formed, or may be formed before the epitaxial layer 26 is formed, and the epitaxial layer 26 may be formed by selective growth.
- II Ion Implant
- II is implanted by self-alignment using the gate 55 of the transfer transistor to form the photodiode 42. Therefore, it is possible to suppress a decrease in robustness with respect to the alignment of the photodiode 42 and the gate 55 of the transfer transistor. For this reason, it is possible to make the design around the gate 55 of the transfer transistor close to the conventional structure arranged on the same plane, and the restriction on the pattern for securing the transfer path in the vertical direction is relaxed. be able to.
- the epitaxial layer 26 is formed even if the floating diffusion 56 is formed by performing II implantation and connecting them. After that, it may be formed in multiple steps.
- the area of the photodiode can be increased by dividing the layer in which the photodiode and the pixel transistor are formed in the incident light incident direction (depth direction), so that sensitivity and pixel capacitance Qs Can be improved.
- each pixel can be arranged completely symmetrically, it is possible to improve the difference between pixels.
- a transfer path in a direction perpendicular to the incident direction of incident light is secured on the silicon substrate 25 using the gate 55 of the transfer transistor embedded in the epitaxial layer 26. As a result, it is possible to improve the transfer characteristic deterioration peculiar to the vertical transfer.
- the area where the pixel transistor can be arranged becomes large, a sufficient length and width can be secured for the size of the photodiode constituting each pixel, so that the influence is reduced by random noise caused by the pixel transistor. Is possible.
- Second Embodiment> In the above, the example in which the epitaxial layer 26 is formed so that the bottom of the floating diffusion 56 coincides with the depth of the upper portion of the photodiode 42 has been described. However, since it is only necessary to secure a charge transfer path from the photodiode 42 in a direction perpendicular to the depth direction (horizontal direction in FIG. 1), the position where the sub-floating diffusion is in contact with the channel 44 connected to the photodiode 42. As such, it may be provided separately from the floating diffusion 56 and electrically connected to each other.
- FIG. 9 shows a configuration in which the sub-floating diffusion (SubFD) 91 is provided at a position and a depth in contact with the channel 44 connected to the photodiode 42 and connected to the floating diffusion (FD) 56 through the channel 101.
- 2 shows a configuration example of a solid-state imaging device.
- symbol are attached
- the sub-floating diffusion 91 is provided at a position that is substantially the same depth as the upper portion of the photodiode 42 and is connected to the channel 44, the charge from the photodiode 42 is increased.
- This transfer path can be set to a direction perpendicular to the depth direction (horizontal direction in FIG. 9). With such a configuration, it is possible to achieve the same effect as the solid-state imaging device in FIG.
- the sub-floating diffusion 91 and the floating diffusion 56 are configured to have a potential difference via the channel 101, it is possible to reduce the influence on afterimages and pumping deterioration.
- the floating diffusion 56 is formed on the silicon substrate 25, and then the epitaxial layer 26 is provided.
- the epitaxial layer 26 is engraved so as to reach the floating diffusion 56, so as to contact the floating diffusion 56.
- 2 is a configuration example of a solid-state imaging device in which a contact 121 is provided.
- the contact 121 can be shortened in the vertical direction, so that deterioration of transfer characteristics can be suppressed. That is, the thickness T2 of the epitaxial layer 26 in FIG. 10 can be made thinner than the thickness T1 (> T2) of the epitaxial layer 26 in FIG.
- the floating diffusion 56 is formed on the silicon substrate 25, the horizontal positional relationship with the photodiode 42 can be brought close to the conventional structure and design.
- the floating diffusion 56 may be formed only on the silicon substrate 25 as shown in FIG. 10, or before and after the formation of the epitaxial layer 26 as in the solid-state imaging device of FIG. It may be formed by a plurality of times II, and one of them can be selected. Incidentally, by forming the floating diffusion 56 by a plurality of times II before and after the formation of the epitaxial layer 26, the epitaxial layer 26 can be made thinner and the length of the contact 121 can be made shorter. It becomes possible.
- a pixel transistor (consisting of a gate 51, a channel 52, a drain 53, and a source 54) such as an amplification transistor (AMP), a reset transistor (RST), or a selection transistor (SEL), a transfer transistor gate 55, and a floating diffusion 56
- AMP amplification transistor
- RST reset transistor
- SEL selection transistor
- a transfer transistor gate 55 a floating diffusion 56
- An oxide film may be used for the separation.
- FIG. 11 shows a pixel transistor (consisting of a gate 51, a channel 52, a drain 53, and a source 54) such as an amplification transistor (AMP), a reset transistor (RST), or a selection transistor (SEL), a gate 55 of a transfer transistor,
- a pixel transistor consisting of a gate 51, a channel 52, a drain 53, and a source 54
- AMP amplification transistor
- RST reset transistor
- SEL selection transistor
- the oxide film 141 is provided as an element isolation layer on the left end portion of the drain 53 and the right end portion of the source 54 on the epitaxial layer 26 in FIG.
- the oxide film 141 is provided as the element isolation layer on the left end portion of the drain 53 and the right end portion of the source 54 on the epitaxial layer 26 has been described.
- the oxide film 141 provided at the left end of the drain 53 is further extended to the silicon substrate 25 side, and a buried oxide film is formed in the silicon substrate 25 to completely separate adjacent pixels. May be.
- FIG. 12 shows a configuration example of the solid-state imaging device in which the oxide film 141 is extended to the silicon substrate 25 side and a buried oxide film is formed in the silicon substrate 25 at that position.
- an oxide film 171 is provided in which the oxide film 141 is extended from the left end of the drain (D) 53 to the silicon substrate 25, and is further connected to the oxide film 171.
- a buried oxide film 181 is provided in the silicon substrate 25. Further, the buried oxide film 181 is in contact with the light shielding metal 23. Further, a buried oxide film 181 is also provided at the right end portion of the photodiode 42, and similarly, is configured to be in contact with the light shielding metal 23.
- An oxide film 171 is also provided at the right end of the source (S) 54.
- the buried oxide film 181 is connected to the oxide film 171 of the epitaxial layer 26, so that adjacent pixels can be completely separated. Further, the buried oxide film 181 may be filled with the same material as the light shielding metal 23 (for example, a metal such as W (tungsten)).
- the buried oxide film 181 is connected to the light shielding metal 23 to suppress the light collected by the on-chip lens 21 from being transmitted to the adjacent pixels, the buried oxide film 181 is formed on the photodiode 42 in the silicon substrate 25. It can be made incident. As a result, the sensitivity of the photodiode 42 can be improved.
- the surface pinning layer (impurity diffusion layer) near the interface between the silicon substrate 25 and the epitaxial layer (P-Epi) 26 may be formed by In-situ doped Epi growth.
- FIG. 13 shows a configuration example of a solid-state imaging device in which a surface pinning layer (impurity diffusion layer) is formed by in-situ doped Epi growth. That is, FIG. 13 shows a configuration example of the solid-state imaging device when the surface pinning layer (p + -Epi) 191 is formed by In-situ doped Epi growth.
- a surface pinning layer impurity diffusion layer
- An oxide film having a thickness equal to or greater than that of the gate oxide film is disposed between the gate 55 and the floating diffusion 56 to suppress a decrease in conversion efficiency due to an increase in capacity of the floating diffusion 56, and between the gate 55 and the floating diffusion 56. The electric field between them may be relaxed.
- FIG. 14 shows a configuration example of a solid-state imaging device in which, for example, SiO 2 is disposed as an oxide film between the gate 55 and the floating diffusion 56.
- the left part of FIG. 14 is a top view when the floating diffusion 56 arranged at the center is shared by 4 pixels of 2 pixels ⁇ 2 pixels indicated by a dashed line.
- the right part of FIG. 14 is a cross-sectional view between ab indicated by a dotted line of 2 pixels ⁇ 2 pixels in the left part of FIG.
- the transfer transistor is provided at the corner of each pixel (photodiode 42) in contact with the floating diffusion 56 shared by the four pixels provided at the center of the two pixels ⁇ two pixels.
- a gate 55 is provided.
- An oxide film 211 made of SiO 2 is provided between the floating diffusion 56 and the gate 55.
- pixel transistor gates 51 are provided above and below the 2 ⁇ 2 pixel diagram.
- an oxide film 211 made of SiO 2 is provided between the floating diffusion 56 and the gate 55.
- a trench is formed in the region of the epitaxial layer 26 where the oxide film 211 is formed, and subsequently, the trench is filled with SiO 2 that forms the oxide film 211.
- the trench may be an air gap.
- the transfer transistor gate 55 and the other pixel transistor gates 51 are formed so as to straddle the photodiode 42 and the floating diffusion 56.
- the FD contact 212 is formed and completed.
- the example in which the manufacturing is started from the state where the impurity implantation of the floating diffusion 56 at the bottom portion of the epitaxial layer 26 is completed has been described.
- the FD contact 212 is formed. Impurities may be implanted in the immediately preceding process.
- SiO2 is disposed as an oxide film between the gate 55 and the floating diffusion 56, and the floating diffusion 56 is connected with a metal wiring so as to realize an embedded floating diffusion 56.
- 2 shows a configuration example of the solid-state imaging device.
- the left part of FIG. 16 is the same as that in FIG. Further, the right part of FIG. 16 is a cross-sectional view between ab indicated by a dotted line of 2 pixels ⁇ 2 pixels in the left part of FIG.
- an oxide film 211 made of SiO 2 or the like is provided between the floating diffusion 56 and the gate 55. Further, the floating diffusion 56 is connected to the bottom portion of the epitaxial layer 26 by the metal wiring 221, thereby forming a buried floating diffusion 56.
- the metal wiring 221 can realize further miniaturization of the pixel.
- a trench is formed so as to be electrically connected to the floating diffusion 56 provided at the bottom of the epitaxial layer 26, and the metal wiring 221 is connected to the floating diffusion. 56 to complete the connection.
- the contact between the floating diffusion 56 and the metal wiring 221 may be formed by sandwiching a thin insulating film.
- an oxide film (SiO 2) having a thickness equal to or larger than the gate oxide film is disposed between the gate 55 and the floating diffusion 56, and further, a solid-state imaging device including the metal wiring 221 connected to the floating diffusion 56 Can be manufactured.
- an oxide film SiO 2 having a thickness greater than that of the gate oxide film is disposed between the gate 55 and the floating diffusion 56, and further, an oxide film SiO 2 having a thickness greater than that of the gate oxide film is surrounded by the gate 55.
- 2 shows an example of the configuration of a solid-state imaging device arranged.
- the transfer transistor is provided at the corner of each pixel (photodiode 42) that is in contact with the floating diffusion 56 shared by the four pixels provided in the center of 2 pixels ⁇ 2 pixels.
- a gate 55 is provided.
- An oxide film made of SiO 2 is provided so as to surround the gate 55.
- pixel transistor gates 51 are provided above and below the 2 ⁇ 2 pixel diagram.
- an oxide film 211 made of SiO 2 or the like is provided between the floating diffusion 56 and the gate 55, and further provided so as to surround the gate 55.
- an oxide film (SiO2) having a thickness greater than or equal to the gate oxide film is arranged around the gate 55, so that only the bottom part of the gate 55 of the transfer transistor is provided. Will contribute to charge transfer. As a result, an increase in the capacity of the floating diffusion 56 can be reduced, and a reduction in conversion efficiency can be suppressed. Further, since the electric field between the gate 55 and the floating diffusion 56 can be relaxed, the reliability of the gate of the transfer transistor can be improved.
- a trench is formed in the epitaxial layer 26, an impurity is implanted, and a floating diffusion 56 is formed. Is filled.
- the gate 55 of the transfer transistor is formed so as to straddle the photodiode 42 and the floating diffusion 56 at the bottom of the oxide film 211.
- a gate 51 of the pixel transistor is formed.
- the metal wiring 221 is connected and completed so that the floating diffusion 56 is embedded.
- FIG. 20 shows a configuration example of a solid-state imaging device in which the gate 55 of the transfer transistor is thinned except for a portion that requires an execution width across the photodiode 42 and the floating diffusion 56.
- the configuration in the top view in the left part of FIG. 20 is the same as in the case of FIG.
- an oxide film 211 made of SiO 2 or the like is provided between the floating diffusion 56 and the gate 55, and further provided so as to surround the gate 55.
- the upper right portion in FIG. 20 is the same as the configuration in the right portion in FIG.
- the top part of the gate 55 is configured to be smaller than the gate 55 shown in the right part of FIG.
- the effective width (diameter) of the bottom portion of the gate 55 surrounded by the dotted line at the lower right in FIG. 20 is the minimum width (diameter) that can straddle the floating diffusion 56 and the photodiode 42.
- Such a configuration makes it possible to suppress a decrease in conversion efficiency due to an increase in the capacity of the floating diffusion 56. Further, since the electric field between the gate 55 and the floating diffusion 56 can be relaxed, the reliability of the gate of the transfer transistor can be improved. Furthermore, it is possible to realize pixel miniaturization with higher accuracy.
- a trench is formed in a region of the epitaxial layer 26 where the oxide film 211 is formed, and the trench is filled with SiO 2 that forms the oxide film 211.
- a trench 231 having a width that spans the photodiode 42 and the floating diffusion 56 in the subsequent process is formed at the bottom of the oxide film 211.
- the bottom part of the trench 231 has a diameter larger than the diameter of the trench 231 by isotropic etching, and the photodiode 42 and the floating diffusion 56 are formed. It is formed by bottom portions 231r and 231n having a diameter that is the minimum width to straddle. By forming the bottom portions 231r and 231n, the photodiode 42 and the floating diffusion 56 can be straddled with an execution width having a minimum width.
- a gate 55 is formed in the trench 231 and only the bottom portions 231r and 231n straddle the photodiode 42 and the floating diffusion 56 in a state that contributes to charge transfer. Shaped.
- the metal wiring 221 is electrically connected to complete the floating diffusion and is completed.
- the diameter of the gate 55 is configured to straddle the photodiode 42 and the floating diffusion 56 at the bottom portions 231r and 231n.
- the top part of the gate 55 can be made smaller compared to the configuration of the upper right part of FIG. 20 (similar to the right part of FIG. 18). Can be further miniaturized.
- the solid-state imaging device shown in the first to tenth embodiments may be applied to an imaging device mounted on an electronic device such as a smartphone or a mobile phone.
- FIG. 22 is a block diagram illustrating a configuration example of an imaging apparatus that includes the solid-state imaging device according to the first to tenth embodiments and is mounted on an electronic apparatus.
- the imaging apparatus 301 includes an optical system 311, a solid-state imaging device 312, a signal processing circuit 313, a monitor 314, a driving circuit 315, and a user interface 316, and displays still images and moving images. Imaging is possible.
- the optical system 311 includes one or a plurality of lenses, guides image light (incident light) from a subject to the solid-state image sensor 312, and forms an image on the imaging surface of the solid-state image sensor 312.
- the solid-state image sensor 312 is one of the solid-state image sensors of the above-described embodiments. Electrons are accumulated in the solid-state imaging device 312 for a certain period according to the image formed on the light receiving surface via the optical system 311. Then, a signal corresponding to the electrons accumulated in the solid-state image sensor 312 is supplied to the signal processing circuit 313. In addition, the solid-state imaging device 312 performs signal transfer according to a drive signal (timing signal) supplied from the drive circuit 315.
- a drive signal timing signal
- the signal processing circuit 313 performs various kinds of signal processing on the pixel signal output from the solid-state imaging device 312. An image signal obtained by the signal processing by the signal processing circuit 313 is supplied to a memory (not shown) and stored (recorded).
- the monitor 314 includes an LCD (Liquid Crystal Display) or the like, and displays an image signal output from the signal processing circuit 313.
- LCD Liquid Crystal Display
- the drive circuit 315 drives the optical system 311 and the solid-state image sensor 312.
- the user interface 316 includes buttons, a touch panel, and the like, receives a user operation, and supplies a signal corresponding to the operation to the monitor 314 or the drive circuit 315.
- An imaging apparatus with improved transfer characteristics of charges accumulated by the photodiode 42 can be realized by a solid-state imaging element mounted on an electronic device as an imaging apparatus as shown in FIG.
- this technique can also take the following structures.
- a pixel transistor formed in the first layer A photodiode formed in a second layer separated from the first layer in the depth direction; A transfer transistor for controlling transfer of charge of the photodiode, The transfer transistor is a back-illuminated solid-state imaging device formed by being embedded in the first layer.
- the back-illuminated solid-state imaging device according to (1) wherein a gate of the transfer transistor is formed in the second layer.
- (3) further includes a floating diffusion for detecting the charge transferred from the photodiode; The back-illuminated solid-state imaging device according to (1) or (2), wherein the floating diffusion is formed at a position including the second layer.
- a part of the floating diffusion is configured to have the same depth as a part of the photodiode with respect to a light incident direction, and the floating diffusion has a part of the floating diffusion having the same depth.
- a back-illuminated solid-state imaging device according to (3), wherein a channel whose opening / closing is controlled by the transfer transistor is formed between a part of the photodiodes.
- the floating diffusion is formed in the second layer, and a contact that electrically connects the floating diffusion is formed by engraving the first layer so as to penetrate the first diffusion layer.
- Back-illuminated solid-state image sensor In the first layer, an oxide film is formed at a position adjacent to each of the drain and the source of the pixel transistor so as to sandwich the pixel transistor.
- the surface-side pinning layer of the photodiode which is a boundary surface between the first layer and the second layer and on the second layer, is formed by p-type epitaxial growth.
- the floating diffusion is formed in the second layer, and a metal wiring that electrically connects the floating diffusion is formed by being engraved so as to penetrate the first layer.
- Back-illuminated solid-state image sensor (14) The back-illuminated solid-state imaging device according to (12), wherein an oxide film having a thickness greater than or equal to a gate oxide film is formed so as to surround the gate of the transfer transistor. (15) The bottom portion of the gate of the transfer transistor is formed so as to straddle the floating diffusion and the photodiode, and other portions are formed with a diameter smaller than that of the bottom portion. Back-illuminated solid-state image sensor.
- a pixel transistor formed in the first layer A photodiode formed in a second layer separated from the first layer in the depth direction; A transfer transistor for controlling transfer of charge of the photodiode,
- the transfer transistor is embedded in the first layer.
- a pixel transistor formed in the first layer;
- a photodiode formed in a second layer separated from the first layer in the depth direction;
- the transfer transistor is an electronic device including a backside illumination type solid-state imaging device formed by being embedded in the first layer.
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Abstract
Description
1.第1の実施の形態(フローティングディフュージョンをフォトダイオードが形成される層まで彫り込んで形成する例)
2.第2の実施の形態(フローティングディフュージョンをフォトダイオードが形成される層と、画素トランジスタが形成される層とのそれぞれに分離して形成する例)
3.第3の実施の形態(フローティングディフュージョンをフォトダイオードが形成される層に形成し、エピタキシャル層にコンタクトを彫り込んで形成する例)
4.第4の実施の形態(画素トランジスタを挟むように酸化膜を形成する例)
5.第5の実施の形態(画素トランジスタを挟むように酸化膜を形成し、さらに、フォトトランジスタが形成されるシリコン基板にも接続して彫り込み酸化膜を形成する例)
6.第6の実施の形態(表面ピニング層をin-site doped成長により形成する例)
7.第7の実施の形態(転送トランジスタのゲートとフローティングディフュージョンとの間に酸化膜を形成する例)
8.第8の実施の形態(転送トランジスタのゲートとフローティングディフュージョンとの間に酸化膜を形成し、FDコンタクトをメタル配線とする例)
9.第9の実施の形態(転送トランジスタのゲートとフローティングディフュージョンとの間に加えて、ゲートを囲むように酸化膜を形成する例)
10.第10の実施の形態(転送トランジスタのゲートとフローティングディフュージョンとの間に加えて、ゲートを囲むように酸化膜を形成し、ゲートのボトム部だけを実行幅として、それ以外を細くする例)
11.第11の実施の形態(本技術の固体撮像素子を有する撮像装置を備えた電子機器の構成例)
図1は、本技術を適用した固体撮像素子の第1の実施の形態の構成例を示した図である。尚、図1の固体撮像素子は、裏面照射型の固体撮像素子である。図1においては、固体撮像素子に対する入射光の進行方向(深さ方向)は、図中の下方向から上方向であり、以降においては、図中の各層における上方の面が表面であり、下方の面が裏面であるものとする。従って、図中の下部が深い位置であり、これに対して、図中の上部が浅い位置である。また、図1は、固体撮像素子の1画素分の側面断面図である。
次に、図2のフローチャートを参照して、図1の固体撮像素子の製造方法について説明する。
以上においては、フローティングディフュージョン56の底部をフォトダイオード42の上部の深さと一致するように、エピタキシャル層26を形成する例について説明してきた。しかしながら、フォトダイオード42からの電荷の転送経路が深さ方向に対して垂直方向(図1における水平方向)に確保できればよいので、サブフローティングディフュージョンを、フォトダイオード42に接続されたチャンネル44に接する位置となるように、フローティングディフュージョン56とは別に設けて、相互に電気的に接続するような構成にしてもよい。
フォトダイオード42からの電荷の転送経路を深さ方向に対して垂直方向(図中の水平方向)に確保できればよいので、フローティングディフュージョン56を、フォトダイオード42に接続されたチャンネル44に接する位置、および深さとなるように、シリコン基板25上に設けるようにしてもよい。この場合、シリコン基板25上にエピタキシャル層26が形成されてから、フローティングディフュージョン56に接触するように彫り込みを生成して、この彫り込みにコンタクトを設けるようにしても良い。
増幅トランジスタ(AMP)、リセットトランジスタ(RST)、または、選択トランジスタ(SEL)といった(ゲート51、チャンネル52、ドレイン53、およびソース54とからなる)画素トランジスタ、転送トランジスタのゲート55、およびフローティングディフュージョン56の分離に酸化膜を用いるようにしても良い。
第4の実施の形態においては、エピタキシャル層26上にドレイン53の左端部、およびソース54の右端部にそれぞれ素子分離層として酸化膜141が設けられる例について説明してきた。しかしながら、ドレイン53の左端部に設けられた酸化膜141をさらにシリコン基板25側に延ばして、シリコン基板25内にも埋め込み酸化膜を形成して隣接画素間を完全に分離する構成とするようにしても良い。
シリコン基板25とエピタキシャル層(P-Epi)26との界面付近の表面ピニング層(不純物拡散層)は、In-situ doped Epi成長により形成するようにしてもよい。
ゲート55とフローティングディフュージョン56との間にゲート酸化膜以上の厚さの酸化膜を配置するようにしてフローティングディフュージョン56の容量増加に伴う変換効率低下を抑制すると共に、ゲート55とフローティングディフュージョン56との間の電界を緩和させるようにしてもよい。
次に、図15を参照して、図14の固体撮像素子の製造方法について説明する。尚、ここでは、埋込式のフォトダイオード42とフローティングディフュージョン56は、形成されている状態であるものとする。
以上においては、ゲート55とフローティングディフュージョン56との間にゲート酸化膜以上の厚さの酸化膜(SiO2)を配置するようにした固体撮像素子について説明してきたが、さらに、フローティングディフュージョンに対しては、メタル配線で接続し、埋め込み式のフローティングディフュージョンを実現するようにしてもよい。
次に、図17を参照して、図16の固体撮像素子の製造方法について説明する。第1の工程において、図17の左上部で示されるように、エピタキシャル層26の酸化膜211が形成される領域とメタル配線221が形成される領域にトレンチが形成され、引き続き、トレンチに酸化膜211を形成するSiO2が充填される。第2の工程は上述の内容と同様の処理であるので、その説明は省略するものとする。
以上においては、フォローティングディフュージョン56とゲート55との間にゲート酸化膜以上の厚さの酸化膜SiO2を配置するようにする例について説明してきたが、さらに、ゲート55を取り囲むようにゲート酸化膜以上の厚さの酸化膜SiO2を充填するようにしてもよい。
次に、図19を参照して、図18の固体撮像素子の製造方法について説明する。
以上においては、フローティングディフュージョン56とゲート55との間に加えて、ゲート55を取り囲むようにゲート酸化膜以上の厚さの酸化膜SiO2を配置するようにする例について説明してきたが、さらに、転送トランジスタのゲート55を、フォトダイオード42とフローティングディフュージョン56とを跨ぐ実行幅が必要な部位以外を細くするようにすることで、より画素の微細化を実現できるようにしてもよい。
次に、図21を参照して、図20の固体撮像素子の製造方法について説明する。
第1乃至第10の実施の形態で示される固体撮像素子は、例えば、スマートフォンや携帯電話機などの電子機器に搭載される撮像装置に適用するようにしてもよい。
(1) 第1の層に形成される画素トランジスタと、
前記第1の層と深さ方向に分離された第2の層に形成されるフォトダイオードと、
前記フォトダイオードの電荷の転送を制御する転送トランジスタとを含み、
前記転送トランジスタは、前記第1の層に埋め込んで形成される
裏面照射型の固体撮像素子。
(2) 前記転送トランジスタのゲートは、前記第2の層に形成される
(1)に記載の裏面照射型の固体撮像素子。
(3) 前記フォトダイオードより転送された電荷を検出するフローティングディフュージョンをさらに含み、
前記フローティングディフュージョンは、前記第2の層を含む位置に形成される
(1)または(2)に記載の裏面照射型の固体撮像素子。
(4) 前記フローティングディフュージョンは、その一部が、前記フォトダイオードの一部と光の入射方向に対して同一の深さとなるように構成され、前記同一の深さの前記フローティングディフュージョンの一部と、前記フォトダイオードの一部との間に、前記転送トランジスタにより開閉が制御されるチャンネルが形成される
(3)に記載の裏面照射型の固体撮像素子。
(5) 前記フローティングディフュージョンは、全体が一体とした構成とされ、前記第1の層を貫通して、前記第2の層を含む位置に形成される
(3)に記載の裏面照射型の固体撮像素子。
(6) 前記フローティングディフュージョンは、前記第1の層と、前記第2の層との、それぞれに分離して形成される
(3)に記載の裏面照射型の固体撮像素子。
(7) 前記フローティングディフュージョンは、前記第2の層に形成され、前記フローティングディフュージョンを電気的に接続するコンタクトが、前記第1の層を貫通するように彫り込んで形成される
(3)に記載の裏面照射型の固体撮像素子。
(8) 前記第1の層において、前記画素トランジスタを挟むように、前記画素トランジスタのドレインおよびソースのそれぞれに隣接する位置に酸化膜が形成される
(3)に記載の裏面照射型の固体撮像素子。
(9) 前記第2の層に、前記第1の層の前記酸化膜と対応する位置に、連続的な構成として、埋め込み酸化膜が形成される
(8)に記載の裏面照射型の固体撮像素子。
(10) 前記第1の層、および前記第2の層との境界面であって、前記第2の層上の、前記フォトダイオードの表面側ピニング層は、p型のエピタキシャル成長により形成される
(1)乃至(9)に記載の裏面照射型の固体撮像素子。
(11) 前記表面ピニング層は、in-site doped Epi成長により形成される
(10)に記載の裏面照射型の固体撮像素子。
(12) 前記フローティングディフュージョンと、前記転送トランジスタのゲートとの間にゲート酸化膜以上の厚さの酸化膜が形成される
(3)に記載の裏面照射型の固体撮像素子。
(13) 前記フローティングディフュージョンは、前記第2の層に形成され、前記フローティングディフュージョンを電気的に接続するメタル配線が、前記第1の層を貫通するように彫り込んで形成される
(12)に記載の裏面照射型の固体撮像素子。
(14) 前記転送トランジスタのゲートを取り囲むようにゲート酸化膜以上の厚さの酸化膜が形成される
(12)に記載の裏面照射型の固体撮像素子。
(15) 前記転送トランジスタのゲートのボトム部のみが前記フローティングディフュージョンと、前記フォトダイオードとを跨ぐように形成され、その他の部位は、前記ボトム部よりも径が小さく形成される
(12)に記載の裏面照射型の固体撮像素子。
(16) 第1の層に形成される画素トランジスタと、
前記第1の層と深さ方向に分離された第2の層に形成されるフォトダイオードと、
前記フォトダイオードの電荷の転送を制御する転送トランジスタとを含み、
前記転送トランジスタが、前記第1の層に埋め込んで形成される
裏面照射型の固体撮像素子の製造方法において、
前記第1の層が形成された後、前記第1の層に、前記転送トランジスタのゲートが、前記第2の層に形成されるように彫り込みを形成し、
前記ゲートが、前記第2の層に形成されるように、前記彫り込みに前記転送トランジスタを形成する
裏面照射型の固体撮像素子の製造方法。
(17) 第1の層に形成される画素トランジスタと、
前記第1の層と深さ方向に分離された第2の層に形成されるフォトダイオードと、
前記フォトダイオードの電荷の転送を制御する転送トランジスタとを含み、
前記転送トランジスタは、前記第1の層に埋め込んで形成される
裏面照射型の固体撮像素子を備えた電子機器。
Claims (17)
- 第1の層に形成される画素トランジスタと、
前記第1の層と深さ方向に分離された第2の層に形成されるフォトダイオードと、
前記フォトダイオードの電荷の転送を制御する転送トランジスタとを含み、
前記転送トランジスタは、前記第1の層に埋め込んで形成される
裏面照射型の固体撮像素子。 - 前記転送トランジスタのゲートは、前記第2の層に形成される
請求項1に記載の裏面照射型の固体撮像素子。 - 前記フォトダイオードより転送された電荷を検出するフローティングディフュージョンをさらに含み、
前記フローティングディフュージョンは、前記第2の層を含む位置に形成される
請求項1に記載の裏面照射型の固体撮像素子。 - 前記フローティングディフュージョンは、その一部が、前記フォトダイオードの一部と光の入射方向に対して同一の深さとなるように構成され、前記同一の深さの前記フローティングディフュージョンの一部と、前記フォトダイオードの一部との間に、前記転送トランジスタにより開閉が制御されるチャンネルが形成される
請求項3に記載の裏面照射型の固体撮像素子。 - 前記フローティングディフュージョンは、全体が一体とした構成とされ、前記第1の層を貫通して、前記第2の層を含む位置に形成される
請求項3に記載の裏面照射型の固体撮像素子。 - 前記フローティングディフュージョンは、前記第1の層と、前記第2の層との、それぞれに分離して形成される
請求項3に記載の裏面照射型の固体撮像素子。 - 前記フローティングディフュージョンは、前記第2の層に形成され、前記フローティングディフュージョンを電気的に接続するコンタクトが、前記第1の層を貫通するように彫り込んで形成される
請求項3に記載の裏面照射型の固体撮像素子。 - 前記第1の層において、前記画素トランジスタを挟むように、前記画素トランジスタのドレインおよびソースのそれぞれに隣接する位置に酸化膜が形成される
請求項3に記載の裏面照射型の固体撮像素子。 - 前記第2の層に、前記第1の層の前記酸化膜と対応する位置に、連続的な構成として、埋め込み酸化膜が形成される
請求項8に記載の裏面照射型の固体撮像素子。 - 前記第1の層、および前記第2の層との境界面であって、前記第2の層上の、前記フォトダイオードの表面側ピニング層は、p型のエピタキシャル成長により形成される
請求項1に記載の裏面照射型の固体撮像素子。 - 前記表面ピニング層は、in-site doped Epi成長により形成される
請求項10に記載の裏面照射型の固体撮像素子。 - 前記フローティングディフュージョンと、前記転送トランジスタのゲートとの間にゲート酸化膜以上の厚さの酸化膜が形成される
請求項3に記載の裏面照射型の固体撮像素子。 - 前記フローティングディフュージョンは、前記第2の層に形成され、前記フローティングディフュージョンを電気的に接続するメタル配線が、前記第1の層を貫通するように彫り込んで形成される
請求項12に記載の裏面照射型の固体撮像素子。 - 前記転送トランジスタのゲートを取り囲むようにゲート酸化膜以上の厚さの酸化膜が形成される
請求項12に記載の裏面照射型の固体撮像素子。 - 前記転送トランジスタのゲートのボトム部のみが前記フローティングディフュージョンと、前記フォトダイオードとを跨ぐように形成され、その他の部位は、前記ボトム部よりも径が小さく形成される
請求項12に記載の裏面照射型の固体撮像素子。 - 第1の層に形成される画素トランジスタと、
前記第1の層と深さ方向に分離された第2の層に形成されるフォトダイオードと、
前記フォトダイオードの電荷の転送を制御する転送トランジスタとを含み、
前記転送トランジスタが、前記第1の層に埋め込んで形成される
裏面照射型の固体撮像素子の製造方法において、
前記第1の層が形成された後、前記第1の層に、前記転送トランジスタのゲートが、前記第2の層に形成されるように彫り込みを形成し、
前記ゲートが、前記第2の層に形成されるように、前記彫り込みに前記転送トランジスタを形成する
裏面照射型の固体撮像素子の製造方法。 - 第1の層に形成される画素トランジスタと、
前記第1の層と深さ方向に分離された第2の層に形成されるフォトダイオードと、
前記フォトダイオードの電荷の転送を制御する転送トランジスタとを含み、
前記転送トランジスタは、前記第1の層に埋め込んで形成される
裏面照射型の固体撮像素子を備えた電子機器。
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