WO2015172459A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2015172459A1
WO2015172459A1 PCT/CN2014/085427 CN2014085427W WO2015172459A1 WO 2015172459 A1 WO2015172459 A1 WO 2015172459A1 CN 2014085427 W CN2014085427 W CN 2014085427W WO 2015172459 A1 WO2015172459 A1 WO 2015172459A1
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Prior art keywords
pixel electrode
array substrate
substrate
test terminal
electrode
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PCT/CN2014/085427
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English (en)
French (fr)
Inventor
薛静
邢红燕
陈雅娟
尹岩岩
崔子巍
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Publication of WO2015172459A1 publication Critical patent/WO2015172459A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present disclosure relates to the field of display devices, and in particular, to an array substrate and a method of fabricating the same.
  • T'F LCD Thin Film Transistor Liquid Crystal Display
  • TN, IPS, VA, and ADS are several modes of liquid crystal display.
  • ADS is the abbreviation of ADSDS (ADvanced Super Dimension Switch), which is an advanced super-dimensional field conversion technology.
  • ADSDS ADvanced Super Dimension Switch
  • the electric field generated by the edge of the slit electrode in the same plane and The electric field generated between the slit electrode layer and the plate electrode layer forms a multi-dimensional electric field, so that all the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrode can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission. effectiveness.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT D products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura. .
  • the ADS product cannot confirm the TFT transistor characteristics of the pixel region during the column substrate manufacturing stage, so that it is impossible to accurately determine whether the thin film transistor characteristics of the pixel region are abnormal. Even if the test requirements are reasonably considered during development, the test Tfeg is designed. (Electrical test point) area, but its thin film transistor characteristics are also deviated from the thin film transistor characteristics of the pixel area, which cannot accurately reflect the characteristics of the thin film transistor in the pixel area, which brings great inconvenience to the development review work and affects the development efficiency; Problems can't be solved in the first place, invisible Increased production costs.
  • An object of the present invention is to provide a column substrate, a method of manufacturing the same, and a display device which contribute to confirmation of characteristics of a thin film transistor in a pixel region, contribute to improvement in development efficiency, and reduce development cost.
  • the array substrate of the present disclosure includes a gate line, a data line, and a pixel electrode formed in a pixel region defined by the cell line and the data line, and further includes a test terminal connected to the pixel electrode to test the characteristics of the thin film transistor.
  • the pixel electrode includes a first pixel electrode disposed on the gate insulating layer and the active layer, and a second pixel electrode disposed in parallel with the first pixel electrode, the test terminal and the The first pixel electrode is connected.
  • the array substrate of the present disclosure including:
  • the test terminal is formed in the same layer as the first pixel electrode and on the substrate; the second pixel electrode is formed on the protective layer.
  • test terminal is located between the pixel region and a flexible circuit board bonding region.
  • an electrostatic ring is disposed between the pixel region and the flexible circuit board bonding region, and the test terminal is located between the electrostatic ring and the flexible circuit board bonding region.
  • a common electrode lead is disposed between the electrostatic ring and the flexible circuit board bonding region, and the test terminal is located between the common electrode lead and the flexible circuit board bonding region.
  • test trace is disposed between the common electrode lead and the flexible circuit board bonding region, and the test terminal is located between the test trace and the flexible circuit board bonding region.
  • the display device of the present disclosure includes the array substrate of the present disclosure.
  • the method for manufacturing an array substrate of the present disclosure includes the following steps:
  • a pattern of the second pixel electrode is formed on the substrate.
  • the step of forming a first pixel electrode and a pattern of a test terminal for testing characteristics of the thin film transistor connected to the first pixel electrode on the substrate includes:
  • the technical solution is to optimize the array substrate as a whole, and set a test terminal connected to the pixel electrode to test the characteristics of the thin film transistor, so that the thin film transistor characteristic of the pixel region can be confirmed by applying a power signal to the test terminal, the first time Responding to bad performance ensures the smooth completion of development, improving development efficiency and reducing development costs.
  • Figure 3 is the A board of Figure 2 : Figure of the person, showing the position of the test terminal;
  • FIG. 4 is a flowchart of a method of manufacturing an array substrate according to an embodiment of the present disclosure
  • staff can be better limited.
  • the array substrate of the present disclosure includes a gate line, a data line, and a pixel electrode formed in the pixel region 10 defined by the cell line and the data line, and further includes a connection with the pixel electrode.
  • the array substrate of the present disclosure wherein the pixel electrode includes a first pixel electrode 11 disposed on the gate insulating layer 3 and the active layer 4 and a second pixel electrode 12 disposed in parallel with the first pixel electrode 11
  • the test terminal 20 is connected to the first pixel electrode 11.
  • the array substrate of the present disclosure includes:
  • a gate insulating layer 3 formed over the gate electrode 2 and the active layer 4;
  • the test terminal 20 is formed on the substrate;
  • the second pixel electrode 12 is formed on the protective layer 7.
  • the array substrate of the present disclosure includes a display area 100 and an upper edge area 200 above the display area 100, and the test terminal 20 is located inside the upper edge area 200.
  • test terminal 20 is located between the pixel region 10 and the flexible circuit board bonding region 30.
  • an electrostatic ring 40 is disposed between the pixel region 10 and the flexible circuit board bonding region 30, and the test terminal 20 is located between the electrostatic ring 40 and the flexible circuit board bonding region 30.
  • a common electrode lead 50 is disposed between the electrostatic ring 40 and the flexible circuit board bonding region 30, and the test terminal 20 is located between the common electrode lead 50 and the flexible circuit board bonding region 30.
  • the electrostatic ring and the common electrode lead can adopt the existing design, and will not be described herein.
  • the first pixel electrode can be used as a pixel electrode of the liquid crystal display panel
  • the second pixel electrode can be used as a common electrode of the liquid crystal display panel
  • the common electrode lead in the embodiment of the present disclosure is an electrode of the second pixel electrode lead.
  • a test trace 60 is disposed between the common electrode lead 50 and the flexible circuit board bonding region 30, and the test terminal 20 is located between the test trace 60 and the flexible circuit board bonding region 30. between.
  • Test traces 60 are used to connect the traces of the electrical test terminals (ET pads). Typically, during routine testing, signals are loaded on test traces 60 to complete the Array test.
  • the display device of the present disclosure includes the array substrate of the present disclosure.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, and the like, or any display product or component.
  • the array substrate is integrally optimized, and a test terminal connected to the pixel electrode for testing the characteristics of the thin film transistor is disposed, so that the TFT transistor characteristic of the pixel region can be applied by applying an electrical signal to the test terminal. Confirmation, the first time to respond to the failure, to ensure the smooth completion of development, improve development efficiency and reduce development costs.
  • Step 1 depositing a gate metal film on the substrate, and forming a pattern of the wire and the cabinet electrode by a patterning process;
  • Step 2 forming a pattern of the gate insulating layer and the active layer on the substrate on which the step 1 is completed;
  • Step 3 forming a first pixel electrode on the substrate on which the step 2 is completed, and a test film connected to the first pixel electrode a pattern of test terminals for transistor characteristics;
  • Step 4 forming a pattern of source/drain electrodes on the substrate on which step 3 is completed;
  • Step 5 forming a pattern of the protective layer on the substrate on which the step 4 is completed;
  • Step 6 Form a pattern of the second pixel electrode on the substrate on which the step 5 is completed.
  • the step 1 includes:
  • Step 11 providing a substrate
  • Step 12 depositing a gate metal film on the substrate
  • Step 13 coating a photoresist on the gate metal film
  • Step 14 Exposing the photoresist with a mask to form a photoresist unretained region and a photoresist retention region, where the photoresist retention region corresponds to a region where the gate line and the gate electrode are patterned.
  • the photoresist unretained area corresponds to an area other than the above-mentioned pattern;
  • Step 15 Perform development processing, the photoresist in the unretained area of the photoresist is completely removed, and the thickness of the photoresist in the photoresist remaining area remains unchanged;
  • Step 16 completely etching away the ruthenium metal film of the unretained region of the photoresist by an etching process.
  • Step 17. Strip the remaining photoresist.
  • the step 2 includes:
  • Step 21 providing a gate insulating layer material and an active layer material on the substrate on which step 1 is completed; Step 22, applying a photoresist on the active layer material, and exposing and developing the photoresist by using a ffi mask
  • the gate insulating layer and the active layer are patterned by an etching process.
  • the step 3 includes:
  • Step 31 depositing a first pixel electrode material and a test terminal material on the substrate on which the step 2 is completed;
  • Step 32 coating a photoresist on the first pixel electrode material and the test terminal material, exposing and developing the photoresist by using a mask, obtaining a first pixel electrode by an etching process, and measuring the step 4 includes:
  • Step 41 depositing a source/drain metal layer on the substrate on which step 3 is completed;
  • Step 42 Applying a photoresist on the source/drain metal layer, exposing and developing the photoresist by using a mask, and obtaining a pattern of source/drain electrodes by an etching process.
  • the step 5 includes:
  • Step 51 depositing a protective layer material on the substrate on which step 4 is completed;
  • Step 52 Applying a photoresist on the protective layer material, exposing and developing the photoresist by using the mask, and obtaining a pattern of the protective layer by an etching process.
  • the step 6 includes:
  • Step 61 depositing a second pixel electrode material on the substrate on which step 6 is completed;
  • Step 62 Apply a photoresist to the second pixel electrode.
  • the photoresist is exposed and developed by the mask, and the pattern of the second pixel electrode is obtained by an etching process.
  • the technical solution of the present disclosure optimizes the array substrate as a whole, and sets a test terminal that is electrically connected to the first pixel electrode 11 in the upper edge region 200, so that by applying a signal to the test terminal, the thin film transistor characteristics of the pixel region can be performed. Confirmation, the first time to respond to the bad, to ensure the smooth completion of development.
  • a data line may be formed under the first pixel electrode 11.
  • a test terminal that is electrically connected to the first pixel electrode 11 may be disposed in the upper edge region 200, either under the first pixel electrode 11 or above.
  • the first pixel electrode 11 is formed while using the same mask to form a test for conducting the first pixel electrode II in the upper edge region 200 and outside the test trace 60. Terminal 20, this avoids over-holes in the protective layer.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

阵列基板及其制造方法、显示装置。其中阵列基板包括栅线、数据线以及形成在栅线和数据线限定的像素区域（10）内的像素电极，还包括与像素电极连接的用于测试薄膜晶体管特性的测试端子（20）。显示装置包括所述阵列基板。所述阵列基板的制造方法包括：在基板上形成第一像素电极（11）以及与第一像素电极（11）连接的用于测试薄膜晶体管特性的测试端子（20）的图形。通过对阵列基板进行整体优化，设置与像素电极连接的用于测试薄膜晶体管特性的测试端子，使得通过给测试端子加电信号可以对像素区域的薄膜晶体管特性进行确认，第一时间对不良做出反应。

Description

本申请主张在 2014 年 5 月 13 日在中国提交的中国专利申请号 No. 201410200687.3的优先权， 其全部内容通过引用包含于此。
本公开涉及显示装置技术领域， 尤其涉及一种阵列基板及其制造方法、
薄膜晶体管液晶显示器 ( Thin Film Transistor Liquid Crystal Display, T'F LCD) 具有体积小、 功耗低、 无辐射等优点， 在当前的平板显示装置市 场中占据了 导地位。对于 TFTNLCD来说， 阵列基板以及制造方法决定了其 产品性能、 成品率和价格。
TN、 IPS、 VA、 ADS 是液晶显示的几种模式， 其中， ADS 是 ADSDS (ADvanced Super Dimension Switch)的简称， 即高级超维场转换技术， 通过 同一平面内狹缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生 的电场形成多维电场， 使液晶盒内狭缝电极间、 电极正上方所有取向液晶分 子都能够产生旋转， 从而提高了液晶工作效率并增大了透光效率。
高级超维场转换技术可以提高 TFT D产品的画面品质， 具有高分辨 率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波紋（push Mura) 等优点。
ADS 产品在 列基板制造阶段无法进行像素区域的薄膜晶体管特性 (TFT Character) 确认， 从而不能准确判断像素区域的薄膜晶体管特性是否 异常， 即使开发过程中很合理的考虑到了测试需求， 设计了测试 Tfeg (电学 测试点） 区域， 但其薄膜晶体管特性也和像素区域的薄膜晶体管特性存在一 定偏差， 无法精确反映像素区域的薄膜晶体管特性， 给开发检讨工作带来极 大的不便， 影响开发效率； 一旦出现问题也不能第一时间得以解决， 无形当 中增加了生产成本。
本公开的目的是提供一种有助于像素区域的薄膜晶体管特性确认、 有助 于提升开发效率同时减少开发成本的 列基板及其制造方法、 显示装置。
本公开的阵列基板， 包括栅线、 数据线以及形成在櫥线和数据线限定的 像素区域内的像素电极， 还包括与所述像素电极连接的^于测试薄膜晶体管 特性的测试端子。
本公开的阵列基板， 其中， 所述像素电极包括设置于栅绝缘层以及有源 层上的第一像素电极以及与所述第一像素电极平行设置的第二像素电极， 所 述测试端子与所述第一像素电极连接。
本公开的阵列基板， 其中， 包括：
形成在基板上的栅电极；
形成在栅电极上方的栅绝缘层以及栅绝缘层上方的有源层；
形成于所述有源层上的源电极以及形成于所述第一像素电极上的漏电 极；
形成于所述源电极、 漏电极上的保护层；
所述测试端子与所述第一像素电极同层形成且位于所述基板上； 所述第二像素电极形成于所述保护层上。
本公开的阵列基板， 其中， 所述测试端子位于所述像素区域与柔性电路 板绑定区域之间。
本公开的阵列基板， 其中， 所述像素区域与柔性电路板绑定区域之间设 置有静电环， 所述测试端子位于所述静电环与柔性电路板绑定区域之间。
本公开的阵列基板， 其中， 所述静电环与柔性电路板绑定区域之间设置 有公共电极引线， 所述测试端子位于公共电极引线与柔性电路板绑定区域之 间。
本公开的阵列基板， 其中， 所述公共电极引线与柔性电路板绑定区域之 间设置有测试走线，所述测试端子位于测试走线与柔性电路板绑定区域之间。
本公开的显示装置， 包括本公开的阵列基板。 本公开的阵列基板的制造方法， 包括以下步骤：
在基板上沉积栅金属薄膜， 通过构图工艺形成栅线和栅电极的图形； 在所述基板上形成栅绝缘层以及有源层的图形；
在所述基板上同层形成第一像素电极以及与所述第一像素电极连接的用 于测试薄膜晶体管特性的测试端子的图形；
在所述基板上形成源电极、 漏电极的图形；
在所述基板上形成保护层的图形；
在所述基板上形成第二像素电极的图形。
本公开的阵列基板的制造方法， 其中， 在所述基板上同层形成第一像素 电极以及与所述第一像素电极连接的用于测试薄膜晶体管特性的测试端子的 图形的步骤包括：
在所述基板上沉积第一像素电极材料以及测试端子材料；
在所述第一像素电极材料以及测试端子材料上涂敷光刻胶， 利用掩膜板 对所述光刻胶进行曝光、 显影处理， 通过刻蚀工艺得到所述第一像素电极以 本公开的技术方案， 对阵列基板进行整体优化， 设置与像素电极连接的 )¾于测试薄膜晶体管特性的测试端子， 这样可以通过给上述测试端子加电信 号对像素区的薄膜晶体管特性进行确认， 第一时间对不良做出反应， 保证了 开发的顺利完成， 提升开发效率同时减少开发成本。
Figure imgf000005_0001
图 3为图 2的 A局 : ΰ乂人图， 示出了测试端子的位置;
图 4为本公开实施例的阵列基板的制造方法的流程图
下面结合 图
，员可以更好的理
Figure imgf000005_0002
限定。
如图 1、 图 2、 图 3所示， 本公开的阵列基板， 包括栅线、 数据线以及形 成在櫥线和数据线限定的像素区域 10内的像素电极，还包括与像素电极连接 的用于测试薄膜晶体管特性的测试端子 20。
如图 1所示， 本公开的阵列基板， 其中， 像素电极包括设置于栅绝缘层 3以及有源层 4上的第一像素电极 11以及与第一像素电极 11平行设置的第二 像素电极 12， 测试端子 20与第一像素电极 11连接。
本公开的阵列基板， 包括：
形成在基板 1上的栅电极 2;
形成于栅电极 2上方的栅绝缘层 3以及有源层 4;
形成于栅绝缘层 3以及有源层 4上的第一像素电极 1】， 测试端子 20形 成在基板〗上；
形成于有源层 4上的源电极 5以及形成于第一像素电极 11上的漏电极 6; 形成于源电极 5、 漏电极 6上的保护层 7;
形成于保护层 7上的第二像素电极 12。
如图 2所示， 本公开的阵列基板上包括显示区域 100以及显示区域 100 上方的上边缘区域 200， 测试端子 20位于上边缘区域 200的内部。
本公开的阵列基板中， 测试端子 20位于像素区域 10与柔性电路板绑定 区域 30之间。
本公开的阵列基板中， 像素区域 10与柔性电路板绑定区域 30之间设置 有静电环 40， 测试端子 20位于静电环 40与柔性电路板绑定区域 30之间。
本公开的阵列基板中， 静电环 40与柔性电路板绑定区域 30之间设置有 公共电极引线 50， 测试端子 20位于公共电极引线 50与柔性电路板绑定区域 30之间。 其中,静电环与公共电极引线可以采 现有的设计,在此不作赘述。
在本公开中， 第一像素电极可以用作液晶显示面板的像素电极、 第二像 素电极可以用作液晶显示面板的公共电极， 因此本公开实施例中的公共电极 引线为第二像素电极的电极引线。
本公开的阵列基板中， 公共电极引线 50与柔性电路板绑定区域 30之间 设置有测试走线 60，测试端子 20位于测试走线 60与柔性电路板绑定区域 30 之间。
测试走线 60用于连接电学测试端子（ET pad) 的走线， 通常在常规测试 中， 在测试走线 60上加载信号， 以完成 列基板测试 （Array test)。
本公开的显示装置包括本公开的阵列基板。 所述显示装置可以为： 液晶 面板、 电子纸、 OLED 面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平 板电脑等任何具有显示功能的产品或部件。
本公开的技术方案， 对阵列基板进行整体优化， 设置与像素电极连接的 用于测试薄膜晶体管特性的测试端子， 这样可以通过给上述测试端子施加电 信号对像素区域的薄膜晶体管特性 （TFT Character) 进行确认， 第一时间对 不良做出反应， 保证了开发的顺利完成， 提升开发效率同时减少开发成本。
本公开的阵列基板的制造方法的实施例， 包括如下步骤：
步骤 1、 在基板上沉积栅金属薄膜， 通过构图工艺形成櫥线和櫥电极的 图形；
步骤 2、 在完成步骤 1的基板上形成栅绝缘层以及有源层的图形； 步骤 3、 在完成步骤 2 的基板上形成第一像素电极以及与所述第一像素 电极连接的用于测试薄膜晶体管特性的测试端子的图形；
步骤 4、 在完成步骤 3的基板上形成源 /漏电极的图形；
步骤 5、 在完成步骤 4的基板上形成保护层的图形；
步骤 6、 在完成步骤 5的基板上形成第二像素电极的图形。
其中， 所述步骤 1包括：
步骤 11、 提供一基板；
步骤 12、 在基板上沉积栅金属薄膜；
步骤 13、 在栅金属薄膜上涂敷一层光刻胶；
步骤 14、 采用掩膜板对光刻胶进行曝光， 使光刻胶形成光刻胶未保留区 域和光刻胶保留区域， 所述光刻胶保留区域对应于栅线和栅电极的图形所在 区域， 所述光刻胶未保留区域对应于上述图形以外的区域；
步骤 15、 进行显影处理， 光刻胶未保留区域的光刻胶被完全去除， 光刻 胶保留区域的光刻胶厚度保持不变；
步骤 16、 通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的欐金属薄膜， 形 步骤 17、 剥离剩余的光刻胶。
所述步骤 2包括：
步骤 21、 在完成步骤 1的基板上设置栅绝缘层材料以及有源层材料； 步骤 22、 在有源层材料上涂敷光刻胶， 利 ffi掩膜板对光刻胶进行曝光、 显影处理， 通过刻蚀工艺得到栅绝缘层以及有源层的图形。
所述步骤 3包括：
步骤 31、 在完成步骤 2的基板上沉积第一像素电极材料以及测试端子材 料；
步骤 32、 在第一像素电极材料以及测试端子材料上涂敷光刻胶， 利用掩 膜板对光刻胶进行曝光、 显影处理， 通过刻蚀工艺得到第一像素电极以及测 所述歩骤 4包括：
步骤 41、 在完成步骤 3的基板上沉积源漏极金属层；
步骤 42、在源漏极金属层上涂敷光刻胶，利用掩膜板对光刻胶进行曝光、 显影处理， 通过刻蚀工艺得到源 /漏电极的图形。
所述歩骤 5包括：
步骤 51、 在完成步骤 4的基板上沉积保护层材料；
步骤 52、 在保护层材料上涂敷光刻胶， 利 掩膜板对光刻胶进行曝光、 显影处理， 通过刻蚀工艺得到保护层的图形。
所述歩骤 6包括：
步骤 61、 在完成步骤 6的基板上沉积第二像素电极材料；
步骤 62、 在第二像素电极.材料上涂敷光刻胶， 利) ¾掩膜板对光刻胶进行 曝光、 显影处理， 通过刻蚀工艺得到第二像素电极的图形。
本公开的技术方案对阵列基板进行整体优化， 在上边缘区域 200内设置 与第一像素电极 11导通的测试端子， 这样通过给此测试端子施加信号， 就可 以对像素区域的薄膜晶体管特性进行确认， 第一时间对不良做出反应， 保证 了开发的顺利完成。
本公开的阵列基板， 可以将数据线形成在第一像素电极 11下面。 无论数 据线在第一像素电极 11下面还是上面，都可以在上边缘区域 200内设置与第 一像素电极 11导通的测试端子。
本公开的阵列基板的制造方法中，在形成第一像素电极 11的同时利用同 一张掩膜板在上边缘区域 200 内、 测试走线 60 的外侧形成与第一像素电极 I I能够导通的测试端子 20, 这样可以避免在保护层上做过孔。
以上所述仅是本公开的优选实施方式， 应当指出， 对于本技术领域的普 通技术人员来说， 在不脱离本公开主旨的前提下， 还可以作出若千改进和润 饰， 这些改进和润饰也应视为本公开的保护范围。

Claims

1、 一种阵列基板， 包括栅线、 数据线以及形成在 »线和数据线限定的像 素区域内的像素电极， 还包括与所述像素电极连接的用于测试薄膜晶体管特 性的测试端子。
2、 如权利要求〗所述的阵列基板， 其中， 所述像素电极包括设置于栅绝 缘层以及有源层上的第一像素电极以及与所述第一像素电极平行设置的第二 像素电极， 所述测试端子与所述第一像素电极连接。
3、 如权利要求 2所述的阵列基板， 其中， 包括：
形成在基板上的 »电极；
形成在所述 »电极上方的栅绝缘层以及栅绝缘层上方的有源层； 形成于所述有源层上的源电极以及形成于所述第一像素电极上的漏电 极；
形成于所述源电极、 漏电极上的保护层；
所述测试端子与所述第一像素电极同层形成且位于所述基板上； 所述第 二像素电极形成于所述保护层上。
4、 如权利要求 1〜3任一项所述的阵列基板.， 其中， 所述测试端子位于所 述像素区域与柔性电路板绑定区域之间。
5、 如权利要求 4所述的阵列基板， 其中， 所述像素区域与柔性电路板绑 定区域之间设置有静电环， 所述测试端子位于所述静电环与柔性电路板绑定 区域之间。
6、 如权利要求 5所述的阵列基板， 其中， 所述静电环与柔性电路板绑定 区域之间设置有公共电极引线， 所述测试端子位于公共电极引线与柔性电路 板绑定区域之间。
7、 如权利要求 6所述的阵列基板， 其中， 所述公共电极引线与柔性电路 板绑定区域之间设置有测试走线， 所述测试端子位于测试走线与柔性电路板 绑定区域之间。
8、 一种显示装置， 包括权利要求 1-7任一项所述的阵列基板。
9、 一种阵列基板的制造方法， 包括以下歩骤： 在基板上沉积栅金属薄膜， 通过构图工艺形成栅线和 »电极的图形； 在所述基板上形成栅绝缘层以及有源层的图形；
在所述基板上同层形成第一像素电极以及与所述第一像素电极连接的用 于测试薄膜晶体管特性的测试端子的图形；
在所述基板上形成源电极、 漏电极的图形；
在所述基板上形成保护层的图形；
在所述基板上形成第二像素电极的图形。
10、 如权利要求 9所述的阵列基板的制造方法， 其中， 在所述基板上同 层形成第一像素电极以及与所述第一像素电极连接的用于测试薄膜晶体管特 性的测试端子的图形的步骤包括：
在所述基板上沉积第一像素电极材料以及测试端子材料；
在所述第一像素电极材料以及测试端子材料上涂敷光刻胶， 利用掩膜板 对所述光刻胶进行曝光、 显影处理， 通过刻蚀工艺得到所述第一像素电极以 及测试端子的图形。
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