WO2015165411A1 - 绝缘体上硅器件及其金属间介质层结构和制造方法 - Google Patents

绝缘体上硅器件及其金属间介质层结构和制造方法 Download PDF

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WO2015165411A1
WO2015165411A1 PCT/CN2015/077877 CN2015077877W WO2015165411A1 WO 2015165411 A1 WO2015165411 A1 WO 2015165411A1 CN 2015077877 W CN2015077877 W CN 2015077877W WO 2015165411 A1 WO2015165411 A1 WO 2015165411A1
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silicon
layer
rich oxide
dielectric layer
insulator device
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English (en)
French (fr)
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王智勇
王德进
马晶晶
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无锡华润上华半导体有限公司
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Priority to US15/119,289 priority Critical patent/US10276430B2/en
Publication of WO2015165411A1 publication Critical patent/WO2015165411A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device, and more particularly to an inter-metal dielectric layer structure of a silicon-on-insulator device, a device having the inter-metal dielectric layer structure, and a method of manufacturing an inter-metal dielectric layer of a silicon-on-insulator device .
  • the traditional 0.18-micron logic 1.8V/3.3V silicon-on-insulator (SOI) process typically uses a 0.18-micron logic process.
  • SOI silicon-on-insulator
  • the inventors have found through experiments that a large amount of movable ions are generated in the latter process. These movable ions are conducted along the metal lead, the via, and the metal film, and are concentrated at the Si-SiO 2 interface. Polysilicon (Poly) edge, etc., affecting the interface state. For the ordinary bulk silicon process, these movable ions can be vented from the substrate, so the performance of the aggregation is not obvious.
  • An inter-metal dielectric layer structure of a silicon-on-insulator device comprising a silicon-rich oxide layer covering a metal interconnect, a fluorosilicate glass layer on a silicon-rich oxide layer, and an undoped silicate on the fluorosilicate glass layer
  • the glass layer, the silicon-rich oxide layer has a thickness of 700 angstroms ⁇ 10%.
  • the silicon-rich oxide layer is an in-situ silicon-rich oxide layer.
  • the undoped silicate glass layer has a thickness of 2000 angstroms ⁇ 10%.
  • a silicon nitride layer disposed between the metal interconnect and the fluorosilicate glass layer is further included.
  • a silicon-on-insulator device comprising a substrate, a buried oxide layer on the substrate, a well region on the buried oxide layer, a source and drain structure in the well region, a gate on the well region, and an interlayer dielectric layer, a first inter-metal dielectric layer on the interlayer dielectric layer and a pad layer on the surface of the device, wherein the first inter-metal dielectric layer has the inter-metal dielectric layer structure according to any one of claims 1 to 4.
  • the interlayer dielectric layer comprises a layer of silicon nitride.
  • a method of fabricating an intermetal dielectric layer of a silicon-on-insulator device comprising the steps of: forming a metal interconnection; depositing a silicon-rich oxide and a fluorosilicate glass to cover the metal interconnection; and plasma-enhanced chemical vapor deposition a fluorine-rich silica glass; chemical mechanical polishing to remove excess fluorosilicate glass to form a silicon-rich oxide layer and a fluorosilicate glass layer having a thickness of 700 angstroms ⁇ 10%; using plasma-enhanced chemistry Vapor deposition forms an undoped silicate glass layer on the fluorosilicate glass layer.
  • the silicon-rich oxide layer is an in-situ silicon-rich oxide layer, and the step of depositing the silicon-rich oxide and fluorosilicate glass is performed in the same deposition chamber.
  • the undoped silicate glass layer has a thickness of 2000 angstroms ⁇ 10%.
  • the step of forming a metal interconnection and the step of depositing a silicon-rich oxide and fluorosilicate glass further includes the step of depositing a silicon nitride layer.
  • the thick silicon-rich oxide layer can trap the movable ions on the unsaturated bond, so that It is difficult for the mobile ions to pass through the silicon-rich oxide layer to achieve the purpose of blocking the movable ions.
  • the device performs well in gate oxide integrity (GOI) evaluation, avoiding the damage of the device caused by the accumulation of movable ions at the interface.
  • GOI gate oxide integrity
  • FIG. 1 is a schematic cross-sectional view of a silicon-on-insulator device in an embodiment
  • FIG. 2 is a flow chart showing a method of fabricating an intermetal dielectric layer of a silicon-on-insulator device in an embodiment
  • Figure 3 is a schematic illustration of the movable ions being blocked by a silicon-rich oxide layer.
  • FIG. 1 is a schematic cross-sectional view of a silicon-on-insulator (SOI) device including a substrate 10, a buried oxide layer 20 on the substrate 10, a well region 32 on the buried oxide layer 20, and a source within the well region 32.
  • a (drain) structure 34 a gate oxide layer (not shown in FIG. 1) on the well region 32, a gate 42 and an interlayer dielectric (ILD) layer 40, and a first intermetal dielectric layer on the interlayer dielectric layer 40. 50 and a pad (PAD) layer 70 on the surface of the device.
  • the interlayer dielectric layer 40 includes a layer of silicon nitride.
  • the first inter-metal dielectric layer 50 adopts a novel IMD structure.
  • the first inter-metal dielectric layer 50 includes a silicon rich oxide (silicon rich oxide) covering the metal interconnect 52 of the layer.
  • SRO silicon rich oxide
  • FSG fluorosilicate glass
  • USG undoped silicate glass
  • the salt glass layers are drawn together in Figure 1.
  • the function of the silicon-rich oxide layer 54 is to block the movable ions, which should be sufficiently thick for this purpose, in the present embodiment having a thickness of 700 angstroms ⁇ 10%, preferably 700 angstroms.
  • the inventors have found through experiments that the silicon-rich oxide layer 54 itself is rich in silicon unsaturated bonds, and the movable ions generated in the latter process are thicker when moving through the structure of the silicon-rich oxide layer 54 downward.
  • the silicon-rich oxide layer 54 can trap the movable ions on the unsaturated bonds, making it difficult for the movable ions to pass through the silicon-rich oxide layer 54, as shown in FIG. 3, for the purpose of blocking the movable ions.
  • the device performs well in gate oxide integrity (GOI) evaluation, avoiding the damage of the device caused by the accumulation of movable ions at the interface.
  • GOI gate oxide integrity
  • the silicon-rich oxide layer 54 is an in-situ silicon-rich oxide layer, i.e., the step of depositing the silicon-rich oxide and fluorosilicate glass is performed in the same deposition chamber. Compared with the use of two machines to deposit silicon-rich oxide and fluorosilicate glass solutions, it is possible to eliminate the time of depositing and unloading, product transfer and online waiting for two times to improve production efficiency.
  • the thickness of the undoped silicate glass layer is 2000 angstroms ⁇ 10%, preferably 2000 angstroms.
  • the first inter-metal dielectric layer 50 further includes a layer of silicon nitride formed between the metal interconnect 52 and the fluorosilicate glass layer. This layer of silicon nitride can further enhance the blocking effect on the movable ions.
  • the invention also provides a method for manufacturing an inter-metal dielectric layer of a silicon-on-insulator device, as shown in FIG. 2, comprising the following steps:
  • Metal interconnects can be formed over the ILD by first depositing and then etching.
  • the step of depositing the silicon-rich oxide and fluorosilicate glass is carried out in the same deposition chamber to form an in-situ silicon-rich oxide layer.
  • this step deposits 8000 angstroms thick fluorosilicate glass.
  • a layer of fluorosilicate glass is deposited by a plasma enhanced chemical vapor deposition (PECVD) process.
  • PECVD plasma enhanced chemical vapor deposition
  • the fluorosilicate glass deposited in steps S220 and S230 was polished by CMP to achieve a planarization effect, which in this embodiment was polished to a remaining 6500 angstrom thick fluorosilicate glass. After the polishing is completed, a silicon-rich oxide layer and a fluorosilicate glass layer are obtained.
  • the deposited undoped silicate glass (USG) layer has a thickness of 2000 angstroms.
  • the invention ensures high pressure/low pressure region, field edge (Field In the case where the test structure GOI performs well, the GOI of the poly edge is significantly improved, especially for the P poly edge.
  • the step of depositing a silicon nitride film is further included between steps S210 and S220.
  • This layer of silicon nitride can further enhance the blocking effect on the movable ions.

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Abstract

提供一种绝缘体上硅器件的金属间介质层结构，包括覆盖金属互连的富硅氧化物层（54），富硅氧化物层上的氟硅玻璃层、及氟硅玻璃层上的非掺杂硅酸盐玻璃层，所述富硅氧化物层（54）的厚度为700埃±10％，厚度较大的富硅氧化物层可以将可动离子俘获在不饱和键上，使得可动离子难以穿过富硅氧化物层，实现了阻挡可动离子的目的。在栅氧化层完整性评估中有良好的表现，避免了可动离子在界面处的聚集造成器件的损坏。还提供了一种绝缘体上硅器件，以及一种绝缘体上硅器件的金属间介质层的制造方法。

Description

绝缘体上硅器件及其金属间介质层结构和制造方法
【技术领域】
本发明涉及半导体器件，特别是涉及一种绝缘体上硅器件的金属间介质层结构，一种具有该金属间介质层结构的器件，还涉及一种绝缘体上硅器件的金属间介质层的制造方法。
【背景技术】
传统的0.18微米逻辑1.8V/3.3V绝缘体上硅（SOI）工艺，后段工艺通常采用0.18微米逻辑工艺。但发明人经实验研究发现，该后段工艺会产生大量可动离子，这些可动离子沿金属引线、通孔（Via）、及金属之间的薄膜传导下去，聚集在Si-SiO2界面、多晶硅（Poly）边缘等处，影响界面态。对于普通体硅工艺，这些可动离子可以从衬底泄放出去，因此该聚集的表现并不明显。但对于SOI工艺，由于埋层氧化的存在，可动离子没法泄放出去，因此对器件的影响较明显，容易造成栅氧（GOX）、结（junction）或多晶硅边缘（Poly edge）的缺陷。在栅氧化层完整性（GOI）评估中，出现GOI fail。
【发明内容】
基于此，为了解决器件在栅氧化层完整性评估中失效的问题，有必要提供一种新型的绝缘体上硅器件的金属间介质层结构。
一种绝缘体上硅器件的金属间介质层结构，包括覆盖金属互连的富硅氧化物层、富硅氧化物层上的氟硅玻璃层、及氟硅玻璃层上的非掺杂硅酸盐玻璃层，所述富硅氧化物层的厚度为700埃±10%。
在其中一个实施例中，所述富硅氧化物层为原位富硅氧化物层。
在其中一个实施例中，所述非掺杂硅酸盐玻璃层的厚度为2000埃±10%。
在其中一个实施例中，还包括设于所述金属互连和氟硅玻璃层之间的氮化硅层。
还有必要提供一种绝缘体上硅器件。
一种绝缘体上硅器件，包括衬底、衬底上的埋氧层、埋氧层上的阱区、阱区内的源极和漏极结构、阱区上的栅极和层间介质层、层间介质层上的第一金属间介质层以及器件表面的焊盘层，所述第一金属间介质层的结构为权利要求1-4中任意一项所述的金属间介质层结构。
在其中一个实施例中，所述层间介质层包括一层氮化硅。
还有必要提供一种绝缘体上硅器件的金属间介质层的制造方法。
一种绝缘体上硅器件的金属间介质层的制造方法，包括下列步骤：形成金属互连线；淀积富硅氧化物和氟硅玻璃，覆盖所述金属互连线；等离子增强型化学气相淀积氟硅玻璃；进行化学机械抛光，去除多余的氟硅玻璃后形成富硅氧化物层和氟硅玻璃层，所述富硅氧化物层的厚度为700埃±10%；采用等离子增强型化学气相淀积在所述氟硅玻璃层上形成非掺杂硅酸盐玻璃层。
在其中一个实施例中，所述富硅氧化物层为原位富硅氧化物层，所述淀积富硅氧化物和氟硅玻璃步骤是在同一淀积腔体中进行。
在其中一个实施例中，所述非掺杂硅酸盐玻璃层的厚度为2000埃±10%。
在其中一个实施例中，所述形成金属互连线步骤和淀积富硅氧化物和氟硅玻璃步骤之间，还包括淀积形成氮化硅层的步骤。
上述SOI器件，后段工艺中产生的可动离子在经过富硅氧化物层向下方的结构运动时，厚度较大的富硅氧化物层可以将可动离子俘获在不饱和键上，使得可动离子难以穿过富硅氧化物层，实现了阻挡可动离子的目的。从而器件在栅氧化层完整性（GOI）评估中有良好的表现，避免了可动离子在界面处的聚集造成器件的损坏。
【附图说明】
图1是一实施例中绝缘体上硅器件的剖面示意图；
图2是一实施例中绝缘体上硅器件的金属间介质层的制造方法的流程图；
图3是可动离子被富硅氧化物层阻挡的示意图。
【具体实施方式】
为使本发明的目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
图1是一实施例中绝缘体上硅（SOI）器件的剖面示意图，器件包括衬底10，衬底10上的埋氧层20，埋氧层20上的阱区32，阱区32内的源极（漏极）结构34，阱区32上的栅氧层（图1中未示）、栅极42和层间介质（ILD）层40，层间介质层40上的第一金属间介质层50以及器件表面的焊盘（PAD）层70。在本实施例中，层间介质层40中包括一层氮化硅。第一金属间介质层50和焊盘层70之间还可以有一层或多层第二金属间介质层60。其中，第一金属间介质层50采用了新型的IMD结构。
具体的，第一金属间介质层50包括覆盖该层金属互连52的富硅氧化物（silicon rich oxide, SRO）层54、富硅氧化物层54上的氟硅玻璃（FSG）层及氟硅玻璃层上的非掺杂硅酸盐玻璃（USG）层，其中氟硅玻璃层和非掺杂硅酸盐玻璃层在图1中是绘制在一起的。富硅氧化物层54的作用是阻挡可动离子，为了达到该目的其应该足够厚，在本实施例中的厚度为700埃±10%，优选为700埃。
发明人经实验研究发现，富硅氧化物层54本身富含硅不饱和键，在后段工艺中产生的可动离子在经过富硅氧化物层54向下方的结构运动时，厚度较大的富硅氧化物层54可以将可动离子俘获在不饱和键上，使得可动离子难以穿过富硅氧化物层54，如图3所示，实现了阻挡可动离子的目的。从而器件在栅氧化层完整性（GOI）评估中有良好的表现，避免了可动离子在界面处的聚集造成器件的损坏。
在本实施例中，富硅氧化物层54为原位（In-situ）富硅氧化物层，即淀积富硅氧化物和氟硅玻璃步骤是在同一淀积腔体中进行的。相比使用两台机台分别淀积富硅氧化物和氟硅玻璃方案，可以省去两次淀积中间的上下货、产品传送和在线等待的时间，提高生产效率。
在本实施例中，非掺杂硅酸盐玻璃层的厚度为2000埃±10%，优选为2000埃。
在其中一个实施例中，第一金属间介质层50还包括一层氮化硅，其形成于金属互连52与氟硅玻璃层之间。该层氮化硅可以进一步增强对可动离子的阻断效果。
本发明还提供一种绝缘体上硅器件的金属间介质层的制造方法，如图2所示，包括下列步骤：
S210，形成金属互连线。
可以用先淀积再刻蚀的方式在ILD上方形成金属互连线。
S220，淀积富硅氧化物和氟硅玻璃，覆盖金属互连线。
在本实施例中，淀积富硅氧化物和氟硅玻璃步骤是在同一淀积腔体中进行的，从而形成原位（In-situ）富硅氧化物层。在本实施例中，本步骤淀积8000埃厚的氟硅玻璃。
S230，等离子增强型化学气相淀积氟硅玻璃。
步骤S220完成后，再使用等离子增强型化学气相淀积（PECVD）的工艺淀积一层氟硅玻璃。在本实施例中，本步骤淀积11500埃厚的氟硅玻璃。
S240，进行化学机械抛光。
通过CMP将步骤S220和S230中淀积的氟硅玻璃抛光以达到平坦化的效果，在本实施例中是抛光至剩余6500埃厚的氟硅玻璃。抛光完成后得到富硅氧化物层和氟硅玻璃层。
S250，采用等离子增强型化学气相淀积在氟硅玻璃层上形成非掺杂硅酸盐玻璃层。
在本实施例中，淀积的非掺杂硅酸盐玻璃（USG）层厚度为2000埃。
本发明在保证高压/低压区域，场区边缘（Field edge）的测试结构GOI表现良好的情况下，对多晶硅边缘（Poly edge）的GOI有明显改善，特别是对P型多晶硅边缘（P Poly edge）。
在其中一个实施例中，步骤S210和S220之间还包括淀积氮化硅薄膜的步骤。该层氮化硅可以进一步增强对可动离子的阻断效果。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种绝缘体上硅器件的金属间介质层结构，其特征在于，包括覆盖金属互连的富硅氧化物层、富硅氧化物层上的氟硅玻璃层、及氟硅玻璃层上的非掺杂硅酸盐玻璃层，所述富硅氧化物层的厚度为700埃±10%。
  2. 根据权利要求1所述的绝缘体上硅器件的金属间介质层结构，其特征在于，所述富硅氧化物层为原位富硅氧化物层。
  3. 根据权利要求1所述的绝缘体上硅器件的金属间介质层结构，其特征在于，所述非掺杂硅酸盐玻璃层的厚度为2000埃±10%。
  4. 根据权利要求1所述的绝缘体上硅器件的金属间介质层结构，其特征在于，还包括设于所述金属互连和氟硅玻璃层之间的氮化硅层。
  5. 一种绝缘体上硅器件，包括衬底、衬底上的埋氧层、埋氧层上的阱区、阱区内的源极和漏极结构、阱区上的栅极和层间介质层、层间介质层上的第一金属间介质层以及器件表面的焊盘层，其特征在于，所述第一金属间介质层的结构为权利要求1-4中任意一项所述的金属间介质层结构。
  6. 根据权利要求5所述的绝缘体上硅器件，其特征在于，所述层间介质层包括一层氮化硅。
  7. 一种绝缘体上硅器件的金属间介质层的制造方法，包括下列步骤：
    形成金属互连线；
    淀积富硅氧化物和氟硅玻璃，覆盖所述金属互连线；
    等离子增强型化学气相淀积氟硅玻璃；
    进行化学机械抛光，去除多余的氟硅玻璃后形成富硅氧化物层和氟硅玻璃层，所述富硅氧化物层的厚度为700埃±10%；
    采用等离子增强型化学气相淀积在所述氟硅玻璃层上形成非掺杂硅酸盐玻璃层。
  8. 根据权利要求7所述的绝缘体上硅器件的金属间介质层的制造方法，其特征在于，所述富硅氧化物层为原位富硅氧化物层，所述淀积富硅氧化物和氟硅玻璃步骤是在同一淀积腔体中进行。
  9. 根据权利要求7所述的绝缘体上硅器件的金属间介质层的制造方法，其特征在于，所述非掺杂硅酸盐玻璃层的厚度为2000埃±10%。
  10. 根据权利要求7所述的绝缘体上硅器件的金属间介质层的制造方法，其特征在于，所述形成金属互连线步骤和淀积富硅氧化物和氟硅玻璃步骤之间，还包括淀积形成氮化硅层的步骤。
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Publication number Priority date Publication date Assignee Title
CN106483758B (zh) 2015-09-02 2019-08-20 无锡华润上华科技有限公司 光学邻近效应修正方法和系统
CN106653842B (zh) 2015-10-28 2019-05-17 无锡华润上华科技有限公司 一种具有静电释放保护结构的半导体器件
CN106816468B (zh) 2015-11-30 2020-07-10 无锡华润上华科技有限公司 具有resurf结构的横向扩散金属氧化物半导体场效应管
CN107465983B (zh) 2016-06-03 2021-06-04 无锡华润上华科技有限公司 Mems麦克风及其制备方法
CN111725180A (zh) * 2020-07-23 2020-09-29 华虹半导体(无锡)有限公司 用于功率mos器件的层间介质层结构及其制作方法
CN112635329A (zh) * 2020-12-14 2021-04-09 华虹半导体(无锡)有限公司 Dmos器件的层间介质层及其制作方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054839A (zh) * 2009-10-28 2011-05-11 无锡华润上华半导体有限公司 一种mos场效应晶体管结构及其制备方法
CN102820256A (zh) * 2011-06-08 2012-12-12 无锡华润上华半导体有限公司 一种金属间介质层的制备方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8133783B2 (en) * 2007-10-26 2012-03-13 Hvvi Semiconductors, Inc. Semiconductor device having different structures formed simultaneously
US7919801B2 (en) * 2007-10-26 2011-04-05 Hvvi Semiconductors, Inc. RF power transistor structure and a method of forming the same
US8125044B2 (en) * 2007-10-26 2012-02-28 Hvvi Semiconductors, Inc. Semiconductor structure having a unidirectional and a bidirectional device and method of manufacture
CN101211800A (zh) * 2007-12-25 2008-07-02 上海集成电路研发中心有限公司 防止水汽和可动离子进入内部电路的方法及相应压焊窗口
JP2011119330A (ja) * 2009-12-01 2011-06-16 Renesas Electronics Corp 半導体集積回路装置の製造方法
US8828787B2 (en) * 2010-09-15 2014-09-09 Precursor Energetics, Inc. Inks with alkali metals for thin film solar cell processes
CN102097441B (zh) * 2010-12-17 2013-01-02 电子科技大学 用于等离子显示屏驱动芯片的soi器件
US8680535B2 (en) * 2011-12-23 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. High electron mobility transistor structure with improved breakdown voltage performance
CN102623491B (zh) * 2012-04-26 2014-04-16 杭州士兰集成电路有限公司 Bipolar低压工艺中耐高压器件及其制造方法
CN103633128B (zh) * 2013-12-10 2016-07-20 杭州士兰集成电路有限公司 双极npn晶体管及其制造方法
US20150206794A1 (en) * 2014-01-17 2015-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Removing Micro Scratches In Chemical Mechanical Polishing Processes
US9882125B2 (en) * 2015-02-11 2018-01-30 Globalfoundries Singapore Pte. Ltd. Selector device for a non-volatile memory cell
US9780207B2 (en) * 2015-12-30 2017-10-03 Globalfoundries Singapore Pte. Ltd. Self-aligned high voltage LDMOS

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054839A (zh) * 2009-10-28 2011-05-11 无锡华润上华半导体有限公司 一种mos场效应晶体管结构及其制备方法
CN102820256A (zh) * 2011-06-08 2012-12-12 无锡华润上华半导体有限公司 一种金属间介质层的制备方法

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