WO2015161640A1 - 一种时间数字转换器、频率跟踪装置及方法 - Google Patents
一种时间数字转换器、频率跟踪装置及方法 Download PDFInfo
- Publication number
- WO2015161640A1 WO2015161640A1 PCT/CN2014/090265 CN2014090265W WO2015161640A1 WO 2015161640 A1 WO2015161640 A1 WO 2015161640A1 CN 2014090265 W CN2014090265 W CN 2014090265W WO 2015161640 A1 WO2015161640 A1 WO 2015161640A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- phase
- clock signal
- frequency
- lock module
- signal
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000005070 sampling Methods 0.000 claims abstract description 116
- 230000001934 delay Effects 0.000 claims description 8
- 230000008859 change Effects 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 11
- 230000001360 synchronised effect Effects 0.000 description 9
- 239000000872 buffer Substances 0.000 description 7
- 230000003111 delayed effect Effects 0.000 description 6
- 238000001514 detection method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 238000001914 filtration Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
Definitions
- the present invention relates to the field of electronic technologies, and in particular, to a time-to-digital converter, a frequency tracking device, and a method.
- the transmitting end Before transmitting the data, the transmitting end first sends a series of synchronous clock pulses to the receiving end, and the receiving end locks the receiving frequency of the receiving end through the frequency tracking system according to the clock frequency and timing, so as to always keep with the transmitting end during the process of receiving data. Synchronize.
- a dual-loop frequency tracking system is generally used to perform frequency tracking on a synchronous clock sent by a transmitting end.
- FIG. 1 a structural diagram of a dual-loop frequency tracking system is shown.
- the first clock signal of the numerically controlled oscillator enters the first phase locked loop.
- the first time digitizer After passing through the first time digitizer, the first time digitizer generates a phase signal according to the input reference clock signal, and passes the first reference.
- the phase detector and the first filter adjust a frequency of the first clock signal output by the numerically controlled oscillator such that the first clock signal is equal to the frequency of the second clock signal received by the receiving end.
- the error caused by the first phase-locked loop is large, so it is necessary to add a second loop outside the first phase-locked loop to track the second clock signal.
- the phase signal is generated according to the second clock signal by the second time-to-digital converter, and the numerically controlled oscillator is adjusted by the second phase detector and the second filter.
- the phase of the output first clock signal is such that the phase of the first clock signal is equal to the phase of the second clock signal, reducing the error.
- An existing time-to-digital converter includes an array of a plurality of buffers and an array of a plurality of flip-flops.
- the clock outputted by the numerically controlled oscillator is passed backward through each buffer, and the output of each buffer is used as The phase detection point of the trigger array. Since the clock frequency of the numerically controlled oscillator output is high, in order to achieve frequency coverage, the number of buffers required is large, corresponding to the required trigger The number is also large, so using two time-to-digital converters increases the energy consumed by the system. In addition, due to the influence of the number of buffers and flip-flops, the occupied area of the system is correspondingly increased, which increases the manufacturing cost and increases the complexity of the system design.
- Embodiments of the present invention provide a time-to-digital converter, a frequency tracking apparatus, and a method, which can achieve the effect of double-loop frequency tracking by using a time-to-digital converter, and reduce the occupied area of the double-loop frequency tracking system.
- a first aspect of the embodiments of the present invention provides a time-to-digital converter, including a delay unit, a first sampling unit, and a second sampling unit, where:
- the delay unit is connected to the first sampling unit, and configured to receive a first clock signal output by the first phase lock module, delay the first clock signal, and output the first clock signal to the first sampling unit;
- the first sampling unit is configured to sample the first clock signal output by the delay unit by using a reference clock signal, generate a first phase signal, and send the first phase signal to the first phase lock phase a module, wherein the first phase lock module adjusts a frequency of the first clock signal according to the first phase signal, and outputs the frequency modulated first clock signal to the delay unit;
- the delay unit is further connected to the second sampling unit, and configured to receive the frequency-modulated first clock signal output by the first phase-locked module, and delay the frequency-modulated first clock signal, Output to the second sampling unit;
- the second sampling unit is configured to sample the frequency-modulated first clock signal output by the delay unit by using a second clock signal, generate a second phase signal, and pass the second phase signal to the second lock
- the phase module is sent to the first phase lock module to cause the first phase lock module to adjust a phase of the first clock signal according to the second phase signal.
- the delay unit is sequentially connected by multiple delay elements
- the first sampling unit and the The second sampling unit is sequentially connected by a plurality of flip-flops, and an output end of each delay element is connected to an input end of the next delay element, a phase acquisition end of the trigger corresponding to the delay element in the first sampling unit, and a phase of a flip-flop corresponding to the delay element in the second sampling unit Acquisition end.
- the reference clock signal and The second clock signal has the same frequency.
- a second aspect of the embodiments of the present invention provides a frequency tracking apparatus, including a first phase lock module, a second phase lock module, and any one of the first aspect of the embodiment of the present invention to the second aspect of the first aspect of the embodiment of the present invention.
- a time-to-digital converter in a possible implementation wherein:
- the first end of the first phase lock module is connected to the delay unit, and is configured to output a first clock signal to the delay unit;
- the second end of the first phase lock module is connected to one end of the second phase lock module for receiving a second clock signal output by the second phase lock module;
- the third end of the first phase locking module is connected to the first sampling unit, and configured to receive a first phase signal output by the first sampling unit, and according to the first phase signal and the second clock a signal, the frequency of the first clock signal is adjusted to be the same as the frequency of the second clock signal, and the first clock signal of the first phase lock module is output to the delay unit;
- the other end of the second phase locking module is connected to one end of the second sampling unit, and is configured to receive a second phase signal output by the second sampling unit, to control the first phase locking module according to the first And adjusting the phase of the frequency-modulated first clock signal to be the same as the phase of the second clock signal, and passing the phase-adjusted first clock signal through the first A first end of the phase lock module is output to the delay unit.
- the device further includes a synchronizer, where:
- One end of the synchronizer is connected to the second clock signal, and the other end of the synchronizer is connected to the other end of the second sampling unit, for changing the timing of the second clock signal, and after outputting the change timing
- the second clock signal is sent to the second sampling unit.
- the first phase locking module includes a first phase detector, a first filter, and a numerical control An oscillator and a divider, where:
- the first phase detector includes a first input end, a second input end, and an output end;
- the first filter includes an input end and an output end
- the numerically controlled oscillator includes an input end and an output end;
- the frequency divider includes an input end and an output end
- a first input end of the first phase detector is a second end of the first phase lock module, and a second input end of the first phase detector is a third end of the first phase lock module,
- An output end of the first phase detector is connected to an input end of the first filter, and the first phase detector is configured to calculate the first clock signal according to the first phase signal and the second clock signal a frequency error with the second clock signal;
- An output end of the first filter is connected to an input end of the numerically controlled oscillator, and the first filter is configured to control the numerically controlled oscillator to adjust the first clock signal according to the frequency error;
- An output end of the numerically controlled oscillator is connected to an input end of the frequency divider, and the numerical control oscillator is configured to adjust a frequency of the first clock signal to be compared with the second clock signal according to the frequency error The same frequency;
- the output end of the frequency divider is a first end of the first phase lock module, and the frequency divider is configured to divide the frequency modulated first clock signal.
- the second phase lock The module includes a second phase detector and a second filter, wherein:
- the second phase detector includes an input end and an output end
- the second filter includes an input end and an output end
- the input end of the second phase detector is the other end of the second phase lock module, and the output end of the second phase detector is connected to the input end of the second filter, the second phase detector And configured to calculate a phase error of the frequency-modulated first clock signal and the second clock signal according to the second phase signal and the input second clock signal;
- An output end of the second filter is one end of the second phase lock module, and the second filter is configured to control the numerical control oscillator according to the phase error, so that the numerical control oscillator is according to the phase
- the error adjusts the phase of the frequency-modulated first clock signal to be the same as the phase of the second clock signal.
- a third aspect of the embodiments of the present invention provides a frequency tracking method, including:
- the delay unit receives the first clock signal output by the first phase lock module, delays the first clock signal, and outputs the first clock signal to the first sampling unit;
- the first sampling unit samples the first clock signal output by the delay unit by using a reference clock signal, generates a first phase signal, and sends the first phase signal to the first phase lock module, so that The first phase lock module adjusts a frequency of the first clock signal according to the first phase signal, and outputs the frequency modulated first clock signal to the delay unit;
- the delay unit receives the frequency-modulated first clock signal output by the first phase-locked module, delays the frequency-modulated first clock signal, and outputs the first clock signal to the second sampling unit;
- the second sampling unit samples the frequency-modulated first clock signal output by the delay unit by using a second clock signal to generate a second phase signal, and passes the second phase signal to the second phase-locked module Sending to the first phase lock module, so that the first phase lock module adjusts a phase of the first clock signal according to the second phase signal.
- the reference clock signal and the second clock signal have the same frequency.
- the second clock signal received by the second sampling unit is changed by a synchronizer. After the second clock signal.
- the first phase lock phase Adjusting, by the module, the frequency of the first clock signal according to the first phase signal includes:
- the first phase detector of the first phase lock module calculates a frequency error of the first clock signal and the second clock signal according to the first phase signal and the second clock signal;
- the first filter of the first phase lock module controls the numerically controlled oscillator of the first phase lock module to adjust the first clock signal according to the frequency error;
- the numerically controlled oscillator adjusts a frequency of the first clock signal to be the same as a frequency of the second clock signal according to the frequency error;
- the frequency divider of the first phase lock module divides the frequency modulated first clock signal.
- the first phase locking module adjusts the first according to the second phase signal
- the phase of the clock signal includes:
- the second phase detector of the second phase lock module calculates a phase error of the frequency modulated first clock signal and the second clock signal according to the second phase signal and the second clock signal;
- the second filter of the first phase lock module controls the numerically controlled oscillator according to the phase error, so that the numerically controlled oscillator adjusts the phase of the frequency modulated first clock signal according to the phase error to The phase is the same as the second clock signal.
- a sampling unit composed of a plurality of flip-flops can be added on the basis of the internal structure of the time-to-digital converter, and two time in the existing double-loop frequency tracking system can be realized by using a time-to-digital converter.
- the respective functions of the digitizers provide a completely new architecture for the dual-loop frequency tracking system, reducing system footprint and power consumption.
- FIG. 1 is a schematic structural view of a conventional double loop frequency tracking system
- FIG. 2 is a schematic structural diagram of an embodiment of a time-to-digital converter according to an embodiment of the present invention
- FIG. 3 is a partial block diagram showing an embodiment of a time-to-digital converter according to an embodiment of the present invention
- FIG. 4 is a schematic structural diagram of an embodiment of a frequency tracking apparatus according to an embodiment of the present invention.
- FIG. 5 is a schematic structural diagram of another embodiment of a frequency tracking apparatus according to an embodiment of the present invention.
- FIG. 6 is a schematic flowchart diagram of an embodiment of a frequency tracking method according to an embodiment of the present invention.
- Embodiments of the present invention provide a time-to-digital converter, a frequency tracking apparatus, and a method, which can achieve the effect of double-loop frequency tracking by using a time-to-digital converter, and reduce the occupied area of the double-loop frequency tracking system.
- FIG. 2 is a schematic structural diagram of an embodiment of a time-to-digital converter according to an embodiment of the present invention.
- the embodiment of the invention modifies the internal structure of the time-to-digital converter 1, and adds a new set of flip-flop arrays to realize the respective functions of the two time-to-digital converters in the existing dual-loop frequency tracking system.
- the delay element involved in the embodiments of the present invention may be any passive component designed to provide signal delay, such as a buffer, an inductor, a resistor, and a capacitor.
- the embodiment of the present invention is illustrated by a buffer.
- the time-to-digital converter 1 shown in FIG. 2 includes a delay unit 11, a first sampling unit 12, and a second sampling unit 13.
- the delay unit 11 is connected to the first sampling unit 12 for receiving the first clock signal output by the first phase lock module 2, delaying the first clock signal, and outputting to the first sampling unit 12.
- the first sampling unit 12 is configured to sample the first clock signal output by the delay unit 11 by using a reference clock signal, generate a first phase signal, and send the first phase signal to the first phase lock module 2 to make the first lock
- the phase module 2 adjusts the frequency of the first clock signal according to the first phase signal, and outputs the frequency-modulated first clock signal to the delay unit 11.
- the delay unit 11 is further connected to the second sampling unit 13 for receiving the frequency-modulated first clock signal output by the first phase-locked module 2, delaying the frequency-modulated first clock signal, and outputting to the second sampling unit 13 .
- the second sampling unit 13 is configured to sample the frequency-modulated first clock signal output by the delay unit 11 by using the second clock signal to generate a second phase signal, and send the second phase signal to the second phase-locking module 3
- a phase lock module 2 is configured to cause the first phase lock module 2 to adjust the phase of the first clock signal according to the second phase signal.
- the first clock signal is an input clock signal of the delay unit 11, and is generally a high frequency clock.
- the delay unit 11 delays the first clock signal output by the first phase lock module 2, and outputs it to the first sampling unit 12, and the first phase lock module 2 connected by the first sampling unit 12 will delay.
- the first clock signal is frequency-modulated, and the frequency-modulated first clock signal is fed back to the delay unit 11, and the delay unit 11 continues to delay and output the frequency-modulated first clock signal to the second.
- Sample unit 13 is an input clock signal of the delay unit 11, and is generally a high frequency clock.
- the delay unit 11 is sequentially connected by a plurality of delay elements, and the first sampling unit 12 and the second sampling unit 13 are sequentially connected by a plurality of triggers.
- the output of each delay element is connected to the input end of the next delay element, the phase acquisition end of the trigger corresponding to the delay element in the first sampling unit 12, and the phase of the trigger corresponding to the delay element in the second sampling unit 13 Acquisition end.
- the common node of the delay element and the connected trigger is a phase detection point.
- the reference clock signal has the same frequency as the second clock signal.
- the signal input end of each flip-flop is connected to a reference clock signal, wherein the frequency of the reference clock signal is the same as the frequency of the second clock signal.
- the input reference clock signal triggers the phase acquisition operation (as shown in FIG. 3, the reference clock signal uses the rising edge to trigger the phase acquisition operation)
- the phase acquisition end of each flip-flop performs the phase detection point of the corresponding delay element.
- Signal sampling output corresponding phase values Q(0) to Q(n-1) and latch, compose each phase value into a series of codes to output a first phase signal, and send the first phase signal to the first phase lock Module 2, so that the first phase lock module 2 adjusts the frequency of the first clock signal according to the first phase signal, and outputs the frequency-modulated first clock signal to the delay unit 11.
- phase values output by each of the flip-flops are converted by the encoder and form a string of codes, and the first phase signal is output.
- each flip-flop in the second sampling unit 13, the signal input end of each flip-flop is connected to the second clock signal. Similar to the working principle of the first sampling unit 12, when the input second clock signal triggers the phase acquisition operation, the phase acquisition end of each flip-flop performs signal sampling on the phase detection point of the corresponding delay element, that is, after the frequency modulation
- the first clock signal is sampled, and the corresponding phase values P(0) to P(n-1) are output and latched, and each phase value is composed into a series of coded output second phase signals, which are passed through the second phase lock module 3.
- the first phase lock module 2 is sent to the first phase lock module 2 to adjust the phase of the first clock signal according to the second phase signal, and finally synchronizes the first clock signal with the second clock signal.
- phase values output by each flip-flop are converted by an encoder and form a string of codes, and a second phase signal is output.
- a sampling unit composed of a plurality of flip-flops can be added to the internal structure of the time-to-digital converter by using a time-to-digital conversion
- the function of each of the two time-to-digital converters in the existing dual-loop frequency tracking system and the functions of each device in the loop of the dual-loop frequency tracking system are reduced, thereby reducing the system footprint and power consumption.
- FIG. 4 is a schematic structural diagram of an embodiment of a frequency tracking apparatus according to an embodiment of the present invention.
- a frequency tracking device provided by an embodiment of the present invention includes a first phase lock module 2, a second phase lock module 3, and a time to digital converter 1 as described in the embodiments of FIGS. 2 and 3. among them:
- the first end of the first phase lock module 2 is connected to the delay unit 11 for outputting a first clock signal to the delay unit 11.
- the second end of the first phase lock module 2 is connected to one end of the second phase lock module 3 for receiving the second clock signal output by the second phase lock module 3.
- the third end of the first phase locking module 2 is connected to the first sampling unit 12 for receiving the first phase signal output by the first sampling unit 12, and the first clock signal according to the first phase signal and the second clock signal.
- the frequency is adjusted to be the same as the frequency of the second clock signal, and the first clock signal after the frequency modulation is output to the delay unit 11 through the first end of the first phase lock module 2.
- the other end of the second phase locking module 3 is connected to one end of the second sampling unit 13 for receiving the second phase signal output by the second sampling unit 13 to control the first phase locking module 2 according to the second phase signal and the second
- the clock signal adjusts the phase of the frequency-modulated first clock signal to be the same as the phase of the second clock signal, and outputs the phase-adjusted first clock signal to the delay unit 11 through the first end of the first phase-locked module 2.
- the second phase lock module 3 outputs the input second clock signal to the second end of the first phase lock module 2, for which the first phase lock module 2 can identify the phase information of the second clock signal, and then The first phase lock module 2 generates a first clock signal according to the second clock signal and outputs the first clock signal to the delay unit 11 through the first end of the first phase lock module 2.
- phase information of the second clock signal can also be identified by the second phase lock module 3 and output to the first phase lock module 2.
- the first clock signal is sampled by the first sampling unit 12 to generate a first phase signal, and the first phase signal is input to the first phase lock module 2 Three ends.
- the first phase lock module 2 identifies the first phase signal, and adjusts the frequency of the first clock signal to the second clock signal according to the phase information of the first phase signal and the second clock signal. The number is the same frequency.
- the specific process of the first sampling unit 12 for generating the first phase signal is shown in FIG. 2 of the embodiment, and details are not described in this embodiment.
- the first phase lock module 2 adjusts the frequency of the first clock signal
- the first clock signal after the frequency modulation is output to the delay unit 11, and the first clock signal after the frequency modulation is sampled by the second sampling unit 13.
- the second phase lock module 3 identifies the second phase signal, and outputs the identified second phase signal to the second end of the first phase lock module 2, so that the first phase lock module 2 is based on the second phase signal and the second clock.
- the phase information of the signal adjusts the phase of the frequency-modulated first clock signal to be the same as the phase of the second clock signal.
- a sampling unit composed of a plurality of flip-flops can be added on the basis of the internal structure of the time-to-digital converter, so that two time-to-digital converters in the existing double-loop frequency tracking system can be realized.
- the function provides a completely new architecture for the dual-loop frequency tracking system, reducing system footprint and power consumption.
- FIG. 5 is a schematic structural diagram of another embodiment of a frequency tracking apparatus according to an embodiment of the present invention.
- a frequency tracking apparatus according to an embodiment of the present invention includes a first phase lock module 2, a second phase lock module 3, and a time-to-digital converter 1 as described in the embodiments of FIGS. 2 and 3.
- the first end of the first phase lock module 2 is connected to the delay unit 11 for outputting the first clock signal to the delay unit 11.
- the second end of the first phase lock module 2 is connected to one end of the second phase lock module 3 for receiving the second clock signal output by the second phase lock module 3.
- the third end of the first phase locking module 2 is connected to the first sampling unit 12 for receiving the first phase signal output by the first sampling unit 12, and the first clock signal according to the first phase signal and the second clock signal.
- the frequency is adjusted to be the same as the frequency of the second clock signal, and the first clock signal after the frequency modulation is output to the delay unit 11 through the first end of the first phase lock module 2.
- the other end of the second phase locking module 3 is connected to one end of the second sampling unit 13 for receiving the second phase signal output by the second sampling unit 13 to control the first phase locking module 2 according to the second phase signal and the second
- the clock signal adjusts the phase of the frequency-modulated first clock signal to be the same as the phase of the second clock signal, and outputs the phase-adjusted first clock signal to the delay unit 11 through the first end of the first phase-locked module 2.
- the device further includes a synchronizer 4, one end of the synchronizer 4 is connected to the second clock signal, and the other end of the synchronizer 4 is connected to the second sampling unit 13, for changing the timing of the second clock signal, and outputting the change timing
- the second clock signal is sent to the second sampling unit 13. Since the first clock signal obtained by the second sampling unit 13 from the delay unit 11 is a delayed clock signal, the synchronizer 4 is required to change the timing of the input second clock signal to match the delayed first clock signal to The first clock signal outputted by the subsequent first phase lock module 2 is synchronized with the second clock signal.
- the first phase lock module 2 includes a first phase detector 21, a first filter 22, a numerically controlled oscillator 23, and a frequency divider 24.
- the first phase detector 21 includes a first input end, a second input end, and an output end;
- the first filter 22 includes an input end and an output end;
- the numerically controlled oscillator 23 includes an input end and an output end; and
- the frequency divider 24 includes an input end And the output.
- the first input end of the first phase detector 21 is the second end of the first phase lock module 2, and the second input end of the first phase detector 21 is the third end of the first phase lock module 2,
- the output of the first phase detector 21 is connected to the input end of the first filter 22, and the first phase detector 21 is configured to calculate the frequency error of the first clock signal and the second clock signal according to the first phase signal and the second clock signal.
- the first phase detector 21 discriminates the phase information of the first phase signal and the second clock signal, compares the phase of the first clock signal with the second clock signal, and calculates a frequency error of the first clock signal and the second clock signal, And output the frequency error voltage.
- the output of the first filter 22 is connected to the input end of the numerically controlled oscillator 23, and the first filter 22 is configured to control the numerically controlled oscillator 23 to adjust the first clock signal according to the frequency error.
- the first filter 22 filters the frequency error voltage output from the first phase detector 21, forms a control voltage, and outputs it to the numerically controlled oscillator 23.
- the output of the numerically controlled oscillator 23 is connected to the input of the frequency divider 24, and the numerically controlled oscillator 23 is configured to adjust the frequency of the first clock signal to be the same as the frequency of the second clock signal according to the frequency error.
- the control voltage output from the first filter 22 acts on the numerically controlled oscillator 23 to pull the output oscillation frequency of the numerically controlled oscillator 23 (i.e., the frequency of the first clock signal) toward the frequency of the second clock signal.
- the frequencies of the two are equal, the loop of the first phase lock module 2 is locked, and the frequency of the output first clock signal remains the same as the frequency of the second clock signal.
- the output of the frequency divider 24 is the first end of the first phase lock module 2, and the frequency divider 24 is configured to divide the frequency-modulated first clock signal.
- the frequency divider 24 passes the frequency modulated first clock signal Performing frequency division, adjusting the correlation coefficient relationship, so that the divided first clock signal can match the relevant parameters of the reference clock input by the first sampling unit 12, so that the first sampling unit 12 can perform sampling.
- the phase information of the second clock signal can be identified by the second phase detector 31 of the second phase lock module 3 and then output to the first phase detector 21 through the second filter 32.
- the second phase lock module 3 includes a second phase detector 31 and a second filter 32.
- the second phase detector 31 includes an input end and an output end.
- the second filter 32 includes an input end and an output end.
- the input end of the second phase detector 31 is the other end of the second phase lock module 3, the output end of the second phase detector 31 is connected to the input end of the second filter 32, and the second phase detector 31 is connected. And configured to calculate a phase error of the frequency-modulated first clock signal and the second clock signal according to the second phase signal and the input second clock signal.
- the second phase detector 31 is identical in operation to the first phase detector 21 for identifying the phase information of the second phase signal and the second clock signal, and performing the phase of the frequency modulated first clock signal and the second clock signal. Comparing, calculating the phase error of the frequency-modulated first clock signal and the second clock signal, and outputting the phase error voltage.
- the output of the second filter 32 is one end of the second phase lock module 3, and the second filter 32 is configured to control the numerically controlled oscillator 23 according to the phase error, so that the numerically controlled oscillator 23 is frequency-modulated according to the phase error.
- the phase of the first clock signal is adjusted to be the same as the phase of the second clock signal.
- the second filter 32 forms a control voltage and acts on the numerically controlled oscillator 23 of the first phase lock module 2 to cause the first clock signal output by the numerically controlled oscillator 23.
- the phase is the same as the phase of the second clock signal, whereby the loop of the second phase lock module 3 is locked, and the output first clock signal is synchronized with the second clock signal.
- the working principle of the device in the embodiment of the present invention is as follows:
- the second clock signal is input to the first phase lock module 2 through the second phase lock module 3, and the first clock signal is oscillated by the numerically controlled oscillator 23. Since the numerically controlled oscillator 23 has a certain error, the first clock signal cannot be synchronized with the second clock signal, the numerically controlled oscillator 23 outputs the first clock signal to the delay unit 11 of the time-to-digital converter 1.
- the delay unit 11 is composed of a plurality of delay elements for delaying the first clock signal and sampling the first clock signal by the first sampling unit 12 to generate a first phase signal.
- the first sampling unit 12 outputs the first phase signal to the first phase detector 21, the first phase detector 21 discriminates the phase of the second clock signal and the first phase signal, and calculates the first clock signal and the second clock signal.
- Frequency error output frequency error voltage to the first filter 22, by the first After filtering by the filter 22, the numerically controlled oscillator 23 is controlled to adjust the frequency of the first clock signal until the frequency of the first clock signal is the same as the frequency of the second clock signal, and the loop of the first phase lock module 2 is locked.
- the first clock signal is again output to the delay unit 11 of the time-to-digital converter 1, and the frequency-modulated first clock signal is delayed by the delay unit 11 and passed through
- the second sampling unit 13 samples the frequency-modulated first clock signal to generate a second phase signal.
- the second sampling unit 13 outputs the second phase signal to the second phase detector 31, the second phase detector 31 discriminates the phase of the second clock signal and the second phase signal, and calculates the first clock signal after the frequency modulation and the second The phase error of the clock signal outputs a phase error voltage to the second filter 32.
- the numerical control oscillator 23 is controlled to adjust the phase of the first clock signal until the phase of the first clock signal and the second clock signal.
- the phases are the same, the loop of the second phase lock module 3 is locked, and finally the first clock signal is synchronized with the second clock signal.
- the functions of the two time-to-digital converters in the existing dual-loop frequency tracking system and the functions of the respective devices in the loop of the dual-loop frequency tracking system can be realized by using a time-to-digital converter.
- FIG. 6 is a schematic flowchart diagram of an embodiment of a frequency tracking method according to an embodiment of the present invention.
- the various devices involved in the method illustrated in FIG. 6 are the devices described in the implementation of FIGS. 2 through 5.
- a frequency tracking method according to an embodiment of the present invention may include the following steps:
- the delay unit receives the first clock signal output by the first phase lock module, delays the first clock signal, and outputs the first clock signal to the first sampling unit.
- the first sampling unit samples the first clock signal output by the delay unit by using a reference clock signal, generates a first phase signal, and sends the first phase signal to the first phase lock module, so that the first phase lock module is configured according to The first phase signal adjusts the frequency of the first clock signal, and outputs the frequency-modulated first clock signal to the delay unit.
- the delay unit receives the frequency-modulated first clock signal output by the first phase-locked module, delays the frequency-modulated first clock signal, and outputs the first clock signal to the second sampling unit.
- the second sampling unit samples the frequency-modulated first clock signal output by the delay unit by using the second clock signal to generate a second phase signal, and sends the second phase signal to the second phase-locked module. And sending to the first phase lock module, so that the first phase lock module adjusts the phase of the first clock signal according to the second phase signal.
- the first phase lock module 2 outputs a first clock signal to the delay unit 11 of the time digitizer 1, and the delay unit 11 delays and outputs the first clock signal to the first sampling unit 12.
- the first sampling unit 12 samples the first clock signal according to the input reference clock signal, and outputs the first phase signal to the first phase lock module 2.
- the step of sampling the first clock signal by the first sampling unit 12 is shown in FIG. 2 of the embodiment, and details are not described in this embodiment.
- the reference clock signal has the same frequency as the second clock signal.
- the second clock signal received by the second sampling unit 13 is a second clock signal after the timing is changed by the synchronizer 4. Since the first clock signal obtained by the second sampling unit 13 from the delay unit 11 is a delayed clock signal, the synchronizer 4 is required to change the timing of the input second clock signal to match the delayed first clock signal to The first clock signal outputted by the subsequent first phase lock module 2 is synchronized with the second clock signal.
- the first phase detector 21 of the first phase lock module 2 calculates a frequency error of the first clock signal and the second clock signal according to the first phase signal and the second clock signal.
- the first phase detector 21 identifies the phase information of the second clock signal and the first phase signal, compares the phase of the first clock signal with the second clock signal, and calculates the first clock signal and The frequency error of the second clock signal and the output frequency error voltage.
- the first filter 22 of the first phase lock module 2 controls the numerically controlled oscillator 23 of the first phase lock module 2 to adjust the first clock signal according to the frequency error.
- the first filter 22 filters the frequency error voltage output from the first phase detector 21, a control voltage is formed and output to the numerically controlled oscillator 23.
- the numerically controlled oscillator 23 adjusts the frequency of the first clock signal to be the same as the frequency of the second clock signal according to the frequency error.
- the control voltage outputted by the first filter 22 acts on the numerically controlled oscillator 23, and the numerically controlled oscillator 23 pulls the oscillation frequency of its output (ie, the frequency of the first clock signal) toward the second clock signal.
- the oscillation frequency of its output ie, the frequency of the first clock signal
- Frequency when the frequencies of the two are equal, the loop of the first phase lock module 2 is locked, and the frequency of the output first clock signal is kept the same as the frequency of the second clock signal.
- the frequency divider 24 of the first phase lock module 2 divides the frequency modulated first clock signal.
- the frequency divider 24 divides the frequency-modulated first clock signal to adjust the correlation coefficient relationship, so that the divided first clock signal can be input with the reference of the first sampling unit 12.
- the correlation coefficients of the clocks are matched to facilitate sampling by the first sampling unit 12.
- the first phase lock module 2 outputs the frequency modulated first clock signal to the delay unit 11 of the time digitizer 1 .
- the delay unit 11 outputs the frequency-modulated first clock signal to the second sampling unit 13 of the time-to-digital converter 1.
- the second sampling unit 13 samples the frequency-modulated first clock signal according to the input second clock signal and outputs the second phase signal to the second phase-locked module 3.
- the step of sampling the second clock signal by the second sampling unit 13 is shown in FIG. 2 of the embodiment, and details are not described in this embodiment.
- the second phase detector 31 of the second phase lock module 3 calculates a phase error of the frequency modulated first clock signal and the second clock signal according to the second phase signal and the phase information of the second clock signal.
- the second filter 32 of the first phase lock module 2 controls the numerically controlled oscillator 23 according to the phase error, so that the numerically controlled oscillator 23 adjusts the phase of the frequency modulated first clock signal to the second clock according to the phase error.
- the phases of the signals are the same.
- the second phase detector 31 is configured to identify phase information of the second clock signal and the second phase signal, and compare the phase of the frequency modulated first clock signal with the second clock signal to calculate A phase error between a clock signal and a second clock signal, and a phase error voltage is output.
- the second filter 32 filters the phase error voltage outputted by the second phase detector 31 to form a control voltage and acts on the numerically controlled oscillator 23 of the first phase lock module 2 to make the numerical control oscillator
- the phase of the first clock signal output by the device 23 is the same as the phase of the second clock signal, whereby the loop of the second phase lock module 3 is locked, and the output first clock signal is synchronized with the second clock signal.
- the functions of the two time-to-digital converters in the existing dual-loop frequency tracking system and the functions of the respective devices in the loop of the dual-loop frequency tracking system can be realized by using a time-to-digital converter.
- the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, ie may be located A place, or it can be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment. Those of ordinary skill in the art can understand and implement without deliberate labor.
- Modules or units in the apparatus of the embodiments of the present invention may be combined, divided, and deleted according to actual needs.
- modules or modules of the embodiments of the present invention may be implemented by a general-purpose integrated circuit (such as a central processing unit CPU) or by an application specific integrated circuit (ASIC).
- a general-purpose integrated circuit such as a central processing unit CPU
- ASIC application specific integrated circuit
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
本发明实施例提供了一种时间数字转换器,包括延迟单元、第一采样单元以及第二采样单元,其中:延迟单元与第一采样单元相连,用于接收第一时钟信号,将第一时钟信号进行延迟;第一采样单元用于对第一时钟信号进行采样,生成第一相位信号,以使第一锁相模块调整第一时钟信号的频率;延迟单元还与第二采样单元相连,用于接收调频后的第一时钟信号,将调频后的第一时钟信号进行延迟;第二采样单元用于对调频后的第一时钟信号进行采样,生成第二相位信号,以使第一锁相模块调整第一时钟信号的相位。本发明实施例还公开了一种频率跟踪装置及方法。采用本发明,可通过使用一个时间数字转换器而达到双环频率跟踪的效果,减小双环频率跟踪系统的占用面积。
Description
本申请要求于2014年4月23日提交中国专利局、申请号为201410167138.0,发明名称为“一种时间数字转换器、频率跟踪装置及方法”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
本发明涉及电子技术领域,尤其涉及一种时间数字转换器、频率跟踪装置及方法。
在数据收发系统中,通常需要在接收端产生与发送端同步的时钟以保持通信。在发送数据之前,发送端先向接收端发送一串同步时钟脉冲,接收端按照这一时钟脉冲频率和时序通过频率跟踪系统锁定接收端的接收频率,以便在接收数据的过程中始终与发送端保持同步。
现有技术中通常采用双环频率跟踪系统对发送端发送的同步时钟进行频率跟踪,如图1所示为双环频率跟踪系统的结构图。在图1中,数控振荡器的第一时钟信号进入第一锁相环,经过第一时间数字转换器后,由第一时间数字转换器根据输入的参考时钟信号产生相位信号,通过第一鉴相器以及第一滤波器调整数控振荡器输出的第一时钟信号的频率,使第一时钟信号与接收端接收的第二时钟信号的频率相等。由于第一锁相环多由模拟的方法实现,造成的误差较大,因此需要在第一锁相环外部添加第二个环路以跟踪第二时钟信号。第一时钟信号进入第二锁相环的第二时间数字转换器之后,通过第二时间数字转换器根据第二时钟信号产生相位信号,通过第二鉴相器以及第二滤波器调整数控振荡器输出的第一时钟信号的相位,以使第一时钟信号的相位与第二时钟信号的相位相等,减小误差。
现有的时间数字转换器包括由多个缓冲器组成的阵列以及由多个触发器组成的阵列,由数控振荡器输出的时钟经过每一个缓冲器向后传递,每一个缓冲器的输出端作为触发器阵列的相位检测点。由于数控振荡器输出的时钟频率较高,为了达到频率覆盖,需要的缓冲器的数量较多,对应的,需要的触发器
的数量也多,因此,使用两个时间数字转换器会增加系统消耗的能量。此外,由于受到缓冲器与触发器的数量的影响,导致系统的占用面积也相应增大,增加了制造成本,同时也增加了系统设计的复杂性。
发明内容
本发明实施例提供一种时间数字转换器、频率跟踪装置及方法,可通过使用一个时间数字转换器而达到双环频率跟踪的效果,减小双环频率跟踪系统的占用面积。
本发明实施例第一方面提供一种时间数字转换器,包括延迟单元、第一采样单元以及第二采样单元,其中:
所述延迟单元与所述第一采样单元相连,用于接收第一锁相模块输出的第一时钟信号,将所述第一时钟信号进行延迟之后,输出至所述第一采样单元;
所述第一采样单元用于通过参考时钟信号对所述延迟单元输出的所述第一时钟信号进行采样,生成第一相位信号,并将所述第一相位信号发送给所述第一锁相模块,以使所述第一锁相模块根据所述第一相位信号调整所述第一时钟信号的频率,并将调频后的第一时钟信号输出至所述延迟单元;
所述延迟单元还与所述第二采样单元相连,用于接收所述第一锁相模块输出的所述调频后的第一时钟信号,将所述调频后的第一时钟信号进行延迟后,输出至所述第二采样单元;
所述第二采样单元用于通过第二时钟信号对所述延迟单元输出的所述调频后的第一时钟信号进行采样,生成第二相位信号,并将所述第二相位信号通过第二锁相模块发送给所述第一锁相模块,以使所述第一锁相模块根据所述第二相位信号调整所述第一时钟信号的相位。
结合本发明实施例第一方面的实现方式,在本发明实施例第一方面的第一种可能的实现方式中,所述延迟单元由多个延迟元件依次连接,所述第一采样单元以及所述第二采样单元由多个触发器依次连接,每个延迟元件的输出端接下一个延迟元件的输入端、所述第一采样单元中与所述延迟元件对应的触发器的相位采集端以及所述第二采样单元中与所述延迟元件对应的触发器的相位
采集端。
结合本发明实施例第一方面或第一方面的第一种中的任一种可能的实现方式,在本发明实施例第一方面的第二种可能的实现方式中,所述参考时钟信号与所述第二时钟信号的频率相同。
本发明实施例第二方面提供一种频率跟踪装置,包括第一锁相模块、第二锁相模块以及本发明实施例第一方面至本发明实施例第一方面的第二种中的任一种可能的实施方式中的时间数字转换器,其中:
所述第一锁相模块的第一端与所述延迟单元相连,用于向所述延迟单元输出第一时钟信号;
所述第一锁相模块的第二端与所述第二锁相模块的一端相连,用于接收所述第二锁相模块输出的第二时钟信号;
所述第一锁相模块的第三端与所述第一采样单元相连,用于接收所述第一采样单元输出的第一相位信号,并根据所述第一相位信号以及所述第二时钟信号,将所述第一时钟信号的频率调整至与所述第二时钟信号的频率相同,通过所述第一锁相模块的第一端输出调频后的第一时钟信号给所述延迟单元;
所述第二锁相模块的另一端与所述第二采样单元的一端相连,用于接收所述第二采样单元输出的第二相位信号,以控制所述第一锁相模块根据所述第二相位信号以及所述第二时钟信号,将所述调频后的第一时钟信号的相位调整至与所述第二时钟信号的相位相同,将调整相位后的第一时钟信号通过所述第一锁相模块的第一端输出给所述延迟单元。
结合本发明实施例第二方面的实现方式,在本发明实施例第二方面的第一种可能的实现方式中,所述装置还包括同步器,其中:
所述同步器的一端接所述第二时钟信号,所述同步器的另一端与所述第二采样单元的另一端相连,用于改变所述第二时钟信号的时序,以及输出改变时序后的第二时钟信号给所述第二采样单元。
结合本发明实施例第二方面的实现方式,在本发明实施例第二方面的第二种可能的实现方式中,所述第一锁相模块包括第一鉴相器、第一滤波器、数控振荡器以及分频器,其中:
所述第一鉴相器包括第一输入端、第二输入端以及输出端;
所述第一滤波器包括输入端以及输出端;
所述数控振荡器包括输入端以及输出端;
所述分频器包括输入端以及输出端;
所述第一鉴相器的第一输入端为所述第一锁相模块的第二端,所述第一鉴相器的第二输入端为所述第一锁相模块的第三端,所述第一鉴相器的输出端接所述第一滤波器的输入端,所述第一鉴相器用于根据所述第一相位信号以及所述第二时钟信号计算所述第一时钟信号与所述第二时钟信号的频率误差;
所述第一滤波器的输出端接所述数控振荡器的输入端,所述第一滤波器用于根据所述频率误差控制所述数控振荡器调整所述第一时钟信号;
所述数控振荡器的输出端与所述分频器的输入端相连,所述数控振荡器用于根据所述频率误差将所述第一时钟信号的频率调整至与所述第二时钟信号的频率相同;
所述分频器的输出端为所述第一锁相模块的第一端,所述分频器用于对所述调频后的第一时钟信号进行分频。
结合本发明实施例第二方面至第二方面的第二种中的任一种可能的实现方式,在本发明实施例第二方面的第三种可能的实现方式中,所述第二锁相模块包括第二鉴相器以及第二滤波器,其中:
所述第二鉴相器包括输入端以及输出端;
所述第二滤波器包括输入端以及输出端;
所述第二鉴相器的输入端为所述第二锁相模块的另一端,所述第二鉴相器的输出端与所述第二滤波器的输入端相连,所述第二鉴相器用于根据所述第二相位信号以及输入的所述第二时钟信号计算所述调频后的第一时钟信号与所述第二时钟信号的相位误差;
所述第二滤波器的输出端为所述第二锁相模块的一端,所述第二滤波器用于根据所述相位误差控制所述数控振荡器,以使所述数控振荡器根据所述相位误差将所述调频后的第一时钟信号的相位调整至与所述第二时钟信号的相位相同。
本发明实施例第三方面提供一种频率跟踪方法,包括:
延迟单元接收第一锁相模块输出的第一时钟信号,将所述第一时钟信号进行延迟之后,输出至第一采样单元;
所述第一采样单元通过参考时钟信号对所述延迟单元输出的所述第一时钟信号进行采样,生成第一相位信号,并将所述第一相位信号发送给第一锁相模块,以使所述第一锁相模块根据所述第一相位信号调整所述第一时钟信号的频率,并将调频后的第一时钟信号输出至所述延迟单元;
所述延迟单元接收所述第一锁相模块输出的所述调频后的第一时钟信号,将所述调频后的第一时钟信号进行延迟后,输出至第二采样单元;
所述第二采样单元通过第二时钟信号对所述延迟单元输出的所述调频后的第一时钟信号进行采样,生成第二相位信号,并将所述第二相位信号通过第二锁相模块发送给所述第一锁相模块,以使所述第一锁相模块根据所述第二相位信号调整所述第一时钟信号的相位。
结合本发明实施例第三方面的实现方式,在本发明实施例第三方面的第一种可能的实现方式中,所述参考时钟信号与所述第二时钟信号的频率相同。
结合本发明实施例第三方面的实现方式,在本发明实施例第三方面的第二种可能的实现方式中,所述第二采样单元接收的所述第二时钟信号为经过同步器改变时序后的第二时钟信号。
结合本发明实施例第三方面或第三方面的第一种中的任一种可能的实现方式,在本发明实施例第三方面的第三种可能的实现方式中,所述第一锁相模块根据所述第一相位信号调整所述第一时钟信号的频率包括:
所述第一锁相模块的第一鉴相器根据所述第一相位信号以及所述第二时钟信号计算所述第一时钟信号与所述第二时钟信号的频率误差;
所述第一锁相模块的第一滤波器根据所述频率误差控制所述第一锁相模块的数控振荡器调整第一时钟信号;
所述数控振荡器根据所述频率误差将所述第一时钟信号的频率调整至与第二时钟信号的频率相同;
所述第一锁相模块的分频器对所述调频后的第一时钟信号进行分频。
结合本发明实施例第三方面的实现方式,在本发明实施例第二方面的第四种可能的实现方式中,所述第一锁相模块根据所述第二相位信号调整所述第一
时钟信号的相位包括:
所述第二锁相模块的第二鉴相器根据所述第二相位信号以及所述第二时钟信号计算所述调频后的第一时钟信号与所述第二时钟信号的相位误差;
所述第一锁相模块的第二滤波器根据所述相位误差控制所述数控振荡器,以使所述数控振荡器根据所述相位误差将所述调频后的第一时钟信号的相位调整至与所述第二时钟信号的相位相同。
采用本发明实施例,能在时间数字转换器内部结构的基础上添加多一个由多个触发器组成的采样单元,通过使用一个时间数字转换器,实现现有的双环频率跟踪系统中两个时间数字转换器各自的功能,为双环频率跟踪系统提供一个全新的架构,减少系统的占用面积和功耗。
为了更清楚地说明本发明实施例的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。
图1是现有的双环频率跟踪系统的结构示意图;
图2是本发明实施例的一种时间数字转换器的一实施例的结构示意图;
图3是本发明实施例的一种时间数字转换器的一实施例的部分具体结构示意图;
图4是本发明实施例的一种频率跟踪装置的一实施例的结构示意图;
图5是本发明实施例的一种频率跟踪装置的另一实施例的结构示意图;
图6是本发明实施例的一种频率跟踪方法的一实施例的流程示意图。
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳
动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明实施例提供一种时间数字转换器、频率跟踪装置及方法,可通过使用一个时间数字转换器而达到双环频率跟踪的效果,减小双环频率跟踪系统的占用面积。
请参阅图2,图2是本发明实施例的一种时间数字转换器的一实施例的结构示意图。本发明实施例对时间数字转换器1的内部结构进行改造,增添了一组新的触发器阵列,实现现有的双环频率跟踪系统中两个时间数字转换器各自的功能。本发明实施例所涉及的延迟元件可为经设计以提供信号延迟的任何无源组件,如缓冲器、电感器、电阻器及电容器等器件,本发明实施例则以缓冲器进行举例说明。如图2所示的时间数字转换器1包括延迟单元11、第一采样单元12以及第二采样单元13。
延迟单元11与第一采样单元12相连,用于接收第一锁相模块2输出的第一时钟信号,将第一时钟信号进行延迟之后,输出至第一采样单元12。
第一采样单元12用于通过参考时钟信号对延迟单元11输出的第一时钟信号进行采样,生成第一相位信号,并将第一相位信号发送给第一锁相模块2,以使第一锁相模块2根据第一相位信号调整第一时钟信号的频率,并将调频后的第一时钟信号输出至延迟单元11。
延迟单元11还与第二采样单元13相连,用于接收第一锁相模块2输出的调频后的第一时钟信号,将调频后的第一时钟信号进行延迟后,输出至第二采样单元13。
第二采样单元13用于通过第二时钟信号对延迟单元11输出的调频后的第一时钟信号进行采样,生成第二相位信号,并将第二相位信号通过第二锁相模块3发送给第一锁相模块2,以使第一锁相模块2根据第二相位信号调整第一时钟信号的相位。
具体实现中,第一时钟信号为延迟单元11的输入时钟信号,一般为高频时钟。初始状态下,延迟单元11将第一锁相模块2输出的第一时钟信号进行延迟,并输出至第一采样单元12,由第一采样单元12所连接的第一锁相模块2将延迟后的第一时钟信号进行调频,再将调频后的第一时钟信号反馈给延迟单元11,此时延迟单元11继续将调频后的第一时钟信号延迟并输出至第二采
样单元13。
可选的,结合图3所示的时间数字转换器1的部分具体结构示意图,延迟单元11由多个延迟元件依次连接,第一采样单元12以及第二采样单元13由多个触发器依次连接,每个延迟元件的输出端接下一个延迟元件的输入端、第一采样单元12中与延迟元件对应的触发器的相位采集端以及第二采样单元13中与延迟元件对应的触发器的相位采集端。其中延迟元件与连接的触发器的公共节点为相位检测点。
可选的,参考时钟信号与第二时钟信号的频率相同。
具体实现中,在第一采样单元12中,每一个触发器的信号输入端接参考时钟信号,其中参考时钟信号的频率与第二时钟信号的频率相同。当输入的参考时钟信号触发相位采集的操作时(如图3所示,参考时钟信号利用上升沿触发相位采集的操作),每一个触发器的相位采集端对对应的延迟元件的相位检测点进行信号采样,输出对应的相位值Q(0)至Q(n-1)并锁存,将每个相位值组成一串编码输出第一相位信号,并将第一相位信号发送给第一锁相模块2,以使第一锁相模块2根据第一相位信号调整第一时钟信号的频率,并将调频后的第一时钟信号输出至延迟单元11。
作为一种可实施的方式,每个触发器输出的相位值通过编码器进行转换并组成一串编码,输出第一相位信号。
具体实现中,在第二采样单元13中,每一个触发器的信号输入端接第二时钟信号。与第一采样单元12的工作原理相同,当输入的第二时钟信号触发相位采集的操作时,每一个触发器的相位采集端对对应的延迟元件的相位检测点进行信号采样,即对调频后的第一时钟信号进行采样,输出对应的相位值P(0)至P(n-1)并锁存,将每个相位值组成一串编码输出第二相位信号,通过第二锁相模块3发送给第一锁相模块2,以使第一锁相模块2根据第二相位信号调整第一时钟信号的相位,最终使第一时钟信号与第二时钟信号达到同步。
作为一种可实施的方式,每个触发器输出的相位值通过编码器进行转换并组成一串编码,输出第二相位信号。
通过实施图2所描述的时间数字转换器,能在时间数字转换器内部结构的基础上添加多一个由多个触发器组成的采样单元,通过使用一个时间数字转换
器,实现现有的双环频率跟踪系统中两个时间数字转换器各自的功能以及双环频率跟踪系统的环路中各个器件的功能,减少系统的占用面积和功耗。
请参阅图4,图4是本发明实施例的一种频率跟踪装置的一实施例的结构示意图。本发明实施例提供的一种频率跟踪装置包括第一锁相模块2、第二锁相模块3以及如图2和图3实施例所描述的时间数字转换器1。其中:
第一锁相模块2的第一端与延迟单元11相连,用于向延迟单元11输出第一时钟信号。
第一锁相模块2的第二端与第二锁相模块3的一端相连,用于接收第二锁相模块3输出的第二时钟信号。
第一锁相模块2的第三端与第一采样单元12相连,用于接收第一采样单元12输出的第一相位信号,并根据第一相位信号以及第二时钟信号,将第一时钟信号的频率调整至与第二时钟信号的频率相同,通过第一锁相模块2的第一端输出调频后的第一时钟信号给延迟单元11。
第二锁相模块3的另一端与第二采样单元13的一端相连,用于接收第二采样单元13输出的第二相位信号,以控制第一锁相模块2根据第二相位信号以及第二时钟信号,将调频后的第一时钟信号的相位调整至与第二时钟信号的相位相同,将调整相位后的第一时钟信号通过第一锁相模块2的第一端输出给延迟单元11。
具体实现中,第二锁相模块3将输入的第二时钟信号输出至第一锁相模块2的第二端,为此第一锁相模块2能够鉴别第二时钟信号的相位信息,再由第一锁相模块2根据第二时钟信号产生第一时钟信号并通过第一锁相模块2的第一端输出至延迟单元11。
作为一种可实施的方式,第二时钟信号的相位信息也可由第二锁相模块3进行鉴别并输出至第一锁相模块2。
具体实现中,第一时钟信号经由延迟单元11延迟之后由第一采样单元12对第一时钟信号进行采样,产生第一相位信号,并将第一相位信号输入至第一锁相模块2的第三端。第一锁相模块2鉴别第一相位信号,并根据第一相位信号以及第二时钟信号的相位信息,将第一时钟信号的频率调整至与第二时钟信
号的频率相同。第一采样单元12产生第一相位信号的具体过程详见实施例图2,本实施例则不再赘述。
具体实现中,当第一锁相模块2调整第一时钟信号的频率之后,将调频后的第一时钟信号输出至延迟单元11,由第二采样单元13对调频后的第一时钟信号进行采样,产生第二相位信号,并将第二相位信号输出至第二锁相模块3的另一端。第二锁相模块3鉴别第二相位信号,将鉴别出的第二相位信号输出至第一锁相模块2的第二端,以使第一锁相模块2根据第二相位信号以及第二时钟信号的相位信息,将调频后的第一时钟信号的相位调整至与第二时钟信号的相位相同。第二采样单元13产生第二相位信号的具体过程详见实施例图2,本实施例则不再赘述。
通过实施图4所描述的装置,能在时间数字转换器内部结构的基础上添加多一个由多个触发器组成的采样单元,能实现现有的双环频率跟踪系统中两个时间数字转换器各自的功能,为双环频率跟踪系统提供一个全新的架构,减少系统的占用面积和功耗。
请参阅图5,图5是本发明实施例的一种频率跟踪装置的另一实施例的结构示意图。如图5所示,本发明实施例提供的一种频率跟踪装置包括第一锁相模块2、第二锁相模块3以及如图2和图3实施例所描述的时间数字转换器1。其中:第一锁相模块2的第一端与延迟单元11相连,用于向延迟单元11输出第一时钟信号。第一锁相模块2的第二端与第二锁相模块3的一端相连,用于接收第二锁相模块3输出的第二时钟信号。第一锁相模块2的第三端与第一采样单元12相连,用于接收第一采样单元12输出的第一相位信号,并根据第一相位信号以及第二时钟信号,将第一时钟信号的频率调整至与第二时钟信号的频率相同,通过第一锁相模块2的第一端输出调频后的第一时钟信号给延迟单元11。第二锁相模块3的另一端与第二采样单元13的一端相连,用于接收第二采样单元13输出的第二相位信号,以控制第一锁相模块2根据第二相位信号以及第二时钟信号,将调频后的第一时钟信号的相位调整至与第二时钟信号的相位相同,将调整相位后的第一时钟信号通过第一锁相模块2的第一端输出给延迟单元11。
可选的,装置还包括同步器4,同步器4的一端接第二时钟信号,同步器4的另一端与第二采样单元13相连,用于改变第二时钟信号的时序,以及输出改变时序后的第二时钟信号给第二采样单元13。由于第二采样单元13从延迟单元11得到的第一时钟信号为延迟后的时钟信号,因此需要同步器4将输入的第二时钟信号改变时序以与延迟后的第一时钟信号相匹配,以保证后续第一锁相模块2输出的第一时钟信号与第二时钟信号同步。
可选的,第一锁相模块2包括第一鉴相器21、第一滤波器22、数控振荡器23以及分频器24。第一鉴相器21包括第一输入端、第二输入端以及输出端;第一滤波器22包括输入端以及输出端;数控振荡器23包括输入端以及输出端;分频器24包括输入端以及输出端。
可选的,第一鉴相器21的第一输入端为第一锁相模块2的第二端,第一鉴相器21的第二输入端为第一锁相模块2的第三端,第一鉴相器21的输出端接第一滤波器22的输入端,第一鉴相器21用于根据第一相位信号以及第二时钟信号计算第一时钟信号与第二时钟信号的频率误差。第一鉴相器21鉴别出第一相位信号以及第二时钟信号的相位信息,将第一时钟信号与第二时钟信号的相位进行比较,计算第一时钟信号与第二时钟信号的频率误差,并输出频率误差电压。
可选的,第一滤波器22的输出端接数控振荡器23的输入端,第一滤波器22用于根据频率误差控制数控振荡器23调整第一时钟信号。第一滤波器22将第一鉴相器21输出的频率误差电压进行滤波之后,形成控制电压并输出至数控振荡器23。
可选的,数控振荡器23的输出端与分频器24的输入端相连,数控振荡器23用于根据频率误差将第一时钟信号的频率调整至与第二时钟信号的频率相同。第一滤波器22输出的控制电压作用于数控振荡器23,把数控振荡器23的输出振荡频率(即第一时钟信号的频率)拉向第二时钟信号的频率。当两者的频率相等时,第一锁相模块2的环路被锁定,输出的第一时钟信号的频率即与第二时钟信号的频率保持相同。
可选的,分频器24的输出端为第一锁相模块2的第一端,分频器24用于对调频后的第一时钟信号进行分频。分频器24通过对调频后的第一时钟信号
进行分频,调节相关系数关系,使其分频后的第一时钟信号能与第一采样单元12输入的参考时钟的相关参数相匹配,便于第一采样单元12进行采样。
作为一种可实施的方式,第二时钟信号的相位信息可由第二锁相模块3的第二鉴相器31鉴别之后通过第二滤波器32输出至第一鉴相器21。
可选的,第二锁相模块3包括第二鉴相器31以及第二滤波器32,第二鉴相器31包括输入端以及输出端;第二滤波器32包括输入端以及输出端。
可选的,第二鉴相器31的输入端为第二锁相模块3的另一端,第二鉴相器31的输出端与第二滤波器32的输入端相连,第二鉴相器31用于根据第二相位信号以及输入的第二时钟信号计算调频后的第一时钟信号与第二时钟信号的相位误差。第二鉴相器31与第一鉴相器21的工作原理相同,用于鉴别第二相位信号以及第二时钟信号的相位信息,将调频后的第一时钟信号与第二时钟信号的相位进行比较,计算调频后的第一时钟信号与第二时钟信号的相位误差,并输出相位误差电压。
可选的,第二滤波器32的输出端为第二锁相模块3的一端,第二滤波器32用于根据相位误差控制数控振荡器23,以使数控振荡器23根据相位误差将调频后的第一时钟信号的相位调整至与第二时钟信号的相位相同。第二滤波器32将第二鉴相器31输出的相位误差电压进行滤波之后,形成控制电压并作用于第一锁相模块2的数控振荡器23,使数控振荡器23输出的第一时钟信号的相位与第二时钟信号的相位相同,由此第二锁相模块3的环路被锁定,输出的第一时钟信号与第二时钟信号同步。
具体实现中,本发明实施例的装置的工作原理大致如下:
第二时钟信号通过第二锁相模块3输入第一锁相模块2,由数控振荡器23振荡输出第一时钟信号。由于数控振荡器23存在一定的误差,导致第一时钟信号不能与第二时钟信号同步,因此数控振荡器23将第一时钟信号输出至时间数字转换器1的延迟单元11。延迟单元11由多个延迟元件组成,用于将第一时钟信号进行延迟,并通过第一采样单元12对第一时钟信号进行采样,产生第一相位信号。第一采样单元12将第一相位信号输出至第一鉴相器21,第一鉴相器21鉴别第二时钟信号的相位以及第一相位信号,计算出第一时钟信号与第二时钟信号的频率误差,输出频率误差电压至第一滤波器22,由第一
滤波器22滤波之后控制数控振荡器23调整第一时钟信号的频率,直至第一时钟信号的频率与第二时钟信号的频率相同,第一锁相模块2的环路则被锁定。
当数控振荡器23对第一时钟信号进行调频之后,将第一时钟信号再次输出至时间数字转换器1的延迟单元11,由延迟单元11将调频后的第一时钟信号进行延迟,并通过第二采样单元13对调频后的第一时钟信号进行采样,产生第二相位信号。第二采样单元13将第二相位信号输出至第二鉴相器31,第二鉴相器31鉴别第二时钟信号的相位以及第二相位信号,计算出调频后的第一时钟信号与第二时钟信号的相位误差,输出相位误差电压至第二滤波器32,由第二滤波器32滤波之后控制数控振荡器23调整第一时钟信号的相位,直至第一时钟信号的相位与第二时钟信号的相位相同,第二锁相模块3的环路被锁定,最终令第一时钟信号与第二时钟信号保持同步。
通过实施图5所描述的装置,能通过使用一个时间数字转换器,实现现有的双环频率跟踪系统中两个时间数字转换器各自的功能以及双环频率跟踪系统的环路中各个器件的功能,为双环频率跟踪系统提供一个全新的架构,减少系统的占用面积和功耗。
请参阅图6,图6是本发明实施例的一种频率跟踪方法的一实施例的流程示意图。实施例图6所示的方法中所涉及的各个器件为实施图2至图5所描述的器件。如图6所示,本发明实施例的一种频率跟踪方法可以包括以下步骤:
600,延迟单元接收第一锁相模块输出的第一时钟信号,将第一时钟信号进行延迟之后,输出至第一采样单元。
610,第一采样单元通过参考时钟信号对延迟单元输出的第一时钟信号进行采样,生成第一相位信号,并将第一相位信号发送给第一锁相模块,以使第一锁相模块根据第一相位信号调整第一时钟信号的频率,并将调频后的第一时钟信号输出至延迟单元。
620,延迟单元接收第一锁相模块输出的调频后的第一时钟信号,将调频后的第一时钟信号进行延迟后,输出至第二采样单元。
630,第二采样单元通过第二时钟信号对延迟单元输出的调频后的第一时钟信号进行采样,生成第二相位信号,并将第二相位信号通过第二锁相模块发
送给第一锁相模块,以使第一锁相模块根据第二相位信号调整第一时钟信号的相位。
具体实现中,参考图5,第一锁相模块2输出第一时钟信号给时间数字转换器1的延迟单元11,延迟单元11将第一时钟信号进行延迟并输出至第一采样单元12。
具体实现中,第一采样单元12按照输入的参考时钟信号对第一时钟信号进行采样,并输出第一相位信号至第一锁相模块2。第一采样单元12对第一时钟信号进行采样的步骤详见实施例图2,本实施例则不再赘述。
可选的,参考时钟信号与第二时钟信号的频率相同。
可选的,第二采样单元13接收的第二时钟信号为经过同步器4改变时序后的第二时钟信号。由于第二采样单元13从延迟单元11得到的第一时钟信号为延迟后的时钟信号,因此需要同步器4将输入的第二时钟信号改变时序以与延迟后的第一时钟信号相匹配,以使后续第一锁相模块2输出的第一时钟信号与第二时钟信号同步。
可选的,第一锁相模块2的第一鉴相器21根据第一相位信号以及第二时钟信号计算第一时钟信号与第二时钟信号的频率误差。
作为一种可实施的方式,第一鉴相器21鉴别出第二时钟信号的相位信息以及第一相位信号,将第一时钟信号与第二时钟信号的相位进行比较,计算第一时钟信号与第二时钟信号的频率误差,并输出频率误差电压。
可选的,第一锁相模块2的第一滤波器22根据频率误差控制第一锁相模块2的数控振荡器23调整第一时钟信号。
作为一种可实施的方式,第一滤波器22将第一鉴相器21输出的频率误差电压进行滤波之后,形成控制电压并输出至数控振荡器23。
可选的,数控振荡器23根据频率误差将第一时钟信号的频率调整至与第二时钟信号的频率相同。
作为一种可实施的方式,第一滤波器22输出的控制电压作用于数控振荡器23,数控振荡器23将其输出的振荡频率(即第一时钟信号的频率)拉向第二时钟信号的频率,当两者的频率相等时,第一锁相模块2的环路被锁定,输出的第一时钟信号的频率即与第二时钟信号的频率保持相同。
可选的,第一锁相模块2的分频器24对调频后的第一时钟信号进行分频。
作为一种可实施的方式,分频器24通过对调频后的第一时钟信号进行分频,调节相关系数关系,使其分频后的第一时钟信号能与第一采样单元12输入的参考时钟的相关系数相匹配,便于第一采样单元12进行采样。
具体实现中,第一锁相模块2输出调频后的第一时钟信号给时间数字转换器1的延迟单元11。
具体实现中,延迟单元11输出调频后的第一时钟信号给时间数字转换器1的第二采样单元13。第二采样单元13按照输入的第二时钟信号对调频后的第一时钟信号进行采样并输出第二相位信号至第二锁相模块3。第二采样单元13对第二时钟信号进行采样的步骤详见实施例图2,本实施例则不再赘述。
可选的,第二锁相模块3的第二鉴相器31根据第二相位信号以及第二时钟信号的相位信息计算调频后的第一时钟信号与第二时钟信号的相位误差。
可选的,第一锁相模块2的第二滤波器32根据相位误差控制数控振荡器23,以使数控振荡器23根据相位误差将调频后的第一时钟信号的相位调整至与第二时钟信号的相位相同。
作为一种可实施的方式,第二鉴相器31用于鉴别第二时钟信号的相位信息以及第二相位信号,将调频后的第一时钟信号与第二时钟信号的相位进行比较,计算第一时钟信号与第二时钟信号的相位误差,并输出相位误差电压。
作为一种可实施的方式,第二滤波器32将第二鉴相器31输出的相位误差电压进行滤波之后,形成控制电压并作用于第一锁相模块2的数控振荡器23,使数控振荡器23输出的第一时钟信号的相位与第二时钟信号的相位相同,由此第二锁相模块3的环路被锁定,输出的第一时钟信号与第二时钟信号同步。
通过实施图6所描述的方法,能通过使用一个时间数字转换器,实现现有的双环频率跟踪系统中两个时间数字转换器各自的功能以及双环频率跟踪系统的环路中各个器件的功能,为双环频率跟踪系统提供一个全新的架构,减少系统的占用面积和功耗。
以上所描述的装置实施例仅仅是示意性的,其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的,作为单元显示的部件可以是或者也可以不是物理单元,即可以位于一个地方,或者也可以分布到多个网络单元上。
可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下,即可以理解并实施。
本发明实施例方法中的步骤可以根据实际需要进行顺序调整、合并和删减。
本发明实施例装置中的模块或单元可以根据实际需要进行合并、划分和删减。
本发明实施例的模块或模块,可以以通用集成电路(如中央处理器CPU),或以专用集成电路(ASIC)来实现。
通过以上的实施方式的描述,本领域的技术人员可以清楚地了解到各实施方式可借助软件加必需的通用硬件平台的方式来实现,当然也可以通过硬件。基于这样的理解,上述技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来,该计算机软件产品可以存储在计算机可读存储介质中,如ROM/RAM、磁碟、光盘等,包括若干指令用以使得一台计算机设备(可以是个人计算机,服务器,或者网络设备等)执行各个实施例或者实施例的某些部分所述的方法。
以上所述的实施方式,并不构成对该技术方案保护范围的限定。任何在上述实施方式的精神和原则之内所作的修改、等同替换和改进等,均应包含在该技术方案的保护范围之内。
Claims (12)
- 一种时间数字转换器,其特征在于,包括延迟单元、第一采样单元以及第二采样单元,其中:所述延迟单元与所述第一采样单元相连,用于接收第一锁相模块输出的第一时钟信号,将所述第一时钟信号进行延迟之后,输出至所述第一采样单元;所述第一采样单元用于通过参考时钟信号对所述延迟单元输出的所述第一时钟信号进行采样,生成第一相位信号,并将所述第一相位信号发送给所述第一锁相模块,以使所述第一锁相模块根据所述第一相位信号调整所述第一时钟信号的频率,并将调频后的第一时钟信号输出至所述延迟单元;所述延迟单元还与所述第二采样单元相连,用于接收所述第一锁相模块输出的所述调频后的第一时钟信号,将所述调频后的第一时钟信号进行延迟后,输出至所述第二采样单元;所述第二采样单元用于通过第二时钟信号对所述延迟单元输出的所述调频后的第一时钟信号进行采样,生成第二相位信号,并将所述第二相位信号通过第二锁相模块发送给所述第一锁相模块,以使所述第一锁相模块根据所述第二相位信号调整所述第一时钟信号的相位。
- 根据权利要求1所述的时间数字转换器,其特征在于,所述延迟单元由多个延迟元件依次连接,所述第一采样单元以及所述第二采样单元由多个触发器依次连接,每个延迟元件的输出端接下一个延迟元件的输入端、所述第一采样单元中与所述延迟元件对应的触发器的相位采集端以及所述第二采样单元中与所述延迟元件对应的触发器的相位采集端。
- 根据权利要求1或2任一项所述的时间数字转换器,其特征在于,所述参考时钟信号与所述第二时钟信号的频率相同。
- 一种频率跟踪装置,其特征在于,包括第一锁相模块、第二锁相模块以及如权利要求1至3任一项所述的时间数字转换器,其中:所述第一锁相模块的第一端与所述延迟单元相连,用于向所述延迟单元输出第一时钟信号;所述第一锁相模块的第二端与所述第二锁相模块的一端相连,用于接收所述第二锁相模块输出的第二时钟信号;所述第一锁相模块的第三端与所述第一采样单元相连,用于接收所述第一采样单元输出的第一相位信号,并根据所述第一相位信号以及所述第二时钟信号,将所述第一时钟信号的频率调整至与所述第二时钟信号的频率相同,通过所述第一锁相模块的第一端输出调频后的第一时钟信号给所述延迟单元;所述第二锁相模块的另一端与所述第二采样单元的一端相连,用于接收所述第二采样单元输出的第二相位信号,以控制所述第一锁相模块根据所述第二相位信号以及所述第二时钟信号,将所述调频后的第一时钟信号的相位调整至与所述第二时钟信号的相位相同,将调整相位后的第一时钟信号通过所述第一锁相模块的第一端输出给所述延迟单元。
- 根据权利要求4所述的装置,其特征在于,所述装置还包括同步器,其中:所述同步器的一端接所述第二时钟信号,所述同步器的另一端与所述第二采样单元的另一端相连,用于改变所述第二时钟信号的时序,以及输出改变时序后的第二时钟信号给所述第二采样单元。
- 根据权利要求4所述的装置,其特征在于,所述第一锁相模块包括第一鉴相器、第一滤波器、数控振荡器以及分频器,其中:所述第一鉴相器包括第一输入端、第二输入端以及输出端;所述第一滤波器包括输入端以及输出端;所述数控振荡器包括输入端以及输出端;所述分频器包括输入端以及输出端;所述第一鉴相器的第一输入端为所述第一锁相模块的第二端,所述第一鉴相器的第二输入端为所述第一锁相模块的第三端,所述第一鉴相器的输出端接所述第一滤波器的输入端,所述第一鉴相器用于根据所述第一相位信号以及所 述第二时钟信号计算所述第一时钟信号与所述第二时钟信号的频率误差;所述第一滤波器的输出端接所述数控振荡器的输入端,所述第一滤波器用于根据所述频率误差控制所述数控振荡器调整所述第一时钟信号;所述数控振荡器的输出端与所述分频器的输入端相连,所述数控振荡器用于根据所述频率误差将所述第一时钟信号的频率调整至与所述第二时钟信号的频率相同;所述分频器的输出端为所述第一锁相模块的第一端,所述分频器用于对所述调频后的第一时钟信号进行分频。
- 根据权利要求4或6所述的装置,其特征在于,所述第二锁相模块包括第二鉴相器以及第二滤波器,其中:所述第二鉴相器包括输入端以及输出端;所述第二滤波器包括输入端以及输出端;所述第二鉴相器的输入端为所述第二锁相模块的另一端,所述第二鉴相器的输出端与所述第二滤波器的输入端相连,所述第二鉴相器用于根据所述第二相位信号以及输入的所述第二时钟信号计算所述调频后的第一时钟信号与所述第二时钟信号的相位误差;所述第二滤波器的输出端为所述第二锁相模块的一端,所述第二滤波器用于根据所述相位误差控制所述数控振荡器,以使所述数控振荡器根据所述相位误差将所述调频后的第一时钟信号的相位调整至与所述第二时钟信号的相位相同。
- 一种频率跟踪方法,其特征在于,包括:延迟单元接收第一锁相模块输出的第一时钟信号,将所述第一时钟信号进行延迟之后,输出至第一采样单元;所述第一采样单元通过参考时钟信号对所述延迟单元输出的所述第一时钟信号进行采样,生成第一相位信号,并将所述第一相位信号发送给第一锁相模块,以使所述第一锁相模块根据所述第一相位信号调整所述第一时钟信号的频率,并将调频后的第一时钟信号输出至所述延迟单元;所述延迟单元接收所述第一锁相模块输出的所述调频后的第一时钟信号,将所述调频后的第一时钟信号进行延迟后,输出至第二采样单元;所述第二采样单元通过第二时钟信号对所述延迟单元输出的所述调频后的第一时钟信号进行采样,生成第二相位信号,并将所述第二相位信号通过第二锁相模块发送给所述第一锁相模块,以使所述第一锁相模块根据所述第二相位信号调整所述第一时钟信号的相位。
- 根据权利要求8所述的方法,其特征在于,所述参考时钟信号与所述第二时钟信号的频率相同。
- 根据权利要求8所述的方法,其特征在于,所述第二采样单元接收的所述第二时钟信号为经过同步器改变时序后的第二时钟信号。
- 根据权利要求8或9任一项所述的方法,其特征在于,所述第一锁相模块根据所述第一相位信号调整所述第一时钟信号的频率包括:所述第一锁相模块的第一鉴相器根据所述第一相位信号以及所述第二时钟信号计算所述第一时钟信号与所述第二时钟信号的频率误差;所述第一锁相模块的第一滤波器根据所述频率误差控制所述第一锁相模块的数控振荡器调整第一时钟信号;所述数控振荡器根据所述频率误差将所述第一时钟信号的频率调整至与第二时钟信号的频率相同;所述第一锁相模块的分频器对所述调频后的第一时钟信号进行分频。
- 根据权利要求8所述的方法,其特征在于,所述第一锁相模块根据所述第二相位信号调整所述第一时钟信号的相位包括:所述第二锁相模块的第二鉴相器根据所述第二相位信号以及所述第二时钟信号计算所述调频后的第一时钟信号与所述第二时钟信号的相位误差;所述第一锁相模块的第二滤波器根据所述相位误差控制所述数控振荡器,以使所述数控振荡器根据所述相位误差将所述调频后的第一时钟信号的相位 调整至与所述第二时钟信号的相位相同。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP14890063.2A EP3125432A4 (en) | 2014-04-23 | 2014-11-04 | Time-to-digital converter and frequency tracking device and method |
US15/331,109 US9720380B2 (en) | 2014-04-23 | 2016-10-21 | Time-to-digital converter, frequency tracking apparatus and method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410167138.0A CN103957003B (zh) | 2014-04-23 | 2014-04-23 | 一种时间数字转换器、频率跟踪装置及方法 |
CN201410167138.0 | 2014-04-23 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/331,109 Continuation US9720380B2 (en) | 2014-04-23 | 2016-10-21 | Time-to-digital converter, frequency tracking apparatus and method |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015161640A1 true WO2015161640A1 (zh) | 2015-10-29 |
Family
ID=51334245
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2014/090265 WO2015161640A1 (zh) | 2014-04-23 | 2014-11-04 | 一种时间数字转换器、频率跟踪装置及方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9720380B2 (zh) |
EP (1) | EP3125432A4 (zh) |
CN (1) | CN103957003B (zh) |
WO (1) | WO2015161640A1 (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103957003B (zh) * | 2014-04-23 | 2017-10-17 | 华为技术有限公司 | 一种时间数字转换器、频率跟踪装置及方法 |
CN109379077A (zh) * | 2015-03-25 | 2019-02-22 | 华为技术有限公司 | 一种锁相环中的时间数字转换器 |
US10067224B2 (en) * | 2015-10-22 | 2018-09-04 | Stmicroelectronics (Research & Development) Limited | Time to digital converter (TDC) with synchronous output and related methods |
CN105910617B (zh) * | 2016-04-14 | 2019-01-15 | 和芯星通科技(北京)有限公司 | 一种车载导航系统中采样点时间同步的方法及装置 |
CN106354001B (zh) * | 2016-08-31 | 2019-03-12 | 中国科学院上海高等研究院 | 时间数字转换电路 |
EP3435098B1 (en) * | 2017-07-25 | 2022-07-06 | Socionext Inc. | Phase measurement |
KR20210054651A (ko) * | 2019-11-05 | 2021-05-14 | 삼성전자주식회사 | 타이밍 데이터 수집 장치 |
CN117480743A (zh) * | 2021-07-31 | 2024-01-30 | 华为技术有限公司 | 一种用于时钟同步的收发电路及收发设备 |
CN115469525B (zh) * | 2022-08-23 | 2024-04-12 | 深圳研控自动化科技股份有限公司 | 输入输出时间测量方法、系统、装置、终端设备及介质 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1329416A (zh) * | 2000-06-08 | 2002-01-02 | 米特尔公司 | 具有双锁相环的定时电路 |
US6429693B1 (en) * | 2000-06-30 | 2002-08-06 | Texas Instruments Incorporated | Digital fractional phase detector |
CN1494216A (zh) * | 2002-10-31 | 2004-05-05 | 百利通电子(上海)有限公司 | 用一条延时链产生多个频点时钟信号的数字锁相环 |
CN1526201A (zh) * | 2001-05-25 | 2004-09-01 | 因芬尼昂技术股份公司 | 储存装置及射频系统用之极低抖动时脉产生装置及方法 |
US20130214959A1 (en) * | 2012-02-16 | 2013-08-22 | Electronics And Telecommunications Research Institute | Low-power high-resolution time-to-digital converter |
CN103957003A (zh) * | 2014-04-23 | 2014-07-30 | 华为技术有限公司 | 一种时间数字转换器、频率跟踪装置及方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5812626A (en) * | 1995-06-13 | 1998-09-22 | Matsushita Electric Industrial Co., Ltd. | Time counting circuit sampling circuit skew adjusting circuit and logic analyzing circuit |
US7888973B1 (en) * | 2007-06-05 | 2011-02-15 | Marvell International Ltd. | Matrix time-to-digital conversion frequency synthesizer |
US7957923B2 (en) * | 2007-07-16 | 2011-06-07 | Himax Technologies Limited | Device for jitter measurement and method thereof |
US8269553B2 (en) * | 2007-12-04 | 2012-09-18 | Advantest Corporation | Delay circuit |
US7795937B2 (en) * | 2008-03-26 | 2010-09-14 | Mstar Semiconductor, Inc. | Semi-digital delay locked loop circuit and method |
WO2010013385A1 (ja) * | 2008-08-01 | 2010-02-04 | 株式会社アドバンテスト | 時間測定回路、時間測定方法、それらを用いた時間デジタル変換器および試験装置 |
TWI364169B (en) * | 2008-12-09 | 2012-05-11 | Sunplus Technology Co Ltd | All digital phase locked loop circuit |
US8415983B2 (en) * | 2009-03-10 | 2013-04-09 | Nec Corporation | Digital phase comparator |
CN102754344B (zh) * | 2009-11-13 | 2015-09-30 | 意法爱立信有限公司 | 连续测量的时间数字转换器 |
US8344772B2 (en) * | 2009-12-18 | 2013-01-01 | Electronics And Telecommunications Research Institute | Time-to-digital converter and all digital phase-locked loop including the same |
JP2012070087A (ja) * | 2010-09-21 | 2012-04-05 | Toshiba Corp | デジタル位相比較器及びデジタル位相同期回路 |
CN102832943B (zh) * | 2011-06-15 | 2015-06-03 | 联发科技(新加坡)私人有限公司 | 时间数字转换器 |
US9098072B1 (en) * | 2012-09-05 | 2015-08-04 | IQ-Analog Corporation | Traveling pulse wave quantizer |
TWI477081B (zh) * | 2012-11-30 | 2015-03-11 | Univ Nat Taiwan | 頻率追蹤電路及其方法 |
CN203434964U (zh) * | 2013-07-10 | 2014-02-12 | 上海凌阳科技有限公司 | 一种用于采样时钟的相位延迟装置 |
CN103957005B (zh) * | 2014-04-30 | 2017-08-25 | 华为技术有限公司 | 时间数字转换器、全数字锁相环电路及方法 |
CN104052474B (zh) * | 2014-06-03 | 2017-03-15 | 华为技术有限公司 | 一种锁相环频率校正方法及系统 |
-
2014
- 2014-04-23 CN CN201410167138.0A patent/CN103957003B/zh active Active
- 2014-11-04 EP EP14890063.2A patent/EP3125432A4/en not_active Ceased
- 2014-11-04 WO PCT/CN2014/090265 patent/WO2015161640A1/zh active Application Filing
-
2016
- 2016-10-21 US US15/331,109 patent/US9720380B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1329416A (zh) * | 2000-06-08 | 2002-01-02 | 米特尔公司 | 具有双锁相环的定时电路 |
US6429693B1 (en) * | 2000-06-30 | 2002-08-06 | Texas Instruments Incorporated | Digital fractional phase detector |
CN1526201A (zh) * | 2001-05-25 | 2004-09-01 | 因芬尼昂技术股份公司 | 储存装置及射频系统用之极低抖动时脉产生装置及方法 |
CN1494216A (zh) * | 2002-10-31 | 2004-05-05 | 百利通电子(上海)有限公司 | 用一条延时链产生多个频点时钟信号的数字锁相环 |
US20130214959A1 (en) * | 2012-02-16 | 2013-08-22 | Electronics And Telecommunications Research Institute | Low-power high-resolution time-to-digital converter |
CN103957003A (zh) * | 2014-04-23 | 2014-07-30 | 华为技术有限公司 | 一种时间数字转换器、频率跟踪装置及方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP3125432A4 * |
Also Published As
Publication number | Publication date |
---|---|
US9720380B2 (en) | 2017-08-01 |
US20170038738A1 (en) | 2017-02-09 |
CN103957003A (zh) | 2014-07-30 |
EP3125432A1 (en) | 2017-02-01 |
CN103957003B (zh) | 2017-10-17 |
EP3125432A4 (en) | 2017-04-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2015161640A1 (zh) | 一种时间数字转换器、频率跟踪装置及方法 | |
US9543970B2 (en) | Circuit for digitizing phase differences, PLL circuit and method for the same | |
US8971455B2 (en) | Near-integer channel spur mitigation in a phase-locked loop | |
US7973578B2 (en) | Time-to-digital converter and all-digital phase-locked loop | |
US10763865B1 (en) | Field programmable gate array with internal phase-locked loop | |
EP3170262B1 (en) | Clock synchronization | |
JP5002528B2 (ja) | ディジタル位相検出器およびpll | |
US20160294398A1 (en) | Clock synchronizer | |
US10496041B2 (en) | Time-to-digital converter circuit | |
US11196429B2 (en) | Locking technique for phase-locked loop | |
US8671305B1 (en) | Techniques for adjusting periodic signals based on data detection | |
US8130048B2 (en) | Local oscillator | |
US9076366B2 (en) | Clock recovery system | |
Marini et al. | Fpga implementation of an nco based cdr for the juno front-end electronics | |
EP3761509A1 (en) | Phase-locked loop circuit | |
JP2013005050A (ja) | クロック生成装置および電子機器 | |
Shan et al. | A reconfigurable distributed architecture for clock generation in large many-core SoC | |
US9258110B2 (en) | Phase detector | |
TW201601566A (zh) | 可同步網路 | |
CN109428592B (zh) | 一种产生高频特定序列脉冲的方法和系统 | |
CN103378823A (zh) | 运用脉波辨识的频率产生方法与系统 | |
JP2018074312A (ja) | 周波数検出器及びクロックデータリカバリ装置 | |
Vamvakos et al. | Discrete-time, cyclostationary phase-locked loop model for jitter analysis | |
TWI533616B (zh) | 高解析度時脈產生裝置及雷達偵測系統 | |
CN117202337A (zh) | 信号处理方法、通信装置、通信系统及芯片 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 14890063 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
REEP | Request for entry into the european phase |
Ref document number: 2014890063 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2014890063 Country of ref document: EP |