WO2015115739A1 - Mémoire flash tridimensionnelle utilisant des couches d'électrode et/ou des couches isolantes intermédiaires ayant différentes propriétés, et son procédé de préparation - Google Patents

Mémoire flash tridimensionnelle utilisant des couches d'électrode et/ou des couches isolantes intermédiaires ayant différentes propriétés, et son procédé de préparation Download PDF

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Publication number
WO2015115739A1
WO2015115739A1 PCT/KR2014/013095 KR2014013095W WO2015115739A1 WO 2015115739 A1 WO2015115739 A1 WO 2015115739A1 KR 2014013095 W KR2014013095 W KR 2014013095W WO 2015115739 A1 WO2015115739 A1 WO 2015115739A1
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Prior art keywords
interlayer insulating
layer
electrode layers
layers
electrode
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PCT/KR2014/013095
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English (en)
Korean (ko)
Inventor
송윤흡
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한양대학교 산학협력단
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Priority claimed from KR1020140122650A external-priority patent/KR101622036B1/ko
Application filed by 한양대학교 산학협력단 filed Critical 한양대학교 산학협력단
Priority to CN201480074446.7A priority Critical patent/CN105940492B/zh
Priority to US15/115,232 priority patent/US9922990B2/en
Priority to CN201811575987.4A priority patent/CN110085597B/zh
Publication of WO2015115739A1 publication Critical patent/WO2015115739A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to a three-dimensional flash memory using an electrode layer and / or an interlayer insulating layer having different characteristics, and to a method of manufacturing the same.
  • each of the plurality of electrode layers has different characteristics or a plurality of interlayer insulating layers.
  • a three-dimensional flash memory and a method of manufacturing the same which improve the threshold voltage distribution of a plurality of electrode layers and make the stress level applied to each of the plurality of interlayer insulating layers by having each of them have different characteristics.
  • Flash memory devices are electrically erasable programmable read only memory (EEPROM), which may be, for example, a computer, a digital camera, an MP3 player, a game system, a memory stick. ) May be commonly used.
  • EEPROM electrically erasable programmable read only memory
  • the flash memory device electrically controls input and output of data by F-N tunneling or hot electron injection.
  • N cell transistors are connected in series to form a unit string, and the unit strings are connected in parallel between a bit line and a ground line.
  • NAND-type flash memory device having a structure in which the cell transistors are connected in parallel between the bit line and the ground line.
  • the flash memory device should be designed to store high capacity data. Therefore, a plurality of cell transistors must be formed in the unit chip. However, it is not easy to highly integrate cell transistors within a limited horizontal area.
  • the three-dimensional memory structure improves the limitation of two-dimensional scaling of NAND flash memory.
  • the structure of the three-dimensional NAND flash memory includes, for example, a BICS (Built-In Current Sensor) structure and a pipe type (BiP Type) Bit Cost Scalable (BIC) NAND flash memory structure having an improved BICS structure.
  • Embodiments of the present invention provide a three-dimensional flash memory and a method of manufacturing the same by improving the threshold voltage distribution of the plurality of electrode layers by different physical structures or materials of the plurality of electrode layers.
  • embodiments of the present invention by making the physical structure or material of the interlayer insulating layers, as well as the plurality of electrode layers different from each other, the three-dimensional flash memory and its fabrication to uniform the stress level applied to each of the interlayer insulating layers Provide a method.
  • 3D flash memory is a channel layer; A plurality of electrode layers connected to the channel layer and stacked vertically; And a plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically, wherein each of the plurality of electrode layers has a different physical structure or is different from each other. It is formed of a substance.
  • the thickness of the first electrode layer among the plurality of electrode layers may be thicker than the thickness of the second electrode layer existing on the upper layer of the first electrode layer.
  • the length of each of the plurality of electrode layers or the pattern formed on the surface of each of the plurality of electrode layers may be different.
  • the material forming the first electrode layer among the plurality of electrode layers may have better electrical transfer characteristics than the material of the second electrode layer existing on the upper layer of the first electrode layer.
  • Each of the at least two electrode layers of the plurality of electrode layers may be formed of different materials.
  • An interlayer oxide film, the silicon nitride film, and a tunnel oxide film may be disposed between each of the plurality of electrode layers and the channel layer.
  • 3D flash memory is a channel layer; A plurality of electrode layers connected to the channel layer and stacked vertically; And a plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically, wherein each of the plurality of interlayer insulating layers is formed of a different material or is different from each other. It has a physical structure.
  • the material forming the first interlayer insulating layer among the plurality of interlayer insulating layers may have a property that is stronger in stress than the material of the second interlayer insulating layer existing on the first interlayer insulating layer.
  • At least two interlayer insulating layers of the plurality of interlayer insulating layers may be formed of different materials.
  • the thickness of the first interlayer insulating layer of the plurality of interlayer insulating layers may be thicker than the thickness of the second interlayer insulating layer on the upper layer of the first interlayer insulating layer.
  • a length of each of the plurality of interlayer insulating layers or a pattern formed on a surface of each of the plurality of interlayer insulating layers may be different.
  • An interlayer oxide film, the silicon nitride film, and a tunnel oxide film may be disposed between each of the plurality of electrode layers and the channel layer.
  • 3D flash memory is a channel layer; A plurality of electrode layers connected to the channel layer and stacked vertically; And a plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically, wherein each of the plurality of interlayer insulating layers is formed of a different material or is different from each other. It has a physical structure, and each of the plurality of electrode layers is formed of different materials or have different physical structures.
  • Embodiments of the present invention can provide a three-dimensional flash memory and a method of manufacturing the same by improving the threshold voltage distribution of the plurality of electrode layers by different physical structures or materials of the plurality of electrode layers. Therefore, the reliability of the data stored in the three-dimensional flash memory can be improved.
  • embodiments of the present invention by making the physical structure or material of the interlayer insulating layers, as well as the plurality of electrode layers different from each other, the three-dimensional flash memory and its fabrication to uniform the stress level applied to each of the interlayer insulating layers It may provide a method.
  • FIG. 1 shows a general cross-sectional view of a three-dimensional flash memory.
  • FIG. 2 is a cross-sectional view of a three-dimensional flash memory formed of the same material and including a plurality of interlayer insulating layers having a uniform physical structure.
  • FIG. 3 is a cross-sectional view of a three-dimensional flash memory formed of different materials and including a plurality of interlayer insulating layers having a uniform physical structure in accordance with an embodiment of the present invention.
  • FIG. 4 illustrates a cross-sectional view of a three-dimensional flash memory formed of different materials and including a plurality of interlayer insulating layers having different physical structures in accordance with an embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of a three-dimensional flash memory having a uniform physical structure and including a plurality of electrode layers formed of the same material.
  • FIG. 6 is a cross-sectional view of a 3D flash memory having a plurality of electrode layers having different physical structures and formed of the same material according to an embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of a three-dimensional flash memory having a plurality of electrode layers having different physical structures and formed of different materials according to an embodiment of the present invention.
  • FIG. 8 illustrates a storage device including a 3D flash memory according to an embodiment of the present invention.
  • FIG. 9 illustrates a structure of a 3D flash memory having a uniform physical structure and including a plurality of electrode layers formed of the same material.
  • FIG. 10 is a graph illustrating a threshold voltage distribution in the three-dimensional flash memory shown in FIG. 9.
  • FIG. 11 is a graph illustrating threshold voltage distribution in a three-dimensional flash memory according to thicknesses of the plurality of electrode layers.
  • FIG. 1 shows a general cross-sectional view of a three-dimensional flash memory.
  • a 3D flash memory includes a channel layer 110 as a vertical structure. That is, the channel layer 110 is formed perpendicular to the substrate (not shown).
  • the channel layer may be formed of monocrystalline silicon, and for example, may be formed through a selective epitaxial growth process or a phase change epitaxial process using a substrate as a seed.
  • the tunnel oxide layer 120, the silicon nitride layer 130, and the interlayer oxide layer 140 may be formed around the channel layer 110, and the plurality of electrode layers 150 may be vertically stacked. Although not shown in FIG. 1, a plurality of interlayer insulating layers are alternately disposed between the plurality of electrode layers 150.
  • the tunnel oxide film 120, the silicon nitride film 130, and the interlayer oxide film 140 formed around the channel layer 110 may store data by trapping charges.
  • external stress or internal stress occurring in the process of trapping charge or spread of charges over time can cause data disturbance.
  • the external stress or the internal stress generated in the process of trapping the charge acts differently on each of the plurality of interlayer insulating layers. For example, a low level of stress may be applied to the interlayer insulating layer present in the upper layer, and a high level of stress may be applied to the interlayer insulating layer present in the lower layer.
  • the threshold voltage of each of the plurality of electrode layers 150 may be different because current densities flowing through the plurality of electrode layers 150 are different.
  • the electrode layer present in the upper layer may have a high current density
  • the electrode layer present in the lower layer may have a relatively low current density.
  • FIG. 2 is a cross-sectional view of a three-dimensional flash memory formed of the same material and including a plurality of interlayer insulating layers having a uniform physical structure.
  • a low level of stress is applied to an interlayer insulating layer of an upper layer among the plurality of interlayer insulating layers 220 arranged alternately with the plurality of electrode layers 210.
  • a high level of stress is applied to the interlayer insulating layer of the lower layer.
  • embodiments of the present invention propose a material or physical structure of the plurality of interlayer insulating layers 220 to apply a substantially uniform level of stress to each of the plurality of interlayer insulating layers 220.
  • FIG. 3 is a cross-sectional view of a three-dimensional flash memory formed of different materials and including a plurality of interlayer insulating layers having a uniform physical structure in accordance with an embodiment of the present invention.
  • an embodiment of the present invention forms a plurality of interlayer insulating layers 320 disposed between the plurality of electrode layers 310 using different materials.
  • the plurality of interlayer insulating layers 320 may include an interlayer insulating layer 330 of material 1, an interlayer insulating layer 331 of material 2, an interlayer insulating layer 332 of material 3, and an interlayer insulating layer of material 4. 333 may be included.
  • the plurality of interlayer insulating layers 320 are used for the purpose of planarization or insulation, and include a gas material formed by CVD such as SiO 2, DSG (SiOF), TFOS, BPSG, and SOG (Spin-on-Glass / Shirokisan-based) It may include a coating material (SOD) represented by. These various materials may have various material properties in terms of mechanical strength, dielectric constant, dielectric loss, chemical stability, thermal stability, conductivity, and the like, and these characteristics determine durability against internal stress or external stress.
  • an embodiment of the present invention may use a relatively stress-sensitive material for the interlayer insulating layers present in the upper layer of the plurality of interlayer insulating layers 320 and relatively for the interlayer insulating layers present in the lower layer. Stress-resistant materials can be used. Therefore, the level of stress applied to each of the plurality of interlayer insulating layers 320 may be uniform.
  • FIG. 4 illustrates a cross-sectional view of a three-dimensional flash memory formed of different materials and including a plurality of interlayer insulating layers having different physical structures in accordance with an embodiment of the present invention.
  • an embodiment of the present invention uses different materials for each of the plurality of interlayer insulating layers as shown in FIG. 3, while designing different physical structures of each of the plurality of interlayer insulating layers. can do.
  • the physical structure may be determined by the thickness, length, etc. of each of the plurality of interlayer insulating layers.
  • the plurality of interlayer insulating layers include a top interlayer insulating layer, a bottom interlayer insulating layer, and a middle interlayer insulating layer. Therefore, hereinafter, the physical structure of each of the plurality of interlayer insulating layers may be differently designed may mean that the physical structure of each of the plurality of interlayer insulating layers is differently designed.
  • the plurality of interlayer insulating layers 420 respectively present between the plurality of electrode layers 410 may include the interlayer insulating layer 430 of material 1 and the interlayer insulation of material 2.
  • the thicknesses of the interlayer insulating layer 430 of the material 1, the interlayer insulating layer 431 of the material 2, the interlayer insulating layer 432 of the material 3, and the interlayer insulating layer 433 of the material 4 may be different from each other. have.
  • the thickness of the interlayer insulating layer 430 of the material 1 is formed to be thicker than the thickness of the interlayer insulating layer 431 of the material 2, the interlayer insulating layer 432 of the material 3, and the interlayer insulating layer 433 of the material 4. This may make the level of stress applied to each of the plurality of interlayer insulating layers 420 uniform.
  • the physical structure is changed by changing the thickness of each of the plurality of interlayer insulating layers 420, but embodiments of the present invention are formed on the surfaces of each of the plurality of interlayer insulating layers 420 of various lengths. It includes a change in the pattern or the like.
  • the embodiment of the present invention proposes a plurality of interlayer insulating layers 420 having different physical structures as well as being formed of different materials, but is not limited thereto and is formed of the same material.
  • a plurality of interlayer insulating layers 420 having only different physical structures may also be proposed.
  • FIG. 5 is a cross-sectional view of a three-dimensional flash memory having a uniform physical structure and including a plurality of electrode layers formed of the same material.
  • an electrode layer of an upper layer of the plurality of electrode layers 510 may be formed. Since the current density flowing in the electrode layer is different from the current density flowing in the electrode layer of the lower layer, a difference between threshold voltages of each of the plurality of electrode layers 510 may occur.
  • embodiments of the present invention propose a material or physical structure of the plurality of electrode layers 510 to have a substantially uniform threshold voltage for each of the plurality of electrode layers 510.
  • the plurality of interlayer insulating layers 520 alternately arranged with the plurality of electrode layers 510 may have a material or a physical structure to which a substantially uniform level of stress is applied to each of the above-described ones. .
  • FIG. 6 is a cross-sectional view of a 3D flash memory having a plurality of electrode layers having different physical structures and formed of the same material according to an embodiment of the present invention.
  • an embodiment of the present invention may design different physical structures of each of the plurality of electrode layers 610.
  • the physical structure may be determined by the thickness, length, etc. of each of the plurality of electrode layers 610.
  • the plurality of electrode layers 610 may include a top electrode layer, a bottom electrode layer, and a middle electrode layer. Therefore, hereinafter, the physical structure of each of the plurality of electrode layers 610 is differently designed may mean that the physical structure of each of the plurality of intermediate electrode layers is designed differently.
  • the plurality of electrode layers 610 may include an electrode layer 1 620, an electrode layer 2 621, an electrode layer 3 622, and an electrode layer 4 623 having different thicknesses.
  • the thickness of the electrode layer 1 620 may be formed to be thicker than the thickness of the electrode layer 2 621, the electrode layer 3 622, and the electrode layer 4 623, and this may increase the threshold voltage of each of the plurality of electrode layers 610. It can be made uniform.
  • the physical structure is changed by changing the thickness of each of the plurality of electrode layers 610, but embodiments of the present invention vary the length, the pattern formed on the surface of each of the plurality of electrode layers 610, and the like. It includes.
  • the plurality of interlayer insulating layers 630 alternately arranged with the plurality of electrode layers 610 may have a material or a physical structure to which a substantially uniform level of stress is applied, as described above. .
  • FIG. 7 is a cross-sectional view of a three-dimensional flash memory having a plurality of electrode layers having different physical structures and formed of different materials according to an embodiment of the present invention.
  • each of the plurality of electrode layers may be differently designed, but different materials may be used for each of the plurality of electrode layers.
  • the plurality of electrode layers 710 may include an electrode layer 720 of material 1, an electrode layer 721 of material 2, an electrode layer 722 of material 3, and an electrode layer of material 4 ( 723).
  • a material having a relatively low electrical transmission property may be used for an electrode layer existing in an upper layer among the plurality of electrode layers 710, and a relatively electrical transmission property for an electrode layer existing in a lower layer.
  • This excellent material can be used.
  • the electrical transfer properties of the electrode layer 720 of material 1 may be superior to the electrical transfer properties of the electrode layer 723 of material 4. Therefore, the threshold voltage of each of the plurality of electrode layers 710 may be uniform.
  • the plurality of interlayer insulating layers 730 disposed alternately with the plurality of electrode layers 710 may have a material or a physical structure to which a substantially uniform level of stress is applied to each of the above-described ones. .
  • the embodiment of the present invention proposes a plurality of electrode layers 710 having different physical structures and formed of different materials, the present invention is not limited thereto and is not limited thereto. A plurality of electrode layers 710 formed only as well may also be proposed.
  • FIG. 8 illustrates a storage device including a 3D flash memory according to an embodiment of the present invention.
  • the memory 810 refers to the above-described three-dimensional flash memory.
  • the memory 810 may be not only a NAND flash memory but also a Arthur flash memory to which the spirit of the present invention is applied.
  • the memory controller 820 provides an input signal to control the operation of the memory 810.
  • the system 500 controls input / output data by transmitting a command of a host when the memory controller used in the memory card is related to the memory, or controls various data in the memory based on an authorized control signal.
  • This structure is applied not only to simple memory cards but also to many digital devices that use memory, and applies to all digital devices that need memory such as portable digital cameras and mobile phones.
  • FIG. 9 illustrates a structure of a 3D flash memory having a uniform physical structure and including a plurality of electrode layers formed of the same material.
  • a 3D flash memory is a NAND flash memory having a structure in which cell transistors are connected in series to form a unit string, and the unit strings are connected in parallel between a bit line and a ground line.
  • the current density becomes weaker as the lower portion of the string decreases.
  • FIG. 10 as shown in FIG. 9B, the number of stacks of cells included in the string is changed to 10, 30, and 50 stages, respectively, and the program bias of 10V is applied to the upper and lower cells, respectively.
  • FIG. 10 is a graph illustrating a threshold voltage distribution in the three-dimensional flash memory shown in FIG. 9.
  • the top and bottom drain currents 1030 and 1040 when the number of stacked cells is 30 stages are reduced than the top and bottom drain currents 1010 and 1020 when the number of cells stacked is 10 stages.
  • the drain currents 1050 and 1060 of the top and bottom when the number of stacked cells is 50 stages are lower than the drain currents 1030 and 1040 of the top and the bottom when the number of stacked cells is 30 stages.
  • Table 1 10-speed cell 30-speed cell 50-speed cell top bottom top bottom top bottom Saturation Drain Current [A] 3.69E-05 3.69E-05 3.69E-05 3.69E-05 3.69E-05 3.69E-05 3.69E-05 Vt [V] 0.7247 0.6549 0.6530 0.5080 0.4715 0.2633 ⁇ Vt [V] 0.0698 0.1450 0.2082
  • FIG. 11 is a graph illustrating threshold voltage distribution in a three-dimensional flash memory according to thicknesses of the plurality of electrode layers.
  • the threshold voltage distributions according to the changed thicknesses are compared.
  • each of the plurality of electrode layers is fixed to 40 nm as shown in (a), it can be seen that the difference between the threshold voltages 1110 and 1120 between the upper electrode layer and the lower electrode layer among the plurality of electrode layers is 0.2082.
  • the thickness of each of the plurality of electrode layers is increased as the thickness of the upper electrode layer increases. It can be seen that the difference between the threshold voltages 1130 and 1140 between the electrode layer and the lower electrode layer is 0.3918.
  • the thickness of each of the plurality of electrode layers decreases as the upper portion is increased, the upper electrode layer among the plurality of electrode layers. It can be seen that the difference between the threshold voltages 1150 and 1160 between the electrode layer and the lower electrode layer is -0.2198.
  • the thickness of each of the plurality of electrode layers decreases as the upper portion is increased, the upper electrode layer among the plurality of electrode layers. It can be seen that the difference between the threshold voltages 1170 and 1180 between the electrode layer and the lower electrode layer is 0.0039.
  • the threshold voltage distribution can be improved by forming the thickness of each of the plurality of electrode layers as the thickness becomes lower. Therefore, the physical structure of each of the plurality of electrode layers is differently designed such that the thickness of the first electrode layer among the plurality of electrode layers is thicker than the thickness of the second electrode layer existing on the upper layer of the first electrode layer. Can improve their threshold voltage distribution.

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Abstract

Des modes de réalisation de la présente invention permettent d'améliorer la distribution de tension de seuil d'une pluralité de couches d'électrode en configurant chacune des couches de la pluralité de couches d'électrode de façon à avoir différentes structures physiques ou différents matériaux, etc., ce qui permet d'améliorer la crédibilité pendant un processus de maintien de données stockées et un processus de lecture.
PCT/KR2014/013095 2014-01-28 2014-12-31 Mémoire flash tridimensionnelle utilisant des couches d'électrode et/ou des couches isolantes intermédiaires ayant différentes propriétés, et son procédé de préparation WO2015115739A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201480074446.7A CN105940492B (zh) 2014-01-28 2014-12-31 利用具有不同特征的电极层和/或层间绝缘层的三维闪存及其制造方法
US15/115,232 US9922990B2 (en) 2014-01-28 2014-12-31 Three dimensional flash memory using electrode layers and/or interlayer insulation layers having different properties, and preparation method therefor
CN201811575987.4A CN110085597B (zh) 2014-01-28 2014-12-31 利用具有不同特征的电极层和/或层间绝缘层的三维闪存

Applications Claiming Priority (4)

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KR20140010744 2014-01-28
KR10-2014-0010744 2014-01-28
KR10-2014-0122650 2014-09-16
KR1020140122650A KR101622036B1 (ko) 2014-01-28 2014-09-16 서로 다른 특성을 갖는 전극층 및/또는 층간 절연층을 이용하는 3차원 플래시 메모리

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