WO2015115739A1

WO2015115739A1 - Three dimensional flash memory using electrode layers and/or interlayer insulation layers having different properties, and preparation method therefor

Info

Publication number: WO2015115739A1
Application number: PCT/KR2014/013095
Authority: WO
Inventors: 송윤흡
Original assignee: 한양대학교 산학협력단
Priority date: 2014-01-28
Filing date: 2014-12-31
Publication date: 2015-08-06
Also published as: CN110085597A; CN110085597B

Abstract

Embodiments of the present invention enable threshold voltage distribution of a plurality of electrode layers to be improved by configuring each of the plurality of electrode layers to have different physical structures or materials, etc., thereby enhancing credibility during a process of maintaining stored data and a reading process.

Description

3D flash memory using an electrode layer and / or an interlayer insulating layer having different characteristics and a manufacturing method thereof

The present invention relates to a three-dimensional flash memory using an electrode layer and / or an interlayer insulating layer having different characteristics, and to a method of manufacturing the same. Specifically, each of the plurality of electrode layers has different characteristics or a plurality of interlayer insulating layers. A three-dimensional flash memory and a method of manufacturing the same which improve the threshold voltage distribution of a plurality of electrode layers and make the stress level applied to each of the plurality of interlayer insulating layers by having each of them have different characteristics.

Flash memory devices are electrically erasable programmable read only memory (EEPROM), which may be, for example, a computer, a digital camera, an MP3 player, a game system, a memory stick. ) May be commonly used. The flash memory device electrically controls input and output of data by F-N tunneling or hot electron injection.

Looking at the flash memory device from a circuit point of view, N cell transistors are connected in series to form a unit string, and the unit strings are connected in parallel between a bit line and a ground line. There is a NAND-type flash memory device having a structure in which the cell transistors are connected in parallel between the bit line and the ground line.

The flash memory device should be designed to store high capacity data. Therefore, a plurality of cell transistors must be formed in the unit chip. However, it is not easy to highly integrate cell transistors within a limited horizontal area.

The three-dimensional memory structure improves the limitation of two-dimensional scaling of NAND flash memory. The structure of the three-dimensional NAND flash memory includes, for example, a BICS (Built-In Current Sensor) structure and a pipe type (BiP Type) Bit Cost Scalable (BIC) NAND flash memory structure having an improved BICS structure.

Embodiments of the present invention provide a three-dimensional flash memory and a method of manufacturing the same by improving the threshold voltage distribution of the plurality of electrode layers by different physical structures or materials of the plurality of electrode layers.

In addition, embodiments of the present invention, by making the physical structure or material of the interlayer insulating layers, as well as the plurality of electrode layers different from each other, the three-dimensional flash memory and its fabrication to uniform the stress level applied to each of the interlayer insulating layers Provide a method.

3D flash memory according to an embodiment of the present invention is a channel layer; A plurality of electrode layers connected to the channel layer and stacked vertically; And a plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically, wherein each of the plurality of electrode layers has a different physical structure or is different from each other. It is formed of a substance.

The thickness of the first electrode layer among the plurality of electrode layers may be thicker than the thickness of the second electrode layer existing on the upper layer of the first electrode layer.

The length of each of the plurality of electrode layers or the pattern formed on the surface of each of the plurality of electrode layers may be different.

The material forming the first electrode layer among the plurality of electrode layers may have better electrical transfer characteristics than the material of the second electrode layer existing on the upper layer of the first electrode layer.

Each of the at least two electrode layers of the plurality of electrode layers may be formed of different materials.

An interlayer oxide film, the silicon nitride film, and a tunnel oxide film may be disposed between each of the plurality of electrode layers and the channel layer.

3D flash memory according to another embodiment of the present invention is a channel layer; A plurality of electrode layers connected to the channel layer and stacked vertically; And a plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically, wherein each of the plurality of interlayer insulating layers is formed of a different material or is different from each other. It has a physical structure.

The material forming the first interlayer insulating layer among the plurality of interlayer insulating layers may have a property that is stronger in stress than the material of the second interlayer insulating layer existing on the first interlayer insulating layer.

At least two interlayer insulating layers of the plurality of interlayer insulating layers may be formed of different materials.

The thickness of the first interlayer insulating layer of the plurality of interlayer insulating layers may be thicker than the thickness of the second interlayer insulating layer on the upper layer of the first interlayer insulating layer.

A length of each of the plurality of interlayer insulating layers or a pattern formed on a surface of each of the plurality of interlayer insulating layers may be different.

3D flash memory according to another embodiment of the present invention is a channel layer; A plurality of electrode layers connected to the channel layer and stacked vertically; And a plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically, wherein each of the plurality of interlayer insulating layers is formed of a different material or is different from each other. It has a physical structure, and each of the plurality of electrode layers is formed of different materials or have different physical structures.

Embodiments of the present invention can provide a three-dimensional flash memory and a method of manufacturing the same by improving the threshold voltage distribution of the plurality of electrode layers by different physical structures or materials of the plurality of electrode layers. Therefore, the reliability of the data stored in the three-dimensional flash memory can be improved.

In addition, embodiments of the present invention, by making the physical structure or material of the interlayer insulating layers, as well as the plurality of electrode layers different from each other, the three-dimensional flash memory and its fabrication to uniform the stress level applied to each of the interlayer insulating layers It may provide a method.

1 shows a general cross-sectional view of a three-dimensional flash memory.

2 is a cross-sectional view of a three-dimensional flash memory formed of the same material and including a plurality of interlayer insulating layers having a uniform physical structure.

3 is a cross-sectional view of a three-dimensional flash memory formed of different materials and including a plurality of interlayer insulating layers having a uniform physical structure in accordance with an embodiment of the present invention.

4 illustrates a cross-sectional view of a three-dimensional flash memory formed of different materials and including a plurality of interlayer insulating layers having different physical structures in accordance with an embodiment of the present invention.

5 is a cross-sectional view of a three-dimensional flash memory having a uniform physical structure and including a plurality of electrode layers formed of the same material.

6 is a cross-sectional view of a 3D flash memory having a plurality of electrode layers having different physical structures and formed of the same material according to an embodiment of the present invention.

7 is a cross-sectional view of a three-dimensional flash memory having a plurality of electrode layers having different physical structures and formed of different materials according to an embodiment of the present invention.

8 illustrates a storage device including a 3D flash memory according to an embodiment of the present invention.

FIG. 9 illustrates a structure of a 3D flash memory having a uniform physical structure and including a plurality of electrode layers formed of the same material.

FIG. 10 is a graph illustrating a threshold voltage distribution in the three-dimensional flash memory shown in FIG. 9.

FIG. 11 is a graph illustrating threshold voltage distribution in a three-dimensional flash memory according to thicknesses of the plurality of electrode layers.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the embodiments. Also, like reference numerals in the drawings denote like elements.

1 shows a general cross-sectional view of a three-dimensional flash memory.

Referring to FIG. 1, a 3D flash memory includes a channel layer 110 as a vertical structure. That is, the channel layer 110 is formed perpendicular to the substrate (not shown). Here, the channel layer may be formed of monocrystalline silicon, and for example, may be formed through a selective epitaxial growth process or a phase change epitaxial process using a substrate as a seed.

The tunnel oxide layer 120, the silicon nitride layer 130, and the interlayer oxide layer 140 may be formed around the channel layer 110, and the plurality of electrode layers 150 may be vertically stacked. Although not shown in FIG. 1, a plurality of interlayer insulating layers are alternately disposed between the plurality of electrode layers 150.

As will be described in detail below, the tunnel oxide film 120, the silicon nitride film 130, and the interlayer oxide film 140 formed around the channel layer 110 may store data by trapping charges. However, external stress or internal stress occurring in the process of trapping charge or spread of charges over time can cause data disturbance. At this time, the external stress or the internal stress generated in the process of trapping the charge acts differently on each of the plurality of interlayer insulating layers. For example, a low level of stress may be applied to the interlayer insulating layer present in the upper layer, and a high level of stress may be applied to the interlayer insulating layer present in the lower layer.

In addition, since the resistivity of the channel layer 110 of the 3D flash memory varies depending on the position, a difference in threshold voltages of the plurality of electrode layers 150 may occur, thereby spreading the threshold voltage distribution. Such spreading of the threshold voltage distribution can degrade the reliability in the process of holding and reading the stored data. At this time, the threshold voltage of each of the plurality of electrode layers 150 may be different because current densities flowing through the plurality of electrode layers 150 are different. For example, the electrode layer present in the upper layer may have a high current density, and the electrode layer present in the lower layer may have a relatively low current density.

Referring to FIG. 2, due to a structural problem of a 3D flash memory, a low level of stress is applied to an interlayer insulating layer of an upper layer among the plurality of interlayer insulating layers 220 arranged alternately with the plurality of electrode layers 210. On the other hand, a high level of stress is applied to the interlayer insulating layer of the lower layer.

As such, a different level of stress acting on each of the plurality of interlayer insulating layers 220 may cause a lower reliability of stored data. Accordingly, embodiments of the present invention propose a material or physical structure of the plurality of interlayer insulating layers 220 to apply a substantially uniform level of stress to each of the plurality of interlayer insulating layers 220.

Referring to FIG. 3, an embodiment of the present invention forms a plurality of interlayer insulating layers 320 disposed between the plurality of electrode layers 310 using different materials. For example, the plurality of interlayer insulating layers 320 may include an interlayer insulating layer 330 of material 1, an interlayer insulating layer 331 of material 2, an interlayer insulating layer 332 of material 3, and an interlayer insulating layer of material 4. 333 may be included.

The plurality of interlayer insulating layers 320 are used for the purpose of planarization or insulation, and include a gas material formed by CVD such as SiO 2, DSG (SiOF), TFOS, BPSG, and SOG (Spin-on-Glass / Shirokisan-based) It may include a coating material (SOD) represented by. These various materials may have various material properties in terms of mechanical strength, dielectric constant, dielectric loss, chemical stability, thermal stability, conductivity, and the like, and these characteristics determine durability against internal stress or external stress.

In this case, an embodiment of the present invention may use a relatively stress-sensitive material for the interlayer insulating layers present in the upper layer of the plurality of interlayer insulating layers 320 and relatively for the interlayer insulating layers present in the lower layer. Stress-resistant materials can be used. Therefore, the level of stress applied to each of the plurality of interlayer insulating layers 320 may be uniform.

Referring to FIG. 4, an embodiment of the present invention uses different materials for each of the plurality of interlayer insulating layers as shown in FIG. 3, while designing different physical structures of each of the plurality of interlayer insulating layers. can do. Here, the physical structure may be determined by the thickness, length, etc. of each of the plurality of interlayer insulating layers. In this case, the plurality of interlayer insulating layers include a top interlayer insulating layer, a bottom interlayer insulating layer, and a middle interlayer insulating layer. Therefore, hereinafter, the physical structure of each of the plurality of interlayer insulating layers may be differently designed may mean that the physical structure of each of the plurality of interlayer insulating layers is differently designed.

Referring back to FIG. 4, according to an embodiment of the present invention, the plurality of interlayer insulating layers 420 respectively present between the plurality of electrode layers 410 may include the interlayer insulating layer 430 of material 1 and the interlayer insulation of material 2. Layer 431, interlayer dielectric layer 432 of material 3, and interlayer dielectric layer 433 of material 4. In this case, the thicknesses of the interlayer insulating layer 430 of the material 1, the interlayer insulating layer 431 of the material 2, the interlayer insulating layer 432 of the material 3, and the interlayer insulating layer 433 of the material 4 may be different from each other. have. For example, the thickness of the interlayer insulating layer 430 of the material 1 is formed to be thicker than the thickness of the interlayer insulating layer 431 of the material 2, the interlayer insulating layer 432 of the material 3, and the interlayer insulating layer 433 of the material 4. This may make the level of stress applied to each of the plurality of interlayer insulating layers 420 uniform.

In FIG. 4, the physical structure is changed by changing the thickness of each of the plurality of interlayer insulating layers 420, but embodiments of the present invention are formed on the surfaces of each of the plurality of interlayer insulating layers 420 of various lengths. It includes a change in the pattern or the like.

As described above, the embodiment of the present invention proposes a plurality of interlayer insulating layers 420 having different physical structures as well as being formed of different materials, but is not limited thereto and is formed of the same material. A plurality of interlayer insulating layers 420 having only different physical structures may also be proposed.

Referring to FIG. 5, due to a structural problem of the 3D flash memory (for example, a problem in that the resistivity of the channel layer included in the 3D flash memory varies depending on a location), an electrode layer of an upper layer of the plurality of electrode layers 510 may be formed. Since the current density flowing in the electrode layer is different from the current density flowing in the electrode layer of the lower layer, a difference between threshold voltages of each of the plurality of electrode layers 510 may occur.

As such, the difference in the threshold voltages of the plurality of electrode layers 510 may lead to the spread of the threshold voltage distribution, and the spread of the threshold voltage may cause the reliability of the stored data and the reading process to be lowered. . Accordingly, embodiments of the present invention propose a material or physical structure of the plurality of electrode layers 510 to have a substantially uniform threshold voltage for each of the plurality of electrode layers 510. In this case, the plurality of interlayer insulating layers 520 alternately arranged with the plurality of electrode layers 510 may have a material or a physical structure to which a substantially uniform level of stress is applied to each of the above-described ones. .

Referring to FIG. 6, an embodiment of the present invention may design different physical structures of each of the plurality of electrode layers 610. Here, the physical structure may be determined by the thickness, length, etc. of each of the plurality of electrode layers 610. In this case, the plurality of electrode layers 610 may include a top electrode layer, a bottom electrode layer, and a middle electrode layer. Therefore, hereinafter, the physical structure of each of the plurality of electrode layers 610 is differently designed may mean that the physical structure of each of the plurality of intermediate electrode layers is designed differently.

For example, the plurality of electrode layers 610 may include an electrode layer 1 620, an electrode layer 2 621, an electrode layer 3 622, and an electrode layer 4 623 having different thicknesses. In this case, the thickness of the electrode layer 1 620 may be formed to be thicker than the thickness of the electrode layer 2 621, the electrode layer 3 622, and the electrode layer 4 623, and this may increase the threshold voltage of each of the plurality of electrode layers 610. It can be made uniform.

In FIG. 6, the physical structure is changed by changing the thickness of each of the plurality of electrode layers 610, but embodiments of the present invention vary the length, the pattern formed on the surface of each of the plurality of electrode layers 610, and the like. It includes.

In this case, the plurality of interlayer insulating layers 630 alternately arranged with the plurality of electrode layers 610 may have a material or a physical structure to which a substantially uniform level of stress is applied, as described above. .

Referring to FIG. 7, as shown in FIG. 6, the physical structure of each of the plurality of electrode layers may be differently designed, but different materials may be used for each of the plurality of electrode layers.

Referring back to FIG. 7, in the embodiment of the present invention, the plurality of electrode layers 710 may include an electrode layer 720 of material 1, an electrode layer 721 of material 2, an electrode layer 722 of material 3, and an electrode layer of material 4 ( 723).

Here, in the embodiment of the present invention, a material having a relatively low electrical transmission property may be used for an electrode layer existing in an upper layer among the plurality of electrode layers 710, and a relatively electrical transmission property for an electrode layer existing in a lower layer. This excellent material can be used. For example, the electrical transfer properties of the electrode layer 720 of material 1 may be superior to the electrical transfer properties of the electrode layer 723 of material 4. Therefore, the threshold voltage of each of the plurality of electrode layers 710 may be uniform.

In this case, the plurality of interlayer insulating layers 730 disposed alternately with the plurality of electrode layers 710 may have a material or a physical structure to which a substantially uniform level of stress is applied to each of the above-described ones. .

In addition, although the embodiment of the present invention proposes a plurality of electrode layers 710 having different physical structures and formed of different materials, the present invention is not limited thereto and is not limited thereto. A plurality of electrode layers 710 formed only as well may also be proposed.

Referring to FIG. 8, in the system 800, a memory 810 and a memory controller 820 are connected. In this case, the memory 810 refers to the above-described three-dimensional flash memory. The memory 810 may be not only a NAND flash memory but also a Noah flash memory to which the spirit of the present invention is applied.

The memory controller 820 provides an input signal to control the operation of the memory 810.

For example, the system 500 controls input / output data by transmitting a command of a host when the memory controller used in the memory card is related to the memory, or controls various data in the memory based on an authorized control signal.

This structure is applied not only to simple memory cards but also to many digital devices that use memory, and applies to all digital devices that need memory such as portable digital cameras and mobile phones.

Referring to FIG. 9, a case in which a 3D flash memory is a NAND flash memory having a structure in which cell transistors are connected in series to form a unit string, and the unit strings are connected in parallel between a bit line and a ground line. . In this case, as shown in FIG. 9A, as the length of the string increases, the resistance of the channel layer increases, and as the read current applied to the bit line flows along the channel layer, the current density becomes weaker as the lower portion of the string decreases. Can be. In FIG. 10, as shown in FIG. 9B, the number of stacks of cells included in the string is changed to 10, 30, and 50 stages, respectively, and the program bias of 10V is applied to the upper and lower cells, respectively. The experiment to check the drain current according to the gate voltage when performing the read operation of the stored data by applying a.

Referring to FIG. 10, it can be seen that the top and

bottom drain currents

1030 and 1040 when the number of stacked cells is 30 stages are reduced than the top and

bottom drain currents

1010 and 1020 when the number of cells stacked is 10 stages. In addition, it can be seen that the

drain currents

1050 and 1060 of the top and bottom when the number of stacked cells is 50 stages are lower than the

drain currents

1030 and 1040 of the top and the bottom when the number of stacked cells is 30 stages.

In addition, the gate voltage difference according to the number of stacked cells is shown in Table 1 below.

Table 1

	10-speed cell		30-speed cell		50-speed cell
	top	bottom	top	bottom	top	bottom
Saturation Drain Current [A]	3.69E-05	3.69E-05	3.69E-05	3.69E-05	3.69E-05	3.69E-05
Vt [V]	0.7247	0.6549	0.6530	0.5080	0.4715	0.2633
ΔVt [V]	0.0698		0.1450		0.2082

Referring to Table 1, it can be seen that as the number of stacked 3D NAND flash memories increases, the difference in the threshold voltage between the upper cell and the lower cell increases. In other words, when the number of cells is small, the difference in the threshold voltage according to the position of the cell is insignificant. However, when the number of cells becomes large, the distribution of the threshold voltages may spread. This result is particularly deteriorated in the reading process of data stored in a MLC (Multi Level Cell) that stores two bits of information per cell.

Referring to FIG. 11, by adjusting the thicknesses of the plurality of electrode layers, which are the gate layers of the 3D flash memory, the threshold voltage distributions according to the changed thicknesses are compared.

When the thickness of each of the plurality of electrode layers is fixed to 40 nm as shown in (a), it can be seen that the difference between the

threshold voltages

1110 and 1120 between the upper electrode layer and the lower electrode layer among the plurality of electrode layers is 0.2082.

In addition, as shown in (b), when the upper electrode layer is set to 70 nm and the lower electrode layer is set to 40 nm, the thickness of each of the plurality of electrode layers is increased as the thickness of the upper electrode layer increases. It can be seen that the difference between the

threshold voltages

1130 and 1140 between the electrode layer and the lower electrode layer is 0.3918.

In addition, as shown in (c), when the upper electrode layer is set to 10 nm and the lower electrode layer is set to 40 nm, the thickness of each of the plurality of electrode layers decreases as the upper portion is increased, the upper electrode layer among the plurality of electrode layers. It can be seen that the difference between the

threshold voltages

1150 and 1160 between the electrode layer and the lower electrode layer is -0.2198.

In addition, as shown in (d), when the upper electrode layer is set to 20 nm and the lower electrode layer is set to 40 nm, the thickness of each of the plurality of electrode layers decreases as the upper portion is increased, the upper electrode layer among the plurality of electrode layers. It can be seen that the difference between the

threshold voltages

1170 and 1180 between the electrode layer and the lower electrode layer is 0.0039.

That is, it can be seen that the threshold voltage distribution can be improved by forming the thickness of each of the plurality of electrode layers as the thickness becomes lower. Therefore, the physical structure of each of the plurality of electrode layers is differently designed such that the thickness of the first electrode layer among the plurality of electrode layers is thicker than the thickness of the second electrode layer existing on the upper layer of the first electrode layer. Can improve their threshold voltage distribution.

Although the embodiments have been described by the limited embodiments and the drawings as described above, various modifications and variations are possible to those skilled in the art from the above description. For example, the described techniques may be performed in a different order than the described method, and / or components of the described systems, structures, devices, circuits, etc. may be combined or combined in a different form than the described method, or other components. Or even if replaced or substituted by equivalents, an appropriate result can be achieved.

Therefore, other implementations, other embodiments, and equivalents to the claims are within the scope of the claims that follow.

Claims

In three-dimensional flash memory,

Channel layer;

A plurality of electrode layers connected to the channel layer and stacked vertically; And

A plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically;

Including,

Each of the plurality of electrode layers has a different physical structure or is formed of different materials.
The method of claim 1,

The thickness of the first electrode layer of the plurality of electrode layers is formed thicker than the thickness of the second electrode layer existing on the upper layer of the first electrode layer.
The method of claim 1,

The length of each of the plurality of electrode layers or the pattern formed on the surface of each of the plurality of electrode layers are different from each other three-dimensional flash memory.
The method of claim 1,

The material forming the first electrode layer of the plurality of electrode layers has a better electrical transfer characteristics than the material of the second electrode layer existing on the upper layer of the first electrode layer.
The method of claim 1,

Each of the at least two electrode layers of the plurality of electrode layers is formed of a different material.
The method of claim 1,

And an interlayer oxide film, the silicon nitride film, and a tunnel oxide film between each of the plurality of electrode layers and the channel layer.
In three-dimensional flash memory,

Channel layer;

A plurality of electrode layers connected to the channel layer and stacked vertically; And

A plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically;

Including,

Each of the plurality of interlayer insulating layers may be formed of different materials or have different physical structures.
The method of claim 7, wherein

The material forming the first interlayer insulating layer of the plurality of interlayer insulating layers has a stress-resistant property than the material of the second interlayer insulating layer present on the first interlayer insulating layer.
The method of claim 7, wherein

At least two interlayer insulating layers of the plurality of interlayer insulating layers are formed of different materials.
The method of claim 7, wherein

The thickness of the first interlayer insulating layer of the plurality of interlayer insulating layers is formed thicker than the thickness of the second interlayer insulating layer existing on the upper layer of the first interlayer insulating layer.
The method of claim 7, wherein

The length of each of the plurality of interlayer insulating layers or a pattern formed on a surface of each of the plurality of interlayer insulating layers are different from each other.
The method of claim 7, wherein

And an interlayer oxide film, the silicon nitride film, and a tunnel oxide film between each of the plurality of electrode layers and the channel layer.
In three-dimensional flash memory,

Channel layer;

A plurality of electrode layers connected to the channel layer and stacked vertically; And

A plurality of interlayer insulating layers connected to the channel layer, alternately disposed with the plurality of electrode layers, and stacked vertically;

Including,

Each of the plurality of interlayer insulating layers may be formed of different materials or have different physical structures.

Each of the plurality of electrode layers may be formed of different materials or have different physical structures.