WO2015109802A1 - 薄膜晶体管及其制备方法、阵列基板 - Google Patents

薄膜晶体管及其制备方法、阵列基板 Download PDF

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Publication number
WO2015109802A1
WO2015109802A1 PCT/CN2014/083072 CN2014083072W WO2015109802A1 WO 2015109802 A1 WO2015109802 A1 WO 2015109802A1 CN 2014083072 W CN2014083072 W CN 2014083072W WO 2015109802 A1 WO2015109802 A1 WO 2015109802A1
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layer
buffer
buffer layer
thin film
film transistor
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PCT/CN2014/083072
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English (en)
French (fr)
Inventor
李正亮
刘震
丁录科
张斌
曹占锋
惠官宝
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京东方科技集团股份有限公司
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Priority to US14/429,059 priority Critical patent/US9653284B2/en
Publication of WO2015109802A1 publication Critical patent/WO2015109802A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/704—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings
    • H10N30/706—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings characterised by the underlying bases, e.g. substrates
    • H10N30/708—Intermediate layers, e.g. barrier, adhesion or growth control buffer layers

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, and an array substrate. Background technique
  • the liquid crystal display is provided with a Thin Film Transistor (TFT) on the substrate, and the thin film transistor is a key component of the liquid crystal display, which has a very important influence on the performance of the display device.
  • TFT Thin Film Transistor
  • Each of the pixel units in the liquid crystal display is driven by a TFT provided therein, so that high-speed, high-brightness, high-contrast display can be achieved.
  • a low-resistance copper film has been used as an electrode and a wiring of a thin film transistor in a semiconductor integrated circuit, a liquid crystal display or the like, and since the resistance of copper is low, the transmission speed of a digital signal can be improved, and power consumption can be reduced.
  • the adhesion between the copper thin film and the semiconductor active layer in the thin film transistor is inferior, and in addition, copper atoms in the copper thin film are diffused into the semiconductor active layer in contact therewith, affecting the characteristics of the semiconductor active layer.
  • the adhesion between the copper film and the underlying substrate and the insulating layer is also poor, and the copper film is easily peeled off during actual use, thereby reducing the life of the product.
  • Embodiments of the present invention provide a thin film transistor, a method of fabricating the same, and an array substrate for improving adhesion between a thin film transistor electrode and a film layer in contact therewith, and effectively preventing atomic diffusion in a thin film transistor electrode In the film layer in contact with it, the reliability of the thin film transistor is improved, and the production cost is lowered.
  • an embodiment of the present invention provides a thin film transistor including: a gate, a source, and a drain, the thin film transistor further includes a buffer layer, and the buffer layer is directly disposed on the gate and the source One or both sides of at least one of the drain and the drain, wherein the buffer layer and the at least one of the gate, the source, and the drain in direct contact with the buffer layer are conformal.
  • embodiments of the present invention also provide an array substrate including a sweep that crosses each other A line and a data line; a plurality of pixel units defined by the scan lines and the data lines crossing each other, wherein each of the pixel units includes the thin film transistor described above.
  • an embodiment of the present invention further provides a method of fabricating a thin film transistor, including a method of preparing a gate, a source, and a drain, the method further comprising: the gate, the source, and Forming a buffer layer directly on one or both sides of at least one of the drains, wherein the buffer layer directly contacts the gate, source, and/or region of the buffer layer during etching
  • the drain is formed using the same etchant.
  • FIG. 1 is a cross-sectional structural view showing a buffer layer on a side of a gate electrode in a thin film transistor according to a first embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view showing a buffer layer on a source and a drain side of a thin film transistor according to a second embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional view showing a buffer layer on a side of a gate, a source, and a drain of a thin film transistor according to a third embodiment of the present invention
  • FIG. 4 is a schematic cross-sectional view showing a buffer layer on both sides of a gate electrode in a thin film transistor according to an embodiment of the present invention
  • FIG. 5 is a schematic cross-sectional view showing a buffer layer on both sides of a source and a drain in a thin film transistor according to an embodiment of the present invention
  • FIG. 6 is a schematic cross-sectional view showing a buffer layer on a side of a gate, a source, and a drain of a thin film transistor according to an embodiment of the present invention
  • FIG. 7 is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide a thin film transistor and a method of fabricating the same, and an array substrate for improving adhesion between a thin film transistor electrode and a film layer connected thereto, and effectively preventing atom diffusion in a thin film transistor electrode In the film layer connected thereto, the reliability of the thin film transistor is improved, and the production cost is lowered.
  • a thin film transistor provided by an embodiment of the present invention includes: a gate, a source, and a drain, wherein the thin film transistor further includes a buffer layer, and the buffer layer is directly disposed in the gate, the source, and the drain
  • the buffer layer is directly disposed in the gate, the source, and the drain
  • One or both sides of at least one of the buffer layers and at least one of the gate, the source and the drain in direct contact with the buffer layer are conformal, and are etched with the same etching solution owned.
  • the following description is based on a bottom gate type thin film transistor, but the embodiment of the present invention does not limit the type of the thin film transistor.
  • the thin film transistor according to the embodiment of the present invention may also be a top gate type thin film transistor.
  • a first embodiment of the present invention provides a thin film transistor including: a gate electrode 12 on a substrate substrate 10, for example, a glass substrate 10; a gate insulating layer on the gate electrode 12. a semiconductor active layer 14 on the gate insulating layer 13; a source 15 and a drain 16 on the semiconductor active layer 14, wherein the thin film transistor further includes a gate electrode 12 and a substrate 10 Buffer layer 11.
  • the gate electrode 12 is formed in conformal with the buffer layer 11.
  • the gate electrode 12 contains metallic copper (Cu), and the gate electrode 12 is, for example, a single-layer metal electrode formed of metallic copper, or is made of metallic copper and other metals such as metal molybdenum (Mo), aluminum (A1), and nickel.
  • a multilayer metal electrode composed of (Ni) or the like. Since the electrode contains copper atoms, adhesion in the actual use and problems caused by diffusion of Cu atoms occur, so that a buffer layer 11 is formed between the gate electrode 12 and the base substrate 10. Alternatively, a buffer layer 11 may be formed between the gate electrode 12 and the gate insulating layer 13.
  • the source 15 and the drain 16 may be a single-layer metal electrode formed of metallic copper, or may be composed of metallic copper and other metals such as metal molybdenum (Mo), aluminum (A1), nickel (Ni), and the like. Multilayer metal electrode.
  • the semiconductor active layer 14 may include amorphous silicon (a-si) and doped amorphous silicon (n+ a-si), wherein the doped amorphous silicon has good ohmic contact with the metal.
  • the material of the buffer layer 11 in this embodiment of the present invention is an alloy material, for example,
  • the alloy material is CuaXbNc, wherein X represents a non-copper metal element, for example, X is a metal calcium (Ca), magnesium (Mg), lithium (Li), ytterbium (Ge), strontium (Sr), bismuth (Ba) element.
  • X represents a non-copper metal element
  • X is a metal calcium (Ca), magnesium (Mg), lithium (Li), ytterbium (Ge), strontium (Sr), bismuth (Ba) element.
  • the metal X element has a mass percentage of 0.05%-30%
  • the N mass percentage is 0.05%-30%
  • the balance is Cu, wherein a, b and c are both greater than 1
  • An integer whose specific value is determined based on the mass percentage of Cu, X, and N, and a specific example is not given here.
  • the Cu a X b N c buffer layer according to the embodiment of the present invention has high adhesion to the substrate, is not easily peeled off, and has a good barrier effect on Cu atoms, and can block the diffusion of Cu atoms.
  • the gate electrode 12, the source electrode 15 and the drain electrode 16 according to an embodiment of the present invention are a single-layer metal electrode formed of metallic copper, or a multilayer metal electrode composed of metallic copper and other metals, a copper thin film It is difficult to use dry etching, generally using wet etching, and the buffer layer according to the embodiment of the present invention can use the same etching liquid as the gate, the source and/or the drain during the etching process, In the actual production process, the buffer layer and the gate on one side or both sides of the gate can be simultaneously etched by only one etching process, or the etching is located on the source or the drain side or both sides. The layer and the source and drain are reduced, thereby reducing the etching process and reducing the production cost.
  • a first embodiment of the present invention further provides a method of fabricating a thin film transistor, comprising: preparing a substrate, forming a gate insulating layer, forming a semiconductor active layer, forming a source and a drain, wherein forming a gate
  • the electrode insulating layer, the formation of the semiconductor active layer, and the formation of the source and drain electrodes are conventionally known to the inventors and will not be described herein.
  • the method of fabricating a thin film transistor according to an embodiment of the present invention further includes: preparing a buffer layer 11 and forming a gate electrode 12. A thin film transistor fabricated according to the method of fabricating the thin film transistor is shown in FIG.
  • the buffer layer 11 and the gate electrode 12 are formed by one patterning process, and preparing the buffer layer 11 and forming the gate electrode 12 includes: placing the substrate substrate 10 in a magnetron sputtering device
  • the sputtering target mainly includes Cu, and further includes at least one alloying element of Ca, Mg, Li, Ge, Sr, Ba, etc., wherein the mass percentage of the metallic copper element in the sputtering target of the alloying element is greater than 70%, by sputtering the alloy target in a vacuum of introducing a nitriding gas, depositing a buffer material layer on the base substrate, the buffer material layer having a composition of CuaXbNc, wherein X is Ca, Mg, At least one of Li, Ge, Sr, Ba, the nitriding gas introduced is nitrogen (N 2 ) or ammonia (N3 ⁇ 4), wherein the nitriding gas introduced during the deposition of the buffer material layer is in the n
  • a patterning process generally includes processes such as photoresist coating, exposure, development, etching, and photoresist stripping, and can be carried out by using a conventional method known to the inventors. This example will not be described in detail.
  • a buffer material layer may be formed by using other sputtering methods than magnetron sputtering.
  • the embodiment of the present invention does not specifically limit the equipment used for preparing the buffer layer. .
  • a second embodiment of the present invention provides a thin film transistor including: a gate electrode 12 on a substrate substrate 10, for example, a glass substrate 10; a gate insulating layer on the gate electrode 12 a semiconductor active layer 14 on the gate insulating layer 13; a source 15 and a drain 16 over the semiconductor active layer 14, wherein the thin film transistor further includes a source 15 and a semiconductor active layer 14
  • the buffer layer 11 is located between the drain layer 16 and the semiconductor active layer 14.
  • the source and buffer layers are conformally formed and the drain and buffer layers are conformally formed.
  • the gate 12, the source 15 and the drain 16 contain metallic copper (Cu).
  • the gate 12, the source 15 and the drain 16 may be a single-layer metal electrode made of metallic copper, or may be made of metallic copper and other metals such as metallic molybdenum (Mo), aluminum (A1), nickel.
  • a buffer layer 11, of course, a buffer layer 11 may also be formed between the source 15 and the subsequent insulating layer, between the drain 16 and the subsequent insulating layer.
  • the material of the buffer layer 11 in this embodiment of the present invention is an alloy material, for example, the alloy material is CuaXbNc, wherein X represents a non-copper metal element, for example, X is a metal calcium (Ca), magnesium ( At least one of Mg, lithium (Li), yttrium (Ge), ytterbium (Sr), and barium (Ba), the mass percentage of the metal X element is 0.05% to 30%, and the mass percentage of N The content is 0.05%-30%, and the rest is Cu, wherein a, b and c are positive integers greater than 1, and the specific values thereof are determined according to the mass percentages of Cu, X and N, and specific examples are not given here.
  • X represents a non-copper metal element
  • X is a metal calcium (Ca), magnesium ( At least one of Mg, lithium (Li), yttrium (Ge), ytterbium (Sr), and barium (Ba)
  • the second embodiment of the present invention further provides a method of fabricating the thin film transistor as shown in FIG. 2, comprising: preparing a substrate, forming a gate, forming a gate insulating layer, forming a semiconductor The source layer, wherein the gate electrode is formed, the gate insulating layer is formed, and the semiconductor active layer is formed, and a common method known to the inventors is used, and details are not described herein.
  • the method of fabricating a thin film transistor according to an embodiment of the present invention further includes: preparing a buffer layer 11 and forming a source and a drain.
  • the buffer layer 11 is formed and the source and drain electrodes are formed by one patterning process.
  • the buffer layer 11 is formed and the source and drain electrodes are formed.
  • the substrate of the source layer is placed in a magnetron sputtering apparatus, the sputtering target mainly includes Cu, and further includes at least one alloying element of Ca, Mg, Li, Ge, Sr, Ba, etc., wherein the alloying element sputtering target
  • the mass percentage of the metallic copper element in the material is greater than 70%, and the buffer layer is deposited on the substrate on which the semiconductor active layer is formed by sputtering the alloy target in a vacuum through which the nitriding gas is introduced.
  • the composition of the buffer material layer is Cu a X b N c , wherein X is at least one of Ca, Mg, Li, Ge, Sr, Ba, and the nitriding gas introduced is nitrogen (N 2 ) or ammonia ( N3 ⁇ 4 ) , wherein the nitriding gas introduced during the deposition of the buffer material layer is in a mixed gas of the nitriding gas and other gases, for example, a flow ratio of 1% to 30% in a mixed gas of nitrogen and argon Forming a source/drain metal layer on the buffer material layer;
  • the punching material layer performs a patterning process in which the source and drain metal layers and the buffer material layer are etched with the same etching solution to simultaneously form the source, the drain, and the buffer layer.
  • the Cu a X b N c buffer layer in the present embodiment has high adhesion to the semiconductor active layer, is not easily peeled off, and has a good barrier effect on Cu atoms, and can block the diffusion of Cu atoms to In the semiconductor active layer.
  • a buffer material layer may be formed by using another sputtering method other than magnetron sputtering.
  • the embodiment of the present invention does not specifically limit the device used for preparing the buffer layer. .
  • a third embodiment of the present invention further provides a thin film transistor including: a gate electrode 12 on a substrate substrate 10, for example, a glass substrate 10; and a gate insulating layer on the gate electrode 12. a semiconductor active layer 14 on the gate insulating layer 13; a source 15 and a drain 16 over the semiconductor active layer 14, wherein the thin film transistor further includes a gate electrode 12 and a substrate 10
  • the buffer layer 11, the buffer layer 11 between the source 15 and the semiconductor active layer 14, is located on the buffer layer 11 between the drain 16 and the semiconductor active layer 14.
  • the buffer layer 11 may also be located between the gate 12 and the gate insulating layer 13 between the source 15 and the subsequent insulating layer, between the drain 16 and the subsequent insulating layer.
  • the material of the buffer layer 11 in FIG. 3 is also CuXN, which is made by The preparation method is similar to the preparation method of the buffer layer in FIGS. 1 and 2, and details are not described herein.
  • the buffer layer and the gate electrode 12, the source electrode 15, and the drain electrode 16 which are in direct contact with the buffer layer are formed in conformal shape.
  • the buffer layers in FIGS. 1, 2, and 3 are all located on one side of the gate and/or the source and the drain, and the buffer layer may also be located at the gate and/or the source and the drain.
  • the buffer layer 11 is located on both sides of the gate electrode 12.
  • the buffer layer 11 is located on both sides of the source and the drain; as shown in FIG. 6, the buffer layer 11 is located on both sides of the source and drain, and is also located on both sides of the gate 12.
  • the case where the buffer layer is located on both sides of the gate and/or the source and the drain is similar to the case of the gate and/or the source and the drain, and will not be described herein.
  • an embodiment of the present invention further provides an array substrate.
  • the array substrate includes scan lines (not shown) and data lines (not shown) crossing each other,
  • the insulating layer 17 and the pixel electrode 18 are made of, for example, Indium Tin Oxide (ITO).
  • ITO Indium Tin Oxide
  • the scan lines and data lines crossing each other define a plurality of pixel units, each of which includes a thin film transistor according to any of the embodiments of the present invention.
  • the array substrate according to an embodiment of the present invention may further include a buffer layer on one side or both sides of the scan line, the material of the buffer layer being an alloy material, exemplarily, in the implementation of the present invention
  • the alloy material is Cu a X b N c
  • X represents a non-copper metal element
  • X is a metal calcium (Ca), magnesium (Mg), lithium (Li), ytterbium (Ge), yttrium (Sr)
  • the mass percentage of the metal X element is 0.05%-30%
  • the mass percentage of N is 0.05%-30%
  • the balance is Cu, wherein a, b And c are positive integers greater than 1, and the specific values thereof are determined according to the mass percentages of Cu, X and N, and specific examples are not given here.
  • the material of the scan line according to the embodiment of the present invention is metallic copper. Since the resistance of the metal copper is low, the embodiment of the present invention can well reduce the resistance of the scan line.
  • the buffer layer on one or both sides of the scan line of the array substrate has a good blocking effect on Cu atoms and can block the diffusion of Cu atoms in the scan lines.
  • the buffer layer uses the same etching liquid as the scan line during the etching process, and the buffer layer and the scan line can be simultaneously formed by only one etching process in the actual production process. Thereby reducing the etching process and reducing the production cost.
  • the array substrate according to the embodiment of the present invention may further include a buffer layer on one side or both sides of the data line, the material of the buffer layer being an alloy material, such as Cu a X b N c , wherein X represents a non-copper metal element, for example, X is a metal calcium (Ca ), strontium (Mg), At least one of lithium (Li), yttrium (Ge), strontium (Sr), and barium (Ba), the mass percentage of metal X is 0.05%-30%, and the mass percentage of N is 0.05.
  • X represents a non-copper metal element
  • X is a metal calcium (Ca ), strontium (Mg), At least one of lithium (Li), yttrium (Ge), strontium (Sr), and barium (Ba)
  • the mass percentage of metal X is 0.05%-30%
  • the mass percentage of N is 0.05.
  • the material of the data line is metallic copper. Since the electrical resistance of the metallic copper is low, in the embodiment of the present invention, the resistance of the data line can be well reduced, thereby reducing energy consumption.
  • the buffer layer on one side or both sides of the data line of the array substrate has a good blocking effect on Cu atoms, and can block the diffusion of Cu atoms in the data lines.
  • the buffer layer uses the same etching liquid as the data line during the etching process, and in the actual production process, the buffer layer and the data can be simultaneously formed by only one etching process. Line, which reduces the etching process and reduces production costs.
  • At least one of a gate, a source, and a drain is performed by sputtering an alloy target in a vacuum in which a nitriding gas is introduced.

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Abstract

提供了一种薄膜晶体管及其制备方法以及阵列基板。该薄膜晶体管包括：栅极（12）、源极（15）和漏极（16），薄膜晶体管还包括缓冲层（11），缓冲层（11）直接设置在栅极（12）、源极（15）和漏极（16）中的至少之一的一侧或两侧，其中，缓冲层（11）和与该缓冲层（11）直接接触的栅极（12）、源极（15）和漏极（16）中的至少之一共形。这样，薄膜晶体管的电极和与之相接触的膜层之间的密接性被改善，同时有效的阻止了薄膜晶体管电极中的原子扩散到与之相连的膜层中，提高了薄膜晶体管的可靠性，降低了生产成本。

Description

薄膜晶体管及其制备方法、 阵列基板 技术领域
本发明的实施例涉及一种薄膜晶体管及其制备方法、 阵列基板。 背景技术
液晶显示器在基板上配置有薄膜晶体管 （Thin Film Transistor, TFT ) ， 而薄膜晶体管是液晶显示器的关键器件， 对显示器件的工作性能具有十分重 要的影响。 液晶显示器中的每一个像素单元都由其中所设置的 TFT来驱动， 从而可以做到高速度、 高亮度、 高对比度显示。
近年来， 开始使用低电阻的铜薄膜作为半导体集成电路、 液晶显示器等 中的薄膜晶体管的电极以及布线， 由于铜的电阻较低， 可以提高数字信号的 传输速度， 并降低耗电量。 然而， 铜薄膜与薄膜晶体管中的半导体有源层的 密接性较差，此外，铜薄膜中的铜原子会扩散至与之接触的半导体有源层中， 影响半导体有源层的特性。 另外， 铜薄膜与衬底基板以及绝缘层的密接性也 较差， 在实际使用过程中， 铜薄膜容易脱落， 从而降低产品的寿命。
由此， 釆用低电阻的铜薄膜制作薄膜晶体管的电极时， 会降低薄膜晶体 管的可靠性。 发明内容
本发明的实施例提供了一种薄膜晶体管及其制备方法、 阵列基板， 用以 提高薄膜晶体管电极和与之相接触的膜层之间的密接性， 同时有效的阻止薄 膜晶体管电极中的原子扩散到与之相接触的膜层中， 提高薄膜晶体管的可靠 性， 降低生产成本。
一方面， 本发明的实施例提供一种薄膜晶体管， 包括： 栅极、 源极和漏 极， 所述薄膜晶体管还包括緩冲层， 所述緩冲层直接设置在所述栅极、 源极 和漏极中的至少之一的一侧或两侧， 其中， 所述緩冲层和与该緩冲层直接接 触的所述栅极、 源极和漏极中的所述至少之一共形。
另一方面， 本发明的实施例还提供了一种阵列基板， 包括彼此交叉的扫 描线和数据线； 多个像素单元， 由彼此交叉的所述扫描线和所述数据线定义， 其中， 每个像素单元包括以上所述的薄膜晶体管。
再一方面， 本发明的实施例还提供了一种薄膜晶体管的制备方法， 包括 制备栅极、 源极和漏极的方法， 所述方法还包括： 在所述栅极、 所述源极和 所述漏极至少之一的一侧或两侧直接形成緩冲层， 其中， 所述緩冲层在刻蚀 过程中与该緩冲层直接接触的所述栅极、源极和 /或所述漏极使用相同的刻蚀 液共形形成。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明第一实施例提供的薄膜晶体管中緩冲层位于栅极一侧的截 面结构示意图；
图 2为本发明第二实施例提供的薄膜晶体管中緩冲层位于源极和漏极一 侧的截面结构示意图；
图 3为本发明第三实施例提供的薄膜晶体管中緩冲层位于栅极、 源极和 漏极一侧的截面结构示意图；
图 4为本发明实施例提供的薄膜晶体管中緩冲层位于栅极两侧的截面结 构示意图；
图 5为本发明实施例提供的薄膜晶体管中緩冲层位于源极和漏极两侧的 截面结构示意图；
图 6为本发明实施例提供的薄膜晶体管中緩冲层位于栅极、 源极和漏极 两侧的截面结构示意图； 以及
图 7为本发明实施例提供的阵列基板的截面结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明的实施例提供了一种薄膜晶体管及其制备方法、 阵列基板， 用以 提高薄膜晶体管电极和与之相连的膜层之间的密接性， 同时有效的阻止薄膜 晶体管电极中的原子扩散到与之相连的膜层中， 提高薄膜晶体管的可靠性， 降低生产成本。
本发明的实施例提供的薄膜晶体管， 包括： 栅极、 源极和漏极， 其中该 薄膜晶体管还包括緩冲层， 所述緩冲层直接设置在所述栅极、 源极和漏极中 的至少之一的一侧或两侧，且所述緩冲层和与该緩冲层直接接触的所述栅极、 源极和漏极至少之一共形， 是釆用相同刻蚀液刻蚀得到的。
下面给出本发明的实施例提供的技术方案的详细介绍。
以下的说明是以底栅型薄膜晶体管作为示例， 但是本发明的实施例并不 对薄膜晶体管的类型做限定， 根据本发明实施例的薄膜晶体管也可以为顶栅 型薄膜晶体管。
第一实施例
如图 1所示， 本发明的第一实施例提供了一种薄膜晶体管， 包括： 位于 衬底基板 10， 例如， 玻璃基板 10 ， 上方的栅极 12; 位于栅极 12上的栅极 绝缘层 13; 位于栅极绝缘层 13上的半导体有源层 14; 位于半导体有源层 14 上的源极 15和漏极 16， 其中， 该薄膜晶体管还包括位于栅极 12和衬底基板 10之间的緩冲层 11。 而且， 栅极 12与緩冲层 11共形形成。 这里， 栅极 12 中含有金属铜 （Cu ) ， 栅极 12例如为由金属铜形成的单层金属电极， 或为 由金属铜和其它金属， 如金属钼（Mo ) 、 铝（A1 ) 、 镍（Ni )等组成的多层 金属电极。 由于电极中含有铜原子， 在实际使用中会出现粘附性以及 Cu原 子扩散导致的问题， 因此在栅极 12和衬底基板 10之间形成一层緩冲层 11。 备选地， 也可以在栅极 12和栅极绝缘层 13之间形成一层緩冲层 11。
示例性地， 源极 15和漏极 16可以为由金属铜形成的单层金属电极， 或 为由金属铜和其它金属， 如金属钼（Mo ) 、 铝（A1 ) 、 镍（Ni )等组成的多 层金属电极。半导体有源层 14可以包括非晶硅（ a-si )和掺杂非晶硅（ n+ a-si ) , 其中， 掺杂非晶硅与金属之间有良好的欧姆接触。
示例性地， 本发明该实施例中的緩冲层 11的材料为合金材料， 例如， 该 合金材料为 CuaXbNc,其中 X表示非铜的金属元素，例如， X为金属钙（ Ca )、 镁（Mg ) 、 锂（Li ) 、 锗（Ge ) 、 锶（Sr ) 、 钡（Ba )元素中的至少一种元 素， 金属 X 元素的质量百分含量为 0.05%-30%， N 的质量百分含量为 0.05%-30%, 其余为 Cu， 其中 a、 b和 c均为大于 1的正整数， 其具体取值根 据 Cu、 X和 N的质量百分含量确定， 这里不给出具体示例。 这样， 根据本 发明实施例的 CuaXbNc緩冲层与衬底基板的粘合性较高， 不易剥离， 而且对 Cu原子有较好的阻挡性作用， 能够阻挡 Cu原子的扩散。
备选地， 由于根据本发明实施例的栅极 12、 源极 15和漏极 16为由金属 铜形成的单层金属电极， 或为由金属铜和其它金属组成的多层金属电极， 铜 薄膜难以釆用干法刻蚀， 一般使用湿法刻蚀， 根据本发明实施例的緩冲层在 刻蚀过程中与栅极、 源极和 /或漏极可以使用相同的刻蚀液， 则在实际的生产 过程中可以只通过一次刻蚀工艺就可同时刻蚀位于栅极一侧或两侧的緩冲层 和栅极， 或同时刻蚀位于源极、 漏极一侧或两侧的緩冲层和源极、 漏极， 从 而减少了一次刻蚀工艺， 降低了生产成本。
此外，本发明的第一实施例还提供了一种薄膜晶体管的制备方法， 包括： 准备衬底基板、 形成栅极绝缘层、 形成半导体有源层、 形成源极和漏极， 其 中， 形成栅极绝缘层、 形成半导体有源层、 形成源极和漏极釆用发明人已知 的常用方法， 在此不予赘述。 此外， 根据本发明实施例的制备薄膜晶体管的 方法还包括： 制备緩冲层 11和形成栅极 12。 根据该薄膜晶体管的制备方法 制得的薄膜晶体管如图 1所示。
示例性地， 在本发明的实施例中， 緩冲层 11和栅极 12通过一次构图工 艺形成，制备緩冲层 11和形成栅极 12包括：将衬底基板 10放入磁控溅射设 备中， 溅射靶体主要包括 Cu， 还包括 Ca、 Mg、 Li、 Ge、 Sr、 Ba等中的至少 一种合金元素， 其中该合金元素溅射靶材中金属铜元素的质量百分含量大于 70%, 通过在通入氮化气体的真空中对合金靶材进行溅射， 在衬底基板上沉 积得到緩冲材料层， 该緩冲材料层的成分为 CuaXbNc, 其中 X为 Ca、 Mg、 Li、 Ge、 Sr、 Ba中的至少一种，通入的氮化气体为氮气（N2 )或氨气（N¾ )， 其中在緩冲材料层沉积时通入的氮化气体在氮化气体与其他气体的混合气体 中， 例如， 在氮气和氩气的混合气体中所占的流量比 1%-30%； 在緩冲材料 层上形成栅极金属层； 对栅极金属层及緩冲材料层实施一次构图工艺， 其中 釆用相同的蚀刻溶液蚀刻栅极金属层以及緩冲材料层以同时形成栅极和緩冲 层。
示例性地， 根据本发明实施例的一次构图工艺通常包括光刻胶涂覆、 曝 光、 显影、 刻蚀以及光刻胶剥离等工序， 可以釆用发明人已知的常用方法， 本发明的实施例对此不做详细描述。
示例性地， 本发明的实施例中还可以釆用除磁控溅射外的其它溅射方法 形成緩冲材料层， 本发明的实施例并不对制备緩冲层时釆用的设备作具体限 定。
第二实施例
如图 2所示， 本发明的第二实施例提供了一种薄膜晶体管， 包括： 位于 衬底基板 10， 例如， 玻璃基板 10， 上的栅极 12; 位于栅极 12上的栅极绝缘 层 13;位于栅极绝缘层 13上的半导体有源层 14;位于半导体有源层 14上方 的源极 15和漏极 16， 其中， 该薄膜晶体管还包括位于源极 15和半导体有源 层 14之间的緩冲层 11， 位于漏极 16和半导体有源层 14之间的緩冲层 11。 而且， 源极和緩冲层共形形成以及漏极和緩冲层共形形成。 图 2中栅极 12、 源极 15和漏极 16中含有金属铜（Cu ) 。 示例性地， 栅极 12、 源极 15和漏 极 16可以为由金属铜制成的单层金属电极，或为由金属铜和其它金属，如金 属钼（Mo ) 、 铝（A1 ) 、 镍（Ni )等组成的多层金属电极。 由于电极中包含 铜， 在实际使用中会出现粘附性以及 Cu原子易扩散导致的问题， 因此在源 极 15和半导体有源层 14之间、 漏极 16和半导体有源层 14之间形成一层緩 冲层 11， 当然， 也可以在源极 15和后续的绝缘层之间、 漏极 16和后续的绝 缘层之间形成一层緩冲层 11。
示例性地， 本发明该实施例中的緩冲层 11的材料为合金材料， 例如， 该 合金材料为 CuaXbNc,其中 X表示非铜的金属元素，例如， X为金属钙（ Ca )、 镁（Mg ) 、 锂（Li ) 、 锗（Ge ) 、 锶（Sr ) 、 钡（Ba )元素中的至少一种元 素， 金属 X 元素的质量百分含量为 0.05%-30%， N 的质量百分含量为 0.05%-30%, 其余为 Cu， 其中 a、 b和 c均为大于 1的正整数， 其具体取值根 据 Cu、 X和 N的质量百分含量确定， 这里不给出具体示例。
备选地， 本发明的第二实施例还提供一种制备如图 2所示的薄膜晶体管 的方法， 包括： 准备衬底基板、 形成栅极、 形成栅极绝缘层、 形成半导体有 源层， 其中， 形成栅极、 形成栅极绝缘层、 形成半导体有源层釆用发明人已 知的常用方法， 在此不予赘述。 此外， 根据本发明实施例的制备薄膜晶体管 的方法还包括： 制备緩冲层 11和形成源极和漏极。
示例性地，在本发明的实施例中，制备緩冲层 11和形成源极和漏极釆用 一次构图工艺形成，制备緩冲层 11和形成源极和漏极包括：将制作有半导体 有源层的基板放入磁控溅射设备中，溅射靶体主要包括 Cu，还包括 Ca、 Mg、 Li、 Ge、 Sr、 Ba等中的至少一种合金元素， 其中该合金元素溅射靶材中金属 铜元素的质量百分含量大于 70%， 通过在通入氮化气体的真空中对合金靶材 进行溅射， 在制作有半导体有源层的基板上沉积得到緩冲材料层， 该緩冲材 料层的成分为 CuaXbNc， 其中 X为 Ca、 Mg、 Li、 Ge、 Sr、 Ba中的至少一种， 通入的氮化气体为氮气（N2 )或氨气（N¾ ) ， 其中在緩冲材料层沉积时通 入的氮化气体在氮化气体与其他气体的混合气体中， 例如， 在氮气和氩气的 混合气体中所占的流量比 1%-30%； 在緩冲材料层上形成源漏极金属层； 对 源漏极金属层及緩冲材料层实施一次构图工艺， 其中釆用相同的蚀刻溶液蝕 刻源漏极金属层以及緩冲材料层以同时形成源极、 漏极和緩冲层。
本实施例中的 CuaXbNc緩冲层与半导体有源层的粘合性较高，不易剥离， 而且对 Cu原子有较好的阻挡性作用，能够艮好的阻挡 Cu原子扩散到半导体 有源层中。
示例性地， 本本发明的实施例中还可以釆用除磁控溅射外的其它溅射方 法形成緩冲材料层， 本发明的实施例并不对制备緩冲层时釆用的设备作具体 限定。
第三实施例
如图 3所示， 本发明的第三实施例还提供一种薄膜晶体管， 包括： 位于 衬底基板 10， 例如， 玻璃基板 10， 上方的栅极 12; 位于栅极 12上的栅极绝 缘层 13; 位于栅极绝缘层 13上的半导体有源层 14; 位于半导体有源层 14 上方的源极 15和漏极 16， 其中， 该薄膜晶体管还包括位于栅极 12和衬底基 板 10之间的緩冲层 11， 位于源极 15和半导体有源层 14之间的緩冲层 11， 位于漏极 16和半导体有源层 14之间的緩冲层 11。 备选地， 緩冲层 11还可 以位于栅极 12和栅极绝缘层 13之间，位于源极 15和后续的绝缘层之间、漏 极 16和后续的绝缘层之间。 图 3中的緩冲层 11的材料同样为 CuXN， 其制 备方法与图 1和图 2中緩冲层的制备方法类似， 在此不予赘述。
这里， 緩冲层和与该緩冲层直接接触的栅极 12、 源极 15、 漏极 16共形 形成。
备选地， 图 1、 图 2、 图 3中的緩冲层均位于栅极和 /或源极和漏极的一 侧， 緩冲层还可以位于栅极和 /或源极和漏极的两侧， 如图 4 所示， 緩冲层 11位于栅极 12的两侧； 如图 5所示， 緩冲层 11位于源极和漏极的两侧； 如 图 6所示， 緩冲层 11位于源极和漏极的两侧， 同时也位于栅极 12的两侧。 緩冲层位于栅极和 /或源极和漏极的两侧的情况与位于栅极和 /或源极和漏极 的一侧的情况类似， 在此不予赘述。
备选地， 本发明的实施例中还提供了一种阵列基板， 如图 7所示， 阵列 基板包括彼此交叉的扫描线（图中未示出）和数据线（图中未示出） 、 绝缘 层 17和像素电极 18， 其中像素电极 18的材料例如为氧化铟锡（ Indium Tin Oxide, ITO ) 。 这里， 彼此交叉的扫描线和数据线定义多个像素单元， 每个 像素单元包括根据本发明任一实施例的薄膜晶体管。
示例性地， 根据本发明实施例的阵列基板还可以包括位于所述扫描线的 一侧或两侧的緩冲层， 该緩冲层的材料为合金材料， 示例性地， 在本发明的 实施例中该合金材料为 CuaXbNc， 其中 X表示非铜的金属元素， 例如， X为 金属钙 （ Ca ) 、 镁（ Mg ) 、 锂（ Li ) 、 锗（ Ge ) 、 锶（ Sr ) 、 钡 （ Ba )元 素中的至少一种元素， 金属 X元素的质量百分含量为 0.05%-30%， N的质量 百分含量为 0.05%-30%,其余为 Cu， 其中 a、 b和 c均为大于 1的正整数， 其具体取值根据 Cu、 X和 N的质量百分含量确定， 这里不给出具体示例。 根据本发明实施例的扫描线的材料为金属铜， 由于金属铜的电阻较低， 故本 发明的实施例能够很好的降低扫描线的电阻。 在本发明的实施例中， 阵列基 板的扫描线一侧或两侧的緩冲层对 Cu原子有较好的阻挡作用， 能够阻挡扫 描线中的 Cu原子扩散。 同时在本发明的实施例中， 緩冲层在刻蚀过程中与 扫描线使用相同的刻蚀液， 则在实际的生产过程中可以只通过一次蚀刻工艺 就同时形成緩冲层和扫描线， 从而减少了一次刻蚀工艺， 降低生产成本。
备选地， 根据本发明实施例的阵列基板还可以包括位于所述数据线的一 侧或两侧的緩冲层， 该緩冲层的材料为合金材料， 该合金材料例如为 CuaXbNc,其中 X表示非铜的金属元素，例如， X为金属钙（ Ca )、鍈（ Mg )、 锂（Li ) 、 锗（Ge ) 、 锶（Sr ) 、 钡 （Ba )元素中的至少一种元素， 金属 X 元素的质量百分含量为 0.05%-30%， N的质量百分含量为 0.05%-30%,其余 为 Cu， 其中 a、 b和 c均为大于 1的正整数， 其具体取值根据 Cu、 X和 N的 质量百分含量确定， 这里不给出具体示例。 其中数据线的材料为金属铜， 由 于金属铜的电阻较低， 故在本发明的实施例中， 数据线的电阻能够被很好的 降低， 进而减少能量的消耗。 另外， 在本发明的实施例中， 阵列基板的数据 线一侧或两侧的緩冲层对 Cu原子有较好的阻挡作用， 能够阻挡数据线中的 Cu原子扩散。 而且， 在本发明的实施例中， 緩冲层在刻蚀过程中与数据线使 用相同的刻蚀液， 则在实际的生产过程中可以只通过一次刻蚀工艺就同时形 成緩冲层和数据线， 从而减少了一次刻蚀工艺， 降低生产成本。
在根据本发明实施例的薄膜晶体管及其制备方法以及阵列基板中， 通过 在通入氮化气体的真空中对合金靶材进行溅射， 在栅极、 源极和漏极中的至 少一个的一侧或两侧形成緩冲层， 其中， 所述緩冲层在刻蚀过程中与所述栅 极、 源极和漏极至少之一使用相同的刻蚀液， 从而故可以提高薄膜晶体管栅 极、 源极和漏极和与之相连的膜层之间的密接性， 同时有效的阻止薄膜晶体 管栅极、 源极和漏极中的原子扩散到与之相连的膜层中， 提高薄膜晶体管的 可靠性， 降低生产成本。 发明的精神和集合。 这样， 倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的集合之内， 则本发明也意图包含这些改动和变型在内。
本申请要求于 2014年 1月 23日递交的中国专利申请第 201410032607.8 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1、 一种薄膜晶体管， 包括： 栅极、 源极和漏极， 所述薄膜晶体管还包括 緩冲层， 所述緩冲层直接设置在所述栅极、 源极和漏极中的至少之一的一侧 或两侧， 其中， 所述緩冲层和与该緩冲层直接接触的所述栅极、 源极和漏极 中的所述至少之一共形。
2、根据权利要求 1所述的薄膜晶体管， 其中所述栅极、 源极和漏极中含 有金属铜。
3、根据权利要求 1所述的薄膜晶体管，其中所述緩冲层的材料为合金材 料。
4、 根据权利要求 3所述的薄膜晶体管， 其中所述合金材料为 CuaXbNc， 其中 X表示非铜的金属元素。
5、 根据权利要求 4所述的薄膜晶体管， 其中所述 X元素的质量百分含 量为 0.05%-30%。
6、 根据权利要求 5所述的薄膜晶体管， 其中所述 X元素为钙、 镁、 锂、 锗、 锶和钡中的至少一种。
7、根据权利要求 1-6中任一项所述的薄膜晶体管， 其中所述緩冲层和与 该緩冲层直接接触的所述栅极、 源极和漏极中的所述至少之一釆用相同的蚀 刻溶液形成。
8、 一种阵列基板， 包括：
彼此交叉的扫描线和数据线；
多个像素单元， 由彼此交叉的所述扫描线和所述数据线定义，
其中， 每个像素单元包括如权利要求 1-7中任一项所述的薄膜晶体管。
9、根据权利要求 8所述的阵列基板，其中所述阵列基板还包括直接设置 于所述扫描线的一侧或两侧的緩冲层。
10、 根据权利要求 8或 9所述的阵列基板， 其中所述阵列基板还包括直 接设置于所述数据线的一侧或两侧的緩冲层。
11、根据权利要求 9或 10所述的阵列基板，其中所述緩冲层的材料为合 金材料。
12、 根据权利要求 11所述的阵列基板， 其中所述合金材料为 CuaXbNc， 其中 X表示非铜的金属元素。
13、 一种制备如权利要求 1所述的薄膜晶体管的方法， 包括制备栅极、 源极和漏极的方法， 所述方法还包括：
在所述栅极、 所述源极和所述漏极至少之一的一侧或两侧直接形成緩冲 层， 其中， 所述緩冲层在刻蚀过程中与该緩冲层直接接触的所述栅极、 源极 和 /或所述漏极使用相同的刻蚀液共形形成。
14、根据权利要求 13所述的方法， 其中形成所述緩冲层包括： 通过在通 入氮化气体的真空中对合金靶材进行溅射而形成緩冲材料层； 以及通过刻蚀 形成所述緩冲层。
15、 根据权利要求 14 所述的方法， 其中所述緩冲材料层的材料为
CuaXbNc, 其中 X表示非铜的金属元素。
16、根据权利要求 14所述的方法，其中在溅射形成緩冲层时所述通入的 氮化气体的所占的流量比为 1%-30%。
17、 根据权利要求 13所述的方法， 其中形成所述緩冲层包括： 将衬底基^ ^文入磁控溅射设备中， 通过在通入氮化气体的真空中对合金 靶材进行溅射， 在衬底基板上沉积得到緩冲材料层； 在緩冲材料层上形成栅 极金属层； 对栅极金属层及緩冲材料层实施一次构图工艺， 其中釆用相同的 蚀刻溶液蚀刻所述栅极金属层以及所述緩冲材料层以同时形成所述栅极和所 述緩冲层。
18、 根据权利要求 13所述的方法， 其中形成所述緩冲层包括： 将衬底基^^入磁控溅射设备中， 通过在通入氮化气体的真空中对合金 靶材进行溅射， 在衬底基板上沉积得到緩冲材料层； 在緩冲材料层上形成栅 极金属层； 将形成有所述栅极金属层的所述衬底基板放入所述磁控溅射设备 中， 通过在通入氮化气体的真空中对所述合金靶材进行溅射， 在形成有所述 栅极金属层的所述衬底基板上沉积得到另一緩冲材料层对所述另一緩冲材料 层、 所述栅极金属层及所述緩冲材料层实施一次构图工艺， 其中釆用相同的 蚀刻溶液蚀刻所述另一緩冲材料层、 所述栅极金属层以及所述緩冲材料层以 同时形成所述栅极和两层所述緩冲层。
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