WO2015106465A1 - 一种显示面板制作方法 - Google Patents

一种显示面板制作方法 Download PDF

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Publication number
WO2015106465A1
WO2015106465A1 PCT/CN2014/071425 CN2014071425W WO2015106465A1 WO 2015106465 A1 WO2015106465 A1 WO 2015106465A1 CN 2014071425 W CN2014071425 W CN 2014071425W WO 2015106465 A1 WO2015106465 A1 WO 2015106465A1
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Prior art keywords
display panel
semiconductor pattern
pattern
gate
metal layer
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PCT/CN2014/071425
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English (en)
French (fr)
Inventor
戴天明
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深圳市华星光电技术有限公司
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Priority to US14/413,161 priority Critical patent/US9634121B2/en
Publication of WO2015106465A1 publication Critical patent/WO2015106465A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Definitions

  • the present invention relates to a method of fabricating a display panel, and more particularly to a method of fabricating a display panel having a Lightly Doped Drain (LDD) structure Thin Film Transistor (TFT).
  • LDD Lightly Doped Drain
  • TFT Thin Film Transistor
  • an embodiment of the present invention provides a display panel manufacturing method for fabricating a display panel having a lightly doped drain structure thin film transistor matrix, and the display panel manufacturing method includes:
  • a low concentration ion doping is performed using the gate as a mask to form a lightly doped region between the heavily doped region and the semiconductor pattern region covered by the gate.
  • the center of the gate formed by etching the metal layer is aligned with the center of the photoresist pattern.
  • the edges of the opposite sides of the gate are inwardly 1HJ with respect to the corresponding side edges of the photoresist pattern by a predetermined horizontal distance.
  • the horizontal distance of the gate edge recessed inward from the edge of the photoresist pattern is 0.5 ⁇ 1.5 ⁇ .
  • the manner of etching the metal layer is selected from one of dry etching and wet etching.
  • the material of the semiconductor pattern is amorphous silicon by Excimer Laser Annealing (ELA), Metal-induced crystallization (MIC), Solid Phase Crystallization (SPC) Low temperature Poly crystalline Silicon formed.
  • ELA Excimer Laser Annealing
  • MIC Metal-induced crystallization
  • SPC Solid Phase Crystallization
  • a buffer layer may be formed on the substrate before forming the semiconductor pattern on the substrate.
  • the doped region of the semiconductor pattern is heated to between 400 degrees Celsius and 1000 degrees Celsius to activate charged ions in the lightly doped region and the heavily doped region.
  • the metal layer is formed on the dielectric layer by sputtering.
  • the projection of the photoresist pattern on the semiconductor pattern is located in a middle portion of the semiconductor pattern.
  • the projection of the opposite side edges of the photoresist pattern on the semiconductor pattern is equal to the distance between the two side edges corresponding to the semiconductor pattern.
  • the display panel manufacturing method provided by the invention only needs to etch the gate metal layer once, which not only reduces the process steps, but also avoids the superposition error caused by multiple etching, and improves the dimensional precision of the LDD structure.
  • FIG. 1 is a flow chart showing the steps of a method for fabricating a display panel according to an embodiment of the present invention.
  • FIG. 2 is a schematic view showing the structure of a display panel produced by the method for fabricating the display panel shown in Fig. 1.
  • FIG. 3 to FIG. 12 are structural diagrams showing the steps of the method for fabricating the display panel shown in FIG. 1.
  • the display panel manufacturing method is used to manufacture a display panel 1 suitable for a liquid crystal display or an organic light emitting diode display.
  • the display panel 1 includes a substrate 10 and TFTs 16 arranged in a matrix on the substrate.
  • the TFT 16 has an LDD structure.
  • the display panel manufacturing method includes the following steps:
  • step S10 the substrate 10 is provided. As shown in FIG. 3, a substrate 10 made of a transparent insulating material is provided.
  • Step S12 a semiconductor pattern 12 is formed, and as shown in FIG. 4, a semiconductor pattern 12 having a predetermined shape is formed on the substrate 10. Specifically, a semiconductor layer is deposited on the substrate 10 first.
  • the material of the reuse body pattern 12 is polycrystalline silicon formed by recrystallizing amorphous silicon by Low Temperature Polycrystalline Silicon (LTPS).
  • the low temperature polysilicon process includes Excimer Laser Annealing (ELA), Metal-induced crystallization (MIC), and Solid Phase Crystallization (SPC).
  • a buffer layer 11 may be formed on the substrate 10 before the formation of the semiconductor pattern 12 to reduce the influence of impurity molecules in the substrate 10 on the properties of the semiconductor pattern 12.
  • Step S13 forming a dielectric layer 13, as shown in FIG. 6, depositing a dielectric material on the substrate 10 to form a dielectric layer 13 overlying the semiconductor pattern 12.
  • Step S14 forming a metal layer 14, as shown in FIG. 7, a metal layer 14 is formed on the dielectric layer 13 by sputtering.
  • a photoresist pattern 15 is formed. As shown in FIG. 8, a photoresist pattern 15 is formed on the metal layer 14 directly above the semiconductor pattern 12. Specifically, a layer of photoresist is deposited on the metal layer 14. The photoresist is then exposed using a photomask having a specific pattern. The exposed photoresist material is then developed to obtain a photoresist pattern 15 corresponding to a predetermined pattern on the reticle.
  • the size of the photoresist pattern 15 is smaller than the semiconductor pattern 12.
  • a projection of the photoresist pattern 15 on the semiconductor pattern 12 is located in the middle of the semiconductor pattern 12.
  • Step S16 etching the metal layer 14 to form the gate electrode 14a.
  • the metal layer 14 is etched to form the gate electrode 14a of the TFT 16 having a specific pattern.
  • the center of the gate electrode 14a and the center of the photoresist pattern 15 are aligned with each other.
  • the size of the gate electrode 14a is smaller than the photoresist pattern 15.
  • the edges of the opposite sides of the gate electrode 14a are inwardly 1HJ with respect to the corresponding side edges of the photoresist pattern 15 by a predetermined horizontal distance L2.
  • the horizontal distance L2 is preferably 0.5 to 1.5 / w.
  • the etching process of the gate electrode 14a may be performed by dry etching or wet etching.
  • wet etching the over-etching effect of the wet etching is performed to partially etch the horizontal distance L2 inwardly after the portion of the metal layer 14 not covered by the photoresist pattern 15 is etched away to form inward with respect to the photoresist pattern 15
  • the gate 14a is recessed.
  • the gate electrode 14a Since the etching progress of the dry etching can be precisely controlled, the gate electrode 14a whose edge is apart from the photoresist pattern 15 by L2 can be accurately formed by controlling the etching progress when dry etching is performed.
  • Step S17 performing high-concentration ion doping, as shown in FIG. 10, using the photoresist pattern 15 as a mask, performing a high-concentration ion doping such that the opposite sides of the semiconductor pattern 12 are not separated from the edge L1.
  • the portions covered by the photoresist pattern 15 respectively form heavily doped regions 12a (N+ doped regions or P+ doped regions).
  • Step S18 the photoresist pattern 15 is removed. As shown in FIG. 11, the photoresist pattern 15 located above the gate electrode 14a is removed after the heavily doped region 12a has been doped with a predetermined concentration of ions.
  • step S19 low concentration ion doping is performed, and as shown in Fig. 12, a low concentration ion doping is performed by using the gate electrode 14a as a mask.
  • the horizontal distance L2 is entered by the edge of the gate electrode 14a inward with respect to the edge of the corresponding photoresist pattern 15 by 1HJ. Therefore, the inner edge of the heavily doped region 12a on both sides of the semiconductor pattern 12 formed after the high concentration ion doping is formed with a region of width L2 with respect to the edge of the gate electrode 14a.
  • a lightly doped region 12b is formed in the above region after low concentration ion doping to form the LDD structure.
  • the region of the semiconductor pattern 12 which is not covered by the gate electrode 14a serves as a channel layer of the TFT 16.
  • the doped region of the semiconductor pattern 12 is heated to between about 400 degrees Celsius and 1000 degrees Celsius by an ion activation method to activate The lightly doped region 12b and the charged ions in the heavily doped region 12a further cause the semiconductor pattern 12 to have a semiconductor function.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种用于制作具有轻掺杂漏极结构薄膜晶体管矩阵的显示面板的方法，先在一基板（10）上形成具有预定形状的半导体图案（12），在基板（10）上形成一覆盖半导体图案（12）的介电层（13），在介电层（13）上形成一金属层（14），在金属层（14）上位于半导体图案（12）的正上方形成一尺寸小于半导体图案（12）的光阻图案（15），蚀刻金属层（14）以形成一尺寸小于光阻图案（15）的栅极（14a），利用光阻图案（15）作为掩膜进行对未被光阻图案（15）覆盖的部分进行高浓度离子掺杂以形成重掺杂区（12a），移除光阻图案（15），利用栅极（14a）作为掩膜对在重掺杂区（12a）与被栅极（14a）覆盖的半导体图案（12）区域之间进行低浓度离子掺杂以形成轻掺杂区（12b）。

Description

一种显示面板制作方法
技术领域
本发明涉及显示面板制作方法， 尤其涉及一种具有轻掺杂漏极 （Lightly Doped Drain, LDD)结构薄膜晶体管 (Thin Film Transistor, TFT)的显示面板制作方 法。
背景技术
现有釆用自对准方式制作具有 LDD结构 TFT的方法大多需要对 TFT的栅 极金属层进行重复蚀刻。 对栅极金属层的第一次蚀刻定义出半导体层内重掺杂 区的位置。 对栅极金属层的第二次蚀刻定义出半导体层内轻掺杂区的位置。 所 以， 釆用对栅极金属层重复蚀刻方法制成的 LDD结构的尺寸因受到多次蚀刻误 差的影响， 其精度较低。 而且， 多次蚀刻也增加了光罩次数提高了显示面板的 制造成本。
因此， 需要提供能够解决上述问题的显示面板制作方法。
发明内容
为了解决上述技术问题， 本发明实施例提供了一种显示面板制作方法， 其 用于制作具有轻掺杂漏极结构薄膜晶体管矩阵的显示面板， 该显示面板制作方 法包括：
提供一基板；
在所述基板上形成具有预定形状的半导体图案；
在所述基板形成一覆盖所述半导体图案的介电层；
在所述介电层上形成一金属层；
在所述金属层上位于半导体图案的正上方形成一尺寸小于所述半导体图案 的光阻图案；
蚀刻所述金属层以形成一尺寸小于光阻图案的栅极；
利用所述光阻图案作为掩膜进行一高浓度离子掺杂， 以使得所述半导体图 案未被光阻图案覆盖的部分形成重掺杂区；
移除所述光阻图案；
利用所述栅极作为掩膜进行一低浓度离子掺杂， 以在所述重掺杂区与被所 述栅极覆盖的半导体图案区域之间形成轻掺杂区。 其中， 经蚀刻金属层所形成的栅极的中心与所述光阻图案的中心对齐。 所 述栅极相对两侧的边缘相对所述光阻图案对应两侧边缘向内 1HJ入一预设的水平 距离。
其中， 所述栅极边缘相对光阻图案的边缘向内凹入的水平距离为 0.5〜1.5 μτη。
其中， 蚀刻所述金属层的方式选自干蚀刻及湿蚀刻中的一种。
其中， 所述半导体图案的材料为非晶硅经过准分子激光退火结晶 (Excimer Laser Annealing, ELA)、 金属诱发结晶 （ Metal-induced crystallization, MIC )、 固 相再结晶（Solid Phase Crystallization, SPC) 而形成的低温多 晶硅（Low Temperature Poly crystalline Silicon)。
其中， 在所述基板上形成半导体图案前还可以先在所述基板上形成一緩冲 层。
其中， 在完成所述低浓度离子掺杂后将所述半导体图案经掺杂后的区域加 热至 400摄氏度与 1000摄氏度之间以活化轻掺杂区与重掺杂区内的带电离子。
其中， 所述金属层以溅镀的方式形成在所述介电层上。
其中， 所述光阻图案在半导体图案上的投影位于所述半导体图案的中部。 其中， 所述光阻图案的相对两侧边缘在半导体图案上的投影与所述半导体 图案对应的两侧边缘的距离相等。
本发明所提供的显示面板制作方法只需要对栅极金属层进行一次蚀刻， 不 仅减少了制程步骤， 还避免了多次蚀刻所造成的叠加误差， 提高了 LDD结构的 尺寸精度。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实施 例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面描述 中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付 出创造性劳动性的前提下， 还可以根据这些附图获得其他的附图。
图 1是本发明实施例所提供的显示面板制作方法的步骤流程图。
图 2是釆用图 1所示的显示面板制作方法制成的显示面板结构示意图。 图 3-图 12为图 1所示的显示面板制作方法各步骤的结构示意图。
具体实施方式 下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行清 楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是 全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有作出创造 性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
如图 1 所示， 本发明实施例所提供的显示面板制作方法用于制作适用于液 晶显示器或有机发光二极管显示器的显示面板 1。 如图 2所示， 所述显示面板 1 包括基板 10及设置在基板上呈矩阵状排列的 TFT 16。所述 TFT 16具有 LDD结 构。 所述显示面板制作方法包括如下步骤：
步骤 S10, 提供所述基板 10, 如图 3所示， 提供一由透明绝缘材料制成的 基板 10。
步骤 S12, 形成半导体图案 12, 如图 4所示， 在所述基板 10上形成具有预 定形状的半导体图案 12。 具体地， 先在所述基板 10上沉积一半导体层。 再利用 体图案 12的材料为非晶硅经过低温多晶硅制程 (Low Temperature Polycrystalline Silicon, LTPS)重新结晶而形成的多晶硅。 所述低温多晶硅制程包括准分子激光 退火结晶 (Excimer Laser Annealing, ELA)、 金属 i秀发结晶 ( Metal-induced crystallization, MIC )、 固相再结晶（Solid Phase Crystallization, SPC)。
优选地， 如图 5所示， 在形成所述半导体图案 12前还可以先在基板 10上 形成一緩冲层 11 , 以减少基板 10中杂质分子对半导体图案 12性质的影响。
步骤 S13 , 形成介电层 13 , 如图 6所示， 在所述基板 10上沉积介电材料以 形成一介电层 13覆盖于所述半导体图案 12上。
步骤 S14, 形成金属层 14, 如图 7所示， 在所述介电层 13上以溅镀的方法 形成一金属层 14。
步骤 S15 , 形成光阻图案 15 , 如图 8所示， 在所述金属层 14上位于半导体 图案 12的正上方形成一光阻图案 15。 具体地， 先在所述金属层 14上沉积一层 光阻材料。 之后利用具有特定图案的光罩对所述光阻材料进行曝光。 再对曝光 后的光阻材料进行显影从而得到与光罩上预定图案对应的光阻图案 15。
所述光阻图案 15的尺寸小于所述半导体图案 12。 所述光阻图案 15在半导 体图案 12上的投影位于所述半导体图案 12的中部。 所述光阻图案 15的相对两 侧边缘在半导体图案 12上的投影与所述半导体图案 12对应的两侧边缘之间的 or- _
距呙巧刀 Ll 0
步骤 S16, 蚀刻金属层 14以形成栅极 14a, 如图 9所示， 蚀刻所述金属层 14以形成具有特定图案的 TFT 16的栅极 14a。 所述栅极 14a的中心与所述光阻 图案 15的中心相互对齐。 所述栅极 14a的尺寸小于所述光阻图案 15。 所述栅极 14a相对两侧的边缘相对所述光阻图案 15对应两侧边缘向内 1HJ入一预设的水平 距离 L2。 在本实施例中， 所述水平距离 L2优选为 0.5〜1.5 /w。
所述栅极 14a 的蚀刻制程可釆用干蚀刻或湿蚀刻的方法。 釆用湿蚀刻时， 利用湿蚀刻的过蚀刻效果在将未被光阻图案 15覆盖的金属层 14部分蚀刻掉后 继续向内过蚀刻所述水平距离 L2以形成相对于光阻图案 15向内凹入的所述栅 极 14a。
因所述干蚀刻的蚀刻进度可精确控制， 在釆用干蚀刻时通过控制蚀刻进度 便可精确地形成边缘与光阻图案 15相距 L2的栅极 14a。
步骤 S17, 进行高浓度离子掺杂， 如图 10所示， 利用所述光阻图案 15作为 掩膜， 进行一高浓度离子掺杂， 使得所述半导体图案 12相对两侧距离边缘 L1 处未被光阻图案 15覆盖的部分分别形成重掺杂区 12a(N+掺杂区或 P+掺杂区）。
步骤 S18, 移除所述光阻图案 15 , 如图 11所示， 在所述重掺杂区 12a内已 掺杂入预定浓度的离子后将位于栅极 14a上方的光阻图案 15去除。
步骤 S19, 进行低浓度离子掺杂， 如图 12所示， 利用所述栅极 14a作为掩 膜， 进行一低浓度离子掺杂。 因所述栅极 14a边缘相对于对应的光阻图案 15边 缘向内 1HJ入所述水平距离 L2。 所以， 在进行高浓度离子掺杂后所形成的所述半 导体图案 12两侧的重掺杂区 12a的内边缘相对于栅极 14a边缘之间形成一宽度 为 L2的区域。 经过低浓度离子掺杂后在上述区域形成一轻掺杂区 12b, 以形成 所述 LDD结构。
而未被栅极 14a所覆盖的半导体图案 12区域则作为 TFT 16的沟道层。 在 确定所述轻掺杂区 12b 中已掺杂入预定浓度的离子后， 通过一离子活化方法将 所述半导体图案 12经掺杂后的区域加热至大约 400摄氏度与 1000摄氏度之间， 以活化轻掺杂区 12b与重掺杂区 12a内的带电离子， 进而使半导体图案 12具有 半导体功能。
因所述显示面板制作方法只需要对金属层 14进行一次蚀刻， 不仅减少了制 程步骤， 还避免了多次蚀刻所造成的叠加误差， 提高了 LDD结构的尺寸精度。 以上所揭露的仅为本发明一种较佳实施例而已， 当然不能以此来限定本发 明之权利范围， 因此依本发明权利要求所作的等同变化， 仍属本发明所涵盖的 范围。

Claims

权 利 要 求 书
1. 一种显示面板制作方法，其用于制作具有轻掺杂漏极结构薄膜晶体管 矩 阵的显示面板， 该显示面板制作方法包括：
提供一基板；
在所述基板上形成具有预定形状的半导体图案；
在所述基板形成一覆盖所述半导体图案的介电层；
在所述介电层上形成一金属层；
在所述金属层上位于半导体图案的正上方形成一尺寸小于所述半导体图案 的光阻图案；
蚀刻所述金属层以形成一尺寸小于光阻图案的栅极；
利用所述光阻图案作为掩膜进行一高浓度离子掺杂， 以使得所述半导体图 案未被光阻图案覆盖的部分形成重掺杂区；
移除所述光阻图案；
利用所述栅极作为掩膜进行一低浓度离子掺杂， 以在所述重掺杂区与被所 述栅极覆盖的半导体图案区域之间形成轻掺杂区。
2. 如权利要求 1所述的显示面板制作方法， 其中， 经蚀刻金属层所形成的 栅极的中心与所述光阻图案的中心对齐， 所述栅极相对两侧的边缘相对所述光 阻图案对应两侧边缘向内凹入一预设的水平距离。
3. 如权利要求 2所述的显示面板制作方法， 其中， 所述栅极边缘相对光阻 图案的边缘向内凹入的水平距离为 0.5 ~ 1.5 // 。
4. 如权利要求 1所述的显示面板制作方法， 其中， 蚀刻所述金属层的方式 选自干蚀刻及湿蚀刻中的一种。
5. 如权利要求 1所述的显示面板制作方法， 其中， 所述半导体图案的材料 为非晶硅经过准分子激光退火结晶、 金属诱发结晶或固相再结晶而形成的低温 多晶硅。
6. 如权利要求 1所述的显示面板制作方法， 其中， 在所述基板上形成半导 体图案前还可以先在所述基板上形成一緩冲层。
7. 如权利要求 1所述的显示面板制作方法， 其中， 在完成所述低浓度离子 掺杂后将所述半导体图案经掺杂后的区域加热至 400摄氏度与 1000摄氏度之间 以活化轻掺杂区与重掺杂区内的带电离子。
8. 如权利要求 1所述的显示面板制作方法， 其中， 所述金属层以溅镀的方 式形成在所述介电层上。
9. 如权利要求 1所述的显示面板制作方法， 其中， 所述光阻图案在半导体 图案上的投影位于所述半导体图案的中部。
10. 如权利要求 1所述的显示面板制作方法， 其中， 所述光阻图案的相对两 侧边缘在半导体图案上的投影与所述半导体图案对应的两侧边缘的距离相等。
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