WO2016095308A1 - 一种用于制作多晶硅薄膜晶体管的方法 - Google Patents

一种用于制作多晶硅薄膜晶体管的方法 Download PDF

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WO2016095308A1
WO2016095308A1 PCT/CN2015/070965 CN2015070965W WO2016095308A1 WO 2016095308 A1 WO2016095308 A1 WO 2016095308A1 CN 2015070965 W CN2015070965 W CN 2015070965W WO 2016095308 A1 WO2016095308 A1 WO 2016095308A1
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layer
region
photoresist
forming
semiconductor material
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PCT/CN2015/070965
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English (en)
French (fr)
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虞晓江
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深圳市华星光电技术有限公司
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Priority to US14/418,186 priority Critical patent/US9515190B2/en
Publication of WO2016095308A1 publication Critical patent/WO2016095308A1/zh

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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation

Definitions

  • the present invention relates to the field of thin film transistor fabrication technology, and in particular to a method for fabricating a polysilicon thin film transistor.
  • LTPS Low Temperature Poly-Silicon
  • the thin film transistor used in the LTPS panel is made of high mobility low temperature polysilicon. This panel has the advantages of high resolution, low power consumption, high response speed, high aperture ratio, etc., and is expected to become the next-generation mainstream small and medium size display panel.
  • the charge and discharge control elements of the pixels, the electrostatic discharge elements, the splitter elements, and the drive elements on the array substrate are often thin film transistors.
  • Ordinary low-temperature polysilicon thin film transistors have higher leakage current.
  • LDD lightly doped drain
  • LDDs low-doped, high-resistance LDDs are used. Zone to reduce leakage current.
  • the present invention provides a simplified method for fabricating a polysilicon thin film transistor for reducing the manufacturing process of a panel and reducing the production cost.
  • a method for fabricating a polysilicon thin film transistor comprising the steps of:
  • An ion lightly doped region corresponding to the wing portion is formed in the semiconductor material layer, and an ion heavily doped region corresponding to the hollow region for forming a source and a drain region.
  • the reticle comprises a light blocking region and a light transmitting region.
  • the direction and the distance of the movement are designed such that the light-shielding region of the reticle covers the exposed region of the photoresist layer. a first portion and a second portion of the unexposed region of the photoresist layer.
  • the width of the first portion is equal to the width of the ion lightly doped region to be generated.
  • a central portion of the photoresist region is formed by a portion of the photoresist layer that is not exposed after two exposures, and a wing portion of the photoresist region is formed by the photoresist layer The upper portion is formed after only one exposure after two exposures.
  • the prefabricated substrate comprises a gate metal layer and a gate insulating layer on the gate metal layer, the intermediate layer being an interlayer insulating layer.
  • the intermediate layer includes a gate insulating layer and a gate metal layer on the gate insulating layer for forming a gate.
  • the step of forming the ion lightly doped region and forming the ion heavily doped region comprises:
  • a low concentration ion implantation is performed to form an ion lightly doped region in the layer of semiconductor material corresponding to the removed wing.
  • the buffer layer before the forming the buffer layer, further comprising forming a light shielding layer corresponding to the semiconductor material layer on the prefabricated substrate.
  • the invention can reduce the manufacturing process of the LTPS panel and reduce the production cost of the panel when manufacturing the LTPS panel.
  • FIG. 1 is a flow chart of a method in accordance with one embodiment of the present invention.
  • FIG. 2a is a schematic cross-sectional view of a substrate after forming a gate metal layer, in accordance with an embodiment of the present invention
  • Figure 2b is a plan view of Figure 2a
  • Figure 3 is a schematic cross-sectional view of the substrate of Figure 2a after coating the photoresist material
  • FIG. 4a is a schematic cross-sectional view showing the first exposure of the substrate of FIG. 3;
  • Figure 4b is a plan view of Figure 4a
  • Figure 5a is a schematic cross-sectional view showing the second exposure of the substrate of Figure 4a;
  • Figure 5b is a top plan view of the second exposure after horizontal movement of the substrate of Figure 5a;
  • Figure 5c is a top plan view of the second exposure after the substrate of Figure 5a is moved vertically;
  • Figure 5d is a plan view of the second exposure after the substrate of Figure 5a is moved at an angle
  • Figure 6a is a schematic cross-sectional view of the substrate of Figure 5d after removing the exposed photoresist material
  • Figure 6b is a plan view of Figure 6a
  • FIG. 7a is a schematic cross-sectional view of the substrate of FIG. 6a with a gate metal layer not covered by a photoresist;
  • Figure 7b is a plan view of Figure 7a
  • Figure 8 is a schematic cross-sectional view showing high concentration ion implantation of the substrate of Figure 7a;
  • Figure 9a is a schematic cross-sectional view of the substrate of Figure 8 with the wings removed;
  • Figure 9b is a plan view of Figure 9a
  • FIG. 10a is a schematic cross-sectional view of the substrate of FIG. 9a with a gate metal layer not covered by a photoresist;
  • Figure 10b is a top view of Figure 10a
  • Figure 11 is a schematic cross-sectional view showing the low concentration ion implantation of the substrate of Figure 10a;
  • Figure 12a is a schematic cross-sectional view of the remaining photoresist in Figure 11;
  • Figure 12b is a top view of Figure 12a
  • Figure 13 is a schematic cross-sectional view of an LTPS display panel in accordance with one embodiment of the present invention.
  • FIG. 1 is a flowchart of a method in accordance with an embodiment of the present invention, and the method of the present invention will be described in detail below with reference to FIG. 1.
  • the polycrystalline silicon thin film transistor is fabricated here, the polycrystalline silicon used is high temperature polycrystalline silicon or low temperature polycrystalline silicon.
  • the present invention is described by taking a low temperature polycrystalline silicon thin film transistor as an example.
  • step S110 a semiconductor material layer is formed on the pre-formed substrate, and an intermediate layer is formed on the semiconductor material layer.
  • the layer of semiconductor material herein is used to form a low temperature polysilicon layer that is arranged as a silicon island on a prefabricated substrate. Since the polysilicon thin film transistor includes a bottom gate structure and a top gate structure, the structure of the prefabricated substrate for forming the semiconductor material layer is different.
  • the prefabricated substrate includes a gate metal layer formed on the substrate, the gate metal layer being used to form a gate.
  • the prefabricated substrate also includes a gate insulating layer deposited on the gate metal layer.
  • the interlayer insulating layer serves to isolate the semiconductor material layer from other material layers formed after the semiconductor material layer.
  • the prefabricated substrate is a substrate (usually a glass substrate).
  • the intermediate layer includes a gate insulating layer and a gate metal layer on the gate insulating layer for forming a gate.
  • a polysilicon thin film transistor having a top gate structure is described as an example, but the method of the present invention is not limited to a polysilicon thin film transistor in which a top gate structure is formed.
  • an intrinsic a-Si layer (amorphous silicon layer) is first deposited on a substrate by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method; The a-Si layer is then subjected to a dehydrogenation treatment; then a semiconductor material layer is formed by a process such as ELA (excimer laser annealing) or SLC (continuous lateral crystallization).
  • the semiconductor material layer is a low temperature polysilicon layer, and the low temperature polysilicon layer is arranged in a silicon island, and each silicon island is a low temperature polysilicon island.
  • a silicon oxide or silicon nitride is deposited on the low temperature polysilicon layer by a PECVD method to form a gate insulating layer.
  • a low temperature polysilicon layer is deposited on the substrate 1, and polysilicon in the low temperature polysilicon layer forms a low temperature polysilicon island 2.
  • a gate insulating layer 3 is deposited on the low temperature polysilicon layer.
  • the gate insulating layer 3 may be composed of a single layer of silicon oxide or a layer of silicon oxide and a layer of silicon nitride on the layer of silicon oxide.
  • a gate metal layer 4 is formed by depositing molybdenum or other metal on the gate insulating layer 3 by a sputtering method.
  • a buffer layer 5 is usually deposited on the substrate 1, and then a low temperature polysilicon island 2 is formed on the buffer layer 5.
  • the buffer layer 5 is usually composed of a layer of silicon nitride and a layer of silicon oxide.
  • the buffer layer 5 can shield the influence of defects of the substrate 1 and prevent impurities such as metal ions or the like on the substrate 1 from diffusing and penetrating into the polysilicon island 2, thereby avoiding various device defects caused thereby.
  • a light shielding layer (LS MO) 6 is disposed on the substrate 1 below the low temperature polysilicon island 2 to be formed to block the illumination, so that the actively formed low temperature polysilicon thin film transistor can be prevented from being irradiated with light.
  • a cross section of the substrate processed in step S110 is as shown in FIG. 2a, and a light shielding layer 6 is disposed on the substrate 1; a buffer layer 5 is deposited on the light shielding layer 6 and the exposed substrate 1, and the buffer layer 5 is composed of a silicon nitride layer 51 and a silicon oxide layer 52 is formed; a low temperature polysilicon island 2 corresponding to the light shielding layer 6 is deposited on the buffer layer 5; a gate insulating layer 3 is deposited on the low temperature polysilicon island 2 and the exposed buffer layer 5; on the gate insulating layer 3 A gate metal layer 4 is deposited.
  • 2b is a top view of FIG. 2a, the surface of FIG. 2b being a gate metal layer 4.
  • step S120 a photoresist material is coated on the intermediate layer to form a photoresist layer, and the photoresist layer is exposed for the first time with a photomask.
  • FIG. 3 is a schematic cross-sectional view showing the formation of the photoresist layer 7 after the photoresist material is coated on the gate metal layer 4.
  • the reticle 8 used for exposure here includes a light-shielding region 81 and a light-transmitting region 82 as shown in Fig. 4a.
  • a certain thickness of photoresist material that is illuminated by UV (vacuum ultraviolet) light is characterized by UV light, as in region 9 of Figure 4a.
  • 4b is a top view of FIG. 4a, in which the portion in the wire frame is the unexposed region of the light-shielding region 81 of the mask 8 on the photoresist layer 7 after the first exposure to the photoresist material.
  • the photoresist material in the unexposed regions is not altered by UV light, while the photoresist material outside the wireframe is characterized by UV light.
  • step S130 the pre-formed substrate having the photoresist layer after the first exposure process is moved relative to the reticle in a predetermined direction, and the photoresist layer is subjected to a second exposure to form a photoresist region and hollowed out. Area.
  • the substrate is moved in a predetermined direction by moving the exposure machine table carrying the prefabricated substrate while the reticle position remains fixed.
  • the light shielding region of the reticle covers the first portion 811 in the exposed region on the photoresist layer and the unexposed region on the photoresist layer by matching the predetermined direction and the distance of the movement.
  • the second part 812 is shown in Figure 5a. Wherein the width of the first portion 811 is related to the lightly doped region of the ion to be generated The widths are equal, and the width of the first portion 811 on both sides of the second portion 812 is equal to the width of the 813 portion.
  • one side of the substrate 1 is generally selected as a reference side, and the substrate 1 is moved in a direction at an angle to the reference side so that the light-shielding region 81 of the photomask 8 is exposed for the first time on the substrate.
  • the unexposed regions partially overlap the unexposed regions of the second exposure, which overlap portions correspondingly form the second portion 812 of the photoresist layer 7.
  • the angle at which the substrate 1 moves includes all the angular ranges that the substrate 1 can move.
  • the substrate 1 is horizontally moved with the long side of the substrate 1 in FIG. 5a as a reference side, such that the unexposed areas of the first exposure on the substrate 1 partially overlap with the unexposed areas of the second exposure, ie, The second part 812.
  • a non-overlapping region of the exposed region after the first exposure process and the exposed region of the second exposure process to be performed is formed on the opposite sides of the horizontal direction of the two unexposed overlapping regions, and the two non-overlapping regions. The same, as shown in Figure 5b.
  • the substrate 1 may also be vertically moved along the reference edge such that the unexposed area after the first exposure process on the substrate 1 partially overlaps the unexposed area of the second exposure process to be performed, that is, the second portion 812 is formed.
  • a non-overlapping region of the exposed region after the first exposure process and the exposed region of the second exposure process to be performed is formed on opposite sides of the vertical direction of the overlap region, and the two non-overlapping regions are the same, as shown in FIG. 5c. Shown.
  • the substrate 1 can also be moved at an angle other than horizontal and vertical to the reference edge. This partially overlaps the unexposed areas after the first exposure process on the substrate 1 and the unexposed areas after the second exposure process, and simultaneously generates a first exposure process on the opposite sides of the overlap region.
  • the non-overlapping area of the exposed area and the unexposed area after the second exposure processing is as shown in FIG. 5d. Wherein, the non-overlapping regions on opposite sides have the same width.
  • the angle here may be selected to be any angle in the range of 30 to 60, but is not limited to the range of angles described above. When the angle is selected to be 45°, the widths of the four non-overlapping regions are equal.
  • the distance by which the substrate 1 moves it is based on the width of the ion lightly doped region to be generated.
  • the substrate is moved in a predetermined direction such that the width of the non-overlapping portion of the first exposed exposure region on the substrate 1 and the exposed portion of the second exposure is equal to the width of the ion lightly doped region to be formed.
  • the distance moved by the substrate 1 is the width of the ion lightly doped region to be generated, that is, the width of the first portion 811 and the width of the lightly doped region to be generated. equal.
  • the distance moved by the substrate 1 is determined according to the predetermined direction and the width of the ion lightly doped region to be generated.
  • the distance moved by the substrate 1 is determined according to the predetermined direction and the width of the ion lightly doped region to be generated.
  • four non-overlapping regions are formed, wherein the opposite two non-overlapping regions are equal in width, and the adjacent two non-overlapping regions are equal or unequal in width. If the adjacent two non-overlapping regions are of equal width, the two non-overlapping regions that are optionally opposite may correspond to the ion-light doped regions to be generated.
  • the thin film transistors can be arranged on the substrate.
  • the widths of the four non-overlapping regions formed are equal, and in this case, the opposite two non-selectable The overlap region corresponds to the ion-doped region to be generated.
  • the widths of the adjacent two non-overlapping regions are not equal, and the opposite two non-overlapping regions may be selected according to the arrangement of the ion lightly doped regions to be generated, thereby determining the distance that the substrate 1 moves.
  • the moving distance is generally set to 1 to 5 ⁇ m, which cannot be greater than the distance between the thin film transistors to be formed.
  • the substrate 1 will be described as an example in which the substrate 1 is moved at any angle within a range of 30° to 60° in a predetermined direction.
  • the photoresist material of a certain thickness in the region irradiated with the UV light on the photoresist layer is changed in characteristics.
  • the photoresist material on the gate metal layer 4 forms two different components.
  • the photoresist layer 7 forms a photoresist region having photoresist materials of different thicknesses.
  • the photoresist region includes a central portion 71 having a first thickness that is not exposed in both exposure processes. For the area where the photoresist material is exposed only once in the double exposure process, the upper photoresist material has been changed by the UV light, but the lower photoresist material is not changed by the UV light, and the region forms the photoresist region. Two thickness wings 72. Wherein the first thickness is greater than the second thickness.
  • FIG. 6a A schematic cross-sectional view of the substrate after removing the exposed photoresist material is shown in FIG. 6a, and the exposed intermediate layer (ie, the gate metal layer 4) outside the photoresist region is a hollow region. The corresponding top view of Figure 6a is shown in Figure 6b.
  • step S140 an ion lightly doped region corresponding to the wing portion is formed in the semiconductor material layer, and an ion heavily doped region corresponding to the hollow region for forming the source and drain regions is formed.
  • the metal material corresponding to the hollow region in the gate metal layer is first removed, and the substrate after the portion of the metal material is removed is as shown in FIG. 7a.
  • the corresponding top view of the light is shown in Figure 7b.
  • the semiconductor material layer is subjected to high-concentration ion implantation, and the ion heavily doped region 10 is formed in the portion corresponding to the hollow region in the low-temperature polysilicon island 2, as shown in Fig. 8, the top view thereof is the same as Fig. 7b.
  • N-type ion implantation is exemplified, but is not limited to N-type ions.
  • the ion heavily doped region 10 is used to form the source and drain of the thin film transistor.
  • the wing portion 72 of the photoresist layer 7 is removed, thereby exposing the gate metal layer covered by the wing. Since the thickness of the photoresist material of the central portion 71 of the photoresist layer 7 is greater than the thickness of the photoresist material of the wing portion 72, after the wing portion 72 is removed, the photoresist portion of the central portion 71 remains, except for the thickness of the photoresist material. Reduced as shown in Figure 9a. The corresponding top view of Figure 9a is shown in Figure 9b.
  • the metal material of the portion of the gate metal layer 4 that is not covered by the photoresist that is, the metal material of the portion of the gate metal layer 4 corresponding to the original wing portion 72 of the photoresist layer 7 is removed.
  • the cross-section of the substrate structure after removing the metal material corresponding to the wing portion 72 is as shown in FIG. 10a, and the corresponding top view is as shown in FIG. 10b.
  • a low concentration ion implantation of the semiconductor material layer is performed.
  • An ion lightly doped region 11 is formed in a portion of the low temperature polysilicon island 2 corresponding to the original wing portion 72 of the photoresist layer 7, as shown in FIG.
  • the corresponding top view of Fig. 11 is the same as Fig. 10b.
  • the ion lightly doped region 11 is used to form an LDD region.
  • the remaining photoresist on the gate metal layer 4 is etched away to expose the gate metal layer covered by the photoresist material.
  • the portion of the gate metal layer correspondingly forms a gate, as shown in FIG. 12a, and its corresponding top view is as shown in FIG. 12b. So far, a thin film transistor having a gate, a source and a drain has been initially completed.
  • silicon nitride and silicon oxide are deposited on the gate insulating layer 3 and the gate by a PECVD process to form an interlayer insulating layer.
  • the interlayer insulating layer is thermally annealed and hydrogenated to activate the doping ions and improve the low temperature polysilicon interface; then the interlayer insulating layer and the gate insulating layer are etched to form contact holes, and the contact holes extend to the ion re-doping a hetero-region; subsequently, a source-drain metal layer is deposited and defined to form a source and a drain; subsequently, an organic planarization layer is formed on the source-drain metal layer, and a via hole is formed at the contact hole portion; A bottom indium tin oxide layer as a common electrode is formed on the layer; a passivation layer is then formed on the organic planarization layer, and a contact hole to the drain is formed in the passivation layer.
  • the resulting display panel has a cross section as shown in FIG. 13 and includes: a substrate 1; a light shielding layer (LS MO) 6; and a buffer layer 5 composed of a silicon nitride layer 51 (SiNx) and a silicon oxide layer 52 (SiOx); Low temperature polysilicon island (Poly 2); ion heavily doped region (N+) 10; ion lightly doped region (LDD) 11; gate (MO gate) 4; gate insulating layer (GI) 3; interlayer insulating layer ( ILD SiOx and ILD SiNx) 12, which consists of a silicon oxide layer 121 (SiOx) and a silicon nitride 122 layer (SiNx); a source 13; a drain 14; an organic planarization layer (PL) 15; common electrode (ITO-Com)

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Abstract

一种用于制作多晶硅薄膜晶体管的方法，包括：在预制基底上形成半导体材料层；在半导体材料层上形成中间层；在中间层上涂布光阻材料形成光阻层（7），并用光罩（8）对光阻层（7）进行第一次曝光；按一预定方向相对于光罩（8）移动具有第一次曝光处理后的光阻层（7）的预制基底，并采用光罩（8）对所述光阻层（7）进行第二次曝光；去除光阻层（7）上受到曝光的光阻材料，以在光阻层（7）上形成光阻区和镂空区，其中，光阻区包括中心部（71）和翼部（72），镂空区不包含光阻材料；在半导体材料层中形成对应于翼部（72）的离子轻掺杂区（11），以及对应于镂空区的用于形成源漏极的离子重掺杂区（10）。上述方法能够在制作ＬＴＰＳ面板时，减少面板的制作工序并能降低面板的生产成本。

Description

一种用于制作多晶硅薄膜晶体管的方法
相关技术的交叉引用
本申请要求享有2014年12月19日提交的名称为：“一种用于制作多晶硅薄膜晶体管的方法”的中国专利申请CN201410796421.X的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及薄膜晶体管制作技术领域，具体地说，涉及一种多晶硅薄膜晶体管的制作方法。
背景技术
近年来，LTPS(Low Temperature Poly-Silicon，即低温多晶硅)面板在高端手机、平板电脑上获得了广泛应用。LTPS面板中使用的薄膜晶体管由高迁移率的低温多晶硅制成。这种面板具有高分辨率、低功耗、高反应速度、高开口率等优点，有望成为下一代主流的中小尺寸显示面板。
在LTPS面板上，像素的充放电控制元件、静电释放元件、分路器元件、栅极在阵列基板上的驱动元件都常会采用薄膜晶体管。普通低温多晶硅薄膜晶体管漏电较高，为减少漏电常需要在低温多晶硅薄膜晶体管的漏极及源极制作LDD(lightly doped drain，轻掺杂漏极)区，用低掺杂、高电阻值的LDD区来降低漏电流。
在早先的LTPS面板制作过程中，通常需要多个光罩来形成LDD区，这样，就会增加面板的制作工序和生产成本。
发明内容
为解决上述问题，本发明提供了一种简化的用于制作多晶硅薄膜晶体管的方法，用以减少面板的制作工序并降低生产成本。
根据本发明的一个实施例，提供了一种用于制作多晶硅薄膜晶体管的方法，包括以下步骤：
在预制基底上形成半导体材料层；
在所述半导体材料层上形成中间层；
在所述中间层上涂布光阻材料形成光阻层，并用光罩对所述光阻层进行第一次曝光；
按一预定方向相对于所述光罩移动具有第一次曝光处理后的光阻层的预制基底，并采用所述光罩对所述光阻层进行第二次曝光；
去除所述光阻层上受到曝光的光阻材料，以在所述光阻层上形成光阻区和镂空区，其中，所述光阻区包括中心部和翼部，所述镂空区不包含光阻材料；
在所述半导体材料层中形成对应于所述翼部的离子轻掺杂区，以及对应于所述镂空区的用于形成源漏极的离子重掺杂区。
根据本发明的一个实施例，所述光罩包括遮光区域和透光区域。
根据本发明的一个实施例，在按预定方向移动所述预制基底时，所述方向及移动的距离配合设计成使得所述光罩的遮光区域覆盖所述光阻层上经过曝光后的区域中的第一部分和所述光阻层上未曝光区域中的第二部分。
根据本发明的一个实施例，所述第一部分的宽度与需生成的离子轻掺杂区的宽度相等。
根据本发明的一个实施例，所述光阻区的中心部由所述光阻层上在经过两次曝光后未被曝光的部分形成，所述光阻区的翼部由所述光阻层上在经过两次曝光后只经过一次曝光的部分形成。
根据本发明的一个实施例，所述预制基底包括栅极金属层及所述栅极金属层上的栅极绝缘层，所述中间层为层间绝缘层。
根据本发明的一个实施例，所述中间层包括栅极绝缘层及该栅极绝缘层上的用于形成栅极的栅极金属层。
根据本发明的一个实施例，形成所述离子轻掺杂区和形成所述离子重掺杂区的步骤包括：
去除所述栅极金属层中对应于所述镂空区的金属材料；
进行高浓度离子植入，以在所述半导体材料层中对应于所述镂空区形成离子重掺杂区；
去除所述光阻区的翼部以裸露出所述栅极金属层；
蚀刻掉裸露出的栅极金属层；
进行低浓度离子植入，以在所述半导体材料层中对应于去除的翼部形成离子轻掺杂区。
根据本发明的一个实施例，在形成所述半导体材料层之前还包括在所述预制基底上 形成一缓冲层。
根据本发明的一个实施例，在形成所述缓冲层之前还包括在所述预制基底上形成与所述半导体材料层对应的遮光层。
本发明可以在制作LTPS面板时减少LTPS面板的制作工序并能降低面板的生产成本。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1是根据本发明的一个实施例的方法流程图；
图2a是根据本发明的一个实施例的形成栅极金属层后的基板截面示意图；
图2b是图2a的俯视图；
图3是对图2a的基板涂布光阻材料后的截面示意图；
图4a是对图3的基板进行第一次曝光的截面示意图；
图4b是图4a的俯视图；
图5a是对图4a的基板进行第二次曝光的截面示意图；
图5b是对图5a的基板水平移动后第二次曝光的俯视图；
图5c是对图5a的基板垂直移动后第二次曝光的俯视图；
图5d是对图5a的基板按一定角度移动后第二次曝光的俯视图；
图6a是对图5d的基板去除曝光的光阻材料后的截面示意图；
图6b是图6a的俯视图；
图7a是图6a的基板去除未被光阻覆盖的栅极金属层的截面示意图；
图7b是图7a的俯视图；
图8是对图7a的基板进行高浓度离子植入的截面示意图；
图9a是对图8的基板去除翼部后的截面示意图；
图9b是图9a的俯视图；
图10a是图9a的基板去除未被光阻覆盖的栅极金属层的截面示意图；
图10b是图10a的俯视图；
图11是对图10a的基板进行低浓度离子植入的截面示意图；
图12a是图11中的去除剩余光阻的截面示意图；
图12b是图12a的俯视图；以及
图13是根据本发明的一个实施例的LTPS显示面板的截面示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。
如图1所示为根据本发明的一个实施例的方法流程图，以下参考图1来对本发明所述的方法进行详细说明。此处制作多晶硅薄膜晶体管时，采用的多晶硅为高温多晶硅或低温多晶硅，本发明以制作低温多晶硅薄膜晶体管为例来进行说明。
在步骤S110中，在预制基底上形成半导体材料层，并在该半导体材料层上形成中间层。
此处的半导体材料层用于形成低温多晶硅层，该低温多晶硅层在预制基底上呈硅岛排布。由于多晶硅薄膜晶体管包括底栅结构和顶栅结构，所以，用于形成半导体材料层的预制基底的结构不同。
在底栅结构的多晶硅薄膜晶体管中，预制基底包括在基板形成的栅极金属层，该栅极金属层用于形成栅极。该预制基底还包括在栅极金属层上沉积形成的栅极绝缘层。对应底栅结构的多晶硅薄膜晶体管，中间层为层间绝缘层。该层间绝缘层用以将半导体材料层与该半导体材料层后形成的其他材料层进行隔离。
在顶栅结构的多晶硅薄膜晶体管中，预制基底即为一基板(通常为玻璃基板)。对应顶栅结构的多晶硅薄膜晶体管，中间层包括栅极绝缘层及该栅极绝缘层上的用于形成栅极的栅极金属层。
在本发明中，以制作顶栅结构的多晶硅薄膜晶体管为例来进行说明，但本发明所述的方法不限于制作顶栅结构的多晶硅薄膜晶体管。
在该步骤中，制作顶栅结构的多晶硅薄膜晶体管时，首先在基板上采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)法沉积本征a-Si层(非晶硅层)；之后对a-Si层进行脱氢处理；然后采用ELA(准分子激光退火)或SLC(连续横向晶化)等工艺形成半导体材料层。该半导体材料层即为低温多晶硅层，该低温多晶硅层呈硅岛排布，各个硅岛为低温多晶硅岛。
接下来，采用PECVD法在低温多晶硅层上沉积氧化硅或氮化硅来形成栅极绝缘层。 如图2a所示，在基板1上沉积有低温多晶硅层，低温多晶硅层中的多晶硅形成低温多晶硅岛2。低温多晶硅层上沉积有栅极绝缘层3。该栅极绝缘层3可由单层氧化硅构成，或者由一层氧化硅和该层氧化硅上的一层氮化硅构成。
接下来，采用溅射法在栅极绝缘层3上沉积钼或其它金属形成栅极金属层4。
在步骤S110中，通常会在基板1上沉积一缓冲层5，然后在该缓冲层5上形成低温多晶硅岛2。缓冲层5通常由一层氮化硅和一层氧化硅组成。该缓冲层5可以屏蔽基板1的缺陷的影响，防止基板1上的杂质如金属离子等扩散并渗透到多晶硅岛2中，避免由此引起的各种器件不良。通常还会在形成缓冲层5之前，对应即将生成的低温多晶硅岛2下方的基板1上设置遮光层(LS MO)6来遮挡光照，这样就可以避免光照照射积极形成的低温多晶硅薄膜晶体管。
经过步骤S110处理后的基板的截面如图2a所示，在基板1上设置有遮光层6；遮光层6和裸露的基板1上沉积有缓冲层5，缓冲层5由氮化硅层51和氧化硅层52构成；在缓冲层5上沉积有与遮光层6对应的低温多晶硅岛2；低温多晶硅岛2和裸露的缓冲层5上沉积有栅极绝缘层3；在栅极绝缘层3上沉积有栅极金属层4。如图2b所示为图2a的俯视图，图2b的表面为栅极金属层4。
在步骤S120中，在中间层上涂布光阻材料形成光阻层，并用光罩对该光阻层进行第一次曝光。
在该步骤中，首先在栅极金属层4上涂布一层光阻材料形成光阻层，并对该该光阻层进行第一次曝光处理。图3为在栅极金属层4上涂布光阻材料后形成光阻层7的截面示意图。
此处曝光采用的光罩8包括遮光区域81和透光区域82，如图4a所示。通过控制曝光的光强和时间，使被UV(真空紫外线)光照射的一定厚度的光阻材料被UV光改变特性，如图4a中的区域9。图4b为图4a的俯视图，图中线框内的部分为对光阻材料进行第一次曝光后，光阻层7上光罩8的遮光区81的未曝光区域。该未曝光区域中的光阻材料未被UV光改变特性，而线框外的光阻材料被UV光改变特性。
在步骤S130中，按一预定方向相对于光罩移动具有第一次曝光处理后的光阻层的预制基底，并采用该光罩对光阻层进行第二次曝光以形成光阻区和镂空区。
此处通过移动承载预制基底的曝光机工作台来使该基底沿预定方向移动，而光罩位置保持固定。在按预定方向移动该基板时，通过配合设计预定方向和移动的距离来使光罩的遮光区域覆盖光阻层上经过曝光后的区域中的第一部分811和光阻层上未曝光区域中的第二部分812，如图5a所示。其中，第一部分811的宽度与需生成的离子轻掺杂区的 宽度相等，第二部分812两侧的第一部分811的宽度与813部分的宽度相等。
确定该预定方向时，通常选定基板1的一边为基准边，沿与该基准边成一定角度的方向移动该基板1，以使得光罩8的遮光区域81在基板上的第一次曝光的未曝光区域与第二次曝光的未曝光区域部分重叠，该重叠部分对应地形成光阻层7的第二部分812。
此处基板1移动的一定角度包括基板1所能移动的全部角度范围。例如，以图5a中的基板1的长边作为基准边，水平移动该基板1，这样使得基板1上的第一次曝光的未曝光区域与第二次曝光的未曝光区域部分重叠，即形成第二部分812。同时，在两次未曝光重叠区域的水平方向的相对两侧各形成一个第一次曝光处理后的曝光区域与将要进行的第二次曝光处理的曝光区域的非重叠区域，两个非重叠区域相同，如图5b所示。
也可以沿该基准边垂直移动该基板1，这样使得基板1上的第一次曝光处理后的未曝光区域与将要进行的第二次曝光处理的未曝光区域部分重叠，即形成第二部分812。同时，在重叠区域的垂直方向相对两侧各形成一个第一次曝光处理后的曝光区域与将要进行的第二次曝光处理的曝光区域的非重叠区域，两个非重叠区域相同，如图5c所示。
在本发明的一个具体的实施例中，还可以沿与该基准边成除水平和垂直之外的角度移动该基板1。这样使得基板1上的原来的第一次曝光处理后的未曝光区域与第二次曝光处理后的未曝光区域部分重叠，并同时在重叠区域的相对两侧各生成一个第一曝光处理时后的曝光区域与第二曝光处理后的未曝光区域的非重叠区域，如图5d所示。其中，相对两侧的非重叠区域的宽度相等。通常，此处的一定角度可选择成30°～60°范围内的任一角度，但不限于以上所述的角度范围。当该角度选择45°时，四个非重叠区域的宽度均相等。
在确定基板1移动的距离时，以需生成的离子轻掺杂区的宽度为基准。沿预定方向移动该基板，使基板1上的第一次曝光的曝光区域与第二次曝光的曝光区域的非重叠部分的宽度与需生成的离子轻掺杂区的宽度相等。如按图5b、5c的预定方向移动基板1时，可确定基板1移动的距离为需生成的离子轻掺杂区的宽度，即第一部分811的宽度与需生成的离子轻掺杂区的宽度相等。
如按图5d的预定方向移动基板1时，则需根据预定方向和需生成的离子轻掺杂区的宽度共同来确定基板1移动的距离。在这种情形下，经过二次曝光处理后共形成了四个非重叠区域，其中，相对的两个非重叠区域宽度相等，相邻的两个非重叠区域宽度相等或不等。如相邻的两个非重叠区域宽度相等，可从中任选相对的两个非重叠区域与需生成的离子轻掺杂区对应。这样，在基板上就可以有两种薄膜晶体管的排布方式。优选的，当预定角度为45°时，形成的四个非重叠区域的宽度均相等，此时，可从中任选相对的两个非 重叠区域与需生成的离子轻掺杂区对应。当预定角度非45°时，相邻的两个非重叠区域宽度不等，可以根据需生成的离子轻掺杂区的排布选择相对的两个非重叠区域，进而确定基板1移动的距离。移动距离一般设置为1～5μm，该距离不能大于要生成的薄膜晶体管之间的距离。
以下以按预定方向为30°～60°范围内的任一角度移动基板1为例来进行说明。通过控制第二次曝光的光强和时间，使光阻层上被UV光照射区域内的一定厚度的光阻材料改变特性。如图5a所示，第二次曝光之后，栅极金属层4上的光阻材料形成两种不同的成分。光阻材料未被UV光改变特性的光阻层7及已被UV光改变特性的光阻9。其中，光阻层7形成具有不同厚度的光阻材料的光阻区。该光阻区包括具有第一厚度的中心部71，该部分在两次曝光处理中均未被曝光。对于在两次曝光处理中，光阻材料只被曝光1次的区域，上层光阻材料已被UV光改变特性但下层光阻材料未被UV光改变特性，此区域形成光阻区的具有第二厚度的翼部72。其中，第一厚度大于第二厚度。去除曝光的光阻材料后的基板的截面示意图如图6a所示，光阻区之外的裸露出中间层(即栅极金属层4)的为镂空区。图6a对应的俯视图如图6b所示。
在步骤S140中，在半导体材料层中形成对应于翼部的离子轻掺杂区，以及对应于镂空区的用于形成源漏极的离子重掺杂区。
在该步骤中，首先去除栅极金属层中对应于镂空区的金属材料，去除该部分金属材料后的基板如图7a所示。其对应形成的光俯视图如图7b所示。
接下来，对半导体材料层进行高浓度离子植入，在低温多晶硅岛2中对应镂空区的部分形成离子重掺杂区10，如图8所示，其俯视图与图7b相同。此处以N型离子植入为例，但不限于N型离子。离子重掺杂区10用于形成薄膜晶体管的源漏极。
接下来，去除光阻层7的翼部72，从而裸露出被翼部覆盖的栅极金属层。由于光阻层7的中心部71的光阻材料的厚度大于翼部72的光阻材料的厚度，所以在翼部72去除后，中心部71的光阻材料部分保留，只是光阻材料的厚度减少，如图9a所示。图9a对应的俯视图如图9b所示。
接下来，去除栅极金属层4中未被光阻覆盖的部分的金属材料，即栅极金属层4中对应光阻层7的原翼部72的部分的金属材料。去除翼部72对应的金属材料后的基板结构截面如图10a所示，其对应的俯视图如图10b所示。
接下来，对半导体材料层进行低浓度离子植入。在低温多晶硅岛2中对应光阻层7的原翼部72的部分形成离子轻掺杂区11，如图11所示。图11对应的俯视图与图10b相同。离子轻掺杂区11用于形成LDD区。
蚀刻掉栅极金属层4上剩余的光阻，裸露出被光阻材料覆盖的栅极金属层。该部分栅极金属层对应形成栅极，如图12a所示，其对应的俯视图如图12b所示。至此，初步完成了具有栅极、源漏极的薄膜晶体管。
通常，将该多晶硅薄膜晶体管用于显示面板时，在栅极绝缘层3上形成栅极后，采用PECVD工艺在栅极绝缘层3上和栅极上沉积氮化硅、氧化硅形成层间绝缘层；随后，对层间绝缘层进行热退火及氢化，激活掺杂离子并改善低温多晶硅界面；然后对层间绝缘层和栅极绝缘层进行蚀刻处理形成接触孔，接触孔延伸至离子重掺杂区；随后，沉积形成源漏极金属层，并定义形成源极和漏极；随后，在源漏极金属层上制作有机平坦化层，并在接触孔部位形成通孔；接着，在有机层上形成作为共通电极的底部氧化铟锡层；然后在有机平坦化层上形成钝化层，并在钝化层上开孔形成至漏极的接触孔。在该基板上涂覆透明导电材料并经黄光、蚀刻、剥离等制程形成与漏极电气连接的像素电极。最终形成的显示面板截面如图13所示，其包括：基板1；遮光层(LS MO)6；缓冲层5，其由氮化硅层51(SiNx)和氧化硅层52(SiOx)构成；低温多晶硅岛(Poly)2；离子重掺杂区(N+)10；离子轻掺杂区(LDD)11；栅极(MO gate)4；栅极绝缘层(GI)3；层间绝缘层(ILD SiOx和ILD SiNx)12，其由其由氧化硅层121(SiOx)和氮化硅122层(SiNx)构成；源极(Source)13；漏极(Drain)14；有机平坦化层(PL)15；共通电极(ITO-Com)16；钝化层(PV-SINx)17和像素电极(TITO)18。
本发明在制作LTPS面板时，只采用一个光罩形成了离子重掺杂区和离子轻掺杂区，从而减少了LTPS面板的制作工序并能降低面板的生产成本。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种用于制作多晶硅薄膜晶体管的方法，包括以下步骤：
    在预制基底上形成半导体材料层；
    在所述半导体材料层上形成中间层；
    在所述中间层上涂布光阻材料形成光阻层，并用光罩对所述光阻层进行第一次曝光；
    按一预定方向相对于所述光罩移动具有第一次曝光处理后的光阻层的预制基底，并采用所述光罩对所述光阻层进行第二次曝光；
    去除所述光阻层上受到曝光的光阻材料，以在所述光阻层上形成光阻区和镂空区，其中，所述光阻区包括中心部和翼部，所述镂空区不包含光阻材料；
    在所述半导体材料层中形成对应于所述翼部的离子轻掺杂区，以及对应于所述镂空区的用于形成源漏极的离子重掺杂区。
  2. 如权利要求1所述的方法，其中，所述光罩包括遮光区域和透光区域。
  3. 如权利要求2所述的方法，其中，在按预定方向移动所述预制基底时，所述方向及移动的距离配合设计成使得所述光罩的遮光区域覆盖所述光阻层上经过曝光后的区域中的第一部分和所述光阻层上未曝光区域中的第二部分。
  4. 如权利要求3所述的方法，其中，所述第一部分的宽度与需生成的离子轻掺杂区的宽度相等。
  5. 如权利要求4所述的方法，其中，所述光阻区的中心部由所述光阻层上在经过两次曝光后未被曝光的部分形成，所述光阻区的翼部由所述光阻层上在经过两次曝光后只经过一次曝光的部分形成。
  6. 如权利要求1所述的方法，其中，所述预制基底包括栅极金属层及所述栅极金属层上的栅极绝缘层，所述中间层为层间绝缘层。
  7. 如权利要求1所述的方法，其中，所述中间层包括栅极绝缘层及该栅极绝缘层上的用于形成栅极的栅极金属层。
  8. 如权利要求7所述的方法，其中，所述光罩包括遮光区域和透光区域。
  9. 如权利要求8所述的方法，其中，在按预定方向移动所述预制基底时，所述方向及移动的距离配合设计成使得所述光罩的遮光区域覆盖所述光阻层上经过曝光后的区域中的第一部分和所述光阻层上未曝光区域中的第二部分。
  10. 如权利要求9所述的方法，其中，所述第一部分的宽度与需生成的离子轻掺杂区的宽度相等。
  11. 如权利要求10所述的方法，其中，所述光阻区的中心部由所述光阻层上在经过 两次曝光后未被曝光的部分形成，所述光阻区的翼部由所述光阻层上在经过两次曝光后只经过一次曝光的部分形成。
  12. 如权利要求7所述的方法，其中，形成所述离子轻掺杂区和形成所述离子重掺杂区的步骤包括：
    去除所述栅极金属层中对应于所述镂空区的金属材料；
    进行高浓度离子植入，以在所述半导体材料层中对应于所述镂空区形成离子重掺杂区；
    去除所述光阻区的翼部以裸露出所述栅极金属层；
    蚀刻掉裸露出的栅极金属层；
    进行低浓度离子植入，以在所述半导体材料层中对应于去除的翼部形成离子轻掺杂区。
  13. 如权利要求12所述的方法，其中，在形成所述半导体材料层之前还包括在所述预制基底上形成一缓冲层。
  14. 如权利要求13所述的方法，其中，在形成所述缓冲层之前还包括在所述预制基底上形成与所述半导体材料层对应的遮光层。
  15. 如权利要求9所述的方法，其中，形成所述离子轻掺杂区和形成所述离子重掺杂区的步骤包括：
    去除所述栅极金属层中对应于所述镂空区的金属材料；
    进行高浓度离子植入，以在所述半导体材料层中对应于所述镂空区形成离子重掺杂区；
    去除所述光阻区的翼部以裸露出所述栅极金属层；
    蚀刻掉裸露出的栅极金属层；
    进行低浓度离子植入，以在所述半导体材料层中对应于去除的翼部形成离子轻掺杂区。
  16. 如权利要求15所述的方法，其中，在形成所述半导体材料层之前还包括在所述预制基底上形成一缓冲层。
  17. 如权利要求16所述的方法，其中，在形成所述缓冲层之前还包括在所述预制基底上形成与所述半导体材料层对应的遮光层。
  18. 如权利要求11所述的方法，其中，形成所述离子轻掺杂区和形成所述离子重掺杂区的步骤包括：
    去除所述栅极金属层中对应于所述镂空区的金属材料；
    进行高浓度离子植入，以在所述半导体材料层中对应于所述镂空区形成离子重掺杂区；
    去除所述光阻区的翼部以裸露出所述栅极金属层；
    蚀刻掉裸露出的栅极金属层；
    进行低浓度离子植入，以在所述半导体材料层中对应于去除的翼部形成离子轻掺杂区。
  19. 如权利要求18所述的方法，其中，在形成所述半导体材料层之前还包括在所述预制基底上形成一缓冲层。
  20. 如权利要求19所述的方法，其中，在形成所述缓冲层之前还包括在所述预制基底上形成与所述半导体材料层对应的遮光层。
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