CN104538307A - 一种用于制作多晶硅薄膜晶体管的方法 - Google Patents

一种用于制作多晶硅薄膜晶体管的方法 Download PDF

Info

Publication number
CN104538307A
CN104538307A CN201410796421.XA CN201410796421A CN104538307A CN 104538307 A CN104538307 A CN 104538307A CN 201410796421 A CN201410796421 A CN 201410796421A CN 104538307 A CN104538307 A CN 104538307A
Authority
CN
China
Prior art keywords
layer
photoresist
semiconductor material
exposure
ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410796421.XA
Other languages
English (en)
Other versions
CN104538307B (zh
Inventor
虞晓江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201410796421.XA priority Critical patent/CN104538307B/zh
Priority to PCT/CN2015/070965 priority patent/WO2016095308A1/zh
Priority to US14/418,186 priority patent/US9515190B2/en
Publication of CN104538307A publication Critical patent/CN104538307A/zh
Application granted granted Critical
Publication of CN104538307B publication Critical patent/CN104538307B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明公开了一种用于制作多晶硅薄膜晶体管的方法，包括：在预制基底上形成半导体材料层；在半导体材料层上形成中间层；在中间层上涂布光阻材料形成光阻层，并用光罩对光阻层进行第一次曝光；按一预定方向相对于光罩移动具有第一次曝光处理后的光阻层的预制基底，并采用光罩对所述光阻层进行第二次曝光；去除光阻层上受到曝光的光阻材料，以在光阻层上形成光阻区和镂空区，其中，光阻区包括中心部和翼部，镂空区不包含光阻材料；在半导体材料层中形成对应于翼部的离子轻掺杂区，以及对应于镂空区的用于形成源漏极的离子重掺杂区。本发明可以在制作LTPS面板时，减少面板的制作工序并能降低面板的生产成本。

Description

一种用于制作多晶硅薄膜晶体管的方法
技术领域
本发明涉及薄膜晶体管制作技术领域，具体地说，涉及一种多晶硅薄膜晶体管的制作方法。
背景技术
近年来，LTPS(Low Temperature Poly-Silicon，即低温多晶硅)面板在高端手机、平板电脑上获得了广泛应用。LTPS面板采用高迁移率的低温多晶硅来制作薄膜晶体管。这种面板具有高分辨率、低功耗、高反应速度、高开口率等优点，有望成为下一代主流的中小尺寸显示面板。
在LTPS面板上，像素的充放电控制、静电释放元件、分路器元件、栅极在阵列基板上的驱动元件都常会采用薄膜晶体管。普通低温多晶硅结构的薄膜晶体管漏电较高，为减少漏电常需要在薄膜晶体管的漏极及源极制作LDD(lightlydoped drain，轻掺杂漏极)区，用低掺杂、高电阻值的LDD区来降低漏电流。
早先的LTPS面板通常需要制作多个光罩来形成LDD区，这样，就会增加面板的制作工序和生产成本。
发明内容
为解决上述问题，本发明提供了一种简化的用于制作多晶硅薄膜晶体管的方法用以减少面板的制作工序并降低生产成本。
根据本发明的一个实施例，提供了一种用于制作多晶硅薄膜晶体管的方法，包括以下步骤：
在预制基底上形成半导体材料层；
在所述半导体材料层上形成中间层；
在所述中间层上涂布光阻材料形成光阻层，并用光罩对所述光阻层进行第一次曝光；
按一预定方向相对于所述光罩移动具有第一次曝光处理后的光阻层的预制基底，并采用所述光罩对所述光阻层进行第二次曝光；
去除所述光阻层上受到曝光的光阻材料，以在所述光阻层上形成光阻区和镂空区，其中，所述光阻区包括中心部和翼部，所述镂空区不包含光阻材料；
在所述半导体材料层中形成对应于所述翼部的离子轻掺杂区，以及对应于所述镂空区的用于形成源漏极的离子重掺杂区。
根据本发明的一个实施例，所述光罩包括遮光区域和透光区域。
根据本发明的一个实施例，在按预定方向移动所述预制基底时，所述方向及移动的距离配合设计成使得所述光罩的遮光区域覆盖所述光阻层上经过曝光后的区域中的第一部分和所述光阻层上未曝光区域中的第二部分。
根据本发明的一个实施例，所述第一部分的宽度与需生成的离子轻掺杂区的宽度相等。
根据本发明的一个实施例，所述光阻区的中心部由所述光阻层上在经过两次曝光后未被曝光的部分形成，所述光阻区的翼部由所述光阻层上在经过两次曝光后只经过一次曝光的部分形成。
根据本发明的一个实施例，所述预制基底包括栅极金属层及所述栅极金属层上的栅极绝缘层，所述中间层为层间绝缘层。
根据本发明的一个实施例，所述中间层包括栅极绝缘层及该栅极绝缘层上的用于形成栅极的栅极金属层。
根据本发明的一个实施例，形成所述离子轻掺杂区和形成所述离子重掺杂区的步骤包括：
去除所述栅极金属层中对应于所述镂空区的金属材料；
进行高浓度离子植入，以在所述半导体材料层中对应于所述镂空区形成离子重掺杂区；
去除所述光阻区的翼部以裸露出所述栅极金属层；
蚀刻掉裸露出的栅极金属层；
进行低浓度离子植入，以在所述半导体材料层中对应于去除的翼部形成离子轻掺杂区。
根据本发明的一个实施例，在形成所述半导体材料层之前还包括在所述预制基底上形成一缓冲层。
根据本发明的一个实施例，在形成所述缓冲层之前还包括在所述预制基底上形成与所述半导体材料层对应的遮光层。
本发明带来了以下有益效果：
本发明可以在制作LTPS面板时，减少LTPS面板的制作工序并能降低面板的生产成本。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要的附图做简单的介绍：
图1是根据本发明的一个实施例的方法流程图；
图2a是根据本发明的一个实施例的形成栅极金属层后的基板截面示意图；
图2b是图2a的俯视图；
图3是对图2a的基板涂布光阻材料后的截面示意图；
图4a是对图3的基板进行第一次曝光的截面示意图；
图4b是图4a的俯视图；
图5a是对图4a的基板进行第二次曝光的截面示意图；
图5b是对图5a的基板水平移动后第二次曝光的俯视图；
图5c是对图5a的基板垂直移动后第二次曝光的俯视图；
图5d是对图5a的基板按一定角度移动后第二次曝光的俯视图；
图6a是对图5d的基板去除曝光的光阻材料后的截面示意图；
图6b是图6a的俯视图；
图7a是图6a的基板去除未被光阻覆盖的栅极金属层的截面示意图；
图7b是图7a的俯视图；
图8是对图7a的基板进行高浓度离子植入的截面示意图；
图9a是对图8的基板去除翼部后的截面示意图；
图9b是图9a的俯视图；
图10a是图9a的基板去除未被光阻覆盖的栅极金属层的截面示意图；
图10b是图10a的俯视图；
图11是对图10a的基板进行低浓度离子植入的截面示意图；
图12a是图11中的去除剩余光阻的截面示意图；
图12b是图12a的俯视图；以及
图13是根据本发明的一个实施例的LTPS显示面板的截面示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
如图1所示为根据本发明的一个实施例的方法流程图，以下参考图1来对本发明所述的方法进行详细说明。此处的多晶硅薄膜晶体管中的多晶硅为高温多晶硅或低温多晶硅，本发明以制作低温多晶硅薄膜晶体管为例来进行说明。
在步骤S110中，在预制基底上形成半导体材料层并在该半导体材料层上形成中间层。
此处的半导体材料层用于形成低温多晶硅层，且该低温多晶硅层在预制基底上呈硅岛排布。由于多晶硅薄膜晶体管包括底栅结构和顶栅结构，所以，用于形成半导体材料层的预制基底的结构不同。
在底栅结构的多晶硅薄膜晶体管中，预制基底包括在基板形成的栅极金属层，该栅极金属层用于形成栅极。该预制基底还包括在栅极金属层上沉积的栅极绝缘层。对应底栅结构的多晶硅薄膜晶体管，中间层为层间绝缘层用以将半导体材料层与其后形成的其他材料层进行隔离。
在顶栅结构的多晶硅薄膜晶体管中，预制基底即为一基板(通常为玻璃基板)。对应顶栅结构的多晶硅薄膜晶体管，中间层包括栅极绝缘层及该栅极绝缘层上的用于形成栅极的栅极金属层。
在本发明中，以制作顶栅结构的多晶硅薄膜晶体管为例来进行说明，但本发明所述的方法不限于制作顶栅结构的多晶硅薄膜晶体管。
在该步骤中，制作顶栅结构的多晶硅薄膜晶体管时，首先在基板上采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)法沉积本征a-Si层(非晶硅层)；之后对a-Si层进行脱氢处理；然后采用ELA(准分子激光退火)或SLC(连续横向晶化)等工艺形成半导体材料层。该半导体材料层即为低温多晶硅层，该低温多晶硅层呈硅岛排布，各个硅岛为低温多晶硅岛。
接下来，采用PECVD法在低温多晶硅层上沉积氧化硅或氮化硅形成栅极绝缘层。如图2a所示，在基板1上沉积有低温多晶硅层，低温多晶硅层中的多晶硅形成低温多晶硅岛2。低温多晶硅层上沉积有栅极绝缘层3。该栅极绝缘层3可由单层氧化硅构成，或者由依次形成的氧化硅和氮化硅组成的双层结构构成。
接下来，采用溅射法在栅极绝缘层3上沉积钼或其它金属形成栅极金属层4。
在步骤S110中，通常会在基板1上沉积一层缓冲层5，然后在该缓冲层5上形成低温多晶硅岛2。缓冲层5通常由一层氮化硅和一层氧化硅组成。该缓冲层5可以屏蔽基板1上缺陷的影响，防止基板1上的杂质如金属离子等扩散并渗透到多晶硅有源岛2中，避免由此引起的各种器件不良。通常还会在形成缓冲层5之前，在基板1上对应低温多晶硅岛2处设置遮光层(LS MO)6来遮挡光照，这样就可以避免光照照射需形成的低温多晶硅薄膜晶体管。
经过步骤S110后的基板的截面如图2a所示，在基板1上设置有遮光层6；遮光层6和裸露的基板1上沉积有缓冲层5，缓冲层5由氮化硅层51和氧化硅层52构成；在缓冲层5上沉积有与遮光层6对应的低温多晶硅岛2；低温多晶硅岛2和裸露的缓冲层5上沉积有栅极绝缘层3；在栅极绝缘层3上沉积有栅极金属层4。如图2b所示为图2a的俯视图，图2b的表面为栅极金属层4。
在步骤S120中，在中间层上涂布光阻材料形成光阻层，并用光罩对该光阻层进行第一次曝光。
在该步骤中，首先在栅极金属层4上涂布一层光阻材料形成光阻层，并对该该光阻层进行第一次曝光处理。图3为在栅极金属层4上涂布光阻层7后的截面示意图。
此处曝光采用的光罩8包括遮光区域81和透光区域82。如图4a所示。通过控制曝光的光强和时间，使被UV(真空紫外线)光照射的一定厚度的光阻材料被UV光改变特性，如图4a中的区域9。图4b为图4a的俯视图，图中线框内的部分为对光阻材料进行第一次曝光后，光罩8的遮光区81在光阻层7上对应的未曝光区域。该区域中的光阻材料未被UV光改变特性，而线框外的光阻材料被UV光改变特性。
在步骤S130中，按一预定方向相对于光罩移动具有第一次曝光处理后的光阻层的预制基底，并采用该光罩对光阻层进行第二次曝光以形成光阻区和镂空区。
此处通过移动承载预制基底的曝光机工作台来使该基底沿预定方向移动，而光罩位置保持固定。在按预定方向移动该基板时，通过配合设计预定方向和移动的距离来使光罩的遮光区域覆盖光阻层上经过曝光后的区域中的第一部分811和光阻层上未曝光区域中的第二部分812，如图5a所示。其中，第一部分811的宽度与需生成的离子轻掺杂区的宽度相等，第一部分811的宽度与第二部分812另一侧的813的宽度相等。
确定该预定方向时，通常选定基板1的一边为基准边，沿与该基准边成一定角度的方向移动该基板1，以使得光罩8的遮光区域81在基板上的第一次曝光的非未曝光区域与第二次曝光的未曝光区域部分重叠，即两次曝光时的未曝光区域对应光阻层7的第二部分812。
此处移动的一定角度包括基板1所能移动的全部角度范围。例如，以图5a中的基板1的长边作为基准边，水平移动该基板1，这样使得基板1上的第一曝光的未曝光区域与第二曝光的未曝光区域部分重叠，即形成第二部分812。同时，在重叠区域的水平方向的相对两侧生成两个相同的第一次曝光处理后的曝光区域与第二次曝光处理后的曝光区域的非重叠区域，如图5b所示。
也可以沿该基准边垂直移动该基板1，这样使得基板1上的第一曝光处理后的未曝光区域与将要进行的第二曝光处理的未曝光区域部分重叠，即第二部分812。同时，在重叠区域的垂直方向相对两侧生成两个相同的第一次曝光处理后的曝光区域与将要进行的第二次曝光处理的曝光区域的非重叠区域，如图5c所示。
在本发明的一个具体的实施例中，还可以沿与该基准边成除水平和垂直之外的角度移动该基板1。这样使得基板1上的原来的第一曝光处理后的未曝光区域与第二曝光处理后的未曝光区域部分重叠，并同时在重叠区域的相对两侧各生成两个相同的第一曝光处理时后的曝光区域与第二曝光处理后的未曝光区域的非重叠区域，如图5d所示。其中，相对两侧的非重叠区域的宽度相等。通常，此处的一定角度可选择成30°～60°范围内的任一角度，但不限于以上所述的角度范围。当该角度选择45°时，四个非重叠区域的宽度均相等。
在确定基板1移动的距离时，以需生成的离子轻掺杂区的宽度为基准。沿预定方向移动该基板，使基板1上的第一次曝光的曝光区域与第二次曝光的曝光区域的非重叠部分的宽度与需生成的离子轻掺杂区的宽度相等。如按图5b、5c的预定方向移动基板1时，可确定基板1移动的距离为需生成的离子轻掺杂区的宽度，即第一部分811的宽度与需生成的离子轻掺杂区的宽度相等。
如按图5d的预定方向移动基板1时，则需根据预定方向和需生成的离子轻掺杂区的宽度共同来确定基板1移动的距离。在这种情形下，经过二次曝光处理后共形成了四个非重叠区域，其中，相对的两个非重叠区域宽度相等，相邻的两个非重叠区域宽度相等或不等。如相邻的两个非重叠区域宽度相等，可从中任选相对的两个非重叠区域与需生成的离子轻掺杂区对应。这样，在基板上就可以有两种薄膜晶体管的排布方式。优选的，当预定角度为45°时形成的四个非重叠区域的宽度均相等，此时，可从中任选相对的两个非重叠区域与需生成的离子轻掺杂区对应。当预定角度非45°，相邻的两个非重叠区域宽度不等时，可以根据需生成的离子轻掺杂区的排布选择相对的两个非重叠区域，进而确定基板1移动的距离。移动距离一般设置为1～5μm，不能大于要生成的薄膜晶体管之间的距离。
以下以按预定方向为30°～60°范围内的任一角度移动基板1为例来进行说明。通过控制第二次曝光的光强和时间，使光阻层上被UV光照射区域内的一定厚度的光阻材料改变特性。如图5a所示，第二次曝光之后，栅极金属层4上的光阻材料形成两种不同的成分。光阻材料未被UV光改变特性的光阻层7及已被UV光改变特性的光阻9。其中，光阻层7对应形成具有不同厚度的光阻材料的光阻区。该光阻区包括具有第一厚度的中心部71，该部分在两次曝光处理中均未被曝光。对于在两次曝光处理中，光阻材料只被曝光1次的区域，上层光阻材料已被UV光改变特性但下层光阻材料未被UV光改变特性，此处对应光阻区的具有第二厚度的翼部72。其中，第一厚度大于第二厚度。去除曝光的光阻材料后的基板的截面示意图如图6a所示，光阻区之外的裸露出中间层(即栅极金属层4)的为镂空区。图6a对应的俯视图如图6b所示。
在步骤S140中，在半导体材料层中形成对应于翼部的离子轻掺杂区，以及对应于镂空区的用于形成源漏极的离子重掺杂区。
在该步骤中，首先去除栅极金属层中对应于镂空区的金属材料，去除该部分金属材料后的基板如图7a所示。其对应形成的光阻图案的俯视图如图7b所示。
接下来，对半导体材料层进行高浓度离子植入，则在低温多晶硅岛2中对应镂空区的部分形成离子重掺杂区10，如图8所示，其俯视图与图7b相同。此处以N型离子植入为例，但不限于N型离子。离子重掺杂区10用于形成薄膜晶体管的源漏极。
接下来，去除光阻层7的翼部72，从而裸露出被翼部覆盖的栅极金属层。由于光阻层7的中心部71的光阻材料的厚度大于翼部72的光阻材料的厚度，所以在翼部72去除后，中心部71的光阻材料部分保留，只是光阻材料的厚度减少，如图9a所示。图9a对应的俯视图如图9b所示。
接下来，去除栅极金属层4中未被光阻覆盖的部分的金属材料，即栅极金属层4中对应光阻层7的原翼部72的部分的金属材料。去除翼部72对应的金属材料后的基板结构截面如图10a所示，其对应的俯视图如图10b所示。
接下来，对半导体材料层进行低浓度离子植入。在低温多晶硅岛2中对应光阻层7的原翼部72的部分形成离子轻掺杂区11，如图11所示。图11对应的俯视图与图10b相同。离子轻掺杂区11用于形成LDD区。
蚀刻掉金属层4上剩余的光阻，裸露出被光阻材料覆盖的栅极金属层。该部分栅极金属层对应形成栅极，如图12a所示，其对应的俯视图如图12b所示。至此，初步完成了具有栅极、源漏极的薄膜晶体管。
通常，将该多晶硅薄膜晶体管用于显示面板时，在栅极绝缘层3上形成栅极后，采用PECVD工艺在栅极绝缘层3上和栅极上沉积氮化硅、氧化硅形成层间绝缘层；随后，对层间绝缘层进行热退火及氢化，激活掺杂离子并改善低温多晶硅界面；然后对层间绝缘层和栅极绝缘层进行蚀刻处理形成接触孔，接触孔延伸至离子重掺杂区；随后，沉积形成源漏极金属层，并定义形成源极和漏极；随后，在源漏极金属层上制作有机平坦化层，并在接触孔部位形成通孔；接着，在有机层上形成作为共通电极的底部氧化铟锡层；然后在有机平坦化层上形成钝化层，并在钝化层上开孔形成至漏极的接触孔。在该基板上涂覆透明导电材料并经黄光、蚀刻、剥离等制程形成与漏极电气连接的像素电极。最终形成的显示面板截面如图13所示，其包括：基板1；遮光层(LS MO)6；缓冲层5，其由氮化硅层51(SiNx)和氧化硅层52(SiOx)构成；低温多晶硅岛(Poly)2；离子重掺杂区(N+)10；离子轻掺杂区(LDD)11；栅极(MO gate)4；栅极绝缘层(GI)3；层间绝缘层(ILD SiOx和ILD SiNx)12，其由其由氧化硅层121(SiOx)和氮化硅122层(SiNx)构成；源极(Source)13；漏极(Drain)14；有机平坦化层(PL)15；共通电极(ITO-Com)16；钝化层(PV-SINx)17和像素电极(TITO)18。
本发明在制作LTPS面板时，只采用一个光罩形成了离子重掺杂区和离子轻掺杂区，从而减少LTPS面板的制作工序并能降低面板的生产成本。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

1.一种用于制作多晶硅薄膜晶体管的方法，包括以下步骤：
在预制基底上形成半导体材料层；
在所述半导体材料层上形成中间层；
在所述中间层上涂布光阻材料形成光阻层，并用光罩对所述光阻层进行第一次曝光；
按一预定方向相对于所述光罩移动具有第一次曝光处理后的光阻层的预制基底，并采用所述光罩对所述光阻层进行第二次曝光；
去除所述光阻层上受到曝光的光阻材料，以在所述光阻层上形成光阻区和镂空区，其中，所述光阻区包括中心部和翼部，所述镂空区不包含光阻材料；
在所述半导体材料层中形成对应于所述翼部的离子轻掺杂区，以及对应于所述镂空区的用于形成源漏极的离子重掺杂区。
2.如权利要求1所述的方法，其特征在于，所述光罩包括遮光区域和透光区域。
3.如权利要求2所述的方法，其特征在于，在按预定方向移动所述预制基底时，所述方向及移动的距离配合设计成使得所述光罩的遮光区域覆盖所述光阻层上经过曝光后的区域中的第一部分和所述光阻层上未曝光区域中的第二部分。
4.如权利要求3所述的方法，其特征在于，所述第一部分的宽度与需生成的离子轻掺杂区的宽度相等。
5.如权利要求4所述的方法，其特征在于，所述光阻区的中心部由所述光阻层上在经过两次曝光后未被曝光的部分形成，所述光阻区的翼部由所述光阻层上在经过两次曝光后只经过一次曝光的部分形成。
6.如权利要求1-5中任一项所述的方法，其特征在于，所述预制基底包括栅极金属层及所述栅极金属层上的栅极绝缘层，所述中间层为层间绝缘层。
7.如权利要求1-5中任一项所述的方法，其特征在于，所述中间层包括栅极绝缘层及该栅极绝缘层上的用于形成栅极的栅极金属层。
8.如权利要求7所述的方法，其特征在于，形成所述离子轻掺杂区和形成所述离子重掺杂区的步骤包括：
去除所述栅极金属层中对应于所述镂空区的金属材料；
进行高浓度离子植入，以在所述半导体材料层中对应于所述镂空区形成离子重掺杂区；
去除所述光阻区的翼部以裸露出所述栅极金属层；
蚀刻掉裸露出的栅极金属层；
进行低浓度离子植入，以在所述半导体材料层中对应于去除的翼部形成离子轻掺杂区。
9.如权利要求8所述的方法，其特征在于，在形成所述半导体材料层之前还包括在所述预制基底上形成一缓冲层。
10.如权利要求9所述的方法，其特征在于，在形成所述缓冲层之前还包括在所述预制基底上形成与所述半导体材料层对应的遮光层。
CN201410796421.XA 2014-12-19 2014-12-19 一种用于制作多晶硅薄膜晶体管的方法 Active CN104538307B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201410796421.XA CN104538307B (zh) 2014-12-19 2014-12-19 一种用于制作多晶硅薄膜晶体管的方法
PCT/CN2015/070965 WO2016095308A1 (zh) 2014-12-19 2015-01-19 一种用于制作多晶硅薄膜晶体管的方法
US14/418,186 US9515190B2 (en) 2014-12-19 2015-01-19 Method for manufacturing polysilicon thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410796421.XA CN104538307B (zh) 2014-12-19 2014-12-19 一种用于制作多晶硅薄膜晶体管的方法

Publications (2)

Publication Number Publication Date
CN104538307A true CN104538307A (zh) 2015-04-22
CN104538307B CN104538307B (zh) 2018-07-06

Family

ID=52853813

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410796421.XA Active CN104538307B (zh) 2014-12-19 2014-12-19 一种用于制作多晶硅薄膜晶体管的方法

Country Status (3)

Country Link
US (1) US9515190B2 (zh)
CN (1) CN104538307B (zh)
WO (1) WO2016095308A1 (zh)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105185788A (zh) * 2015-09-01 2015-12-23 武汉华星光电技术有限公司 阵列基板及其制造方法
CN105336683A (zh) * 2015-09-30 2016-02-17 武汉华星光电技术有限公司 一种ltps阵列基板及其制作方法、显示装置
CN105549249A (zh) * 2016-02-23 2016-05-04 武汉华星光电技术有限公司 一种液晶显示面板及手机
CN105789325A (zh) * 2016-04-18 2016-07-20 深圳市华星光电技术有限公司 薄膜晶体管、薄膜晶体管的制备方法及cmos器件
CN106019694A (zh) * 2016-08-02 2016-10-12 武汉华星光电技术有限公司 一种彩色滤光片、液晶面板、液晶显示器及形成方法
CN107331668A (zh) * 2017-06-09 2017-11-07 武汉华星光电技术有限公司 一种tft基板及制作方法
CN107464806A (zh) * 2017-09-05 2017-12-12 武汉华星光电技术有限公司 一种低温多晶硅面板
CN108417587A (zh) * 2018-03-16 2018-08-17 中华映管股份有限公司 制作半导体元件及显示器的阵列基板的方法
CN109659316A (zh) * 2018-12-03 2019-04-19 武汉华星光电半导体显示技术有限公司 阵列基板及其制备方法、显示装置

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104916584A (zh) * 2015-04-30 2015-09-16 京东方科技集团股份有限公司 一种制作方法、阵列基板及显示装置
CN106409873B (zh) * 2016-10-12 2019-06-04 上海天马微电子有限公司 柔性显示装置及制造方法
CN108550581A (zh) * 2018-05-04 2018-09-18 武汉华星光电技术有限公司 一种低温多晶硅阵列基板及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020083557A1 (en) * 2000-12-28 2002-07-04 Yun-Ho Jung Apparatus and method of crystallizing amorphous silicon
CN101900947A (zh) * 2010-02-24 2010-12-01 福州华映视讯有限公司 一种曝光图案形成的方法
WO2013094555A1 (ja) * 2011-12-20 2013-06-27 シャープ株式会社 露光装置および露光マスク
CN104064472A (zh) * 2014-06-13 2014-09-24 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI366218B (en) * 2004-06-01 2012-06-11 Semiconductor Energy Lab Method for manufacturing semiconductor device
US7033902B2 (en) * 2004-09-23 2006-04-25 Toppoly Optoelectronics Corp. Method for making thin film transistors with lightly doped regions
JP5503995B2 (ja) * 2009-02-13 2014-05-28 株式会社半導体エネルギー研究所 半導体装置の作製方法
US8173527B2 (en) * 2009-10-19 2012-05-08 Varian Semiconductor Equipment Associates, Inc. Stepped masking for patterned implantation
US8692296B2 (en) * 2012-02-09 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and manufacturing methods thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020083557A1 (en) * 2000-12-28 2002-07-04 Yun-Ho Jung Apparatus and method of crystallizing amorphous silicon
CN101900947A (zh) * 2010-02-24 2010-12-01 福州华映视讯有限公司 一种曝光图案形成的方法
WO2013094555A1 (ja) * 2011-12-20 2013-06-27 シャープ株式会社 露光装置および露光マスク
CN104064472A (zh) * 2014-06-13 2014-09-24 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示装置

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105185788A (zh) * 2015-09-01 2015-12-23 武汉华星光电技术有限公司 阵列基板及其制造方法
CN105336683A (zh) * 2015-09-30 2016-02-17 武汉华星光电技术有限公司 一种ltps阵列基板及其制作方法、显示装置
CN105549249A (zh) * 2016-02-23 2016-05-04 武汉华星光电技术有限公司 一种液晶显示面板及手机
CN105789325B (zh) * 2016-04-18 2019-05-03 深圳市华星光电技术有限公司 薄膜晶体管、薄膜晶体管的制备方法及cmos器件
CN105789325A (zh) * 2016-04-18 2016-07-20 深圳市华星光电技术有限公司 薄膜晶体管、薄膜晶体管的制备方法及cmos器件
WO2017181449A1 (zh) * 2016-04-18 2017-10-26 深圳市华星光电技术有限公司 薄膜晶体管、薄膜晶体管的制备方法及cmos器件
CN106019694A (zh) * 2016-08-02 2016-10-12 武汉华星光电技术有限公司 一种彩色滤光片、液晶面板、液晶显示器及形成方法
CN107331668A (zh) * 2017-06-09 2017-11-07 武汉华星光电技术有限公司 一种tft基板及制作方法
WO2019047329A1 (zh) * 2017-09-05 2019-03-14 武汉华星光电技术有限公司 一种低温多晶硅面板
CN107464806A (zh) * 2017-09-05 2017-12-12 武汉华星光电技术有限公司 一种低温多晶硅面板
US10784286B2 (en) 2017-09-05 2020-09-22 Wuhan China Star Optoelectronics Technology Co., Ltd. Low temperature polysilicon panel
CN108417587A (zh) * 2018-03-16 2018-08-17 中华映管股份有限公司 制作半导体元件及显示器的阵列基板的方法
CN109659316A (zh) * 2018-12-03 2019-04-19 武汉华星光电半导体显示技术有限公司 阵列基板及其制备方法、显示装置
WO2020113747A1 (zh) * 2018-12-03 2020-06-11 武汉华星光电半导体显示技术有限公司 阵列基板及其制备方法、显示装置

Also Published As

Publication number Publication date
US9515190B2 (en) 2016-12-06
WO2016095308A1 (zh) 2016-06-23
CN104538307B (zh) 2018-07-06
US20160247936A1 (en) 2016-08-25

Similar Documents

Publication Publication Date Title
CN104538307A (zh) 一种用于制作多晶硅薄膜晶体管的方法
CN105489552B (zh) Ltps阵列基板的制作方法
CN104332477B (zh) 薄膜晶体管组件、阵列基板及其制作方法、和显示装置
CN103472646B (zh) 一种阵列基板及其制备方法和显示装置
CN102543860B (zh) 一种低温多晶硅tft阵列基板的制造方法
CN107482066B (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
CN106847703B (zh) 低温多晶硅薄膜晶体管的制造方法和显示装置
CN105702623B (zh) Tft阵列基板的制作方法
CN104409416A (zh) 用于制作阵列基板的方法及阵列基板
CN105789327A (zh) 一种薄膜晶体管及其制备方法、阵列基板、显示装置
US10290663B2 (en) Manufacturing method of thin film transistor and manufacturing method of array substrate
US9947696B2 (en) LTPS TFT substrate structure and method of forming the same
CN105304500B (zh) N型tft的制作方法
CN104882485A (zh) 薄膜晶体管及其制造方法
US10978495B2 (en) Array substrate and method of manufacturing the same, and display device
CN105390443B (zh) Tft基板的制作方法
CN103794566A (zh) 一种显示面板制作方法
CN103383989A (zh) 像素结构的制造方法及其结构
CN108447822A (zh) Ltps tft基板的制作方法
US9159773B2 (en) Thin film transistor and active matrix organic light emitting diode assembly
CN103985716A (zh) 薄膜晶体管阵列基板制造方法及薄膜晶体管阵列基板
TWI573226B (zh) 薄膜電晶體基板及其製作方法
US10290655B2 (en) Low temperature polysilicon array substrate and method for manufacturing the same
CN103681350B (zh) 薄膜晶体管的制作方法
CN107946244B (zh) 一种阵列基板及其制备方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant