WO2015103976A1 - 半导体衬底、半导体器件及半导体衬底制造方法 - Google Patents
半导体衬底、半导体器件及半导体衬底制造方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 148
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02609—Crystal orientation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
- H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
Definitions
- the present invention relates to the field of microelectronics, and in particular to a semiconductor substrate, a semiconductor device, and a method of fabricating a semiconductor substrate.
- Group III nitrides which are represented by gallium nitride, are receiving more and more attention because III-nitrides can be widely used as light-emitting diodes (LEDs) and high-power electronic devices for semiconductor illumination. Due to the lack of intrinsic substrates, gallium nitride devices are commonly fabricated on heterogeneous substrates such as sapphire, silicon carbide, and silicon. Due to its wide applicability, silicon substrates are the best in size and quality among the above several substrate materials. At present, the mainstream technology of complementary metal oxide semiconductor (CMOS) is based on a 12-inch silicon substrate, and the price of silicon is unmatched by several other materials. Therefore, the preparation of gallium nitride material on a large-sized silicon substrate is the best way to reduce the cost of the gallium nitride-based device.
- CMOS complementary metal oxide semiconductor
- the present invention proposes a concept of a composite substrate structure.
- the gallium nitride epitaxial wafer is preferably prepared on a Si (111) substrate, so that the prepared epitaxial film has better crystal quality, electrical properties and optical properties.
- the lattice structure of gallium nitride has a hexagonal symmetry and follows the same relationship when stress is released.
- the dissociation surface of Si(111) is also characterized by triangular symmetry, and the silicon substrate is triangular symmetrical when it is damaged by stress.
- the gallium nitride crystal prepared on Si(111) Due to the symmetrical matching relationship, the gallium nitride crystal prepared on Si(111) has the best quality, but correspondingly, it is also the most easily broken when subjected to stress.
- the present invention proposes to fabricate a gallium nitride epitaxial layer using a silicon asymmetric composite substrate.
- the stress in the silicon semiconductor is continuously accumulated as the thickness of the silicon in the same crystal orientation increases, and when the surface of the silicon of the same crystal orientation comes into contact with the silicon of the other crystal orientation, the stress is reduced without accumulating.
- the invention introduces two or more layers of Si(111) in different crystal orientations, so that the dissociation surfaces of the Si(111) semiconductor layers which are in contact with each other do not overlap, thereby reducing the damage of the stress through the silicon substrate and preventing the silicon substrate from being damaged.
- the cracking of the gallium nitride semiconductor layer caused by the cracking achieves the purpose of improving the robustness and reliability of the gallium nitride semiconductor layer.
- the above composite substrate can also be formed by combining two different crystal orientation silicon semiconductor layers, such as a Si (111) semiconductor layer and a Si (100) semiconductor layer to form a composite substrate structure.
- a Si (111) semiconductor layer By controlling the angle at which the silicon wafer is bonded, the dissociation surfaces of the Si (111) semiconductor layer and the Si (100) semiconductor layer are not overlapped, so that defects generated by the gallium nitride epitaxial layer are transferred to one of the silicon semiconductor layers. It will be greatly reduced, thereby avoiding the continuation of another silicon semiconductor layer, reducing the probability of substrate fracture caused by the stress of the gallium nitride epitaxial layer, and enhancing the robustness and reliability of the substrate.
- the fabrication of the above composite substrate can be accomplished by wafer bonding.
- two thinner substrates can be bonded at different angles in different crystal orientations to form a composite substrate.
- a semiconductor substrate including a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are in a vertical direction Having a different dissociation surface, the semiconductor layer obtained by rotating the first semiconductor layer after the lattice symmetry of the first semiconductor layer has a different dissociation surface in the vertical direction from the second semiconductor layer.
- the semiconductor layer obtained by rotating the first semiconductor layer and the second semiconductor layer in accordance with the lattice symmetry of the second semiconductor layer has a different dissociation surface in the vertical direction, or the first half a semiconductor layer obtained by rotating a conductor layer in a lattice symmetry of the first semiconductor layer and a lattice layer obtained by rotating the second semiconductor layer in a lattice symmetry of the second semiconductor layer has a vertical direction Different dissociation surfaces.
- the materials of the first semiconductor layer and the second semiconductor layer are the same or different.
- the first semiconductor layer and the second semiconductor layer have the same lattice structure, and the first semiconductor layer and the second semiconductor layer have the same crystal orientation in a vertical direction, The crystal directions in the horizontal direction do not coincide.
- the crystal structures of the first semiconductor layer and the second semiconductor layer are different, and the crystal directions of the first semiconductor layer and the second semiconductor layer in the horizontal direction do not coincide.
- the material form of the first semiconductor layer includes a combination of one or more of a crystalline state, an amorphous state, and an amorphous state.
- the material of the first semiconductor layer is an amorphous material
- the amorphous material includes a non-semiconductor material including aluminum nitride, polycrystalline silicon carbide, ceramic, and quartz. .
- the first semiconductor layer is an amorphous material, and the bonding direction of the first semiconductor layer and the second semiconductor layer is not limited.
- the second semiconductor layer is a crystal layer.
- the first semiconductor layer and the second semiconductor layer are alternately formed in a stacked structure of three or more layers in this order.
- the laminated structure includes a dielectric layer between the first semiconductor layer and the second semiconductor layer.
- the dielectric layer has the same crystal orientation in the vertical direction and the crystal orientation in the horizontal direction does not coincide with the adjacent first semiconductor layer;
- the dielectric layer and the adjacent second semiconductor layer have the same crystal orientation in the vertical direction and do not coincide in the crystal orientation in the horizontal direction.
- the dielectric layer and the crystal of the adjacent first semiconductor layer The structure is different, and the crystal orientation does not coincide in the horizontal direction;
- the dielectric layer is different from the crystal structure of the adjacent second semiconductor layer, and the crystal orientation does not coincide in the horizontal direction.
- a semiconductor device includes a semiconductor substrate and a semiconductor epitaxial layer on the semiconductor substrate, the semiconductor substrate being the semiconductor substrate of any of the above embodiments.
- the semiconductor epitaxial layer comprises a combination of one or more of silicon, gallium arsenide, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum gallium indium nitride.
- the semiconductor device includes a light emitting diode, a laser diode, a high electron mobility transistor, a field effect transistor, a Schottky diode, a PIN diode, and a solar cell.
- a method of manufacturing a semiconductor substrate comprising:
- the semiconductor layer obtained by the lattice symmetry rotation of the first semiconductor layer has a different dissociation surface in the vertical direction from the second semiconductor layer, and the first semiconductor layer and the second semiconductor layer are as described above.
- the semiconductor layer obtained after the lattice symmetry rotation of the second semiconductor layer has a different dissociation surface in the vertical direction, or the semiconductor obtained by rotating the first semiconductor layer in accordance with the lattice symmetry of the first semiconductor layer
- the semiconductor layer obtained after the layer and the second semiconductor layer are rotated by the lattice symmetry of the second semiconductor layer has different dissociation faces in the vertical direction.
- the method further includes:
- a semiconductor epitaxial layer is formed on the second semiconductor layer.
- the method of preparing the first semiconductor layer and the second semiconductor layer includes a combination of one or more of a Czochralski method, a zone melting method, a physical vapor deposition, and a chemical vapor deposition.
- the first semiconductor layer is prepared in the step S2.
- the method of the two semiconductor layers includes wafer bonding.
- the method of preparing the semiconductor epitaxial layer includes a combination of one or more of metal organic chemical vapor deposition, molecular beam epitaxy, and hydride vapor phase epitaxy.
- the method further includes:
- the first semiconductor layer and the second semiconductor layer are alternately prepared on the second semiconductor layer in order to form a stacked structure of three or more layers.
- the method further comprises:
- a dielectric layer is grown between the first semiconductor layer and the second semiconductor layer.
- the dielectric layer is formed by a method of deposition, thermal oxidation or nitridation, the method of deposition including one or a combination of CVD, PECVD, LPCVD, RTCVD, MOCVD, MBE, ALD .
- the semiconductor substrate, the semiconductor device and the semiconductor substrate manufacturing method provided by the invention enable the semiconductor substrate to have a special lattice structure and a mechanical structure, and the semiconductor substrate is a composite substrate structure, and under the same substrate thickness condition,
- the damage caused by the stress applied by the epitaxial layer of the semiconductor on the silicon substrate can be reduced, thereby reducing the probability of breakage of the silicon substrate; at the same time, the process difficulty can be reduced and the reliability of the semiconductor device can be enhanced.
- FIG. 1 is a schematic view showing respective crystal orientations of silicon involved in the present invention
- FIG. 2 is a structural view of a semiconductor substrate in which the ⁇ -211> direction of the upper layer Si (111) and the ⁇ 1-10> direction of the lower layer Si (111) are parallel in the first embodiment of the present invention;
- FIG. 3 is a ⁇ -211> direction of the upper layer Si (111) and a lower layer Si (111) in the second embodiment of the present invention. a semiconductor substrate structure diagram parallel to the ⁇ -101> direction;
- FIG. 4(a) is a structural view of a semiconductor substrate having an off angle of a ⁇ -211> direction of an upper Si (111) and a ⁇ -211> direction of an underlying Si (111) in a third embodiment of the present invention
- FIG. 4 (b) and FIG. 4(c) are plan views of the upper layer Si (111) and the lower layer Si (111), respectively;
- FIG. 5(a) is a structural view of a semiconductor substrate having an off angle of the ⁇ -211> direction of the upper layer Si (111) and the ⁇ -110> direction of the lower layer Si (100) in the fourth embodiment of the present invention
- FIG. 5 (b) and FIG. 5(c) are plan views of the upper layer Si (111) and the lower layer Si (100), respectively;
- FIG. 6 is a structural diagram of a semiconductor substrate having an alternate composite substrate structure of Si (111) layer and Si (100) layer in a fifth embodiment of the present invention
- FIG. 7 is a structural diagram of a semiconductor substrate having an alternate composite substrate structure of Si (110) layer and Si (100) layer in a sixth embodiment of the present invention.
- Figure 8 is a structural view of a semiconductor substrate having an alternate composite substrate structure of Si (111) layer and Si (110) layer in a seventh embodiment of the present invention.
- FIG. 1 is a schematic view showing the respective crystal orientations of silicon involved in the present invention, and the present invention will be further described below with reference to FIG. 1 for different embodiments.
- the semiconductor substrate 1 includes: a first semiconductor layer 11; a second semiconductor layer 12 on the first semiconductor layer 11, and a second semiconductor layer 12 may be used to prepare the semiconductor epitaxial layer 2.
- the first semiconductor layer 11 and the second semiconductor layer 12 have different dissociation faces in the vertical direction.
- the first semiconductor layer 11 may be one of a semiconductor material, an amorphous material, and a crystal.
- the semiconductor material selected by the first semiconductor layer 11 includes one or more of Si, GaN, AlN, SiC, GaAs, InP, and diamond, and the amorphous material includes aluminum nitride, ceramic, quartz, and the like.
- the bonding direction of the first semiconductor layer 11 and the second semiconductor layer 12 is not limited.
- the first semiconductor layer 12 may be a crystal layer, and the semiconductor material selected for the first semiconductor layer 12 includes one or more of Si, GaN, AlN, SiC, GaAs, InP, diamond, the first semiconductor layer 11 and the second semiconductor.
- the materials of layer 12 may be the same or different, but with different crystal orientations. If the first semiconductor layer and the second semiconductor layer have the same lattice structure, the first semiconductor layer and the second semiconductor layer have the same crystal orientation in the vertical direction, the crystal orientations in the horizontal direction do not coincide; or the first semiconductor The crystal structure of the layer and the second semiconductor layer are different, and the crystal directions of the first semiconductor layer and the second semiconductor layer in the horizontal direction do not coincide.
- the first semiconductor layer 11 and the second semiconductor layer 12 may have the same lattice structure Si (111), have the same crystal orientation in the vertical direction, but have different crystal symmetry in the horizontal direction.
- the semiconductor epitaxial layer 2 may include a combination of one or more of silicon, gallium arsenide, gallium nitride, aluminum gallium nitride, indium gallium nitride, and aluminum gallium indium nitride.
- LEDs light-emitting diodes
- HEMTs high electron mobility transistors
- FETs field effect transistors
- Schottky diodes Schottky diodes
- PIN diodes etc.
- a method of manufacturing the above semiconductor substrate 1 including the following steps:
- step S2 the method further comprises: preparing a semiconductor epitaxial layer 2 on the second semiconductor layer 12.
- the method may further include:
- a first semiconductor layer 13 may also be formed on the second semiconductor layer 12 to form a stacked structure of a three-layer structure. It should be noted that, in the embodiment of the present invention, the first semiconductor layer 13 and the first semiconductor layer 11 have the same lattice structure, and both have the same crystal orientation in the vertical direction, and the crystals in the horizontal direction. The directions can be coincident or not coincident.
- the method may further include:
- the first semiconductor layer 13 and the second semiconductor layer may be alternately formed on the second semiconductor layer 12 in order to form a stacked structure of three or more layers.
- both the first semiconductor layer 11 and the second semiconductor layer 12 include a Si (111) semiconductor layer, wherein the second semiconductor layer 12 is the ⁇ -211> direction of the upper Si (111) semiconductor layer and the first semiconductor layer 11 is that the ⁇ 1-10> directions of the underlying Si (111) semiconductor layers are parallel to each other.
- an angle may be set between the ⁇ -211> direction of the second semiconductor layer 12 and the ⁇ 1-10> direction of the first semiconductor layer 11, such as an angle of 10°, 20°, or 30.
- the first semiconductor layer 11 and the second semiconductor layer 12 may be alternately laminated to form a composite structure such that the dissociation faces of the upper Si (111) semiconductor layer and the underlying Si (111) semiconductor layer are shifted from each other, and a single silicon semiconductor layer
- this method can reduce the accumulation of stress at the interface between the upper Si (111) semiconductor layer and the lower Si (111) semiconductor layer, and can avoid the local stress accumulation of the silicon semiconductor layer to the entire silicon semiconductor layer, resulting in the entire silicon.
- the substrate is cracked.
- the semiconductor substrate 1 includes: a first semiconductor layer 11; a second semiconductor layer 12 on the first semiconductor layer 11, and a second semiconductor layer 12 may be used to prepare the semiconductor epitaxial layer 2.
- the first semiconductor layer 11 includes a lower Si (111) semiconductor layer
- the second semiconductor layer 12 includes an upper Si (111) semiconductor layer, and the ⁇ -211> direction of the upper Si (111) semiconductor layer and the lower Si (111) layer
- the ⁇ -101> directions are parallel to each other.
- the first semiconductor layer 11 and the second semiconductor layer 12 may be alternately laminated to form a composite structure. This can ensure that the upper Si (111) semiconductor layer and the lower Si (111) semiconductor layer have different dissociation surfaces in the same direction, thereby avoiding the crack of the silicon substrate caused by the accumulation of stress, and the silicon substrate can be greatly improved. Reliability.
- FIGS. 4(b) and 4(c) are schematic diagrams showing the structure of a semiconductor substrate in a third embodiment of the present invention, that is, the ⁇ -211> direction of the upper Si (111) and the lower Si (111).
- 4(a) is a schematic cross-sectional view of the structure
- FIGS. 4(b) and 4(c) are plan views of the upper layer Si (111) and the lower layer Si (111), respectively.
- the semiconductor substrate 1 includes: a first semiconductor layer 11; a second semiconductor layer 12 on the first semiconductor layer 11, and a second semiconductor layer 12 may be used to prepare the semiconductor epitaxial layer 2.
- the first semiconductor layer 11 includes a lower Si (111) semiconductor layer
- the second semiconductor layer 12 includes an upper Si (111) semiconductor layer, and the ⁇ -211> direction of the upper Si (111) semiconductor layer and the lower Si (111) layer
- the first semiconductor layer 11 and the second semiconductor layer 12 may be alternately laminated to form a composite structure. This can ensure that the upper Si (111) semiconductor layer and the lower Si (111) semiconductor layer have different dissociation surfaces in the same direction, thereby avoiding the crack of the silicon substrate caused by the accumulation of stress, and the silicon substrate can be greatly improved. Reliability.
- 5(a), 5(b) and 5(c) are schematic views showing the structure of a semiconductor substrate in a fourth embodiment of the present invention, that is, the ⁇ -211> direction of the upper Si (111) and the lower Si (100).
- 5(a) is a schematic cross-sectional view of the structure
- FIGS. 5(b) and 5(c) are plan views of the upper layer Si (111) and the lower layer Si (100), respectively.
- the semiconductor substrate 1 includes a first semiconductor layer 11 and a second semiconductor layer 12 on the first semiconductor layer 11, which may be used to prepare the semiconductor epitaxial layer 2.
- the crystal structures of the first semiconductor layer 11 and the second semiconductor layer 12 are different, and the crystal directions of the first semiconductor layer 11 and the second semiconductor layer 12 in the horizontal direction do not overlap.
- the first semiconductor layer 11 includes a lower Si (100) semiconductor layer
- the second semiconductor layer 12 includes an upper Si (111) semiconductor layer, and the ⁇ -211> direction of the upper Si (111) semiconductor layer and the lower Si (100) layer There is a declination in the ⁇ -110> direction, and the magnitude of the declination is not equal to an integer multiple of 90° or 90°.
- the first semiconductor layer and the second semiconductor layer may be alternately laminated to form a composite structure. This can ensure that the upper Si (111) semiconductor layer and the lower Si (100) semiconductor layer have different dissociation surfaces in the same direction, thereby avoiding the crack of the silicon substrate caused by the accumulation of stress, and the silicon substrate can be greatly improved. Reliability.
- the semiconductor substrate 1 may be formed by laminating three or more semiconductor layers, and the semiconductor epitaxial layer 2 is formed on the semiconductor substrate 1.
- the semiconductor layer includes the first semiconductor layer 11 and the second semiconductor layer 12. It should be noted that when the semiconductor substrate includes two or more first semiconductor layers, the plurality of first semiconductor layers each have the same lattice structure, and the plurality of first semiconductor layers have the same in the vertical direction. In the crystal orientation, the crystal orientations in the horizontal direction may or may not coincide.
- the semiconductor substrate includes two or more second semiconductor layers
- the plurality of second semiconductor layers each have the same lattice structure, and the plurality of second semiconductor layers are in a vertical direction
- the crystal grains have the same crystal orientation upward, and the crystal orientations in the horizontal direction may or may not coincide.
- Fig. 6 is a schematic structural view of a semiconductor substrate in a fifth embodiment of the present invention.
- the composite substrate shown in FIG. 6 includes three semiconductor layers, which are the first semiconductor layer 11, the second semiconductor layer 12, and the first semiconductor layer 13, respectively, from the bottom to the top.
- the first semiconductor layer 11 and the second semiconductor layer have the same lattice structure, and both have the same crystal orientation in the vertical direction, and the crystal orientations in the horizontal direction may or may not coincide.
- the first semiconductor layer and the second semiconductor layer alternately form a stacked structure composed of three semiconductor layers in this order.
- the first semiconductor layer 11 includes a lower Si (111) semiconductor layer
- the second semiconductor layer 12 includes an upper Si (100) semiconductor layer.
- the semiconductor substrate formed by alternately laminating the first semiconductor layer 11 and the second semiconductor layer 12 in this order is not limited to the three-layer structure shown in FIG. 6.
- the first The semiconductor layer 11 and the second semiconductor layer 12 may be alternately laminated to form a laminated structure of three or more layers.
- Si may be formed by alternately laminating the first semiconductor layer 11 and the second semiconductor layer 12 in this order.
- the stacked structure in which the first semiconductor layer 11 and the second semiconductor layer 12 are alternately formed in three or more layers may further include a dielectric layer between the first semiconductor layer 11 and the second semiconductor layer 12 (FIG. 6).
- the dielectric layer material includes SiO 2 , SiN, AlN, or the like.
- the dielectric layer has the same crystal orientation in the vertical direction as the first semiconductor layer 11 adjacent thereto, and does not coincide in the horizontal direction in the horizontal direction; and/or the second layer adjacent to the dielectric layer
- the semiconductor layers 12 have the same crystal orientation in the vertical direction and do not overlap in the crystal direction in the horizontal direction.
- the material of the dielectric layer may also be amorphous, as a buffer layer of the substrate material, reducing the accumulation of stress; on the other hand, the material of the dielectric layer has a higher dielectric constant (such as the dielectric constant of SiO 2 ) 3.9, SiN has a dielectric constant of 7.0, AlN has a dielectric constant of 8.5) and a critical breakdown electric field. Under the premise of ensuring sufficient breakdown voltage of the substrate, it can have a sufficient thickness of dielectric material to ensure the quality of the dielectric material. Increase the robustness and reliability of the substrate material.
- Fig. 7 is a schematic view showing the structure of a semiconductor substrate in a sixth embodiment of the present invention, which is a composite substrate formed by alternately laminating Si (110) layers and Si (100) layers.
- the semiconductor substrate 1 may be formed by alternately laminating three or more semiconductor layers, and the semiconductor epitaxial layer 2 is formed on the semiconductor substrate 1.
- the semiconductor layer includes the first semiconductor layer 11 and the second semiconductor layer 12.
- the composite substrate shown in FIG. 7 includes three semiconductor layers, which are the first semiconductor layer 11, the second semiconductor layer 12, and the first semiconductor layer 13, respectively, from the bottom to the top.
- the first semiconductor layer 11 and the second semiconductor layer have the same lattice structure, and both have the same crystal orientation in the vertical direction, and the crystal orientations in the horizontal direction may or may not coincide.
- the first semiconductor layer 11 comprises a lower Si (110) semiconductor layer
- the second semiconductor layer 12 comprises an upper Si (100) semiconductor layer.
- a composite substrate structure of Si (110), Si (100), Si (110), and Si (100) can be formed when the first semiconductor layer 11 and the second semiconductor layer 12 are alternately stacked in this order.
- the composite substrate structure may include a laminated structure of three or more layers. This method also ensures that the dissociation surfaces of the respective silicon semiconductor layers are not in the same direction, thereby avoiding the cracking of the silicon substrate caused by the accumulation of stress, and the reliability of the silicon substrate can be greatly improved.
- the laminated structure further includes a dielectric layer (not shown in FIG. 7) between the first semiconductor layer 11 and the second semiconductor layer 12, and the dielectric layer material includes SiO 2 , SiN, AlN, or the like.
- the dielectric layer has the same crystal orientation in the vertical direction as the adjacent first semiconductor layer 11 and/or the second semiconductor layer 12, and does not overlap in the horizontal direction in the horizontal direction; or the dielectric layer and the adjacent first semiconductor layer 11 And/or the crystal structure of the second semiconductor layer 12 is different, and the crystal orientation does not coincide in the horizontal direction.
- the dielectric layer can act as a buffer layer for the substrate material, reducing stress accumulation; on the other hand, the dielectric layer has a higher dielectric constant (eg, SiO 2 dielectric constant is 3.9, SiN dielectric constant is 7.0, AlN) The dielectric constant is 8.5). Under the premise of ensuring sufficient breakdown voltage of the substrate, the dielectric material can be of sufficient thickness to ensure the quality of the dielectric layer and increase the robustness and reliability of the substrate.
- FIG 8 is a schematic view showing the structure of a semiconductor substrate in a seventh embodiment of the present invention, which is a composite substrate in which Si (111) layers and Si (110) layers are alternately formed.
- the semiconductor substrate 1 may be formed by alternately laminating three or more semiconductor layers, and the semiconductor epitaxial layer 2 is formed on the semiconductor substrate 1.
- the semiconductor layer includes the first semiconductor layer 11 and the second semiconductor layer 12.
- the composite substrate shown in FIG. 8 includes three semiconductor layers, which are respectively the first semiconductor from bottom to top.
- the first semiconductor layer 11 and the second semiconductor layer have the same lattice structure, and both have the same crystal orientation in the vertical direction, and the crystal orientations in the horizontal direction may or may not coincide.
- the first semiconductor layer and the second semiconductor layer are alternately formed in a stacked structure of three or more layers in this order.
- the first semiconductor layer 11 includes a lower Si (111) semiconductor layer
- the second semiconductor layer 12 includes an upper Si (110) semiconductor layer.
- the two semiconductor layers are laminated to form a composite substrate structure of Si (111), Si (110), Si (111), and Si (110). This method also ensures that the dissociation surfaces of the respective silicon semiconductor layers are not in the same direction, thereby avoiding the cracking of the silicon substrate caused by the accumulation of stress, and the reliability of the silicon substrate can be greatly improved.
- the stacked structure further includes a dielectric layer between the first semiconductor layer and the second semiconductor layer, the dielectric layer material including SiO 2 , SiN, AlN, or the like.
- the dielectric layer has the same crystal orientation in the vertical direction as the adjacent first semiconductor layer and/or the second semiconductor layer, and does not coincide in the horizontal direction in the horizontal direction; or the dielectric layer and the adjacent first semiconductor layer and/or The crystal structure of the second semiconductor layer is different, and the crystal orientation does not coincide in the horizontal direction.
- the material of the dielectric layer may also be amorphous, as a buffer layer of the substrate, reducing the accumulation of stress; on the other hand, the dielectric layer material has a high dielectric constant (such as a dielectric constant of 3.9 for SiO 2 , SiN has a dielectric constant of 7.0, AlN has a dielectric constant of 8.5) and a critical breakdown electric field. Under the premise of ensuring sufficient breakdown voltage of the substrate, it can have a dielectric layer of sufficient thickness to ensure the quality of the dielectric layer. The robustness and reliability of large substrates.
- the first semiconductor layer and the second semiconductor layer in the substrate may be The accumulation of stress at the interface of the semiconductor layer can be prevented, and the entire substrate can be prevented from being cracked due to local stress accumulation of the second semiconductor layer to the entire semiconductor layer.
- the first semiconductor layer and the second semiconductor layer have different dissociation faces in a vertical direction
- the first semiconductor layer is rotated after lattice symmetry of the first semiconductor layer
- the obtained semiconductor layer and the second semiconductor layer have different dissociation surfaces in a vertical direction
- the first semiconductor layer and the second semiconductor layer are rotated by lattice symmetry of the second semiconductor layer to obtain a semiconductor layer having a different dissociation surface in a vertical direction, or a semiconductor layer obtained by rotating the first semiconductor layer in a lattice symmetry of the first semiconductor layer and the second semiconductor layer according to the first
- the semiconductor layers obtained after the lattice symmetry rotation of the two semiconductor layers have different dissociation faces in the vertical direction.
- the present invention provides a semiconductor substrate, a semiconductor device and a semiconductor
- the bulk substrate manufacturing method makes the semiconductor substrate have a special lattice structure and mechanical structure, and the semiconductor substrate is set as a composite substrate structure, and under the condition of the substrate thickness, the stress applied to the semiconductor epitaxial layer can be reduced to the silicon lining. Damage caused by the bottom, thereby reducing the probability of silicon substrate fracture; at the same time, it can reduce the process difficulty and enhance the reliability of the semiconductor device.
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Abstract
Description
Claims (23)
- 一种半导体衬底,其特征在于,所述半导体衬底包括第一半导体层以及位于所述第一半导体层上的第二半导体层;其中,所述第一半导体层和所述第二半导体层在垂直方向上具有不同的解离面,所述第一半导体层按所述第一半导体层的晶格对称性旋转后得到的半导体层与所述第二半导体层在垂直方向上具有不同的解离面,所述第一半导体层与所述第二半导体层按所述第二半导体层的晶格对称性旋转后得到的半导体层在垂直方向上具有不同的解离面,或者所述第一半导体层按所述第一半导体层的晶格对称性旋转后得到的半导体层与所述第二半导体层按所述第二半导体层的晶格对称性旋转后得到的半导体层在垂直方向上具有不同的解离面。
- 根据权利要求1所述的半导体衬底,其特征在于,所述第一半导体层和所述第二半导体层的材料相同或不同。
- 根据权利要求2所述的半导体衬底,其特征在于,所述第一半导体层和所述第二半导体层具有相同的晶格结构,所述第一半导体层和所述第二半导体层在垂直方向上具有相同的晶向、在水平方向上的晶向不重合。
- 根据权利要求2所述的半导体衬底,其特征在于,所述第一半导体层和所述第二半导体层的晶体结构不同,所述第一半导体层和所述第二半导体层在水平方向的晶向不重合。
- 根据权利要求1所述的半导体衬底,其特征在于,所述第一半导体层的材料形态包括晶态、非晶态和无定形态的一种或多种的组合。
- 根据权利要求5所述的半导体衬底,其特征在于,所述第一半导体层的材料为无定形态材料,所述无定形态材料包括非半导体材料,所述非半导体材料包括氮化铝、多晶碳化硅、陶瓷和石英。
- 根据权利要求5所述的半导体衬底,其特征在于,所述第一半导体层为无定形态材料,第一半导体层和第二半导体层的键合方向不受限制。
- 根据权利要求1所述的半导体衬底,其特征在于,所述第二半导体层为晶体层。
- 根据权利要求1所述的半导体衬底,其特征在于,所述第一半导体层和所述第二半导体层依次交替形成三层或三层以上的层叠结构。
- 根据权利要求9所述的半导体衬底,其特征在于,所述层叠结构包括位于所述第一半导体层和所述第二半导体层之间的介质层。
- 根据权利要求10所述的半导体衬底,其特征在于,所述介质层与其相邻的所述第一半导体层在垂直方向上具有相同的晶向、在水平方向上晶向不重合;和/或,所述介质层与其相邻的所述第二半导体层在垂直方向上具有相同的晶向、在水平方向上晶向不重合。
- 根据权利要求10所述的半导体衬底,其特征在于,所述介质层与相邻的所述第一半导体层的晶体结构不同,且在水平方向上晶向不重合;和/或,所述介质层与相邻的所述第二半导体层的晶体结构不同,且在水平方向上晶向不重合。
- 一种半导体器件,其特征在于,包括半导体衬底以及位于所述半导体衬底之上的半导体外延层,所述半导体衬底为权利要求1~12任一项所述的半导体衬底。
- 根据权利要求13所述的半导体器件,其特征在于,所述半导体外延层包括硅、砷化镓、氮化镓、铝镓氮、铟镓氮、铝镓铟氮中的一种或多种的组合。
- 根据权利要求13所述的半导体器件,其特征在于,所述半导体器件包括发光二极管、激光二极管、高电子迁移率晶体管、场效应晶体管、肖特基二极管、PIN二极管或太阳能电池。
- 一种半导体衬底的制造方法,其特征在于,所述方法包括:S1、提供第一半导体层;S2、在所述第一半导体层上制备第二半导体层,其中,所述第一半导体层和所述第二半导体层在垂直方向上具有不同的解离面,所述第一半导体层按所述第一半导体层的晶格对称性旋转后得到的半导体层与所述第二半导体层在垂直方向上具有不同的解离面,所述第一半导体层与所述第二半导体层按所述第二半导体层的晶格对称性旋转后得到的半导体层在垂直方向上具有不同的解离面,或者所述第一半导体层按所述第一半导体层的晶格对称性旋转后得到的半导体层与所述第二半导体层按所述第二半导体层的晶格对称性旋转后得到的半导体层在垂直方向上具有不同的解离面。
- 根据权利要求16所述的制造方法,其特征在于,所述步骤S2后还包括:在所述第二半导体层上制备半导体外延层。
- 根据权利要求16所述的制造方法,其特征在于,所述第一半导体层和所述第二半导体层的制备方法包括直拉法、区熔法、物理气相沉积和化学气相沉积中的一种或多种的组合。
- 根据权利要求16所述的制造方法,其特征在于,所述步骤S2中在所述第一半导体层上制备第二半导体层的方法包括晶片键合。
- 根据权利要求16所述的制造方法,其特征在于,所述半导体外延层的制备方法包括金属有机物化学气相沉积、分子束外延和氢化物气相外延中的一种或多种的组合。
- 根据权利要求16所述的制造方法,其特征在于,所述步骤S2后还包括:在所述第二半导体层上制备所述第一半导体层,以形成三层结构的层叠结构;或者,在所述第二半导体层上依次交替制备所述第一半导体层和所述第二半导体层,以形成三层以上结构的层叠结构。
- 根据权利要求21所述的制造方法,其特征在于,所述方法还包括:在所述第一半导体层和所述第二半导体层之间生长介质层。
- 根据权利要求22所述的制造方法,其特征在于,所述介质层通过沉积、热氧化或者氮化的方法制成,所述沉积的方法包括CVD、PECVD、LPCVD、RTCVD、MOCVD、MBE、ALD中的一种或多种的组合。
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JP6863423B2 (ja) * | 2019-08-06 | 2021-04-21 | 信越半導体株式会社 | 電子デバイス用基板およびその製造方法 |
WO2023100577A1 (ja) * | 2021-12-01 | 2023-06-08 | 信越半導体株式会社 | 電子デバイス用基板及びその製造方法 |
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WO2017222513A1 (en) * | 2016-06-22 | 2017-12-28 | Intel Corporation | Techniques for monolithic co-integration of silicon and iii-n semiconductor transistors |
US20190279908A1 (en) * | 2016-06-22 | 2019-09-12 | Intel Corporation | Techniques for monolithic co-integration of silicon and iii-n semiconductor transistors |
US10879134B2 (en) | 2016-06-22 | 2020-12-29 | Intel Corporation | Techniques for monolithic co-integration of silicon and III-N semiconductor transistors |
Also Published As
Publication number | Publication date |
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EP3093891A1 (en) | 2016-11-16 |
US10249788B2 (en) | 2019-04-02 |
DK3093891T3 (da) | 2019-05-06 |
SG11201605542RA (en) | 2016-08-30 |
CN103681992A (zh) | 2014-03-26 |
JP2017507478A (ja) | 2017-03-16 |
US20160315220A1 (en) | 2016-10-27 |
EP3093891B1 (en) | 2019-03-06 |
EP3093891A4 (en) | 2017-01-25 |
KR20160104723A (ko) | 2016-09-05 |
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