WO2015097874A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2015097874A1
WO2015097874A1 PCT/JP2013/085148 JP2013085148W WO2015097874A1 WO 2015097874 A1 WO2015097874 A1 WO 2015097874A1 JP 2013085148 W JP2013085148 W JP 2013085148W WO 2015097874 A1 WO2015097874 A1 WO 2015097874A1
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WO
WIPO (PCT)
Prior art keywords
base plate
semiconductor device
groove
semiconductor
flat
Prior art date
Application number
PCT/JP2013/085148
Other languages
English (en)
French (fr)
Inventor
吉村　晃一
倉地　和博
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to US15/023,870 priority Critical patent/US9543227B2/en
Priority to DE112013007721.3T priority patent/DE112013007721B4/de
Priority to CN201380081897.9A priority patent/CN105849904B/zh
Priority to PCT/JP2013/085148 priority patent/WO2015097874A1/ja
Priority to JP2015554453A priority patent/JP6024838B2/ja
Publication of WO2015097874A1 publication Critical patent/WO2015097874A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L2023/4018—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by the type of device to be heated or cooled
    • H01L2023/4031—Packaged discrete devices, e.g. to-3 housings, diodes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L2023/4037—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink
    • H01L2023/405—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink heatsink to package
    • H—ELECTRICITY
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    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L2023/4037—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink
    • H01L2023/4068—Heatconductors between device and heatsink, e.g. compliant heat-spreaders, heat-conducting bands
    • H—ELECTRICITY
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    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
    • H01L2023/4075—Mechanical elements
    • H01L2023/4087—Mounting accessories, interposers, clamping or screwing parts
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device.
  • a semiconductor device having a groove portion that suppresses spread of grease between a base plate and a cooling fin is known.
  • heat conductive grease is applied to the lower surface of the base plate of the power module, and the base plate and the cooling fin are fixed with screws through the grease.
  • the pressure is applied to improve the compatibility between the cooling fin and the grease, and further, the screw is fixed by tightening with the screw, so that the grease spreads in the plane direction of the base plate at the time of fixing.
  • the grease diffusion preventing portion is provided on at least one of the opposing surfaces of the base plate and the cooling fin, and the grease diffusion preventing portion is a groove portion or a protrusion. Part.
  • Japanese Unexamined Patent Publication No. 2003-168772 Japanese Unexamined Patent Publication No. 2006-196576 Japanese Unexamined Patent Publication No. 2010-92999 Japanese Unexamined Patent Publication No. 2010-283222 Japanese Unexamined Patent Publication No. 2008-4745
  • the semiconductor element in the power module generates heat when energized, the base plate expands, and when not energized, the temperature decreases and the base plate contracts. Heat generation and cooling are alternately repeated depending on whether or not the semiconductor element is energized, so that the grease applied between the base plate and the cooling fin gradually protrudes outside the edge of the base plate. As a result, there is a problem that the insulating grease between the base plate and the cooling fin is insufficient from the initial state, and the cooling performance is deteriorated.
  • the prior art described above prevents grease from entering the screw holes, and maintenance of the amount of grease has not been studied.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of obtaining a stable cooling performance while maintaining an appropriate amount of grease.
  • a semiconductor device includes a base plate having an upper surface and a lower surface, and a plurality of flat plate-like semiconductor elements provided side by side on the upper surface side, and the base plate is provided on the lower surface of the base plate.
  • grooves each individually surrounding the plurality of semiconductor elements on the upper surface side are provided.
  • a semiconductor device includes a base plate having an upper surface and a lower surface, and a semiconductor element provided on the upper surface side, and the lower surface of the base plate is in the plan view of the base plate.
  • a groove surrounding the semiconductor element on the upper surface side is provided, and the cross-sectional shape of the groove is connected to the first portion and the first portion opening with a first width on the lower surface side, and the upper surface side from the first portion.
  • a first cross-sectional shape including a second portion having a width larger than that of the first portion, or two sides that increase in width toward the lower surface side, and the two sides protrude toward the inside of the groove. It is the 2nd section shape which is a curve.
  • a semiconductor device includes a base plate having an upper surface and a lower surface, and a plurality of flat plate-like semiconductor elements provided side by side on the upper surface side, and a plurality of semiconductor devices on the lower surface of the base plate.
  • a groove region that extends so as to overlap with the plurality of semiconductor elements is provided, and the groove depth of the groove region at the center of the base plate is such that the groove depth of the groove region on the end side of the base plate is Greater than depth.
  • a semiconductor device comprising: a base plate having an upper surface and a lower surface; a flat plate-like semiconductor element provided side by side on the upper surface side; and a cooling surface having the flat surface superimposed on the lower surface. And an annular groove having a smaller outer shape than the base plate in plan view.
  • the groove is provided on the lower surface of the base plate so that the amount of grease can be maintained below each of the plurality of semiconductor elements, stable cooling performance can be obtained.
  • the groove having a special shape is provided on the lower surface of the base plate so as to reliably maintain the amount of grease, stable cooling performance can be obtained.
  • the groove region having the spread on the lower surface of the base plate is provided so that the amount of grease can be sufficiently maintained at the center portion of the base plate where heat is easily accumulated, stable cooling performance can be obtained.
  • the grooves are provided on the cooling fin side so that the amount of grease can be maintained, stable cooling performance can be obtained.
  • 1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention.
  • 1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention.
  • 1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention.
  • 1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention.
  • 1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention. It is a figure which shows the semiconductor device concerning Embodiment 2 of this invention. It is a figure which shows the semiconductor device concerning Embodiment 2 of this invention. It is a figure which shows the semiconductor device concerning Embodiment 2 of this invention. It is a figure which shows the semiconductor device concerning Embodiment 2 of this invention. It is a figure which shows the semiconductor device concerning Embodiment 2 of this invention.
  • FIG. 7 is a diagram illustrating a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 7 is a diagram illustrating a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 7 is a diagram illustrating a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 7 is a diagram illustrating a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 7 is a diagram illustrating a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 7 is a diagram illustrating a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 7 is a diagram illustrating a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 1 to 5 are diagrams showing a semiconductor device according to a first embodiment of the present invention.
  • FIG. 1 is a cross-sectional view taken along the line AA of FIG. 2, and
  • FIG. 2 is a chip layout view of the inside of the semiconductor device 10 as viewed from the upper surface side.
  • the semiconductor device 10 according to the first embodiment includes a metal base plate 22 having an upper surface 22a and a lower surface 22b, a plurality of insulating substrates 24 provided on the upper surface 22a, and is mounted side by side on the respective insulating substrates 24.
  • a plurality of semiconductor elements 26 and 28 that sometimes generate heat are provided.
  • the semiconductor element 26 is an IGBT and the semiconductor element 28 is a free wheel diode.
  • the housing 34 covers the upper surface 22 a side of the base plate 22, and the electrodes 30 and 32 are exposed outside the housing 34.
  • annular grooves 50 and 52 for storing insulating grease are provided on the lower surface 22b of the base plate 22 .
  • the surface 40 a of the metal cooling fin 40 is overlapped with the thermally conductive insulating grease 42 interposed therebetween, and the annular grooves 50 and 52 are filled with the insulating grease 42.
  • the base plate 22 includes a plurality of fixing holes 23 on the outer peripheral side of the annular grooves 50 and 52. Although not shown, the base plate 22 and the cooling fin 40 are connected through screws through the fixing holes 23.
  • FIG. 3A is a top view of the periphery of one insulating substrate 24 in FIG. 2 as viewed from the upper surface 22a side of the base plate 22.
  • FIG. 3B is a bottom view of FIG. 3A viewed from the bottom surface 22 b side of the base plate 22.
  • a plurality of annular grooves 50 and 52 are provided that respectively surround the plurality of semiconductor elements 26 and 28 on the upper surface 22a side in plan view of the base plate 22.
  • FIG. 3C is an enlarged cross-sectional view taken along the line BB in FIG.
  • the annular groove 50 has a rectangular cross-sectional shape including a bottom portion 50a and a side surface portion 50b.
  • the metal base plate 22 When the temperature of the base plate 22 rises while the semiconductor elements 26 and 28 are energized, the metal base plate 22 is thermally expanded. In this case, the insulating grease 42 protrudes from the annular grooves 50 and 52, and the amount of the insulating grease 42 between the base plate 22 and the cooling fin 40 is kept constant. On the other hand, when the temperature of the base plate 22 decreases when the energization is stopped, the insulating grease 42 returns to the annular grooves 50 and 52 as the base plate 22 contracts. By repeating heat generation and cooling alternately, such discharge and storage of the insulating grease 42 are repeated. Thereby, the amount of the insulating grease 42 between the base plate 22 and the cooling fin 40 can be kept constant under each of the semiconductor elements 26 and 28.
  • the annular grooves 50 and 52 are provided separately for each of the semiconductor elements 26 and 28, the insulating grease 42 can be reliably maintained at an appropriate amount below each of the semiconductor elements 26 and 28.
  • the cross-sectional shape of the annular grooves 50 and 52 is not limited to FIG. As shown in FIG. 4, it is good also as the annular groove 74 which has an elliptical cross section. Moreover, as shown in FIG. 5, it is good also as the annular groove 84 which has a cross section of an isosceles triangle.
  • a lattice-like groove continuously extending so as to separate the plurality of semiconductor elements 26 and 28 one by one in plan view of the base plate 22 may be provided on the lower surface 22b. Good.
  • FIG. 6 to 11 are diagrams showing a semiconductor device 110 according to the second embodiment of the present invention.
  • 6 is a cross-sectional view taken along the line CC of FIG.
  • the semiconductor device 110 is the same as the semiconductor device 10 except that the base plate 122 is provided instead of the base plate 22.
  • FIG. 7 is a chip layout diagram viewed from the upper surface 122 a side of the base plate 122.
  • a wavy line in FIG. 7 shows an annular groove 150 provided on the lower surface 122b.
  • the annular groove 150 is a continuous annular groove surrounding the semiconductor elements 26 and 28 on the upper surface side and the insulating substrate 24 in plan view of the base plate 122.
  • the inside of the annular groove 150 is filled with insulating grease 42.
  • FIG. 8 shows a cross-sectional shape of the annular groove 150.
  • the annular groove 150 has two sides that increase in distance toward the lower surface 122 b, and these two sides are curves that are convex toward the inside of the annular groove 150.
  • the width of the annular groove 150 increases as the base plate 122 expands, the vicinity of the tip on the upper surface 122a side of the annular groove 150 is abruptly narrowed, so that the gap is small near the tip. For this reason, the effect which pushes out the insulation grease 42 at the time of the thermal expansion of the base board 122 is still higher.
  • annular groove 170 having a cross-sectional shape shown in FIG.
  • the annular groove 170 includes a first portion 172 and a second portion 174.
  • the first portion 172 opens to the lower surface 122b side with a width W1.
  • the second portion 174 is connected to the first portion 172, is located closer to the upper surface 122a than the first portion 172, and has a width W2 larger than the width W1.
  • the outline of the second portion 174 is an arc.
  • the second portion 174 secures a large space so that a large amount of insulating grease 42 can be stored.
  • the pattern of the annular groove 150 in plan view of the base plate 122 may be modified as shown in FIG.
  • annular grooves 180 separately surrounding the plurality of semiconductor elements 26 and 28 may be provided.
  • channel 190 extended continuously so that the several semiconductor elements 26 and 28 may be divided separately one by one.
  • the annular groove 190 may have a large partition, and may be a lattice-like groove extending so as to partition the six insulating substrates 24, thereby stabilizing the amount of insulating grease 42 for each of the insulating substrates 24. Can be secured.
  • Embodiment 3. 12 to 14 are diagrams showing a semiconductor device 210 according to the third embodiment of the present invention. 12 is a cross-sectional view taken along the line DD of FIG.
  • the semiconductor device 210 is the same as the semiconductor device 10 except that a base plate 222 is provided instead of the base plate 22.
  • FIG. 14 is an enlarged cross-sectional view of the groove region 250. On the lower surface 222b of the base plate 222, a groove region 250 in which a plurality of grooves are continuous in the planar direction is provided.
  • the groove region 250 is divided into a groove region 250 a at the center of the base plate 222 and a groove region 250 b on the end side of the base plate 222.
  • the groove depth of the groove region 250a is larger than the groove depth of the groove region 250b.
  • the depth of the groove in the groove region 250a is increased toward the center of the base plate 222. Since the groove region 250 is filled with the insulating grease 42, the insulating grease 42 can be stored and discharged in the same manner as described in the first and second embodiments over the entire lower surface 222b of the base plate 222. The amount of insulating grease 42 between the plate 222 and the cooling fin 40 can be kept constant. Since the deep groove region 250a is provided in the central portion of the base plate 222 where heat is most easily trapped, a sufficient filling amount of the insulating grease 42 in the central portion can be secured.
  • the cross-sectional shape of each groove in the groove region 250 is the same as the cross-sectional shape of the annular groove 150 shown in FIG. 8, and the groove regions 250a and 250b have different depths.
  • the present invention is not limited to this, and the cross-sectional shape of each groove of the groove region 250 is rectangular as shown in FIG. 3, elliptical as shown in FIG. 4, or isosceles triangle as shown in FIG.
  • the depth of the groove may be large at the center of the base plate 222 and small at the outer end side of the base plate 222.
  • FIG. FIG. 15 is a diagram showing a semiconductor device 310 according to the fourth embodiment of the present invention.
  • the semiconductor device 310 is the same as the semiconductor device 10 except that the sealing material 312 is provided.
  • a sealing material 312 is provided so as to seal the insulating grease 42 along the edge of the base plate 22. Thereby, it can suppress that the insulation grease 42 protrudes in the plane direction of the base board 22, and the amount of insulation grease is insufficient.
  • the sealing material 312 may be combined with the semiconductor devices 110 and 210 according to the second and third embodiments.
  • FIG. 16 and 17 are diagrams showing semiconductor devices 410 and 460 according to the fifth embodiment of the present invention.
  • the cooling fin 440 provided in the semiconductor device 410 is provided with an annular groove 444 having an outer shape smaller than that of the base plate 422 in a plan view on a plane 440 a that overlaps the base plate 422 with the insulating grease 42 interposed therebetween.
  • the base plate 422 includes a convex portion 424 that fits into the annular groove 444 on the lower surface 422b. By fitting the convex portions 424 and the grooves 444 together, it is possible to suppress the insulating grease 42 from protruding in the planar direction of the base plate 422 and the amount of insulating grease being insufficient. As shown in FIG.
  • a semiconductor device 460 in which the sealing material 312 of Embodiment 4 is combined may be provided.
  • the cooling fin 40 may be provided with one or a plurality of convex portions that fit into the annular grooves 50 to 190 on the lower surfaces of the base plates 22 and 122 according to the first and second embodiments.
  • FIG. 18 to 19 are diagrams showing semiconductor devices 510 and 560 according to the sixth embodiment of the present invention.
  • the semiconductor device 510 is a combination of a base plate 322 having an upper surface 322a and a lower surface 322b and a cooling fin 540 having a groove 544 provided on the surface 540a.
  • the lower surface 322b is flat.
  • the shape of the groove 544 in plan view of the base plate 322 is the same as the annular groove 150 in FIG.
  • the outer shape of the annular groove 544 is smaller than the base plate 322 in plan view.
  • the groove 544 functions in the same manner as the annular grooves 50 and 52 of the first embodiment, it is possible to suppress the insulating grease 42 from protruding in the planar direction of the base plate 422 and the amount of insulating grease being insufficient.
  • a semiconductor device 560 in which a groove 546 is further provided inside the groove 544 may be provided.
  • the base plate 322 may be replaced with any one of the base plates 22 to 222 according to the first to third embodiments.
  • the semiconductor elements 26 and 28 may be semiconductor devices such as MOSFETs using silicon carbide (SiC) as a semiconductor material. Since the SiC semiconductor device is used at a higher temperature than the silicon device during energization during normal driving, the base plate 22 has a higher expansion / extension ratio. Therefore, the merit of applying each embodiment described above is high.
  • SiC silicon carbide

Abstract

　半導体装置１０は、上面２２ａと下面２２ｂを備えた金属製のベース板２２と、上面２２ａに設けられた複数の絶縁基板２４と、それぞれの絶縁基板２４に並べて実装された複数の半導体素子２６、２８とを備えている。ベース板２２の下面２２ｂには絶縁グリス貯蓄用の環状溝５０、５２が設けられている。下面２２ｂには絶縁グリス４２を挟んで冷却フィン４０の表面４０ａが重ねられており、環状溝５０、５２内部は絶縁グリス４２で充填されている。

Description

半導体装置
　本発明は、半導体装置に関する。
　従来、例えば、日本特開２００３－１６８７７２号公報に開示されているように、ベース板と冷却フィンとの間におけるグリスの広がりを抑制する溝部などを有する半導体装置が知られている。一般に、パワーモジュールのベース板下面に熱伝導性グリスが塗布され、このグリスを介してベース板と冷却フィンがネジで固定される。ネジ固定の際には、冷却フィンとグリスとのなじみをよくするために加圧され、さらにネジで締め付け固定されるために、固定時にグリスがベース板平面方向に広がる。上記従来の技術によれば、グリスがネジ穴に浸入するのを避けるために、ベース板と冷却フィンの少なくとも一方の対向面にグリス拡散防止部が設けられ、このグリス拡散防止部は溝部あるいは突起部とすることができる。
日本特開２００３－１６８７７２号公報 日本特開２００６－１９６５７６号公報 日本特開２０１０－９２９９９号公報 日本特開２０１０－２８３２２２号公報 日本特開２００８－４７４５号公報
　パワーモジュールに金属製のベース板が設けられる仕様の半導体装置では、通電時にパワーモジュール内の半導体素子が発熱してベース板が伸張し、非通電時には温度が低下するのでベース板が収縮する。半導体素子への通電の有無により、発熱と冷却が交互に繰り返されることにより、ベース板と冷却フィンの間に塗布されたグリスが徐々にベース板の縁の外側にはみ出してしまう。その結果、ベース板と冷却フィンの間の絶縁グリスが初期状態から不足し、冷却性能が低下する問題がある。上記従来の技術はネジ穴にグリスが侵入するのを防ぐものであり、グリス量の維持は検討されていなかった。
　本発明は、上述のような課題を解決するためになされたもので、グリス量を適正に保って安定な冷却性能を得ることができる半導体装置を提供することを目的とする。
　第１の発明にかかる半導体装置は、上面と下面を備えたベース板と、前記上面側に並べて設けられた平板状の複数の半導体素子と、を備え、前記ベース板の前記下面に、前記ベース板の平面視において、それぞれが前記上面側の前記複数の半導体素子を１つずつ別々に囲む溝が設けられている。
　第２の発明にかかる半導体装置は、上面と下面を備えたベース板と、前記上面側に設けられた半導体素子と、を備え、前記ベース板の前記下面に、前記ベース板の平面視において前記上面側の前記半導体素子を囲む溝が設けられ、前記溝の断面形状が、前記下面側に第１の幅で開口する第１部分と前記第１部分と接続し前記第１部分より前記上面側に位置し前記第１部分より大きな幅を有する第２部分とを含む第１断面形状、または前記下面側に行くほど幅が広がる２辺を有し前記２辺は前記溝の内側に凸となる曲線である第２断面形状である。
　第３の発明にかかる半導体装置は、上面と下面を備えたベース板と、前記上面側に並べて設けられた平板状の複数の半導体素子と、を備え、前記ベース板の前記下面に、複数の溝が連なって前記複数の半導体素子と重なるように広がる溝領域が設けられ、前記ベース板の中央における前記溝領域の溝の深さが、前記ベース板の端部側における前記溝領域の溝の深さよりも、大きい。
　第４の発明にかかる半導体装置は、上面と下面を備えたベース板と、前記上面側に並べて設けられた平板状の半導体素子と、平面を有し、前記下面に前記平面が重ねられた冷却フィンと、を備え、前記平面に、平面視で前記ベース板よりも外形が小さい環状の溝が設けられている。
　第１の発明によれば、複数の半導体素子の１つ１つの下方でグリス量を維持できるようにベース板下面に溝を設けたので、安定した冷却性能を得ることができる。
　第２の発明によれば、グリス量を確実に維持できるようにベース板下面に特別の形状の溝を設けたので、安定した冷却性能を得ることができる。
　第３の発明によれば、熱のこもりやすいベース板中央部でグリス量を十分に維持できるようにベース板下面に広がりを有する溝領域を設けたので、安定した冷却性能を得ることができる。
　第４の発明によれば、グリス量を維持できるように冷却フィン側に溝を設けたので、安定した冷却性能を得ることができる。
本発明の実施の形態１にかかる半導体装置を示す図である。 本発明の実施の形態１にかかる半導体装置を示す図である。 本発明の実施の形態１にかかる半導体装置を示す図である。 本発明の実施の形態１にかかる半導体装置を示す図である。 本発明の実施の形態１にかかる半導体装置を示す図である。 本発明の実施の形態２にかかる半導体装置を示す図である。 本発明の実施の形態２にかかる半導体装置を示す図である。 本発明の実施の形態２にかかる半導体装置を示す図である。 本発明の実施の形態２にかかる半導体装置を示す図である。 本発明の実施の形態２にかかる半導体装置を示す図である。 本発明の実施の形態２にかかる半導体装置を示す図である。 本発明の実施の形態３にかかる半導体装置を示す図である。 本発明の実施の形態３にかかる半導体装置を示す図である。 本発明の実施の形態３にかかる半導体装置を示す図である。 本発明の実施の形態４にかかる半導体装置を示す図である。 本発明の実施の形態５にかかる半導体装置を示す図である。 本発明の実施の形態５にかかる半導体装置を示す図である。 本発明の実施の形態６にかかる半導体装置を示す図である。 本発明の実施の形態６にかかる半導体装置を示す図である。
実施の形態１．
　図１～図５は、本発明の実施の形態１にかかる半導体装置を示す図である。図１は図２のＡ－Ａ線に沿う断面図であり、図２は、半導体装置１０の内部を上面側から見たチップ配置図である。実施の形態１にかかる半導体装置１０は、上面２２ａと下面２２ｂを備えた金属製のベース板２２と、上面２２ａに設けられた複数の絶縁基板２４と、それぞれの絶縁基板２４に並べて実装され通電時に発熱する複数の半導体素子２６、２８とを備えている。典型的には、半導体素子２６はＩＧＢＴであり、半導体素子２８はフリーホイールダイオードである。
　筐体３４がベース板２２の上面２２ａ側を覆っており、筐体３４の外部には電極３０、３２が露出している。ベース板２２の下面２２ｂには絶縁グリス貯蓄用の環状溝５０、５２が設けられている。下面２２ｂには、熱伝導性の絶縁グリス４２を挟んで金属製の冷却フィン４０の表面４０ａが重ねられており、環状溝５０、５２内部は絶縁グリス４２で充填されている。なお、ベース板２２は、環状溝５０、５２のさらに外周側に複数の固定穴２３を備えている。図示しないが固定穴２３にねじを通してベース板２２と冷却フィン４０の接続がなされる。
　図３（ａ）は図２における１枚の絶縁基板２４の周辺を、ベース板２２の上面２２ａ側から見下ろした上面図である。図３（ｂ）は図３（ａ）をベース板２２の下面２２ｂ側から見た下面図である。下面２２ｂに、ベース板２２の平面視において、それぞれが上面２２ａ側の複数の半導体素子２６、２８を別々に囲む複数の環状溝５０、５２が設けられている。図３（ｃ）は、図３（ａ）のＢ－Ｂ線に沿う拡大断面図である。環状溝５０は、底部５０ａおよび側面部５０ｂを備えた矩形の断面形状を有している。
　半導体素子２６、２８の通電中にベース板２２の温度が上昇すると、金属製のベース板２２が熱膨張する。この場合、環状溝５０、５２内から絶縁グリス４２がはみ出して、ベース板２２と冷却フィン４０の間の絶縁グリス４２の量が一定に保たれる。一方、通電停止時にベース板２２の温度が下降すると、ベース板２２の収縮に伴い絶縁グリス４２が環状溝５０、５２へと戻る。発熱と冷却が交互に繰り返されることで、このような絶縁グリス４２の排出と貯留が繰り返される。これにより、半導体素子２６、２８の１つ１つの下方において、ベース板２２と冷却フィン４０の間の絶縁グリス４２の量を一定に保つことができる。その結果、長時間の使用により熱伸縮が繰り返されても絶縁グリス４２のはみ出しによる冷却性能悪化を抑制できる。環状溝５０、５２を半導体素子２６、２８の１つ１つに別々に設けたので、絶縁グリス４２を半導体素子２６、２８それぞれの下方で確実に適正量に維持できる。なお、環状溝５０、５２の断面形状は、図３（ｃ）に限られない。図４に示すように、楕円形の断面を有する環状溝７４としてもよい。また、図５に示すように、二等辺三角形の断面を有する環状溝８４としてもよい。なお、複数の環状溝５０の代わりに、ベース板２２の平面視で複数の半導体素子２６、２８を１つずつ別々に仕切るように連続して伸びる格子状の溝が下面２２ｂに設けられてもよい。
実施の形態２．
　図６～図１１は、本発明の実施の形態２にかかる半導体装置１１０を示す図である。図６は図７のＣ－Ｃ線に沿う断面図である。半導体装置１１０は、ベース板２２の代わりにベース板１２２を備えた点以外は半導体装置１０と同じである。図７はベース板１２２の上面１２２ａ側からみたチップ配置図である。図７に波線で示したのは下面１２２ｂに設けられた環状溝１５０である。環状溝１５０は、ベース板１２２の平面視において上面側の半導体素子２６、２８および絶縁基板２４を囲む連続した１つの環状の溝である。環状溝１５０内部は絶縁グリス４２で充填されている。
　図８は、環状溝１５０の断面形状を示す。環状溝１５０は下面１２２ｂ側に行くほど間隔が広がる２辺を有し、この２辺は環状溝１５０の内側に凸となる曲線である。ベース板１２２が熱膨張に伴って環状溝１５０の幅も拡大するけれども、環状溝１５０のうち上面１２２ａの側の先端付近は急激に細くなっているのでこの先端付近は隙間の拡大が小さい。このためベース板１２２の熱膨張時に絶縁グリス４２を押し出す効果がより一層高い。
　環状溝１５０に代えて、図９に示す断面形状を有する環状溝１７０としてもよい。環状溝１７０は、第１部分１７２および第２部分１７４を備える。第１部分１７２は、下面１２２ｂ側に幅Ｗ１で開口する。第２部分１７４は、第１部分１７２と接続し、第１部分１７２より上面１２２ａ側に位置し、幅Ｗ１より大きな幅Ｗ２を有する。特に、本実施の形態では第２部分１７４は、その輪郭が円弧である。第２部分１７４で広いスペースを確保して大量の絶縁グリス４２を貯蓄できるようにしている。また、ベース板１２２の平面視における環状溝１５０のパターンは、図１０または図１１のように変形しても良い。例えば図１０に示すように、実施の形態１と同様に、複数の半導体素子２６、２８を別々に囲う複数の環状溝１８０を設けても良い。また、図１１に示すように、複数の半導体素子２６、２８を１つずつ別々に仕切るように連続して伸びる格子状の溝１９０としてもよい。また、環状溝１９０の仕切り目を大きく取って６つの絶縁基板２４の間を仕切るように伸びる格子状の溝としてもよく、これにより絶縁基板２４の１つずつについて絶縁グリス４２の量を安定して確保できる。
実施の形態３.
　図１２～図１４は、本発明の実施の形態３にかかる半導体装置２１０を示す図である。図１２は図１３のＤ－Ｄ線に沿う断面図である。半導体装置２１０は、ベース板２２の代わりにベース板２２２を備えた点以外は半導体装置１０と同じである。図１４は、溝領域２５０の拡大断面図である。ベース板２２２の下面２２２ｂに、その平面方向に複数の溝が連なった溝領域２５０が設けられている。
　溝領域２５０は、ベース板２２２の中央の溝領域２５０ａとベース板２２２の端部側における溝領域２５０ｂとに区分される。溝領域２５０ａの溝の深さが、溝領域２５０ｂの溝の深さよりも、大きい。特に、本実施の形態では、ベース板２２２の中央にいくほど溝領域２５０ａの溝の深さを大きくしている。溝領域２５０内部は絶縁グリス４２で充填されているので、ベース板２２２の下面２２２ｂの全体において実施の形態１、２で説明したのと同様に絶縁グリス４２の貯蓄排出を行うことができ、ベース板２２２と冷却フィン４０の間の絶縁グリス４２の量を一定に保つことができる。最も熱がこもりやすいベース板２２２の中央部に深い溝領域２５０ａを設けているので、中央部の絶縁グリス４２の充填量を十分に確保できる。
　なお、図１４に示すように溝領域２５０の１つ１つの溝の断面形状は、図８に示した環状溝１５０の断面形状と同じであり、溝領域２５０ａ、２５０ｂでは深さが互いに違う。しかしながら本発明はこれに限られず、溝領域２５０の１つ１つの溝の断面形状は、図３のごとく矩形にしたり、図４のごとく楕円形にしたり、図５のごとく二等辺三角形にしたりしてもよく、溝の深さをベース板２２２の中央で大きくベース板２２２の外端部側で小さくすればよい。
実施の形態４．
　図１５は、本発明の実施の形態４にかかる半導体装置３１０を示す図である。半導体装置３１０は、シール材３１２が設けられた点を除き、半導体装置１０と同じである。ベース板２２の縁に沿って絶縁グリス４２をシールするようにシール材３１２が設けられている。これにより、絶縁グリス４２がベース板２２の平面方向にはみ出して絶縁グリス量が不足することを抑制することができる。なお、シール材３１２は、実施の形態２、３にかかる半導体装置１１０、２１０に組み合わせてもよい。
実施の形態５．
　図１６および図１７は、本発明の実施の形態５にかかる半導体装置４１０、４６０を示す図である。半導体装置４１０が備える冷却フィン４４０は、絶縁グリス４２を挟んでベース板４２２と重なる平面４４０ａに、平面視でベース板４２２よりも外形が小さい環状の溝４４４が設けられている。さらに、ベース板４２２は、その下面４２２ｂに、環状の溝４４４と嵌合する凸部４２４を備えている。凸部４２４と溝４４４とが嵌めあわさることで、絶縁グリス４２がベース板４２２の平面方向にはみ出して絶縁グリス量が不足することを抑制することができる。図１７に示すように、実施の形態４のシール材３１２を組み合わせた半導体装置４６０を提供しても良い。なお、図示しないが、実施の形態１、２にかかるベース板２２、１２２の下面の環状溝５０～１９０と嵌まりあう１つまたは複数の凸部を冷却フィン４０に設けてもよい。
実施の形態６．
　図１８～１９は、本発明の実施の形態６にかかる半導体装置５１０、５６０を示す図である。半導体装置５１０は、上面３２２ａおよび下面３２２ｂを備えたベース板３２２と、表面５４０ａに溝５４４を設けた冷却フィン５４０とを組み合わせたものである。下面３２２ｂは平坦である。ベース板３２２の平面視における溝５４４の形は、図７の環状溝１５０と同じである。環状の溝５４４の外形は、平面視でベース板３２２よりも小さい。溝５４４が実施の形態１の環状溝５０，５２と同じ働きをすることで、絶縁グリス４２がベース板４２２の平面方向にはみ出して絶縁グリス量が不足することを抑制することができる。図１９に示すように、溝５４４の内側にさらに溝５４６を設けた半導体装置５６０を提供してもよい。なお、ベース板３２２を、実施の形態１～３にかかるベース板２２～２２２のいずれか１つに置換してもよい。
　上述した各実施形態において、半導体素子２６、２８は、炭化ケイ素（ＳｉＣ）を半導体材料とするＭＯＳＦＥＴなどの半導体デバイスであってもよい。ＳｉＣ半導体デバイスは通常駆動時の通電中にシリコンデバイスよりも高温で使用されるので、ベース板２２の膨張伸縮の割合が高い。よって上述した各実施の形態を適用するメリットが高い。
１０　半導体装置、２２　ベース板、２２ａ　上面、２２ｂ　下面、２４　絶縁基板、２６、２８　半導体素子、３０、３２　電極、３４　筐体、４０　冷却フィン、４０ａ　表面、４２　絶縁グリス、５０，５２　環状溝

Claims (10)

  1. 　上面と下面を備えたベース板と、前記上面側に並べて設けられた平板状の複数の半導体素子と、を備え、
    　前記ベース板の前記下面に、前記ベース板の平面視において、それぞれが前記上面側の前記複数の半導体素子を１つずつ別々に囲む溝が設けられた半導体装置。
  2. 　平面を有し、前記下面に前記平面が重ねられた冷却フィンを備え、
    　前記平面には、前記溝にはまり込む凸部が設けられた請求項１に記載の半導体装置。
  3. 　上面と下面を備えたベース板と、前記上面側に設けられた半導体素子と、を備え、
    　前記ベース板の前記下面に、前記ベース板の平面視において前記上面側の前記半導体素子を囲む溝が設けられ、
    　前記溝の断面形状が、前記下面側に第１の幅で開口する第１部分と前記第１部分と接続し前記第１部分より前記上面側に位置し前記第１部分より大きな幅を有する第２部分とを含む第１断面形状、または前記下面側に行くほど幅が広がる２辺を有し前記２辺は前記溝の内側に凸となる曲線である第２断面形状である半導体装置。
  4. 　前記第２部分の輪郭は、円弧である請求項３に記載の半導体装置。
  5. 　平面を有し、前記下面に前記平面が重ねられた冷却フィンを備え、
    　前記平面には、前記溝にはまり込む凸部が設けられた請求項３または４に記載の半導体装置。
  6. 　上面と下面を備えたベース板と、前記上面側に並べて設けられた平板状の複数の半導体素子と、を備え、
    　前記ベース板の前記下面に、複数の溝が連なって前記複数の半導体素子と重なるように広がる溝領域が設けられ、前記ベース板の中央における前記溝領域の溝の深さが、前記ベース板の端部側における前記溝領域の溝の深さよりも、大きい半導体装置。
  7. 　上面と下面を備えたベース板と、前記上面側に並べて設けられた平板状の半導体素子と、平面を有し前記下面に前記平面が重ねられた冷却フィンと、を備え、
    　前記平面に、平面視で前記ベース板よりも外形が小さい環状の溝が設けられた半導体装置。
  8. 　前記下面に、前記環状の溝と勘合する凸部が設けられた請求項７に記載の半導体装置。
  9. 　平面を有し、前記下面に前記平面が重ねられた冷却フィンを備え、
    　前記下面と前記平面の間に絶縁グリスが設けられ、
    　前記ベース板の縁に沿って前記絶縁グリスをシールするようにシール材が設けられた請求項１～８のいずれか１項に記載の半導体装置。
  10. 　前記半導体素子が、炭化ケイ素を半導体材料とする請求項１～９のいずれか１項に記載の半導体装置。
PCT/JP2013/085148 2013-12-27 2013-12-27 半導体装置 WO2015097874A1 (ja)

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