WO2015096441A1 - 互补型薄膜晶体管驱动背板及其制作方法、显示面板 - Google Patents

互补型薄膜晶体管驱动背板及其制作方法、显示面板 Download PDF

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WO2015096441A1
WO2015096441A1 PCT/CN2014/081190 CN2014081190W WO2015096441A1 WO 2015096441 A1 WO2015096441 A1 WO 2015096441A1 CN 2014081190 W CN2014081190 W CN 2014081190W WO 2015096441 A1 WO2015096441 A1 WO 2015096441A1
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Prior art keywords
layer
type transistor
type
drain
thin film
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French (fr)
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任章淳
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general

Definitions

  • Embodiments of the present invention relate to a complementary thin film transistor driving backplane, a method of fabricating the same, and a display panel. Background technique
  • LCDs liquid crystal displays
  • LCDs liquid crystal displays
  • AMOLEDs Active matrix organic light-emitting diode panels
  • Samsung Electronics, LG, and Philips are paying attention to this new display technology.
  • Philips to develop large-size active matrix organic light-emitting diode panel products as the main direction, Samsung SDI, AUO, etc. are small and medium-sized development direction. Because the active matrix organic light-emitting diode panel is theoretically superior to TFT LCD in terms of image quality, performance and cost.
  • An active matrix organic light emitting diode panel such as a complementary thin film transistor driving backplane for driving panel development, is mainly fabricated by multiple patterning processes, for example, by eleven mask lithography processes and The three-doping process forms a pattern required for a device such as a thin film transistor on each of the thin film layers therein.
  • One embodiment of the present invention provides a complementary thin film transistor driving backplane and a manufacturing method thereof, and a display panel; to simplify the manufacturing steps and save manufacturing costs.
  • An embodiment of the present invention provides a method for fabricating a complementary thin film transistor driving backplane, comprising the steps of: providing a lower semiconductor layer on a substrate, the substrate comprising a P-type semiconductor active layer; a gate insulating layer is disposed on the semiconductor layer; a lower electrode layer is disposed on the gate insulating layer, the lower electrode layer includes a P-type transistor gate, an N-type transistor source, and an N-type transistor drain, and the P-type a transistor gate is located above the P-type semiconductor active layer; utilizing oxidation
  • the semiconductor material is provided with an upper semiconductor layer on the lower electrode layer, the upper semiconductor layer includes a pixel transistor source and the N-type transistor drain overlap; and plasma is applied to the oxide semiconductor material corresponding to the pixel electrode region
  • An isolation insulating protective layer is disposed on the upper semiconductor layer, the isolation insulating protective layer includes a contact hole and a protection unit, and the contact hole is located at both ends of the P-type semiconductor active layer and corresponding to the pixel electrode
  • Another embodiment of the present invention provides a complementary thin film transistor driving backplane including a substrate and sequentially disposed on the substrate: a lower semiconductor layer including a P-type semiconductor active layer; a gate insulating layer; a lower electrode layer including a P-type transistor gate, an N-type transistor source, and an N-type transistor drain; an upper semiconductor layer including a pixel electrode and an N-type semiconductor active layer; an isolation insulating protective layer including a contact hole and a protection unit; An upper electrode layer including a P-type transistor source, a P-type transistor drain, and a plurality of N-type transistor gates; and a pixel defining layer including a pixel connection port.
  • Still another embodiment of the present invention provides a display panel including the above-described complementary thin film transistor driving back plate.
  • 1 to 8 are schematic views showing the steps of a manufacturing method according to an embodiment of the present invention (main sectional view). detailed description
  • the inventors have noted that for the fabrication of a complementary thin film transistor-driven backplane, the number of patterning processes is reduced, the fabrication steps are simplified, and the development requirements of the lighter and thinner layers of the active matrix organic light emitting diode panel are reasonably It is desirable to reduce the thickness.
  • One embodiment of the present invention provides a method of fabricating a complementary thin film transistor driving backplane, including the following steps:
  • a lower semiconductor layer is provided on the base substrate 101.
  • the buffer layer 102 is disposed on the substrate 101 by, for example, plasma enhanced chemical vapor deposition (PECVD).
  • the base substrate 101 may be a transparent material having good light transmittance such as glass or hard transparent plastic;
  • the buffer layer 102 includes a silicon oxide structural layer and a silicon nitride structural layer which are sequentially disposed, or include a silicon oxide structural layer and silicon nitride.
  • the composite layer of the structural layer in one example, the silicon oxide structural layer has a thickness of 50-100 nm, and the silicon nitride structural layer has a thickness of 100-300 nm.
  • a lower semiconductor layer is disposed on the buffer layer 102.
  • an amorphous silicon film is disposed on the buffer layer 102 by, for example, plasma enhanced chemical vapor deposition, for example, an amorphous silicon film having a thickness of 40 to 50 nm; and the substrate 101 is fed into a high temperature reactor. Dehydrogenating the amorphous silicon film to reduce the hydrogen content in the amorphous silicon film, generally controlling the hydrogen content to not more than 2%; performing an amorphous silicon film such as excimer laser annealing to make the amorphous silicon film The polysilicon film is transformed, and the polysilicon film is a lower semiconductor layer.
  • a plurality of P-type semiconductor active layers 103 are formed on the lower semiconductor layer by a mask lithography process; the P-type semiconductor active layer 103 includes a source contact region 104, a drain contact region 105, and a source contact region 104 and a drain.
  • the mask lithography process in the embodiment of the present invention may include processes such as photoresist coating, mask plate setting, exposure, development, etching, and photoresist stripping.
  • a gate insulating layer 107 is provided on the lower semiconductor layer.
  • the gate insulating layer 107 is disposed on the lower semiconductor layer by plasma enhanced chemical vapor deposition; in one example, the gate insulating layer 107 includes a composite layer of a silicon oxide structural layer and a silicon nitride structural layer, in another example The thickness of the silicon oxide structural layer is 50-100 nm, and the silicon nitride structural layer The thickness is 40-80 nm.
  • the gate insulating layer 107 serves to block the P-type semiconductor active layer 103 and the P-type transistor gate so that electrical crosstalk does not occur during operation.
  • a lower electrode layer is provided on the gate insulating layer 107 by, for example, a magnetron sputtering process.
  • a plurality of P-type transistor gates 108, a plurality of N-type transistor source electrodes 109 and a plurality of N-type transistor drains 110 are formed on the lower electrode layer by a mask lithography process; the P-type transistor gates 108 are located at the P-type semiconductor active Above layer 103.
  • the lower electrode layer is made of any one of molybdenum, tungsten, titanium or chromium.
  • the P-type semiconductor active layer 103 is doped by, for example, an ion implantation process. During the implantation process, self-alignment is achieved by using the P-type transistor gate 108 over the active layer connection region 106 as a mask; dopants are implanted into the source contact region 104 and the drain contact region 105, respectively, to form A source contact region 104 and a drain contact 105 region have dopants.
  • the dopants in the source contact region 104 and the drain contact region 105 are highly activated by an activation process; so that the activated ion species dopant has a higher mobility, making it in the source contact region 104 and
  • the drain contact region 105 is automatically filled to a suitable location to repair the lattice defects therein.
  • an upper semiconductor layer is provided on the lower electrode layer by, for example, an oxide semiconductor material and by, for example, a magnetron sputtering process.
  • the pixel electrode 111 and the N-type semiconductor active layer 112 are formed on the upper semiconductor layer by, for example, a patterning process. In one example, both ends of the N-type semiconductor active layer 112 overlap the N-type transistor source 109 and the N-type transistor drain 110, respectively.
  • the oxide semiconductor material corresponding to the region of the pixel electrode 111 is subjected to, for example, plasma treatment.
  • the plasma processing process includes: treating, in a vacuum chamber, an oxide semiconductor material corresponding to the pixel electrode 111 region with a 0 2 plasma, a N 2 O plasma, or an N 2 plasma,
  • the power is 1500-2500W
  • the pressure is 1000-2000mtorr
  • the gas flow rate is 5000-15000sccm; this operation can increase the density of carriers in the oxide semiconductor material to increase its conductivity.
  • the upper semiconductor layer is one or more of transparent metal oxide semiconductor materials such as indium gallium oxide, germanium oxide, indium oxide, and indium tin oxide.
  • an isolation insulating protective layer 113 is provided on the upper semiconductor layer by, for example, a plasma enhanced chemical vapor deposition process.
  • the isolation insulating protective layer 113 includes a composite layer of a silicon oxide structural layer and a silicon nitride structural layer. 6. As shown in FIG. 6, the contact hole 114 at both ends of the N-type active layer 103 and the corresponding region of the pixel electrode 111 is formed on the isolation insulating protective layer 113 by a mask lithography process; the contact hole 114 penetrates the isolation insulating protective layer 113. Up to the source contact region 104 and the drain contact region 105 of the P-type semiconductor active layer 103.
  • an upper electrode layer is provided on the isolation insulating protective layer 113 by, for example, a magnetron sputtering process.
  • the upper electrode layer is made of an alloy of any one of aluminum, titanium or silver or an alloy of any of several metals.
  • a P-type transistor source 116, a P-type transistor drain 117 and an N-type transistor gate 118 are formed on the upper electrode layer by a mask lithography process; the P-type transistor source 116 and the P-type transistor drain 117 pass through the contact hole.
  • 114 is connected to both ends of the P-type semiconductor active layer 103, and the P-type transistor drain 117 is also connected to the pixel electrode 111; the N-type transistor gate 118 is located above the N-type semiconductor active layer 112.
  • the P-type transistor includes a P-type semiconductor active layer 103, a P-type transistor gate 108, a P-type transistor source 116, and a P-type transistor drain 117;
  • the N-type transistor includes an N-type semiconductor active layer 112, an N-type transistor gate 118.
  • a pixel defining layer 119 is disposed on the upper electrode layer by, for example, a spin coating process, and a pixel connection port 120 is formed on the pixel defining layer by, for example, a mask lithography process.
  • the pixel connection port 120 is disposed on the pixel electrode 111 between the adjacent two protection units 115. At this point, the complementary thin film transistor drive backplane is completed.
  • the pixel connection port 120 is used for the corresponding connection of the organic light-emitting layer and the pixel electrode in the organic electroluminescent substrate to realize the light-emission driving of the complementary thin film transistor driving back plate to the organic electroluminescent substrate.
  • the pixel electrode in this embodiment is a part of the anode layer in the electroluminescent substrate.
  • the steps of forming the P-type transistor gate 108, the N-type transistor source 109, and the N-type transistor drain 110 of the same metal material on the same lower electrode layer and once on the same upper semiconductor layer Forming the pixel electrode 111 and the N-type semiconductor active layer 112; this combines the N-type transistor source and the source contact region of the material into a metal material N-type transistor source, and correspondingly the N-type transistor
  • the drain and material are the drain contact regions of the semiconductor material combined into a metal N-type transistor drain.
  • the N-type semiconductor active layer 112 connects the N-type transistor source 109 and the N-type transistor drain 110 to replace the active layer connection region of the N-type transistor, thereby eliminating the source contact region for the N-type transistor, N-type.
  • a contact hole is formed in the same isolation insulating protective layer 113 at a time.
  • the protection unit 115 serves as an interlayer dielectric layer on the P-type transistor gate 108 and a gate insulating layer serving as the N-type transistor gate 118, respectively, which combines the interlayer dielectric layer and the gate insulating layer into A layer structure is formed by a mask lithography process, which reduces the thickness of the complementary thin film transistor driving backplane.
  • the embodiment of the present invention simplifies the process steps, saves manufacturing costs, and improves manufacturing efficiency.
  • the same upper electrode layer forms a P-type transistor source 116, a P-type transistor drain 117, and an N-type transistor gate 118, so that the three have the same metal material, and the N-type can be omitted.
  • the fabrication method of the embodiment can be completed into a complementary thin film transistor driving back plate by performing six mask lithography processes; the mask lithography process is reduced by at least five times compared with other fabrication methods, and the manufacturing cost is greatly saved. At the same time, the complementary thin film transistor driving backplane is made lighter and thinner.
  • P-type transistor sources and P-type transistor drains in the embodiments of the present invention are not distinguished, and the corresponding N-type transistor source and N-type transistor drain are not distinguished.
  • the source of the P-type transistor can also be called the drain of the P-type transistor.
  • the drain of the P-type transistor can also be called the source of the P-type transistor.
  • the complementary thin film transistor driving backplane in this embodiment is made by the manufacturing method in the first embodiment. Therefore, the technical content disclosed in the first embodiment is not repeatedly described, and the content disclosed in the first embodiment also belongs to the embodiment. Public content.
  • this embodiment provides a complementary thin film transistor driving backplane, which is fabricated by a method of fabricating a complementary thin film transistor driving backplane as described in the first embodiment.
  • the complementary thin film transistor driving backplane in this embodiment includes a base substrate 101 on which a buffer layer 102 is disposed in order from bottom to top; a lower semiconductor including a plurality of P-type semiconductor active layers 103 a gate insulating layer 107; including a plurality of P-type transistor gates 108, a plurality of N a transistor source 109 and a lower electrode layer of the plurality of N-type transistor drains 110; an upper semiconductor layer including a plurality of pixel electrodes 111 and a plurality of N-type semiconductor active layers 112; a plurality of contact holes 114 and a plurality of protections An isolation insulating protective layer 113 of the cell 115; an upper electrode layer including a plurality of P-type transistor source 116, a plurality of P-type transistor drains 117 and a plurality of N-type transistor gates 118; and including on the upper electrode layer
  • the pixel connection port 120 is
  • the P-type semiconductor active layer 103 described in this embodiment includes a source contact region 104, a drain contact region 105, and an active layer connection region 106 disposed between the source contact region 104 and the drain contact region 105;
  • the P-type transistor gate 108 is disposed above the P-type semiconductor active layer 103 and corresponds to the position of the active layer connection region 106; the gate insulating layer 107 is disposed on the P-type transistor gate 108 and the P-type semiconductor active layer
  • a P-type transistor gate 108 is provided with a protection unit 115.
  • the protection unit 115 completely encapsulates the P-type transistor gate 108.
  • the P-type transistor source upper portion is disposed on the protection unit 115, and the lower portion penetrates the contact hole 114.
  • the protection unit 115 on the gate 108 of the P-type transistor is completely covered.
  • the pixel electrode 111 described in this embodiment is disposed on the gate insulating layer 107 between the P-type semiconductor active layer 103 and the N-type semiconductor active layer 112; the N-type transistor source 109 and the N-type transistor drain 110 pass The N-type semiconductor active layer 112 is connected; the N-type transistor gate 118 is disposed above the N-type semiconductor active layer 112 and corresponds to the position of the N-type semiconductor active layer 112; at the N-type transistor gate 118 and A protection unit 115 is disposed between the N-type semiconductor active layers 112, and the protection unit 115 completely covers the N-type semiconductor active layer 112 together with the N-type transistor source 116 and the N-type transistor drain 117; the pixel defining layer 119 as a whole Overlying the N-type transistor gate 118, the protection unit 115 between the N-type transistor gate 118 and the N-type semiconductor active layer 112 is completely covered.
  • the upper portion of the P-type transistor drain 117 described in this embodiment is connected to the pixel electrode 111.
  • the right end of the protection unit 115 on the P-type transistor gate 108 is placed on the left end of the pixel electrode; the protection unit 115 is located between the N-type transistor gate 118 and the N-type semiconductor active layer 112, and the left end is disposed.
  • the pixel connection port 120 extends through the pixel defining layer 119, and the pixel connection port 120 is correspondingly disposed on the pixel electrode 111.
  • the driving backplane of the embodiment uses a design in which the pixel electrode 111 is disposed between the adjacent two protection units 115; this can reasonablyly replace the pixel electrode without changing the structural characteristics of the complementary thin film transistor driving backplane itself.
  • 111 is placed in the space between the P-type transistor and the N-type transistor.
  • the pixel electrode 111 and the P-type semiconductor active layer 103 can be simultaneously formed by one mask lithography process, which eliminates the step of separately forming the pixel electrode 111 through the mask lithography process, and can effectively reduce the complementary film.
  • the transistor drives the overall thickness of the backplate.
  • the embodiment effectively simplifies the process steps, saves manufacturing costs, and improves production efficiency.
  • the P-type transistor gate 108, the N-type transistor source 109 and the N-type transistor drain 110 described in this embodiment are each made of any one of molybdenum, tungsten, titanium or chromium or an alloy of any of several metals. production.
  • the pixel electrode 111, the N-type transistor source 109, and the N-type transistor drain 110 are each made of a transparent metal oxide such as indium gallium oxide, oxon oxide, indium oxide, and indium tin oxide. Any one or any combination of the semiconductor materials is made.
  • the P-type transistor source 116, the P-type transistor drain 117 and the N-type transistor gate 118 are both made of any one of aluminum, titanium or silver or an alloy of any metal. .
  • the display panel in this embodiment includes the complementary thin film transistor driving backplane described in the second embodiment. Therefore, the technical content disclosed in the second embodiment is not repeatedly described. The content disclosed in the second embodiment is also disclosed in the embodiment. content.
  • the embodiment provides a display panel.
  • the display panel is an active matrix organic light emitting diode panel
  • the display panel includes a complementary thin film transistor driving backplane as described in the second embodiment, and An organic electroluminescent substrate disposed on the complementary thin film transistor driving backplane.
  • the organic electroluminescent substrate is provided with an anode layer, an organic light-emitting layer, and a cathode layer, for example, from bottom to top.
  • the organic light emitting layer is mounted corresponding to the pixel electrode to realize the light emitting driving of the complementary thin film transistor driving the back plate to the organic electroluminescent substrate; the pixel electrode described in this embodiment is the organic electroluminescent substrate. Part of the anode layer.
  • a P-type transistor gate of the same metal material is formed by the same lower electrode layer a pole, an N-type transistor source and an N-type transistor drain and a pixel electrode and an N-type semiconductor active layer formed by the same upper semiconductor layer; this combines the N-type transistor source and the source contact region of the semiconductor material into one
  • the N-type transistor source of metal material correspondingly combines the drain of the N-type transistor and the drain contact region of the material into a metal material N-type transistor drain.
  • Embodiments of the present invention use an N-type semiconductor active layer to connect the N-type transistor source and the N-type transistor drain to replace the active layer connection region of the N-type transistor, which eliminates the source contact region of the N-type transistor. a step of doping the drain contact region of the N-type transistor and the N-type semiconductor active layer.
  • a contact hole and a protection unit are formed in the same isolation insulating protective layer, and the protection unit is used as an interlayer dielectric layer on the gate of the P-type transistor and a gate insulating layer serving as a gate of the N-type transistor, respectively.
  • This combines the interlayer dielectric layer and the gate insulating layer into a single layer structure and is formed by a single mask lithography process.
  • the embodiment of the present invention reduces the thickness of the complementary thin film transistor driving backplane; and simplifies the process steps, saves manufacturing costs, and improves fabrication efficiency.
  • the P-type transistor source, the P-type transistor drain and the N-type transistor gate are formed by the same upper electrode layer, so that the three have the same metal material, and the N-type transistor gate can be omitted.
  • the embodiment of the present invention uses a design in which a pixel electrode is disposed between two adjacent protection units; this is to place the pixel electrode on the P-type transistor without changing the structural characteristics of the complementary thin film transistor driving back plate itself.
  • the embodiment of the present invention effectively simplifies the process steps, saves manufacturing costs, and improves production efficiency.

Landscapes

  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种互补型薄膜晶体管驱动背板及其制作方法、显示面板，该方法包括：在衬底基板(101)上设置下半导体层，并形成P型半导体有源层(103)；在下半导体层上设置栅绝缘层(107)；在栅绝缘层(107)上设置下电极层，并形成P型晶体管栅极(108)、N型晶体管源极(109)和N型晶体管漏极(110)；在下电极层上设置上半导体层，并形成像素电极(111)和N型半导体有源层(112)；在上半导体层上设置隔离绝缘保护层(113)，并形成接触孔(114)和保护单元(115)；在隔离绝缘保护层(113)上设置上电极层，并形成P型晶体管源极(116)、P型晶体管漏极(117)和N型晶体管栅极(118)；在上电极层上设置像素定义层(119)，并形成像素连接口(120)。

Description

互补型薄膜晶体管驱动背板及其制作方法、 显示面板 技术领域
本发明的实施例涉及一种互补型薄膜晶体管驱动背板及其制作方法、 显 示面板。 背景技术
随着人们生活水平的提高， 液晶显示器（LCD ) 已经非常常见， 手机、 相机、 电脑、 电视等都可见 LCD 的身影。 人们对显示产品的大量需求， 客 观上推动了显示技术的发展， 使新的显示技术不断出现， 如低温多晶硅、 有 机显示技术等。 有源矩阵有机发光二极体面板（AMOLED )被称为下一代显 示技术， 包括三星电子、 LG、 飞利浦在内的各公司都十分重视这项新的显示 技术。 目前除了三星电子与 LG、 飞利浦以发展大尺寸有源矩阵有机发光二 极体面板产品为主要方向外， 三星 SDI、友达等都是以中小尺寸为发展方向。 因为有源矩阵有机发光二极体面板不管在画质、 效能还是成本上， 理论上都 较 TFT LCD优势很多。
一种有源矩阵有机发光二极体面板， 例如用于驱动面板显像的互补型薄 膜晶体管驱动背板， 其制作工艺主要是通过多次构图工艺， 例如通过十一次 掩膜光刻工艺以及三次掺杂工艺， 在其内的各薄膜层上形成如薄膜晶体管等 器件所需的图形。 发明内容
本发明的一个实施例提供了一种互补型薄膜晶体管驱动背板及其制作方 法、 显示面板； 以简化制作步骤， 节约制作成本。
本发明的一个实施例提供了一种互补型薄膜晶体管驱动背板的制作方 法， 包括如下步骤： 在衬底基板上设置下半导体层， 所述衬底基板包括 P型 半导体有源层； 在所述下半导体层上设置栅绝缘层； 在所述栅绝缘层上设置 下电极层， 所述下电极层包括 P型晶体管栅极、 N型晶体管源极和 N型晶体 管漏极， 所述 P型晶体管栅极位于所述 P型半导体有源层的上方； 利用氧化 物半导体材料在所述下电极层上设置上半导体层， 所述上半导体层包括像素 晶体管源极和所述 N型晶体管漏极搭接；对所述像素电极区域对应的氧化物 半导体材料进行等离子体处理； 在所述上半导体层上设置隔离绝缘保护层， 所述隔离绝缘保护层包括接触孔和保护单元， 所述接触孔位于所述 P型半导 体有源层两端和所述像素电极对应区域； 在所述隔离绝缘保护层上设置上电 极层， 所述上电极层包括 P型晶体管源极、 P型晶体管漏极和 N型晶体管栅 极， 所述 P型晶体管源极、 所述 P型晶体管漏极分别通过所述接触孔与所述 P型半导体有源层的两端相连，所述 N型晶体管栅极位于所述 N型半导体有 源层的上方； 以及在所述上电极层上设置像素定义层， 所述像素定义层包括 像素连接口。
本发明的另一个实施例提供了一种互补型薄膜晶体管驱动背板， 包括衬 底基板以及在该衬底基板上依次设置的： 包括 P型半导体有源层的下半导体 层； 栅绝缘层； 包括 P型晶体管栅极、 N型晶体管源极和 N型晶体管漏极的 下电极层； 包括像素电极和 N型半导体有源层的上半导体层； 包括接触孔和 保护单元的隔离绝缘保护层； 包括 P型晶体管源极、 P型晶体管漏极和多个 N型晶体管栅极的上电极层； 以及包括像素连接口的像素定义层。
本发明的再一个实施例提供了一种显示面板， 包括上述互补型薄膜晶体 管驱动背板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1-图 8是本发明一个实施例的制作方法的步骤示意图 （主剖视图） 。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
发明人注意到， 对于互补型薄膜晶体管驱动背板的制作而言， 减少构图 工艺的次数、 简化制作步骤， 并且为适应有源矩阵有机发光二极体面板更轻 更薄的发展需求， 合理地减小其厚度是人们所希望的。
实施例一
本发明一个实施例提供一种互补型薄膜晶体管驱动背板的制作方法， 包 括如下步骤：
1、如图 1所示， 对衬底基板 101进行清洗处理后， 在衬底基板 101上设 置下半导体层。
在一个示例中， 通过例如等离子体增强化学气相沉积法（ PECVD )在衬 底基板 101上设置緩冲层 102。 衬底基板 101可以为玻璃、 硬质透明塑料等 透光率好的透明材料； 緩冲层 102包括依次设置的氧化硅结构层和氮化硅结 构层， 或包括氧化硅结构层和氮化硅结构层的复合层， 在一个示例中， 氧化 硅结构层的厚度为 50-100纳米， 氮化硅结构层的厚度为 100-300纳米。
在緩冲层 102上设置下半导体层。 在一个示例中， 通过例如等离子体增 强化学气相沉积法在緩冲层 102上设置非晶硅薄膜， 例如， 非晶硅薄膜厚度 为 40-50纳米； 将衬底基板 101送入高温反应炉中， 对非晶硅薄膜进行脱氢 处理以减少非晶硅薄膜中氢含量， 一般将氢的含量控制在不超过 2%; 对非 晶硅薄膜进行例如准分子激光退火处理， 使非晶硅薄膜转变多晶硅薄膜， 该 多晶硅薄膜即为下半导体层。
通过掩膜光刻工艺在下半导体层上形成多个 P型半导体有源层 103; P 型半导体有源层 103包括源极接触区 104、 漏极接触区 105以及设置在源极 接触区 104与漏极接触区 105之间的有源层连接区 106。 本发明实施例中的 掩膜光刻工艺可以包括光刻胶涂布、 掩膜板设置、 曝光、 显影、 刻蚀、 光刻 胶剥离等工序。
2、 如图 2所示， 在下半导体层上设置栅绝缘层 107。
例如， 通过等离子体增强化学气相沉积法在下半导体层上设置栅绝缘层 107;在一个示例中，该栅绝缘层 107包括氧化硅结构层和氮化硅结构层的复 合层， 在另一个示例中， 氧化硅结构层的厚度为 50-100纳米， 氮化硅结构层 的厚度为 40-80纳米。 该栅绝缘层 107用于阻隔 P型半导体有源层 103与 P 型晶体管栅极， 使两者在工作时不会发生电信号串扰。
3、如图 3所示，通过例如磁控溅射工艺在栅绝缘层 107上设置下电极层。 通过掩膜光刻工艺在下电极层上形成多个 P型晶体管栅极 108、 多个 N 型晶体管源极 109和多个 N型晶体管漏极 110; P型晶体管栅极 108位于 P 型半导体有源层 103的上方。 在一个示例中， 下电极层釆用钼、 钨、 钛或铬 中任意一种金属制成。
通过例如离子注入工艺对 P型半导体有源层 103进行掺杂。 在注入过程 中， 通过位于有源层连接区 106上方的 P型晶体管栅极 108作为掩模， 实现 自对准； 将掺杂剂分别注入源极接触区 104和漏极接触区 105中以形成具有 掺杂剂的源极接触区 104和漏极接触 105区。
通过活化工艺将源极接触区 104和漏极接触区 105中的掺杂剂高度活化； 以使活化后的离子形态的掺杂剂具有更高的移动能力， 使之在源极接触区 104和漏极接触区 105中自动填补到合适的位置，用以修复其内的晶格缺陷。
4、如图 4所示，利用例如氧化物半导体材料以及通过例如磁控溅射工艺 在下电极层上设置上半导体层。
通过例如构图工艺在上半导体层上形成像素电极 111和 N型半导体有源 层 112。 在一个示例中， N型半导体有源层 112的两端分别与 N型晶体管源 极 109和 N型晶体管漏极 110搭接。对像素电极 111区域对应的氧化物半导 体材料进行例如等离子体处理。 在一个示例中， 该等离子体处理过程包括： 在真空腔室中， 对所述像素电极 111 区域对应的氧化物半导体材料釆用 02 等离子体、 N20等离子体或 N2等离子体处理， 功率为 1500-2500W， 压力为 1000-2000mtorr, 气体流量为 5000-15000sccm; 该操作可以提高氧化物半导 体材料中载流子的密度， 以增加其导电性。
上半导体层釆用如铟镓辞氧化物、 辞氧化物、 铟辞氧化物和铟锡辞氧化 物等透明金属氧化物半导体材料中一种或多种。
5、如图 5所示，通过例如等离子体增强化学气相沉积工艺在上半导体层 上设置隔离绝缘保护层 113。
在一个示例中， 该隔离绝缘保护层 113包括氧化硅结构层和氮化硅结构 层的复合层。 6、 如图 6所示， 通过掩膜光刻工艺在隔离绝缘保护层 113上形成 N型 有源层 103两端和像素电极 111对应区域的接触孔 114; 接触孔 114贯穿隔 离绝缘保护层 113直至 P型半导体有源层 103的源极接触区 104和漏极接触 区 105。
7、如图 7所示，通过例如磁控溅射工艺在隔离绝缘保护层 113上设置上 电极层。
在一个示例中， 该上电极层釆用铝、 钛或银中任意一种金属制成或任意 几种金属组成的合金制成。 通过掩膜光刻工艺在上电极层上形成 P型晶体管 源极 116、 P型晶体管漏极 117和 N型晶体管栅极 118; P型晶体管源极 116、 P型晶体管漏极 117均通过接触孔 114与 P型半导体有源层 103的两端相连， P型晶体管漏极 117还与像素电极 111连接； N型晶体管栅极 118位于 N型 半导体有源层 112的上方。
至此， P型晶体管和 N型晶体管制作完毕。 P型晶体管包括 P型半导体 有源层 103、P型晶体管栅极 108、P型晶体管源极 116和 P型晶体管漏极 117; N型晶体管包括 N型半导体有源层 112、 N型晶体管栅极 118、 N型晶体管 源极 109和 N型晶体管漏极 110。
8、 如图 8所示， 通过例如旋涂工艺在上电极层上设置像素定义层 119， 并通过例如掩膜光刻工艺在像素定义层上形成像素连接口 120。
所述像素连接口 120设置在相邻两保护单元 115之间的像素电极 111上。 至此， 互补型薄膜晶体管驱动背板制作完毕。 像素连接口 120用于有机电致 发光基板中的有机发光层与像素电极的对应连接， 以实现互补性薄膜晶体管 驱动背板对于有机电致发光基板的发光驱动。 本实施例中的像素电极即为有 机电致发光基板中阳极层的一部分。
本实施例的制作方法中， 在同一下电极层上一次形成同金属材质的 P型 晶体管栅极 108、 N型晶体管源极 109和 N型晶体管漏极 110的步骤以及在 同一上半导体层上一次形成像素电极 111和 N型半导体有源层 112的步骤； 这将 N型晶体管源极和材料为半导体材料的源极接触区合并为一个金属材质 的 N型晶体管源极，相应地将 N型晶体管漏极和材料为半导体材料的漏极接 触区合并为一个金属材质的 N型晶体管漏极。 本实施例的制作方法中， 釆用 N型半导体有源层 112将 N型晶体管源极 109和 N型晶体管漏极 110连接， 以替代 N型晶体管的有源层连接区， 以此省去对于 N型晶体管源极接触区、 N型晶体管漏极接触区以及 N型半导体有源层进行掺杂的步骤。 由此， 本实 施例的制作方法有效简化了工艺步骤， 节约了制作成本， 提高了制作效率。
本实施例的制作方法中， 在同一隔离绝缘保护层 113中一次形成接触孔
114和保护单元 115， 保护单元 115分别用作 P型晶体管栅极 108上的层间 电介质层以及用作 N型晶体管栅极 118的栅绝缘层，这使层间电介质层和栅 绝缘层合并为一层结构并通过一次掩膜光刻工艺即可形成， 这减少了互补型 薄膜晶体管驱动背板的厚度。 由此， 本发明的实施例简化了工艺步骤， 节约 了制作成本， 提高了制作效率。
本实施例的制作方法中， 同一上电极层形成 P型晶体管源极 116、 P型 晶体管漏极 117和 N型晶体管栅极 118, 这使三者具有同样的金属材料， 可 省去对 N型晶体管栅极 118单独通过掩膜光刻工艺形成的步骤。 由此， 本发 明的实施例简化了工艺步骤， 节约了制作成本， 提高了制作效率。
本实施例的制作方法只需进行六次掩膜光刻工艺即可制成互补型薄膜晶 体管驱动背板； 与其他制作方法相比减少了至少五次掩膜光刻工艺， 大大节 省了制作成本； 同时制作出的互补型薄膜晶体管驱动背板更加轻薄。
需要说明的是， 本发明实施例中的所有 P型晶体管源极、 P型晶体管漏 极不做区分， 相应的 N型晶体管源极、 N型晶体管漏极也不做区分。 例如， P型晶体管源极也可以叫 P型晶体管漏极， 相应地， 此时 P型晶体管漏极也 可以叫 P型晶体管源极。
实施例二
本实施例中的互补型薄膜晶体管驱动背板是由实施例一中的制作方法制 成的， 因此， 实施例一中公开的技术内容不重复描述， 实施例一公开的内容 也属于本实施例公开的内容。
如图 8所示， 本实施例提供一种互补型薄膜晶体管驱动背板， 由如实施 例一中所述的互补型薄膜晶体管驱动背板的制作方法制成。
本实施例中的互补型薄膜晶体管驱动背板包括衬底基板 101， 在该衬底 基板 101上由下至上依次设置有： 緩冲层 102; 包括多个 P型半导体有源层 103的下半导体层； 栅绝缘层 107; 包括多个 P型晶体管栅极 108、 多个 N 型晶体管源极 109和多个 N型晶体管漏极 110的下电极层； 包括多个像素电 极 111和多个 N型半导体有源层 112的上半导体层； 包括多个接触孔 114和 多个保护单元 115的隔离绝缘保护层 113; 包括多个 P型晶体管源极 116、 多个 P型晶体管漏极 117和多个 N型晶体管栅极 118的上电极层； 以及设置 在上电极层上的包括多个像素连接口 120的像素定义层 119。像素连接口 120 设置在相邻两保护单元 115之间。
本实施例中所述的 P型半导体有源层 103包括源极接触区 104、 漏极接 触区 105以及设置在源极接触区 104与漏极接触区 105之间的有源层连接区 106; P型晶体管栅极 108设置在 P型半导体有源层 103的上方， 并与有源层 连接区 106的位置相对应； 栅绝缘层 107设置在 P型晶体管栅极 108与 P型 半导体有源层 103之间； P型晶体管栅极 108上设有保护单元 115， 该保护 单元 115将 P型晶体管栅极 108完全包覆； P型晶体管源极上部设置在保护 单元 115上， 下部深入接触孔 114与源极接触区 104连接； P型晶体管漏极 117上部设置在保护单元 115上， 下部深入接触孔 114与漏极接触区 105连 接； 像素定义层 119整体覆盖于 P型晶体管源极 116和 P型晶体管漏极 117 之上， 并将位于 P型晶体管栅极 108上的保护单元 115完全包覆。
本实施例中所述的像素电极 111设置在 P型半导体有源层 103与 N型半 导体有源层 112之间的栅绝缘层 107上； N型晶体管源极 109与 N型晶体管 漏极 110通过 N型半导体有源层 112连接； N型晶体管栅极 118设置在 N型 半导体有源层 112的上方， 并与该 N型半导体有源层 112的位置相对应； 在 N型晶体管栅极 118与 N型半导体有源层 112之间设置有保护单元 115， 该 保护单元 115将 N型半导体有源层 112连同 N型晶体管源极 116和 N型晶 体管漏极 117全部包覆；像素定义层 119整体覆盖于 N型晶体管栅极 118之 上，并将位于 N型晶体管栅极 118与 N型半导体有源层 112之间的保护单元 115完全包覆。
本实施例中所述的 P型晶体管漏极 117的上部与像素电极 111连接。 本 实施例中位于 P型晶体管栅极 108上的保护单元 115右端置于像素电极左端 之上； 位于 N型晶体管栅极 118与 N型半导体有源层 112之间的保护单元 115，其左端置于像素电极右端之上。本实施例中像素连接口 120贯穿像素定 义层 119， 像素连接口 120对应设置在像素电极 111上。 本实施例的驱动背板釆用将像素电极 111设置在相邻两保护单元 115之 间的设计； 这在不改变互补型薄膜晶体管驱动背板本身结构特性的前提下， 可以合理地将像素电极 111置于 P型晶体管与 N型晶体管之间的空间。并且， 像素电极 111与 P型半导体有源层 103可通过一次掩膜光刻工艺同时形成， 这省去了对像素电极 111单独通过掩膜光刻工艺形成的步骤， 可有效减小互 补型薄膜晶体管驱动背板的整体厚度。 由此，本实施例有效简化了工艺步骤， 节约了制作成本， 提高了制作效率。
本实施例中所述的 P型晶体管栅极 108、 N型晶体管源极 109和 N型晶 体管漏极 110均釆用钼、 钨、 钛或铬中的任意一种金属或任意几种金属的合 金制成。
本实施例中像素电极 111、 N型晶体管源极 109和 N型晶体管漏极 110 均釆用如铟镓辞氧化物、 辞氧化物、 铟辞氧化物和铟锡辞氧化物等透明金属 氧化物半导体材料中的任意一种或任意几种的组合物制成。
本实施例中 P型晶体管源极 116、 P型晶体管漏极 117和 N型晶体管栅 极 118均釆用铝、 钛或银中的任意一种金属制成或任意几种金属组成的合金 制成。
实施例三
本实施例中的显示面板包括实施例二中所述的互补型薄膜晶体管驱动背 板， 因此， 实施例二中公开的技术内容不重复描述， 实施例二公开的内容也 属于本实施例公开的内容。
本实施例提供了一种显示面板， 在一个示例中， 该显示面板是有源矩阵 有机发光二极体面板， 该显示面板包括如实施例二中所述的互补型薄膜晶体 管驱动背板， 以及设置在该互补型薄膜晶体管驱动背板上的有机电致发光基 板。 所述有机电致发光基板例如由下至上依次设有阳极层、 有机发光层和阴 极层。
在一个示例中， 有机发光层与像素电极对应安装， 以实现互补性薄膜晶 体管驱动背板对于有机电致发光基板的发光驱动； 本实施例中所述的像素电 极即为有机电致发光基板中阳极层的一部分。
本发明的上述实施例具有以下的优点：
1、 本发明实施例中， 由同一下电极层形成同金属材质的 P型晶体管栅 极、 N型晶体管源极和 N型晶体管漏极以及由同一上半导体层形成像素电极 和 N型半导体有源层；这将 N型晶体管源极和材料为半导体材料的源极接触 区合并为一个金属材质的 N型晶体管源极，相应地将 N型晶体管漏极和材料 为半导体材料的漏极接触区合并为一个金属材质的 N型晶体管漏极。本发明 的实施例釆用 N型半导体有源层将 N型晶体管源极和 N型晶体管漏极连接， 以替代 N型晶体管的有源层连接区，这省去对 N型晶体管源极接触区、 N型 晶体管漏极接触区以及 N型半导体有源层进行掺杂的步骤。 由此， 本发明的 实施例有效简化了工艺步骤， 节约了制作成本， 提高了制作效率。
2、本发明实施例中， 同一隔离绝缘保护层中形成接触孔和保护单元，保 护单元分别用作 P型晶体管栅极上的层间电介质层以及用作 N型晶体管栅极 的栅绝缘层， 这使层间电介质层和栅绝缘层合并为一层结构， 并通过一次掩 膜光刻工艺即可形成。 由此， 本发明的实施例减少了互补型薄膜晶体管驱动 背板的厚度； 且简化了工艺步骤， 节约了制作成本， 提高了制作效率。
3、 本发明实施例中， 由同一上电极层形成 P型晶体管源极、 P型晶体管 漏极和 N型晶体管栅极，这使三者具有同样的金属材料，可省去对 N型晶体 管栅极单独通过掩膜光刻工艺形成的步骤。 由此， 本发明的实施例简化了工 艺步骤， 节约了制作成本， 提高了制作效率。
4、本发明实施例釆用将像素电极设置在相邻两保护单元之间的设计；这 在不改变互补型薄膜晶体管驱动背板本身结构特性的前提下， 将像素电极置 于 P型晶体管与 N型晶体管之间的空间，并釆用像素电极与 P型半导体有源 层通过一次掩膜光刻工艺同时形成的方法， 省去了对像素电极单独通过掩膜 光刻工艺形成的步骤，且可有效减小互补型薄膜晶体管驱动背板的整体厚度。 由此， 本发明的实施例有效简化了工艺步骤， 节约了制作成本， 提高了制作 效率。
本申请要求于 2013年 12月 27日递交的中国专利申请第 201310742725.3 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1、 一种互补型薄膜晶体管驱动背板的制作方法， 包括：
在衬底基板上设置下半导体层，所述下半导体层包括 P型半导体有源层； 在所述下半导体层上设置栅绝缘层；
在所述栅绝缘层上设置下电极层， 所述下电极层包括 P型晶体管栅极、 N型晶体管源极和 N型晶体管漏极，所述 P型晶体管栅极位于所述 P型半导 体有源层的上方；
利用氧化物半导体材料在所述下电极层上设置上半导体层， 所述上半导 体层包括像素电极和 N型半导体有源层，所述 N型半导体有源层的两端分别 与所述 N型晶体管源极和所述 N型晶体管漏极搭接；
对所述像素电极区域对应的氧化物半导体材料进行等离子体处理； 在所述上半导体层上设置隔离绝缘保护层， 所述隔离绝缘保护层包括接 触孔和保护单元， 所述接触孔位于所述 P型半导体有源层两端和所述像素电 极对应区 i或；
在所述隔离绝缘保护层上设置上电极层， 所述上电极层包括 P型晶体管 源极、 P型晶体管漏极和 N型晶体管栅极， 所述 P型晶体管源极、 所述 P型 晶体管漏极分别通过所述接触孔与所述 P型半导体有源层的两端相连， 所述 N型晶体管栅极位于所述 N型半导体有源层的上方； 以及
在所述上电极层上设置像素定义层， 所述像素定义层包括像素连接口。
2、如权利要求 1所述互补型薄膜晶体管驱动背板的制作方法， 其中， 所 述在衬底基板上设置下半导体层包括：
在所述衬底基板上设置緩冲层；
在所述緩冲层上设置非晶硅薄膜； 以及
对所述非晶硅薄膜进行脱氢处理和准分子激光退火处理。
3、如权利要求 2所述互补型薄膜晶体管驱动背板的制作方法， 其中， 所 述在衬底基板上设置下半导体层还包括：
在所述下半导体层上形成多个所述 P型半导体有源层； 所述 P型半导体 有源层包括源极接触区、 漏极接触区以及设置在所述源极接触区与所述漏极 接触区之间的有源层连接区； 对所述 P型半导体有源层进行掺杂剂注入， 将所述掺杂剂分别注入所述 源极接触区和所述漏极接触区； 以及
对所述掺杂剂进行活化的步骤。
4、 如权利要求 3所述互补型薄膜晶体管驱动背板的制作方法， 其中： 所述接触孔位于所述 P型晶体管栅极两侧， 并贯穿所述隔离绝缘保护层 直至所述 P型半导体有源层的所述源极接触区和所述漏极接触区； 所述像素 连接口设置在所述像素电极上。
5、如权利要求 1-4任一所述互补型薄膜晶体管驱动背板的制作方法， 其 中：
所述 P型晶体管漏极与所述像素电极连接；所述 N型半导体有源层连接 在所述 N型晶体管源极和所述 N型晶体管漏极之间。
6、如权利要求 1-5任一所述互补型薄膜晶体管驱动背板的制作方法， 其 中：
所述上半导体层釆用铟镓辞氧化物、 辞氧化物、 铟辞氧化物、 和铟锡辞 氧化物中的任意一种或任意几种的组合物。
7、一种互补型薄膜晶体管驱动背板， 包括衬底基板以及在该衬底基板上 依次设置的：
包括 P型半导体有源层的下半导体层；
栅绝缘层；
包括 P型晶体管栅极、 N型晶体管源极和 N型晶体管漏极的下电极层； 包括像素电极和 N型半导体有源层的上半导体层；
包括接触孔和保护单元的隔离绝缘保护层；
包括 P型晶体管源极、 P型晶体管漏极和多个 N型晶体管栅极的上电极 层； 以及
包括像素连接口的像素定义层。
8、 如权利要求 7所述互补型薄膜晶体管驱动背板， 其中：
所述 P型半导体有源层包括源极接触区、 漏极接触区以及设置在所述源 极接触区与所述漏极接触区之间的有源层连接区；
所述 P型晶体管栅极设置在所述 P型半导体有源层的上方；
所述 P型晶体管源极通过所述接触孔与所述源极接触区连接； 所述 P型晶体管漏极通过所述接触孔与所述漏极接触区连接。
9、 如权利要求 7或 8所述互补型薄膜晶体管驱动背板， 其中： 间；
所述 N型晶体管源极与所述 N型晶体管漏极通过所述 N型半导体有源 层连接；
所述 N型晶体管栅极设置在所述 N型半导体有源层的上方。
10、 如权利要求 7-9任一所述互补型薄膜晶体管驱动背板， 其中： 所述 P型晶体管漏极与所述像素电极连接。
11、 如权利要求 7-10任一所述互补型薄膜晶体管驱动背板， 其中： 位于所述 P型晶体管栅极上的所述保护单元右端置于像素电极左端之 上；
位于所述 N型晶体管栅极与所述 N型半导体有源层之间的所述保护单 元， 其左端置于所述像素电极右端之上。
12、 如权利要求 7-11任一所述互补型薄膜晶体管驱动背板， 其中： 所述 像素连接口设置在所述像素电极上。
13、 如权利要求 7-12任一所述互补型薄膜晶体管驱动背板， 其中： 所述 像素电极、所述 N型晶体管源极和所述 N型晶体管漏极均釆用铟镓辞氧化物、 辞氧化物、 铟辞氧化物和铟锡辞氧化物中的任意一种或任意几种的组合物制 成。
14、 一种显示面板， 包括如权利要求 7-13中任一所述的互补型薄膜晶体 管驱动背板。
PCT/CN2014/081190 2013-12-27 2014-06-30 互补型薄膜晶体管驱动背板及其制作方法、显示面板 Ceased WO2015096441A1 (zh)

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