WO2015096304A1 - 在半导体衬底表面制备锌掺杂超浅结的方法 - Google Patents

在半导体衬底表面制备锌掺杂超浅结的方法 Download PDF

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WO2015096304A1
WO2015096304A1 PCT/CN2014/075402 CN2014075402W WO2015096304A1 WO 2015096304 A1 WO2015096304 A1 WO 2015096304A1 CN 2014075402 W CN2014075402 W CN 2014075402W WO 2015096304 A1 WO2015096304 A1 WO 2015096304A1
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zinc
semiconductor substrate
zinc oxide
shallow junction
preparing
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PCT/CN2014/075402
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English (en)
French (fr)
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孙兵
刘洪刚
赵威
王盛凯
常虎东
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中国科学院微电子研究所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities

Definitions

  • the invention relates to a method for preparing an ultra-shallow junction of a semiconductor substrate, in particular to a semiconductor
  • a method for preparing a zinc-doped ultra-shallow junction on a surface of a substrate belongs to the field of semiconductor integration technology.
  • CMOS integration technology has followed over the past 40 years Moore's Law increases the operating speed and integration of devices by reducing the feature size of the device And reduce costs.
  • the gate length of the MOS device is reduced to below 90 nm, especially entering To the 65 nm and below nodes, the source/drain regions and the source/drain extension regions are required to be correspondingly shallower.
  • the shallow junction can better improve the short channel effect of the device, but with the size and performance of the device
  • junction leakage phenomenon is an increasingly problem that ultra-shallow junction technology needs to solve.
  • Plasma immersion doping, projection gas immersion laser doping, fast vapor phase doping, separation Sub-shower doping and single-layer atom diffusion doping techniques have been proposed to prepare ultra-shallow junctions.
  • the single atom diffusion doping technique has small lattice damage and doped junction. The deep and controllable advantages have gained more and more attention.
  • the method of atomic layer deposition has high uniformity, good surface coverage, and self-limiting surface adsorption
  • the advantages of accurate and controllable growth rate have been applied to the current CMOS technology gate media.
  • how to combine atomic layer deposition and single atom diffusion doping will help to achieve Preparation of precisely controllable ultra-shallow junctions.
  • the main purpose of the present invention is to atomic layer deposition technology and single atom diffusion.
  • Doping technology combines to provide a zinc-doped ultra-shallow junction on the surface of a semiconductor substrate method.
  • the present invention provides a method for preparing zinc doping on a surface of a semiconductor substrate.
  • the ultra-shallow junction method is to diffuse zinc in the zinc oxide obtained by atomic layer deposition.
  • a zinc-doped ultra-shallow junction is prepared on the surface of the semiconductor substrate, the method comprising:
  • Step 1 cleaning the surface of the semiconductor substrate
  • Step 2 A method of using atomic layer deposition in an atomic layer deposition system in the semiconductor Depositing a zinc oxide layer on the substrate;
  • Step 3 depositing a cap layer on the zinc oxide layer
  • Step 4 high temperature annealing diffuses zinc atoms in the zinc oxide layer to the semiconductor substrate surface
  • Step 5 Remove the cap layer and the zinc oxide layer.
  • the semiconductor substrate described in the step 1 is a silicon substrate, a germanium substrate, or a silicon germanium. Substrate or III-V compound semiconductor substrate.
  • the surface of the semiconductor substrate is cleaned as described in step 1, first using acetone. And ultrasonically cleaning the organic matter on the surface of the semiconductor substrate by ultrasonic cleaning for 1-10 minutes. And grease staining, followed by washing the semiconductor substrate with hydrochloric acid, hydrofluoric acid, ammonia water or hydrobromic acid a surface that removes a native oxide of the surface of the semiconductor substrate.
  • the reaction chamber temperature is The reaction chamber pressure is from 0.5 mbar to 10 mbar at 20 ° C to 500 ° C.
  • the method of using atomic layer deposition described in step 2 is performed on the semiconductor lining
  • a zinc oxide layer is deposited on the bottom, and a zinc precursor is first introduced into the reaction chamber of the atomic layer deposition system.
  • the pulse of the source is then washed with high purity nitrogen to flush out the by-products of the reaction and the precursor of residual zinc.
  • a source then a pulse of a precursor source of oxygen into the reaction chamber of the atomic layer deposition system, and High-purity nitrogen purge, flushing out the reaction by-products and residual oxygen precursor source to form a complete Zinc oxide growth cycle, precise control of zinc oxide by controlling the number of cycles of zinc oxide growth Growth thickness.
  • the precursor source of zinc is diethyl zinc (Zn(C 2 H 5 ) 2 ), dimethyl zinc (Zn(CH 3 ) 2 ) or acetic acid.
  • the precursor source of oxygen is one or more combinations of water (H 2 O), oxygen (O 2 ) and ozone (O 3 ), and zinc oxide is deposited in the atomic layer.
  • the pulse of the precursor source of zinc is from 1 millisecond to 60 seconds, and the pulse source of the precursor of oxygen is from 1 millisecond to 60 seconds.
  • the thickness of the zinc oxide layer described in the step 2 is 1 angstrom to 100 nm.
  • the cap layer described in step 3 is formed by atomic layer deposition and plasma enhancement. Deposited by chemical vapor deposition or sputtering, the cap layer is aluminum oxide, silicon dioxide Or silicon nitride, the cap layer has a thickness of 3 angstroms to 200 nanometers.
  • the high temperature annealing described in step 4 the annealing temperature is 400 ° C - 1000 ° C,
  • the annealing time of the high temperature annealing is 1 millisecond to 1 hour.
  • the cap layer and the zinc oxide layer described in step 5 are etched or Corrosion method to remove the cap layer and zinc oxide layer, where etching or etching is performed by wet or dry method formula.
  • the invention has the beneficial effects that the invention provides zinc doping on the surface of a semiconductor substrate.
  • the ultra-shallow junction method is to deposit a zinc oxide layer on a semiconductor substrate and deposit a cap on the zinc oxide layer. a layer, and then diffusing the zinc atoms in the zinc oxide layer into the semiconductor substrate by annealing, The cap layer and the zinc oxide layer are removed by etching or etching to form a zinc-doped ultra-shallow junction.
  • monoatomic layer diffusion has the advantages of tight junction depth and small lattice damage, while atomic layer deposition Good surface coverage, precise and controllable growth thickness, low growth temperature, uniformity of growth thickness Good advantage, the present invention combines atomic layer deposition technology with single atom diffusion doping technology, To prepare ultra-shallow junctions of zinc-doped semiconductor substrates, ultra-shallow junction depth control, ultra-shallow junction uniformity, Semiconductor substrate surface damage, doping concentration control, etc. have great advantages, suitable for flat Fabrication of ultra-shallow junctions for surface and non-planar semiconductor devices.
  • FIG. 1 is a diagram showing the formation of a zinc-doped ultra-shallow junction on a semiconductor substrate in accordance with an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a semiconductor substrate in accordance with an embodiment of the present invention.
  • FIG. 3 is a structure after depositing a zinc oxide layer on a semiconductor substrate in accordance with an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a cap layer deposited on a zinc oxide layer according to an embodiment of the invention.
  • FIG. 5 is an illustration of annealing to cause zinc to diffuse to the surface of a semiconductor substrate in accordance with an embodiment of the present invention.
  • FIG. 6 is a zinc-doped ultra-shallow formed on the surface of a semiconductor substrate in accordance with an embodiment of the present invention. Schematic diagram of the knot;
  • the method for preparing a zinc-doped ultra-shallow junction on the surface of a semiconductor substrate provided by the present invention is in the middle A zinc oxide layer is deposited on the conductor substrate, a cap layer is deposited on the zinc oxide layer, and then annealed Dispersing zinc atoms in the zinc oxide layer into the semiconductor substrate by etching or etching The cap layer and the zinc oxide layer are removed to form a zinc-doped ultra-shallow junction.
  • FIG. 1 is a graph showing zinc doping on a semiconductor substrate in accordance with an embodiment of the present invention.
  • a flow chart of a method for mixing ultra-shallow junctions is to expand zinc in zinc oxide obtained by atomic layer deposition. Dispersing a zinc-doped ultra-shallow junction on a surface of a semiconductor substrate, the method comprising:
  • Step 1 cleaning the surface of the semiconductor substrate
  • Step 2 A method of using atomic layer deposition in an atomic layer deposition system in the semiconductor Depositing a zinc oxide layer on the substrate;
  • Step 3 depositing a cap layer on the zinc oxide layer
  • Step 4 high temperature annealing diffuses zinc atoms in the zinc oxide layer to the semiconductor substrate surface
  • Step 5 Remove the cap layer and the zinc oxide layer.
  • the semiconductor substrate described in step 1 is a silicon substrate, a germanium substrate, a silicon germanium substrate or III-V compound semiconductor substrate.
  • the cleaning of the surface of the semiconductor substrate, first using acetone and Ethanol is sequentially ultrasonically cleaned for 1-10 minutes to remove organic matter on the surface of the semiconductor substrate and Grease staining, followed by cleaning the semiconductor substrate with hydrochloric acid, hydrofluoric acid, ammonia or hydrobromic acid The surface removes the native oxide of the surface of the semiconductor substrate.
  • the atomic layer deposition system described in the step 2 has a reaction chamber temperature of 20 ° C to 500 ° C and a reaction chamber pressure of 0.5 mbar to 10 mbar.
  • the method of depositing a zinc oxide on the semiconductor substrate by using a method of atomic layer deposition firstly introducing a pulse of a precursor source of zinc into a reaction chamber of the atomic layer deposition system, followed by washing with high-purity nitrogen gas, flushing the reaction A by-product and a precursor source of residual zinc, and then a pulse of a precursor source of oxygen is introduced into the reaction chamber of the atomic layer deposition system, and washed with high-purity nitrogen to wash away the reaction by-product and the precursor source of residual oxygen.
  • the precursor source of zinc is diethyl zinc (Zn(C 2 H 5 ) 2 ), dimethyl zinc (Zn(CH 3 ) 2 ) or zinc acetate (Zn (CH 3 COO) 2 ),
  • the precursor source of oxygen is one or a combination of water (H 2 O), oxygen (O 2 ) and ozone (O 3 ), the precursor of the zinc when the zinc oxide is deposited in the atomic layer
  • the pulse of the body source is 1 millisecond to 60 seconds, and the pulse time of the precursor of the oxygen is 1 millisecond to 60 seconds.
  • the zinc oxide layer has a thickness of 1 angstrom to 100 nanometers.
  • the cap layer described in step 3 is atomic layer deposition, plasma enhanced chemical vapor deposition Or deposited by a sputtering method, the cap layer is aluminum oxide, silicon dioxide or silicon nitride.
  • the thickness of the cap layer is from 3 angstroms to 200 nanometers.
  • the annealing temperature is 400 ° C - 1000 ° C
  • the high temperature retreat The annealing time of the fire is 1 millisecond to 1 hour.
  • the cap layer and the zinc oxide layer described in step 5 are removed by etching or etching.
  • the etching or etching is performed by a wet method or a dry method.
  • a method for fabricating a zinc-doped ultra-shallow junction using a gallium substrate comprising the steps of:
  • Step 2 As shown in FIG. 3, the precursor source of zinc in the atomic layer deposition system is diethyl zinc (Zn(C 2 H 5 ) 2 ), and the precursor source of oxygen may be water (H 2 O). .
  • the atomic layer deposition system has a reaction chamber temperature of 250 degrees Celsius and a reaction chamber pressure of 1.5 mbar. First, a pulse of diethylzinc is introduced into the reaction chamber of the atomic layer deposition system, and the pulse is 200 milliseconds, followed by high purity.
  • a pulse of water is introduced into the reaction chamber of the atomic layer deposition system for a pulse time of 200 megaseconds, followed by high-purity nitrogen purge followed by high-purity nitrogen, and the purity of the high-purity nitrogen is 99.999%.
  • the flow rate is 300 sccm and the cleaning time is 2 seconds.
  • the reaction by-product and residual water are washed away to form a complete zinc oxide growth cycle, and 2 angstroms of zinc oxide is deposited per growth cycle, and 25 growth cycles of zinc oxide are grown on the gallium arsenide substrate 1 to form oxidation.
  • Zinc layer 2 2.
  • Step 3 as shown in FIG. 4, using a plasma enhanced chemical vapor deposition method in the A 20 nm thick silicon dioxide layer 3 was deposited on the zinc oxide layer 2.
  • Step 4 As shown in FIG. 5, the substrate obtained in the step 3 is retracted at 600 degrees Celsius. Fire for 20 minutes, diffusing zinc atoms in the zinc oxide layer 2 into the gallium arsenide substrate 1 Zinc-doped ultra-shallow junction 4.
  • the semi-insulating gallium arsenide substrate is used as the semiconductor substrate, and the sheet resistance of the semi-insulating gallium arsenide substrate is 10 6 ⁇ /sq, and the semiconductor lining obtained in the step 5 is adopted by the ring transmission line method.
  • the bottom is characterized as shown in FIG. 7.
  • the test results show that the sheet resistance of the semiconductor substrate obtained in the step 5 is 2123 ⁇ /sq, and it can be seen that the zinc element diffuses into the gallium arsenide substrate when the step 4 is performed. Activated.

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Abstract

一种在半导体衬底表面制备锌掺杂超浅结的方法，属于半导体集成技术领域，该方法是将由原子层沉积得到的氧化锌中的锌以扩散的方式在半导体衬底表面制备锌掺杂的超浅结，该方法包括：清洗半导体衬底表面（1）；在原子层沉积系统中利用原子层沉积的方法在半导体衬底上沉积氧化锌层（2）；在氧化锌层上沉积帽层（3）；高温退火将氧化锌层中的锌原子扩散到半导体衬底表面（4）；去除帽层和氧化锌层（5）。该方法可用于平面、非平面半导体器件的超浅结制备，在小尺寸半导体器件掺杂方面具有结深可控、半导体衬底晶格损伤小的优点。

Description

在半导体衬底表面制备锌掺杂超浅结的方法 技术领域
本发明涉及半导体衬底超浅结的制备方法，尤其涉及一种在半导体 衬底表面制备锌掺杂超浅结的方法，属于半导体集成技术领域。
背景技术
半导体技术作为信息产业的核心和基础，是衡量一个国家科学技术 进步和综合国力的重要标志。在过去的40多年中，CMOS集成技术遵循 摩尔定律通过缩小器件的特征尺寸来提高器件的工作速度、增加集成度 以及降低成本。然而当MOS器件的栅长缩小到90纳米以下，特别是进入 到65纳米及以下节点，要求源／漏区以及源／漏极延伸区相应地变浅，超 浅结可以更好的改善器件的短沟道效应，但是随着器件尺寸及性能的进 一步提高，结漏电现象是超浅结技术越来越需要解决的问题。
等离子体浸没掺杂、投射式气体浸入激光掺杂、快速汽相掺杂、离 子淋浴掺杂和单层原子扩散掺杂等技术相继被提出用以制备超浅结，进 而解决结漏电问题，其中单原子扩散掺杂技术以其晶格损伤小、掺杂结 深可控的优势获得了越来越多的关注。
原子层沉积的方法具有均匀性高、表面覆盖好、自限制表面吸附反 应及生长速度精确可控等优点，已经应用于当前CMOS技术栅介质的生 长过程中，如何将原子层沉积和单原子扩散掺杂相结合，将有利于实现 精确可控的超浅结的制备。
发明内容
有鉴于此，本发明的主要目的在于将原子层沉积技术和单原子扩散 掺杂技术相结合，从而提供一种在半导体衬底表面制备锌掺杂超浅结的 方法。
为达到上述目的，本发明提供了一种在半导体衬底表面制备锌掺杂 超浅结的方法，是将由原子层沉积得到的氧化锌中的锌以扩散的方式在 半导体衬底表面制备锌掺杂的超浅结，该方法包括：
步骤1：清洗半导体衬底表面；
步骤2：在原子层沉积系统中利用原子层沉积的方法在所述半导体 衬底上沉积氧化锌层；
步骤3：在所述氧化锌层上沉积帽层；
步骤4：高温退火将所述氧化锌层中的锌原子扩散到半导体衬底表 面；
步骤5：去除帽层和氧化锌层。
上述方案中，步骤1中所述的半导体衬底是硅衬底、锗衬底、硅锗 衬底或III-V族化合物半导体衬底。
上述方案中，步骤1中所述的清洗半导体衬底表面，首先利用丙酮 和乙醇依次分别超声清洗1-10分钟去除所述半导体衬底表面的有机物 及油脂沾污，接着用盐酸、氢氟酸、氨水或氢溴酸清洗所述半导体衬底 表面，去除所述半导体衬底表面的自然氧化物。
上述方案中，步骤2中所述的原子层沉积系统，反应腔温度为 20℃-500℃，反应腔压力为0.5毫巴-10毫巴。
上述方案中，步骤2中所述利用原子层沉积的方法在所述半导体衬 底上沉积氧化锌层，首先向原子层沉积系统反应腔体中通入锌的前驱体 源的脉冲，接着用高纯氮气清洗，冲掉反应副产物和残留的锌的前驱体 源，然后向原子层沉积系统反应腔体中通入氧的前驱体源的脉冲，并用 高纯氮气清洗，冲掉反应副产物和残留的氧的前驱体源，形成一个完整 的氧化锌生长周期，通过控制氧化锌生长的周期数来精确控制氧化锌的 生长厚度。
上述方案中，步骤2中所述原子层沉积系统中，锌的前驱体源为二 乙基锌(Zn(C 2H 5) 2)、二甲基锌(Zn(CH 3) 2)或醋酸锌(Zn(CH 3COO) 2)， 氧的前驱体源为水(H 2O)、氧气(O 2)和臭氧(O 3)中的一种或多种组 合，在原子层沉积氧化锌时，所述锌的前驱体源的脉冲为1毫秒-60秒， 所述氧的前驱体源的脉冲时间为1毫秒-60秒。
上述方案中，步骤2中所述的氧化锌层的厚度为1埃-100纳米。
上述方案中，步骤3中所述的帽层是采用原子层沉积、等离子增强 化学气相沉积或溅射的方法沉积的，所述帽层为三氧化二铝、二氧化硅 或氮化硅，所述帽层的厚度为3埃-200纳米。
上述方案中，步骤4中所述的高温退火，退火温度为400℃-1000℃， 所述高温退火的退火时间为1毫秒-1小时。
上述方案中，步骤5中所述的去除帽层和氧化锌层，是通过刻蚀或 腐蚀的方式去除帽层和氧化锌层，其中刻蚀或腐蚀采用湿法或干法的方 式。
本发明的有益效果是：本发明提供的在半导体衬底表面制备锌掺杂 超浅结的方法，是在半导体衬底上沉积氧化锌层，在氧化锌层上沉积帽 层，然后通过退火的方式将氧化锌层中的锌原子扩散到半导体衬底中， 采用腐蚀或刻蚀的方式去除帽层和氧化锌层，从而形成锌掺杂的超浅结。 其中，单原子层扩散具有结深可控、晶格损伤小的优点，而原子层沉积 具有表面覆盖性好、生长厚度精确可控、生长温度低、生长厚度均匀性 好的优点，本发明将原子层沉积技术和单原子扩散掺杂技术相结合，用 以制备锌掺杂的半导体衬底超浅结，在超浅结结深控制、超浅结均匀性、 半导体衬底表面损伤、掺杂浓度控制等方面具有很大的优势，适用于平 面、非平面半导体器件超浅结的制作。
附图说明
图1为依照本发明实施例的在半导体衬底上形成锌掺杂的超浅结的 方法流程图；
图2为依照本发明实施例的半导体衬底的结构示意图；
图3为依照本发明实施例的在半导体衬底上沉积氧化锌层后的结构 示意图；
图4为依照本发明实施例的在氧化锌层上沉积帽层后的结构示意图；
图5为依照本发明实施例的退火使得锌扩散到半导体衬底表面形成 超浅结的示意图；
图6为依照本发明实施例的在半导体衬底表面形成的锌掺杂的超浅 结的示意图；
图7为依照本发明实施例的砷化镓衬底锌掺杂的超浅结的方块电阻 的测试结果。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体 实施例，并参照附图，对本发明进一步详细说明。
本发明提供的在半导体衬底表面制备锌掺杂超浅结的方法，是在半 导体衬底上沉积氧化锌层，在氧化锌层上沉积帽层，然后通过退火的方 式将氧化锌层中的锌原子扩散到半导体衬底中，采用腐蚀或刻蚀的方式 去除帽层及氧化锌层，从而形成锌掺杂的超浅结。
如图1所示，图1为依照本发明实施例的在半导体衬底上形成锌掺 杂的超浅结的方法流程图，是将由原子层沉积得到的氧化锌中的锌以扩 散的方式在半导体衬底表面制备锌掺杂的超浅结，该方法包括：
步骤1：清洗半导体衬底表面；
步骤2：在原子层沉积系统中利用原子层沉积的方法在所述半导体 衬底上沉积氧化锌层；
步骤3：在所述氧化锌层上沉积帽层；
步骤4：高温退火将所述氧化锌层中的锌原子扩散到半导体衬底表 面；
步骤5：去除帽层和氧化锌层。
其中，步骤1中所述的半导体衬底是硅衬底、锗衬底、硅锗衬底或 III-V化合物半导体衬底。所述的清洗半导体衬底表面，首先利用丙酮和 乙醇依次分别超声清洗1-10分钟去除所述半导体衬底表面的有机物及 油脂沾污，接着用盐酸、氢氟酸、氨水或氢溴酸清洗所述半导体衬底表 面，去除所述半导体衬底表面的自然氧化物。
步骤2中所述的原子层沉积系统，反应腔温度为20℃-500℃，反应 腔压力为0.5毫巴-10毫巴。所述利用原子层沉积的方法在所述半导体衬 底上沉积氧化锌层，首先向原子层沉积系统反应腔体中通入锌的前驱体 源的脉冲，接着用高纯氮气清洗，冲掉反应副产物和残留的锌的前驱体 源，然后向原子层沉积系统反应腔体中通入氧的前驱体源的脉冲，并用 高纯氮气清洗，冲掉反应副产物和残留的氧的前驱体源，形成一个完整 的氧化锌生长周期，通过控制氧化锌生长的周期数来精确控制氧化锌的 生长厚度。所述原子层沉积系统中，锌的前驱体源为二乙基锌 (Zn(C 2H 5) 2)、二甲基锌(Zn(CH 3) 2)或醋酸锌(Zn(CH 3COO) 2)，氧的 前驱体源为水(H 2O)、氧气(O 2)和臭氧(O 3)中的一种或多种组合， 在原子层沉积氧化锌时，所述锌的前驱体源的脉冲为1毫秒-60秒，所 述氧的前驱体源的脉冲时间为1毫秒-60秒。所述的氧化锌层的厚度为1 埃-100纳米。
步骤3中所述的帽层是采用原子层沉积、等离子增强化学气相沉积 或溅射的方法沉积的，所述帽层为三氧化二铝、二氧化硅或氮化硅，所 述帽层的厚度为3埃-200纳米。
步骤4中所述的高温退火，退火温度为400℃-1000℃，所述高温退 火的退火时间为1毫秒-1小时。
步骤5中所述的去除帽层和氧化锌层，是通过刻蚀或腐蚀的方式去 除帽层和氧化锌层，其中刻蚀或腐蚀采用湿法或干法的方式。
以下实施例仅用于更加清楚地说明本发明的技术方案，而不能以此 来限制本发明的保护范围。本实施例具体描述本发明所提供的一种砷化 镓衬底制作锌掺杂超浅结的方法，该方法包括如下步骤：
步骤1：如图2所示，首先利用丙酮和乙醇依次分别超声清洗5分 钟去除砷化镓衬底1表面的有机物及油脂沾污，接着用体积比HCl∶ H 2O=1∶10的稀盐酸去除所述砷化镓衬底1表面的自然氧化物。
步骤2：如图3所示，所述原子层沉积系统中锌的前驱体源为二乙 基锌(Zn(C 2H 5) 2)、氧的前驱体源可以为水(H 2O)。所述原子层沉积系 统的反应腔温度为250摄氏度，反应腔压力为1.5毫巴，首先向原子层 沉积系统反应腔体中通入二乙基锌脉冲，脉冲为200毫秒，紧接着用高 纯氮气清洗，紧接着用高纯氮气清洗，高纯氮气的纯度为99.999％，高 纯氮气的流量为300sccm，清洗时间为2秒，冲掉反应副产物和残留的 二乙基锌，紧着着向原子层沉积系统反应腔体中通入水的脉冲，脉冲时 间为200豪秒，紧接着用高纯氮气清洗，紧接着用高纯氮气清洗，高纯 氮气的纯度为99.999％，高纯氮气的流量为300sccm，清洗时间为2秒。 冲掉反应副产物和残留的水，形成一个完整的氧化锌生长周期，每个生 长周期沉积2埃氧化锌，在所述砷化镓衬底1上生长25个生长周期的 氧化锌，形成氧化锌层2。
步骤3：如图4所示，利用等离子增强化学气相沉积的方法在所述 氧化锌层2上沉积20纳米厚的二氧化硅层3。
步骤4：如图5所示，在600摄氏度下对所述步骤3获得的衬底退 火20分钟，将氧化锌层2中的锌原子扩散到所述砷化镓衬底1中，形 成锌掺杂的超浅结4。
步骤5：如图6所示，利用体积比CH 3COOH∶NH 4F∶H 2O=1∶1∶1的溶液 腐蚀40秒去除步骤4所获得的衬底表面的二氧化硅层3，利用体积比 HCl∶H 2O=1∶10的溶液腐蚀20秒去除步骤4所获得的衬底上残余的氧化锌 层2。
所述步骤1中，是以半绝缘砷化镓衬底作为半导体衬底，半绝缘砷 化镓衬底的方块电阻为10 6Ω／sq，采用环形传输线方法对所述步骤5获 得的半导体衬底进行表征，如图7所示，测试结果表明，所述步骤5获 得的半导体衬底的方块电阻为2123Ω／sq，可见锌元素在进行所述步骤4 时扩散到砷化镓衬底中并被激活。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进 行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施 例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的 任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种在半导体衬底表面制备锌掺杂超浅结的方法，是将由原子 层沉积得到的氧化锌中的锌以扩散的方式在半导体衬底表面制备锌掺 杂的超浅结，该方法包括：
    步骤1：清洗半导体衬底表面；
    步骤2：在原子层沉积系统中利用原子层沉积的方法在所述半导体 衬底上沉积氧化锌层；
    步骤3：在所述氧化锌层上沉积帽层；
    步骤4：高温退火将所述氧化锌层中的锌原子扩散到半导体衬底表 面；
    步骤5：去除帽层和氧化锌层。
  2. 根据权利要求1所述的在半导体衬底表面制备锌掺杂超浅结的 方法，其特征在于，步骤1中所述的半导体衬底是硅衬底、锗衬底、硅 锗衬底或III-V族化合物半导体衬底。
  3. 根据权利要求1所述的在半导体衬底表面制备锌掺杂超浅结的 方法，其特征在于，步骤1中所述的清洗半导体衬底表面，首先利用丙 酮和乙醇依次分别超声清洗1-10分钟去除所述半导体衬底表面的有机 物及油脂沾污，接着用盐酸、氢氟酸、氨水或氢溴酸清洗所述半导体衬 底表面，去除所述半导体衬底表面的自然氧化物。
  4. 根据权利要求1所述的在半导体衬底表面制备锌掺杂超浅结的 方法，其特征在于，步骤2中所述的原子层沉积系统，反应腔温度为 20℃-500℃，反应腔压力为0.5毫巴-10毫巴。
  5. 根据权利要求1所述的在半导体衬底表面制备锌掺杂超浅结的 方法，其特征在于，步骤2中所述利用原子层沉积的方法在所述半导体 衬底上沉积氧化锌层，首先向原子层沉积系统反应腔体中通入锌的前驱 体源的脉冲，接着用高纯氮气清洗，冲掉反应副产物和残留的锌的前驱 体源，然后向原子层沉积系统反应腔体中通入氧的前驱体源的脉冲，并 用高纯氮气清洗，冲掉反应副产物和残留的氧的前驱体源，形成一个完 整的氧化锌生长周期，通过控制氧化锌生长的周期数来精确控制氧化锌 的生长厚度。
  6. 根据权利要求5所述的在半导体衬底表面制备锌掺杂超浅结的 方法，其特征在于，步骤2中所述原子层沉积系统中，锌的前驱体源为 二乙基锌(Zn(C 2H 5) 2)、二甲基锌(Zn(CH 3) 2)或醋酸锌(Zn(CH 3COO) 2)， 氧的前驱体源为水(H 2O)、氧气(O 2)和臭氧(O 3)中的一种或多种组 合，在原子层沉积氧化锌时，所述锌的前驱体源的脉冲为1毫秒-60秒， 所述氧的前驱体源的脉冲时间为1毫秒-60秒。
  7. 根据权利要求1所述的在半导体衬底表面制备锌掺杂超浅结的 方法，其特征在于，步骤2中所述的氧化锌层的厚度为1埃-100纳米。
  8. 根据权利要求1所述的在半导体衬底表面制备锌掺杂超浅结的 方法，其特征在于，步骤3中所述的帽层是采用原子层沉积、等离子增 强化学气相沉积或溅射的方法沉积的，所述帽层为三氧化二铝、二氧化 硅或氮化硅，所述帽层的厚度为3埃-200纳米。
  9. 根据权利要求1所述的在半导体衬底表面制备锌掺杂超浅结的 方法，其特征在于，步骤4中所述的高温退火，退火温度为400℃-1000℃， 所述高温退火的退火时间为1毫秒-1小时。
  10. 根据权利要求1所述的在半导体衬底表面制备锌掺杂超浅结的 方法，其特征在于，步骤5中所述的去除帽层和氧化锌层，是通过刻蚀 或腐蚀的方式去除帽层和氧化锌层，其中刻蚀或腐蚀采用湿法或干法的 方式。
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