WO2015096174A1 - 低温多晶硅薄膜及其制备方法、晶体管 - Google Patents

低温多晶硅薄膜及其制备方法、晶体管 Download PDF

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WO2015096174A1
WO2015096174A1 PCT/CN2013/090858 CN2013090858W WO2015096174A1 WO 2015096174 A1 WO2015096174 A1 WO 2015096174A1 CN 2013090858 W CN2013090858 W CN 2013090858W WO 2015096174 A1 WO2015096174 A1 WO 2015096174A1
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layer
low
temperature polysilicon
thin film
amorphous silicon
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French (fr)
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张隆贤
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/234,985 priority Critical patent/US9209025B2/en
Priority to GB1607451.0A priority patent/GB2534771B/en
Priority to RU2016124647A priority patent/RU2642140C2/ru
Priority to DE112013007720.5T priority patent/DE112013007720B4/de
Priority to KR1020167016631A priority patent/KR101880835B1/ko
Priority to JP2016539934A priority patent/JP6163270B2/ja
Publication of WO2015096174A1 publication Critical patent/WO2015096174A1/zh
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40Crystalline structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90Thermal treatments, e.g. annealing or sintering
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743Silicon
    • H10D30/6745Polycrystalline or microcrystalline silicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10D86/021Manufacture or treatment of multiple TFTs
    • H10D86/0221Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0227Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using structural arrangements to control crystal growth, e.g. placement of grain filters
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411Silicon, silicon germanium or germanium
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3451Structure
    • H10P14/3452Microstructure
    • H10P14/3456Polycrystalline
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H10P14/3808Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H10P14/381Beam shaping, e.g. using a mask
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H10P14/3808Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H10P14/3816Pulsed laser beam

Definitions

  • the present invention relates to the field of liquid crystal display technology, and relates to a low temperature polysilicon film and a method for fabricating the same, and a low temperature polysilicon thin film transistor.
  • a liquid crystal display is a flat and ultra-thin display device composed of a certain number of color or black and white pixels placed in front of a light source or a reflecting surface. LCD monitors have low power consumption, high image quality, small size, and light weight. Therefore, they are favored by everyone and become the mainstream of displays.
  • liquid crystal displays are mainly Thin Film Transistors (TFT) liquid crystal displays.
  • TFT Thin Film Transistors
  • amorphous silicon electron mobility is low
  • low temperature polysilicon Low Temperature Ploy-silicon
  • the rate of shift and the ability to make C-M0S circuits have been extensively studied to achieve high resolution, low power consumption.
  • SPC Solid Phase Crystallization
  • MIC Metal Induced Crystallization
  • EL A Excimer Laser Annealer
  • the excimer laser annealing technique uses an excimer laser beam to irradiate an amorphous silicon film on a substrate for a short period of time, and the amorphous silicon is recrystallized by high temperature to form polycrystalline silicon.
  • the size of the low-temperature polycrystalline silicon crystals has an important influence on the electrical properties of the polycrystalline silicon.
  • the amorphous silicon becomes a completely melted (Nearly Completely Melts) state after being subjected to high temperature, and then recrystallized to form polycrystalline silicon.
  • recrystallization it crystallizes in a high energy direction in accordance with low energy, and crystallizes in a high temperature direction at a low temperature.
  • the present invention provides a method for preparing a low temperature polysilicon film.
  • a low-temperature polysilicon film is prepared by an excimer laser annealing process, the starting point and direction of recrystallization are controllable, and a large polycrystalline silicon crystal grain is obtained.
  • the present invention adopts the following technical solution: a method for preparing a low temperature polysilicon film, comprising the step of growing an amorphous silicon film layer, wherein first, a silicon oxide is grown on the amorphous silicon film layer. a plurality of concave arcuate surfaces on the silicon oxide layer, the concave arcuate surface refracting a light beam that is vertically irradiated to the silicon oxide layer; and finally using an excimer laser beam from the silicon oxide layer The layer is irradiated onto the amorphous silicon film layer to crystallize the amorphous silicon film layer to form a low temperature polysilicon film.
  • the method specifically includes the steps of:
  • the method further comprises the step of: removing the silicon oxide layer after crystallizing the low temperature polysilicon film.
  • the concave arcuate array is distributed on the silicon oxide layer. Wherein, the distance between two adjacent concave curved surfaces is 300 ⁇ 600 ⁇ ⁇ .
  • the outer circumference of the concave curved surface is circular, and the diameter is 10-20 ⁇ m ; the concave arc surface depth is 150-200 nm.
  • the amorphous silicon thin film layer is prepared in the step (b), the amorphous silicon thin film layer is subjected to high temperature dehydrogenation treatment.
  • the material of the buffer layer is silicon oxide.
  • Another aspect of the present invention provides a low temperature polysilicon film which is prepared by the method described above.
  • a low temperature polysilicon thin film transistor comprising: a substrate, a semiconductor layer formed on the substrate, the semiconductor layer being composed of a low temperature polysilicon film as described above, the semiconductor layer including a source region, a drain region, and the source region and the drain region a channel region; a gate insulating layer and a gate electrode are sequentially formed on the semiconductor layer, the gate insulating layer is for isolating the gate electrode and the semiconductor layer, and the gate electrode corresponds to the trench a dielectric layer formed on the gate insulating layer and above the gate, wherein the dielectric layer is provided with a first via and a second via, and the source electrode passes through the first via The source region is connected, and the drain electrode is connected to the drain region through the second via hole.
  • the method for preparing a low temperature polysilicon film provided by the present invention has a plurality of concave arcs grown on the amorphous silicon film layer
  • the amorphous silicon thin film layer is recrystallized by excimer laser beam irradiation, the laser beam is refracted in the concave curved surface region to disperse the light beam, which corresponds to the amorphous under the concave curved surface.
  • FIG. 1 is a schematic view showing a process flow of a method for preparing a low-temperature polysilicon film according to an embodiment of the present invention.
  • Fig. 2 is a top plan view of a plurality of concave arcuate surfaces prepared on a silicon oxide layer in accordance with an embodiment of the present invention.
  • Fig. 3 is an exemplary illustration of grain growth upon recrystallization in an embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As described above, the object of the present invention is to solve the problem that the starting point and direction of recrystallization in the preparation of low-temperature polysilicon film by the excimer laser annealing process in the prior art are messy, resulting in grain crystallization after crystallization, crystal A method for preparing a low-temperature polysilicon film is proposed.
  • a silicon oxide layer is first grown on the amorphous silicon film layer; Silicon Forming a plurality of concave curved surfaces on the layer, the concave curved surface refracting a light beam vertically irradiated to the silicon oxide layer; and finally irradiating the amorphous silicon from the silicon oxide layer by using an excimer laser beam On the film layer, the amorphous silicon film layer is crystallized to form a low temperature polysilicon film.
  • FIG. 1 is a schematic diagram of a process flow of a method for preparing a low-temperature polysilicon film according to the embodiment, including the steps:
  • a substrate 1 is first provided, and a buffer layer 2 is prepared on the substrate 1.
  • the substrate 1 is a glass substrate, and the buffer layer 2 is made of silicon oxide.
  • an amorphous silicon thin film layer 3 is formed on the buffer layer 2, and the amorphous silicon thin film layer 3 is subjected to high temperature dehydrogenation treatment.
  • the concave curved surface 401 corresponds to a concave lens surface, and the light beam that is vertically irradiated to the silicon oxide layer 4 can be refracted.
  • the thickness of the silicon oxide layer 4 is 300 nm. As shown in FIG.
  • the array of concave curved surfaces 401 is distributed on the silicon oxide layer 4, wherein the outer circumference of the concave curved surface 401 is Circular, 20 ⁇ m in diameter, 150 nm in depth (the depth here refers to the vertical distance between the lowest point of the concave curved surface 401 and the surface of the silicon oxide layer 4), and the distance between the adjacent two concave curved surfaces 401 is 450 ⁇ . ⁇ .
  • the thickness of the silicon oxide layer 4 is preferably in the range of 280 to 350 nm, and the diameter of the concave curved surface 401 may be set to be between 10 and 20 ⁇ m, and the depth of the concave curved surface 401 is The range that can be selected is 150 ⁇ 200nm, and the spacing between two adjacent concave curved faces 401 can be set between 300 ⁇ 600 ⁇ .
  • an excimer laser beam 5 is irradiated from the silicon oxide layer 4 onto the amorphous silicon thin film layer 3, and the amorphous silicon thin film layer 3 is crystallized to form a low temperature polycrystalline silicon thin film.
  • the excimer laser beam 5 is perpendicularly incident on the silicon oxide layer 4, it is refracted in the concave curved surface 401 region to disperse the light beam, and the temperature of the amorphous silicon thin film layer 3 corresponding to the concave curved surface 401 is relatively high.
  • the low temperature region 301 is formed low; and in the peripheral region of the concave curved surface 401, the excimer laser beam 5 is incident perpendicularly to the amorphous silicon film layer 3 to form the high temperature region 302.
  • polycrystalline silicon When polycrystalline silicon is recrystallized, it crystallizes according to low energy to high energy direction, and low temperature to high temperature.
  • Directional crystallization therefore, as shown in the exemplary illustration of FIG. 3, when the amorphous silicon thin film layer 3 is recrystallized, the starting point of crystallizing of the crystal grains 6 is formed in the low temperature region 301, and the growth becomes large toward the surrounding high temperature region 302 (as shown in the drawing).
  • the direction of the black arrow in 3 thereby obtaining a low-temperature polysilicon film whose direction is controllable and has a large polycrystalline silicon crystal grain.
  • the low-temperature polysilicon film prepared according to the above method has high electron mobility and stable electrical properties, and can be used for preparing a thin film transistor, particularly a thin film transistor in a TFT array in a liquid crystal display.
  • a semiconductor layer is formed on the substrate, the semiconductor layer is formed by a low temperature polysilicon film prepared by the foregoing method, the semiconductor layer includes a source region, a drain region, and the source region and the drain region a channel region; a gate insulating layer and a gate are sequentially formed over the semiconductor layer, the gate insulating layer is for isolating the gate and the semiconductor layer, and the gate corresponds to the channel a location of the region; the dielectric layer is formed over the gate insulating layer and the gate, the dielectric layer is provided with a first via and a second via, and the source electrode passes through the first via The source region is connected, and the drain electrode is connected to the drain region through the second via.
  • the transistor array in the liquid crystal display is prepared by using the low-temperature polysilicon film provided by the invention, and the transistor has high electron mobility and stable electrical performance, and improves the display quality of the liquid crystal display.
  • the method for preparing a low-temperature polysilicon film provided by the present invention grows a silicon oxide layer having a plurality of concave arc faces on an amorphous silicon film layer; and the amorphous silicon film layer is heavily colored by excimer laser beam irradiation. During crystallization, the laser beam is refracted in the concave arcuate region to disperse the light beam.
  • the temperature of the amorphous silicon film layer below the concave arc surface is relatively low to form a low temperature region; and the concave arc peripheral region,
  • the laser beam is incident perpendicularly to the amorphous silicon film layer to form a high temperature region.
  • polycrystalline silicon When polycrystalline silicon is recrystallized, it crystallizations according to low energy to high energy direction and low temperature to high temperature direction. Therefore, the starting point of crystallization is formed in the low temperature region, and the growth in the high temperature region is large, thereby obtaining a controllable direction and having a large polycrystalline silicon crystal.
  • the transistor formed by the preparation of the low-temperature polysilicon film obtained by the present invention has high electron mobility and stable electrical properties.

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  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)

Abstract

本发明公开了一种低温多晶硅薄膜的制备方法,包括生长非晶硅薄膜层的步骤,首先在所述非晶硅薄膜层上生长一氧化硅层;然后在所述氧化硅层上制备多个凹形弧面,所述凹形弧面可使垂直照射于所述氧化硅层的激光束发生折射;最后采用准分子激光束从所述氧化硅层照射到所述非晶硅薄膜层上,使所述非晶硅薄膜层结晶形成低温多晶硅薄膜。本发明还公开了一种由如上所述的方法制备获得的低温多晶硅薄膜以及包含该低温多晶硅薄膜的晶体管。本发明在采用准分子激光退火工艺制备低温多晶硅薄膜时,重结晶的起点和方向可控,获得较大的多晶硅晶粒。

Description

低温多晶硅薄膜及其制备方法、 晶体管
技术领域 本发明属于液晶显示器技术领域, 涉及一种低温多晶硅薄膜及其制备方法, 以及一种低温多晶硅薄膜晶体管。
背景技术 液晶显示器(Liquid Crystal Display, LCD), 为平面超薄的显示设备, 它由 一定数量的彩色或黑白像素组成, 放置于光书源或者反射面前方。 液晶显示器功 耗很低, 并且具有高画质、 体积小、 重量轻的特点, 因此倍受大家青睐, 成为 显示器的主流, 目前液晶显示器是以薄膜晶体管 (Thin Film Transistor, TFT) 液晶显示器为主。 随着平板显示的发展, 高分辨率, 低能耗的面板需求不断被 提出, 非晶硅电子迀移率低, 低温多晶硅 (Low Temperature Ploy-silicon) 由于 可在低温下制作, 且拥有高的电子迀移率及可制作 C-M0S电路而被广泛研宄用以 达到面板高分辨率, 低能耗的需求。
目前制作低温多晶硅的方法包括固相结晶(Solid Phase Crystallization, SPC)、 金属诱导结晶(Metal Induced Crystallization, MIC)和准分子激光退火(Excimer Laser Annealer, EL A) 等几种, 其中准分子激光退火是目前使用最为广泛的方 法。 准分子激光退火技术是采用准分子激光束对基板上的非晶硅薄膜进行短时 间照射, 非晶硅受到高温熔化重结晶形成多晶硅。
低温多晶硅晶粒的大小对多晶硅的电学性能有重要影响, 在准分子激光退 火制程中, 非晶硅受到高温后变成完全熔融 (Nearly Completely Melts) 状态, 然后重结晶形成多晶硅。 重结晶时会按照低能量向高能量方向结晶, 低温向高 温方向结晶。 由于目前采用准分子激光束均匀的照射到非晶硅薄膜层上, 非晶 硅薄膜层的各部分温度大致相等, 所以重结晶时的起点和方向是凌乱的, 导致 结晶后晶粒偏小, 晶粒间晶界偏多, 就会影响多晶硅的电子迀移率。 发明内容 鉴于现有技术存在的不足, 本发明提供了一种低温多晶硅薄膜的制备方法, 在采用准分子激光退火工艺制备低温多晶硅薄膜时, 重结晶的起点和方向可控, 获得较大的多晶硅晶粒。 为了达到上述的目的, 本发明采用了如下的技术方案: 一种低温多晶硅薄膜的制备方法, 包括生长非晶硅薄膜层的步骤, 其中, 首先在所述非晶硅薄膜层上生长一氧化硅层; 然后在所述氧化硅层上制备多个 凹形弧面, 所述凹形弧面可使垂直照射于所述氧化硅层的光束发生折射; 最后 采用准分子激光束从所述氧化硅层照射到所述非晶硅薄膜层上, 使所述非晶硅 薄膜层结晶形成低温多晶硅薄膜。 其中, 该方法具体包括步骤:
( a ) 提供一基板, 在所述基板上制备一缓冲层;
( b ) 在所述缓冲层上制备一非晶硅薄膜层;
( c )在所述非晶硅薄膜层上制备一氧化硅层, 并通过刻蚀工艺在所述氧化 硅层上制备多个凹形弧面;
( d )采用准分子激光束从所述氧化硅层照射到所述非晶硅薄膜层上, 使所 述非晶硅薄膜层结晶形成低温多晶硅薄膜。 其中, 该方法还包括步骤: 在结晶形成低温多晶硅薄膜后去除所述氧化硅 层。 其中, 所述凹形弧面阵列分布于所述氧化硅层。 其中, 相邻两个凹形弧面的距离为 300~600 μ πι。 其中, 所述凹形弧面的外周呈圆形, 直径为 10~20 μ πι; 所述凹形弧面深度 为 150~200nm。 其中, 步骤 (b ) 中制备得到非晶硅薄膜层之后, 对所述非晶硅薄膜层进行 高温去氢处理。 其中, 所述缓冲层的材料为氧化硅。 本发明的另一方面是提供了一种低温多晶硅薄膜, 采用如上所述的方法制 备得到。 本发明的另一方面是提供了一种低温多晶硅薄膜晶体管, 包括: 基板, 形成于所述基板上的半导体层, 所述半导体层由如上所述的低温多晶硅薄 膜构成, 所述半导体层包括源极区、 漏极区以及位于所述源极区和漏极区之间 的沟道区; 栅绝缘层以及栅极, 依次形成于所述半导体层之上, 所述栅绝缘层用于隔 离所述栅极与所述半导体层, 所述栅极对应于所述沟道区的位置; 介电层, 形成于所述栅绝缘层以及栅极上方, 所述介电层中设置有第一过 孔和第二过孔, 源电极通过所述第一过孔与所述源极区连接, 漏电极通过所述 第二过孔与所述漏极区连接 有益效果: 本发明提供的低温多晶硅薄膜的制备方法, 在非晶硅薄膜层上生长具有多 个凹形弧面的氧化硅层; 采用准分子激光束照射使非晶硅薄膜层发生重结晶时, 激光束在凹形弧面区域发生折射而使光束分散, 此时对应于凹形弧面下方的非 晶硅薄膜层的温度相对较低形成低温区; 而凹形弧面周边区域, 激光束垂直入 射到达非晶硅薄膜层形成高温区。 多晶硅重结晶时按照低能量向高能量方向结 晶, 低温向高温方向结晶, 因此在低温区形成结晶的起点, 向四周高温区生长 变大, 由此获得了方向可控且具有较大的多晶硅晶粒的低温多晶硅薄膜。 由本 发明获得的低温多晶硅薄膜制备形成的晶体管, 具有很高的电子迀移率以及稳 定的电性能。 附图说明 图 1是本发明一实施例的低温多晶硅薄膜的制备方法的工艺流程示意图。 图 2是本发明一实施例中在氧化硅层上制备的多个凹形弧面的俯视图。 图 3是本发明一实施例中重结晶时晶粒生长的示例性图示。 具体实施方式 如前所述,本发明的目的是解决现有技术中采用准分子激光退火工艺制备 低温多晶硅薄膜时, 重结晶时的起点和方向是凌乱的, 导致结晶后晶粒偏小, 晶粒间晶界偏多的问题,提出了一种低温多晶硅薄膜的制备方法, 在生长非晶硅 薄膜层之后, 首先在所述非晶硅薄膜层上生长一氧化硅层; 然后在所述氧化硅 层上制备多个凹形弧面, 所述凹形弧面可使垂直照射于所述氧化硅层的光束发 生折射; 最后采用准分子激光束从所述氧化硅层照射到所述非晶硅薄膜层上, 使所述非晶硅薄膜层结晶形成低温多晶硅薄膜。 通过凹形弧面区域对激光束发 生折射而使光束分散,在非晶硅薄膜层上形成低温区, 低温区的周围则为高温 区 (激光束不发生折射的区域), 重结晶时在低温区形成结晶的起点, 向四周高 温区生长变大, 由此获得了方向可控且具有较大的多晶硅晶粒的低温多晶硅薄 膜。 下面将对结合附图用实施例对本发明做进一步说明。 参阅图 1-3,图 1是本实施例提供的低温多晶硅薄膜的制备方法的工艺流程 示意图, 包括步骤:
( a)、 如图 la所示, 首先提供一基板 1, 在所述基板 1上制备一缓冲层 2; 所述基板 1为玻璃基板, 所述缓冲层 2的材料为氧化硅。
( b)、 如图 lb所示, 在所述缓冲层 2上制备一非晶硅薄膜层 3, 并对非晶 硅薄膜层 3进行高温去氢处理。
( c )如图 lc、 Id所示, 在所述非晶硅薄膜层 3上制备一氧化硅层 4, 并通 过刻蚀工艺在所述氧化硅层 4上制备多个凹形弧面 401,所述凹形弧面 401相当 于一凹透镜面, 可使垂直照射于所述氧化硅层 4 的光束发生折射。 在本实施例 中, 氧化硅层 4的厚度为 300nm, 如图 2所示, 所述凹形弧面 401阵列分布于所 述氧化硅层 4, 其中, 所述凹形弧面 401的外周呈圆形, 直径为 20 μ πι, 深度为 150nm (这里的深度是指凹形弧面 401最低点与氧化硅层 4表面的垂直距离), 相邻两个凹形弧面 401的距离为 450 μ πι。 在另外的一些实施例中, 所述氧化硅 层 4的厚度比较优选的范围是 280~350nm,凹形弧面 401的直径可以设置为 10~20 μ πι之间, 凹形弧面 401的深度可以选择的范围是 150~200nm, 相邻两个凹形弧 面 401的间距可以设置为 300~600 μ πι之间。
( d) 如图 le所示, 采用准分子激光束 5从所述氧化硅层 4照射到所述非 晶硅薄膜层 3上, 使所述非晶硅薄膜层 3结晶形成低温多晶硅薄膜。 准分子激 光束 5垂直入射到氧化硅层 4上时, 在凹形弧面 401区域发生折射而使光束分 散, 此时对应于凹形弧面 401下方的非晶硅薄膜层 3的温度相对较低形成低温 区 301 ; 而凹形弧面 401周边区域, 准分子激光束 5垂直入射到达非晶硅薄膜层 3形成高温区 302。 多晶硅重结晶时按照低能量向高能量方向结晶, 低温向高温 方向结晶, 因此, 如图 3所示的示例性图示, 非晶硅薄膜层 3重结晶时, 在低 温区 301形成晶粒 6结晶的起点, 向四周高温区 302生长变大 (如附图 3中黑 色箭头的方向), 由此获得了方向可控且具有较大的多晶硅晶粒的低温多晶硅薄 膜。
( e )在非晶硅薄膜层 3重结晶完成后,去除氧化硅层 4 (附图中未标示出)。 可以选择通过刻蚀工艺去除。 按照以上方法制备得到的低温多晶硅薄膜, 具有很高的电子迀移率以及稳 定的电性能, 可用于制备薄膜晶体管, 特别是液晶显示器中的 TFT 阵列中的薄 膜晶体管。 下面介绍本发明提供的一种低温多晶硅薄膜晶体管, 该晶体管包括: 基板、 半导体层、 栅绝缘层、 栅极、 介电层以及源电极和漏电极。 其中: 半导体层形成于所述基板上, 所述半导体层由前述方法制备得到的低温多 晶硅薄膜构成, 所述半导体层包括源极区、 漏极区以及位于所述源极区和漏极 区之间的沟道区; 栅绝缘层和栅极依次形成于所述半导体层之上, 所述栅绝缘 层用于隔离所述栅极与所述半导体层, 所述栅极对应于所述沟道区的位置; 所 述介电层形成于所述栅绝缘层以及栅极上方, 所述介电层中设置有第一过孔和 第二过孔, 源电极通过所述第一过孔与所述源极区连接, 漏电极通过所述第二 过孔与所述漏极区连接。 采用本发明提供的低温多晶硅薄膜制备液晶显示器中的晶体管阵列, 晶体 管具有很高的电子迀移率以及稳定的电性能, 提高了液晶显示器的显示质量。 综上所述, 本发明提供的低温多晶硅薄膜的制备方法, 在非晶硅薄膜层上 生长具有多个凹形弧面的氧化硅层; 采用准分子激光束照射使非晶硅薄膜层发 生重结晶时, 激光束在凹形弧面区域发生折射而使光束分散, 此时对应于凹形 弧面下方的非晶硅薄膜层的温度相对较低形成低温区; 而凹形弧面周边区域, 激光束垂直入射到达非晶硅薄膜层形成高温区。 多晶硅重结晶时按照低能量向 高能量方向结晶, 低温向高温方向结晶, 因此在低温区形成结晶的起点, 向四 周高温区生长变大, 由此获得了方向可控且具有较大的多晶硅晶粒的低温多晶 硅薄膜。 由本发明获得的低温多晶硅薄膜制备形成的晶体管, 具有很高的电子 迀移率以及稳定的电性能。 需要说明的是, 在本文中, 诸如第一和第二等之类的关系术语仅仅用来将 一个实体或者操作与另一个实体或操作区分开来, 而不一定要求或者暗示这些 实体或操作之间存在任何这种实际的关系或者顺序。 而且, 术语 "包括"、 "包 含"或者其任何其他变体意在涵盖非排他性的包含, 从而使得包括一系列要素 的过程、 方法、 物品或者设备不仅包括那些要素, 而且还包括没有明确列出的 其他要素, 或者是还包括为这种过程、 方法、 物品或者设备所固有的要素。 在 没有更多限制的情况下, 由语句 "包括一个…… " 限定的要素, 并不排除在包 括所述要素的过程、 方法、 物品或者设备中还存在另外的相同要素。
以上所述仅是本申请的具体实施方式, 应当指出, 对于本技术领域的普通 技术人员来说, 在不脱离本申请原理的前提下, 还可以做出若干改进和润饰, 这些改进和润饰也应视为本申请的保护范围。

Claims

权 利 要 求 书
1、一种低温多晶硅薄膜的制备方法, 包括生长非晶硅薄膜层的步骤, 其中, 首先在所述非晶硅薄膜层上生长一氧化硅层; 然后在所述氧化硅层上制备多个 凹形弧面, 所述凹形弧面可使垂直照射于所述氧化硅层的光束发生折射; 最后 采用准分子激光束从所述氧化硅层照射到所述非晶硅薄膜层上, 使所述非晶硅 薄膜层结晶形成低温多晶硅薄膜。
2、 根据权利要求 1所述的低温多晶硅薄膜的制备方法, 其中, 该方法具体 包括步骤:
( a) 提供一基板, 在所述基板上制备一缓冲层;
( b ) 在所述缓冲层上制备一非晶硅薄膜层;
( c )在所述非晶硅薄膜层上制备一氧化硅层, 并通过刻蚀工艺在所述氧化 硅层上制备多个凹形弧面;
( d)采用准分子激光束从所述氧化硅层照射到所述非晶硅薄膜层上, 使所 述非晶硅薄膜层结晶形成低温多晶硅薄膜。
3、 根据权利要求 2所述的低温多晶硅薄膜的制备方法, 其中, 该方法还包 括步骤: 在结晶形成低温多晶硅薄膜后去除所述氧化硅层。
4、 根据权利要求 2所述的低温多晶硅薄膜的制备方法, 其中, 所述凹形弧 面阵列分布于所述氧化硅层。
5、 根据权利要求 4所述的低温多晶硅薄膜的制备方法, 其中, 相邻两个凹 形弧面的距离为 300~600 μ m。
6、 根据权利要求 5所述的低温多晶硅薄膜的制备方法, 其中, 所述凹形弧 面的外周呈圆形, 直径为 10~20 μ πι, 所述凹形弧面深度为 150~200nm。
7、 根据权利要求 2 所述的低温多晶硅薄膜的制备方法, 其中, 步骤 (b ) 中制备得到非晶硅薄膜层之后, 对所述非晶硅薄膜层进行高温去氢处理。
8、 根据权利要求 2所述的低温多晶硅薄膜的制备方法, 其中, 所述缓冲层 的材料为氧化硅。
9、 一种低温多晶硅薄膜, 其中, 所述低温多晶硅薄膜的制备方法包括: 首先生长非晶硅薄膜层并在非晶硅薄膜层上生长一氧化硅层; 然后在所述氧化硅层上制备多个凹形弧面, 所述凹形弧面可使垂直照射于 所述氧化硅层的光束发生折射; 最后采用准分子激光束从所述氧化硅层照射到所述非晶硅薄膜层上, 使所 述非晶硅薄膜层结晶形成低温多晶硅薄膜。
10、 根据权利要求 9所述的低温多晶硅薄膜, 其中, 所述低温多晶硅薄膜 的制备方法具体包括步骤:
( a) 提供一基板, 在所述基板上制备一缓冲层;
( b) 在所述缓冲层上制备一非晶硅薄膜层;
( c )在所述非晶硅薄膜层上制备一氧化硅层, 并通过刻蚀工艺在所述氧化 硅层上制备多个凹形弧面;
( d)采用准分子激光束从所述氧化硅层照射到所述非晶硅薄膜层上, 使所 述非晶硅薄膜层结晶形成低温多晶硅薄膜。
11、 根据权利要求 10所述的低温多晶硅薄膜, 其中, 所述低温多晶硅薄膜 的制备方法还包括步骤: 在结晶形成低温多晶硅薄膜后去除所述氧化硅层。
12、 根据权利要求 10所述的低温多晶硅薄膜, 其中, 所述凹形弧面阵列分 布于所述氧化硅层。
13、 根据权利要求 12所述的低温多晶硅薄膜, 其中, 相邻两个凹形弧面的 距离为 300~600 m。
14、 根据权利要求 13所述的低温多晶硅薄膜, 其中, 所述凹形弧面的外周 呈圆形, 直径为 10~20 μ πι, 所述凹形弧面深度为 150~200nm。
15、 根据权利要求 10所述的低温多晶硅薄膜, 其中, 步骤 (b) 中制备得 到非晶硅薄膜层之后, 对所述非晶硅薄膜层进行高温去氢处理。
16、 根据权利要求 10所述的低温多晶硅薄膜, 其中, 所述缓冲层的材料为 氧化硅。
17、 一种低温多晶硅薄膜晶体管, 其中, 包括: 基板, 形成于所述基板上的半导体层, 所述半导体层由低温多晶硅薄膜构成, 所 述半导体层包括源极区、 漏极区以及位于所述源极区和漏极区之间的沟道区; 栅绝缘层以及栅极, 依次形成于所述半导体层之上, 所述栅绝缘层用于隔 离所述栅极与所述半导体层, 所述栅极对应于所述沟道区的位置; 介电层, 形成于所述栅绝缘层以及栅极上方, 所述介电层中设置有第一过 孔和第二过孔, 源电极通过所述第一过孔与所述源极区连接, 漏电极通过所述 第二过孔与所述漏极区连接; 其中, 所述低温多晶硅薄膜的制备方法包括: 首先生长非晶硅薄膜层并在非晶硅薄膜层上生长一氧化硅层; 然后在所述氧化硅层上制备多个凹形弧面, 所述凹形弧面可使垂直照射于 所述氧化硅层的光束发生折射; 最后采用准分子激光束从所述氧化硅层照射到所述非晶硅薄膜层上, 使所 述非晶硅薄膜层结晶形成低温多晶硅薄膜。
18、 根据权利要求 17所述的低温多晶硅薄膜晶体管, 其中, 所述低温多晶 硅薄膜的制备方法具体包括步骤:
( a ) 提供一基板, 在所述基板上制备一缓冲层;
( b ) 在所述缓冲层上制备一非晶硅薄膜层;
( c )在所述非晶硅薄膜层上制备一氧化硅层, 并通过刻蚀工艺在所述氧化 硅层上制备多个凹形弧面;
( d )采用准分子激光束从所述氧化硅层照射到所述非晶硅薄膜层上, 使所 述非晶硅薄膜层结晶形成低温多晶硅薄膜。
19、 根据权利要求 18所述的低温多晶硅薄膜晶体管, 其中, 所述低温多晶 硅薄膜的制备方法还包括步骤: 在制备得到非晶硅薄膜层之后, 对所述非晶硅薄膜层进行高温去氢处理; 在结晶形成低温多晶硅薄膜后去除所述氧化硅层。
20、 根据权利要求 18所述的低温多晶硅薄膜晶体管, 其中, 所述凹形弧面 阵列分布于所述氧化硅层; 所述凹形弧面的外周呈圆形, 直径为 10~20 μ πι, 所 述凹形弧面深度为 150~200nm; 相邻两个凹形弧面的距离为 300~600 μ m。
PCT/CN2013/090858 2013-12-25 2013-12-30 低温多晶硅薄膜及其制备方法、晶体管 Ceased WO2015096174A1 (zh)

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