JP6163270B2 - 低温ポリシリコン薄膜の製造方法 - Google Patents
低温ポリシリコン薄膜の製造方法 Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims description 84
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 52
- 229920005591 polysilicon Polymers 0.000 title claims description 52
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 45
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 34
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 4
- 230000001678 irradiating Effects 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 239000011159 matrix material Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 238000002425 crystallisation Methods 0.000 description 6
- 230000005712 crystallization Effects 0.000 description 6
- 238000001953 recrystallisation Methods 0.000 description 6
- 238000005224 laser annealing Methods 0.000 description 5
- 230000000875 corresponding Effects 0.000 description 4
- 230000002093 peripheral Effects 0.000 description 3
- 238000006356 dehydrogenation reaction Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
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- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
Description
低温ポリシリコンの結晶粒の大きさはポリシリコンの電気特性に重大な影響を与え、エキシマレーザアニールのプロセスにおいて、アモルファスシリコンは高温下で完全溶融(Nearly Completely Melts)状態となり、その後、再結晶によりポリシリコンを形成する。再結晶時には、低エネルギーから高エネルギーへの方向、低温から高温への方向に結晶化される。現在は、エキシマレーザ―ビームをアモルファスシリコン薄膜層に均一に照射し、アモルファスシリコン薄膜層の各部分の温度が大体等しいため、再結晶時の起点と方向は乱れており、結晶後の結晶粒が小さくなり、結晶粒界が多くなり、ポリシリコンの電子移動度に影響を与える。
低温ポリシリコン薄膜の製造方法であって、アモルファスシリコン薄膜層を成長させるステップを含み、まず、前記アモルファスシリコン薄膜層に酸化シリコン層を成長させ、その後、前記酸化シリコン層に垂直に照射される光束を屈折させる複数の凹弧面を形成し、最後に、前記アモルファスシリコン薄膜が結晶化され低温ポリシリコン薄膜を形成するように、エキシマレーザービームを前記酸化シリコン層から前記アモルファスシリコン薄膜層に照射する。
基板を提供し、前記基板上にバッファ層を形成するステップ(a)と、
前記バッファ層にアモルファスシリコン薄膜層を形成するステップ(b)と、
前記アモルファスシリコン薄膜層に酸化シリコン層を製造させ、エッチングプロセスにより前記酸化シリコン層に複数の凹弧面を形成するステップ(c)と、
前記アモルファスシリコン薄膜層が結晶化され低温ポリシリコン薄膜を形成するように、エキシマレーザービームを前記酸化シリコン層から前記アモルファスシリコン薄膜層に照射するステップ(d)と、を含む。
基板と、
前記基板上に形成され、上記のような低温ポリシリコン薄膜からなり、ソース領域、ドレイン領域、及び前記ソース領域とドレイン領域との間に位置するチャネル領域を含む半導体層と、
前記半導体層に順次形成され、前記ゲートと前記半導体層を隔離するゲート絶縁層、及び前記チャネル領域の位置に対応するゲートと、
前記ゲート絶縁層及びゲートの上方に形成され、第1ビアホールと第2ビアホールが設置され、ソース電極が前記第1ビアホールを介して前記ソース領域に接続され、ドレイン電極が前記第2ビアホールを介して前記ドレイン領域に接続される誘電体層と、
を含む低温ポリシリコン薄膜トランジスタを提供する。
図1〜3に示すように、図1は本実施例により提供される低温ポリシリコン薄膜の製造方法の工程の流れを示す図であり、前記工程の流れは以下のステップを含む。
Claims (5)
- 低温ポリシリコン薄膜の製造方法であって、
まず、アモルファスシリコン薄膜層に酸化シリコン層を成長させ、
その後、前記酸化シリコン層に垂直に照射された光束を屈折させる複数の弧状の凹面を形成し、
最後に、前記アモルファスシリコン薄膜層が結晶化され前記低温ポリシリコン薄膜を形成するように、エキシマレーザービームを前記酸化シリコン層から前記アモルファスシリコン薄膜層に照射する前記アモルファスシリコン薄膜層を成長させるステップを含み、
前記弧状の凹面は前記酸化シリコン層にマトリックス状に配列され、
隣接する二つの前記弧状の凹面の距離は300〜600μmであることを特徴とする低温ポリシリコン薄膜の製造方法。 - 具体的に、
基板を提供し、前記基板上にバッファ層を形成するステップ(a)と、
前記バッファ層にアモルファスシリコン薄膜層を形成するステップ(b)と、
前記アモルファスシリコン薄膜層に酸化シリコン層を形成し、エッチングプロセスにより前記酸化シリコン層に複数の弧状の凹面を形成するステップ(c)と、
前記アモルファスシリコン薄膜層が結晶化され低温ポリシリコン薄膜を形成するように、
エキシマレーザービームを前記酸化シリコン層から前記アモルファスシリコン薄膜層に照射するステップ(d)と、
を含む、
ことを特徴とする請求項1に記載の低温ポリシリコン薄膜の製造方法。 - さらに、結晶化され低温ポリシリコン薄膜を形成した後、前記酸化シリコン層を除去するステップを含むことを特徴とする請求項2に記載の低温ポリシリコン薄膜の製造方法。
- 前記弧状の凹面の外周は円形を呈し、直径が10〜20μmであり、前記弧状の凹面の深さは150〜200nmであることを特徴とする請求項1に記載の低温ポリシリコン薄膜の製造方法。
- 前記バッファ層の材料は酸化シリコンであることを特徴とする請求項2に記載の低温ポリシリコン薄膜の製造方法。
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PCT/CN2013/090858 WO2015096174A1 (zh) | 2013-12-25 | 2013-12-30 | 低温多晶硅薄膜及其制备方法、晶体管 |
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WO2016023246A1 (zh) * | 2014-08-15 | 2016-02-18 | 深圳市华星光电技术有限公司 | 低温多晶硅薄膜的制备方法、制备设备及低温多晶硅薄膜 |
CN104241173B (zh) * | 2014-09-03 | 2017-01-25 | 深圳市华星光电技术有限公司 | 一种低温多晶硅薄膜的制备机构及方法 |
CN104576318B (zh) * | 2014-12-24 | 2017-09-05 | 深圳市华星光电技术有限公司 | 一种非晶硅表面氧化层形成方法 |
CN104465371A (zh) * | 2014-12-31 | 2015-03-25 | 深圳市华星光电技术有限公司 | 准分子激光退火前处理方法、薄膜晶体管及其生产方法 |
CN104538310A (zh) * | 2015-01-16 | 2015-04-22 | 京东方科技集团股份有限公司 | 低温多晶硅薄膜的制备方法、tft、阵列基板及显示装置 |
CN104658891B (zh) * | 2015-03-03 | 2019-03-15 | 京东方科技集团股份有限公司 | 低温多晶硅薄膜的制备方法、薄膜晶体管及显示装置 |
CN104867812A (zh) | 2015-03-27 | 2015-08-26 | 京东方科技集团股份有限公司 | 多晶硅薄膜和半导体器件的制备方法、显示基板及装置 |
CN105161498B (zh) * | 2015-08-03 | 2017-09-19 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制作方法、阵列基板以及显示装置 |
KR102130688B1 (ko) * | 2015-11-03 | 2020-07-07 | 삼성디스플레이 주식회사 | 레이저 결정화 방법 |
CN106024708A (zh) * | 2016-08-12 | 2016-10-12 | 武汉华星光电技术有限公司 | 低温多晶硅薄膜晶体管阵列基板及其制备方法 |
CN108831894A (zh) * | 2018-06-14 | 2018-11-16 | 深圳市华星光电技术有限公司 | 低温多晶硅薄膜的制作方法、低温多晶硅薄膜及低温多晶硅tft基板 |
CN109979383B (zh) * | 2019-04-24 | 2021-04-02 | 深圳市华星光电半导体显示技术有限公司 | 像素驱动电路以及显示面板 |
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JP2002231629A (ja) * | 2001-02-01 | 2002-08-16 | Matsushita Electric Ind Co Ltd | 半導体薄膜の形成方法および薄膜トランジスタの製造方法 |
TW565944B (en) * | 2002-10-09 | 2003-12-11 | Toppoly Optoelectronics Corp | Method of forming a low temperature polysilicon thin film transistor |
US7235466B2 (en) * | 2002-10-31 | 2007-06-26 | Au Optronics Corporation | Method of fabricating a polysilicon layer |
CN1275291C (zh) * | 2003-06-04 | 2006-09-13 | 友达光电股份有限公司 | 利用准分子激光再结晶工艺来制作多晶硅薄膜的方法 |
JP2005064078A (ja) * | 2003-06-18 | 2005-03-10 | Advanced Lcd Technologies Development Center Co Ltd | 半導体薄膜の結晶化方法並びに結晶化装置 |
TWI310585B (en) * | 2003-10-14 | 2009-06-01 | Ind Tech Res Inst | Method of controlling polysilicon crystallization |
JP2005158943A (ja) * | 2003-11-25 | 2005-06-16 | Sharp Corp | 半導体膜の製造方法 |
TWI233457B (en) * | 2003-12-23 | 2005-06-01 | Ind Tech Res Inst | Method of forming poly-silicon crystallization |
JP4540359B2 (ja) * | 2004-02-10 | 2010-09-08 | シャープ株式会社 | 半導体装置およびその製造方法 |
WO2005107327A1 (ja) * | 2004-04-30 | 2005-11-10 | Sanyo Electric Co., Ltd. | 発光ディスプレイ |
CN100359651C (zh) * | 2004-05-17 | 2008-01-02 | 统宝光电股份有限公司 | 应用于高效能薄膜晶体管的多晶硅退火结构及其方法 |
CN1716071A (zh) * | 2004-06-04 | 2006-01-04 | 株式会社液晶先端技术开发中心 | 结晶方法、薄膜晶体管制造方法、薄膜晶体管及显示装置 |
TWI241637B (en) * | 2004-07-08 | 2005-10-11 | Au Optronics Corp | Method for manufacturing polysilicon layer |
US20060024870A1 (en) * | 2004-07-27 | 2006-02-02 | Wen-Chun Wang | Manufacturing method for low temperature polycrystalline silicon cell |
TWI244214B (en) * | 2004-09-23 | 2005-11-21 | Au Optronics Corp | Semiconductor device and method of fabricating a LTPS film |
KR100753432B1 (ko) * | 2005-11-08 | 2007-08-31 | 경희대학교 산학협력단 | 다결정 실리콘 및 그의 결정화 방법 |
JP2007134501A (ja) * | 2005-11-10 | 2007-05-31 | Advanced Lcd Technologies Development Center Co Ltd | エキシマレーザーアニール法で作製したSi膜を用いた半導体トランジスタ製造方法 |
TW200830426A (en) * | 2007-01-12 | 2008-07-16 | Xu-Xin Chen | Method for fabricating a bottom-gate low-temperature polysilicon thin film transistor |
US8077230B2 (en) * | 2008-06-18 | 2011-12-13 | Aptina Imaging Corporation | Methods and apparatus for reducing color material related defects in imagers |
JP2009200526A (ja) * | 2009-05-29 | 2009-09-03 | Sharp Corp | Soi基板およびそれを用いる表示装置 |
JP2011040594A (ja) * | 2009-08-12 | 2011-02-24 | Seiko Epson Corp | 薄膜トランジスターの製造方法 |
JP5564879B2 (ja) * | 2009-10-01 | 2014-08-06 | 三菱電機株式会社 | 非晶質半導体膜の結晶化方法、並びに薄膜トランジスタ、半導体装置、表示装置、及びその製造方法 |
RU2431215C1 (ru) * | 2010-06-02 | 2011-10-10 | Учреждение Российской академии наук Институт физики полупроводников им. А.В. Ржанова Сибирского отделения РАН (ИФП СО РАН) | Способ получения слоя поликристаллического кремния |
CN102629558B (zh) * | 2012-01-09 | 2015-05-20 | 深超光电(深圳)有限公司 | 低温多晶硅薄膜晶体管制造方法 |
JP5657069B2 (ja) * | 2013-07-16 | 2015-01-21 | 株式会社半導体エネルギー研究所 | 半導体装置 |
-
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RU2016124647A (ru) | 2017-12-26 |
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JP2017504965A (ja) | 2017-02-09 |
DE112013007720B4 (de) | 2020-03-12 |
GB2534771B (en) | 2018-11-28 |
US20150194310A1 (en) | 2015-07-09 |
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GB2534771A (en) | 2016-08-03 |
US9209025B2 (en) | 2015-12-08 |
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