CN103745916B - 定义多晶硅生长方向的方法 - Google Patents

定义多晶硅生长方向的方法 Download PDF

Info

Publication number
CN103745916B
CN103745916B CN201310747070.9A CN201310747070A CN103745916B CN 103745916 B CN103745916 B CN 103745916B CN 201310747070 A CN201310747070 A CN 201310747070A CN 103745916 B CN103745916 B CN 103745916B
Authority
CN
China
Prior art keywords
polycrystalline silicon
growth direction
amorphous silicon
silicon
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310747070.9A
Other languages
English (en)
Other versions
CN103745916A (zh
Inventor
余威
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201310747070.9A priority Critical patent/CN103745916B/zh
Priority to US14/348,873 priority patent/US9589796B2/en
Priority to PCT/CN2014/070963 priority patent/WO2015100817A1/zh
Publication of CN103745916A publication Critical patent/CN103745916A/zh
Application granted granted Critical
Publication of CN103745916B publication Critical patent/CN103745916B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02488Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02678Beam shaping, e.g. using a mask
    • H01L21/0268Shape of mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02422Non-crystalline insulating materials, e.g. glass, polymers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02483Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02502Layer structure consisting of two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02592Microstructure amorphous
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02595Microstructure polycrystalline
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02609Crystal orientation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02658Pretreatments
    • H01L21/02661In-situ cleaning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686Pulsed laser beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

本发明涉及定义多晶硅生长方向的方法。该定义多晶硅生长方向的方法包括:步骤1、在基板上形成缓冲层;步骤2、在该缓冲层上形成非晶硅薄膜;步骤3、使该非晶硅薄膜表面形成规律的非晶硅凸起部;步骤4、经由准分子镭射退火使该非晶硅薄膜形成多晶硅。本发明定义多晶硅生长方向的方法能够控制多晶硅形成时的生长方向,进而可以提高多晶硅晶粒大小。

Description

定义多晶硅生长方向的方法
技术领域
本发明涉及液晶显示技术领域,尤其涉及一种定义多晶硅生长方向的方法。
背景技术
随着平板显示的发展,高分辨率,低能耗的面板需求不断被提出。不同于非晶硅电子迁移率低,低温多晶硅因可在低温下制作,具有高的电子迁移率及可制作C-MOS(Complementary Metal Oxide Semiconductor,互补金属氧化物半导体)电路而被广泛研究用以达到面板高分辨率,低能耗的需求。
低温多晶硅(Low Temperature Poly-Silicon,LTPS)是多晶硅技术的一个分支。对平板显示器来说,采用多晶硅液晶材料有许多优点,如薄膜电路可以做得更薄更小、功耗更低等。
在多晶硅技术发展的初期,为了将玻璃基板从非晶硅结构(a-Si)转变为多晶硅结构,就必须借助一道镭射退火(Laser Anneal)的高温氧化工序,此时玻璃基板的温度将超过摄氏1000度。与传统的高温多晶硅相比,低温多晶硅虽然也需要激光照射工序,但它采用的是准分子激光作为热源,激光经过透射系统后,会产生能量均匀分布的激光束并被投射于非晶硅结构的玻璃基板上,当非晶硅结构的玻璃基板吸收准分子激光的能量后,就会转变成为多晶硅结构。由于整个处理过程是在摄氏500-600度以下完成,普通的玻璃基板也可承受,这就大大降低了制造成本。而除了制造成本降低外,低温多晶硅技术的优点还体现在:电子迁移速率更快;薄膜电路面积更小;更高的分辨率;结构简单、稳定性更高。
目前制作低温多晶硅的方法包括固相结晶(SPC),金属诱导结晶(MIC)和准分子镭射退火(ELA)几种,其中准分子镭射退火(ELA)是目前使用最为广泛的方法。
ELA制作低温多晶硅的方法是在玻璃上生长一缓冲层,然后生长非晶硅,高温去氢后经过HF预清洗,再利用ELA的镭射扫描非晶硅,非晶硅受到高温熔化重结晶形成多晶硅。
低温多晶硅晶粒的大小(Grain size)对多晶硅的电学性能有重要影响,在ELA制程中,非晶硅受到高温后变成完全熔融(nearly completely melts)状态,然后重结晶形成多晶硅。重结晶时会按照低能量向高能量方向结晶,低温向高温方向结晶;所以结晶的起点和方向是凌乱的,导致晶粒偏小,晶粒间晶界(Grain boundary)偏多,就会影响多晶硅的电子迁移率。
发明内容
因此,本发明的目的在于提供一种定义多晶硅生长方向的方法,能够控制多晶硅形成时的生长方向。
为实现上述目的,本发明提供了一种定义多晶硅生长方向的方法,其包括:
步骤1、在基板上形成缓冲层;
步骤2、在该缓冲层上形成非晶硅薄膜;
步骤3、使该非晶硅薄膜表面形成规律的非晶硅凸起部;
步骤4、经由准分子镭射退火使该非晶硅薄膜形成多晶硅。
其中,该步骤3包括:
步骤3.1、根据欲形成的非晶硅凸起部光刻该非晶硅薄膜;
步骤3.2、干法蚀刻该非晶硅薄膜;
步骤3.3、剥离光阻。
其中,该步骤4中进行准分子镭射退火前,对该非晶硅薄膜进行高温去氢和HF预清洗处理。
其中,该缓冲层的材料为氮化硅或二氧化硅。
其中,该基板为玻璃。
其中,根据所欲定义的该步骤4中所形成的多晶硅的生长方向来预先设置所述非晶硅凸起部在该非晶硅薄膜表面的分布。
其中,该缓冲层和非晶硅薄膜分别经由化学气相沉积法形成。
其中,在该基板和该缓冲层之间还形成有绝缘层。
其中,该绝缘层的材料为氮化铝,氮化硼,氧化铝或氧化镁。
其中,该绝缘层通过磁控溅射或化学气相沉积法形成。
本发明定义多晶硅生长方向的方法能够控制多晶硅形成时的生长方向,进而可以提高多晶硅晶粒大小。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其他有益效果显而易见。
附图中,
图1为本发明定义多晶硅生长方向的方法的流程图;
图2为按照本发明定义多晶硅生长方向的方法形成非晶硅薄膜的截面图;
图3为按照本发明定义多晶硅生长方向的方法刻蚀后的非晶硅薄膜截面图;
图4为按照本发明定义多晶硅生长方向的方法进行准分子镭射退火制程时非晶硅薄膜的截面图;
图5为按照本发明定义多晶硅生长方向的方法在非晶硅薄膜中籽晶控制多晶硅生长方向的截面图。
具体实施方式
参见图1,其为本发明定义多晶硅生长方向的方法的流程图。结合图2至图5所示的按照本发明定义多晶硅生长方向的方法生长多晶硅的一较佳实施例,本发明的定义多晶硅生长方向的方法主要包括:
步骤1、在基板10上形成缓冲层20;该基板10可以为玻璃或者其它适合的透明材料。
步骤2、在该缓冲层20上形成非晶硅薄膜30;该缓冲层20的材料可以为氮化硅或二氧化硅,或者其它适合的材料。
参见图2,其为按照本发明定义多晶硅生长方向的方法形成非晶硅薄膜的截面图,基板10上生长一缓冲层20,然后再生长非晶硅薄膜30,该缓冲层20和非晶硅薄膜30可以分别经由化学气相沉积法形成,也可以通过其它适合的制程来制作。
步骤3、使该非晶硅薄膜30表面形成规律的非晶硅凸起部40。该步骤3可以包括:
步骤3.1、根据欲形成的非晶硅凸起部40光刻(photo)该非晶硅薄膜30;
步骤3.2、干法蚀刻(dry etching)该非晶硅薄膜30;
步骤3.3、剥离(stripper)光阻。
参见图3,其为按照本发明定义多晶硅生长方向的方法刻蚀后的非晶硅薄膜截面图。通过一次光刻(photo)+干法蚀刻(dry etching)+剥离(stripper)的制程在非晶硅薄膜30上形成多个规律的凸起部40,也就是通过干法刻蚀工艺刻蚀掉一部分非晶硅薄膜30,则凸起部40即形成。
具体方式可为,在非晶硅薄膜30上覆一层感光材料,该层即所谓的光致抗蚀剂层,然后使光线通过掩膜照射于光致抗蚀剂层上使其曝光。由于掩膜上具有对应于非晶硅凸起部40的图案,使得部分光线得以穿过掩膜而照射于光致抗蚀剂层上,使得光致抗蚀剂层的曝光具有选择性,借此将掩膜上的图案复印纸光致抗蚀剂层上。然后,利用合适的显影液除去部分光致抗蚀剂,使得光致抗蚀剂层显现所需要的图案。接着通过干法蚀刻将部分非晶硅薄膜30去除。最后,将剩余的图案化的光致抗蚀剂层全部去除。
步骤4、经由准分子镭射退火使该非晶硅薄膜30形成多晶硅。该步骤4中进行准分子镭射退火前,可以对该非晶硅薄膜30进行高温去氢和HF预清洗处理。
参见图4及图5,图4为按照本发明定义多晶硅生长方向的方法进行准分子镭射退火制程时非晶硅薄的截面图,图5为在非晶硅薄膜中籽晶控制多晶硅生长方向的截面图。利用激光扫描进行准分子镭射退火的过程中,非晶硅薄膜30受到高温,薄区的非晶硅薄膜30变成完全熔融(nearly completely melts)状态,非晶硅凸起部40因厚度偏厚,所以处于部分熔融状态,能量偏低,非晶硅凸起部40未熔融的非晶硅则会如图5所示作为多晶硅生长的籽晶控制多晶硅向四周生长形成,从而实现控制多晶硅生长方向的目的,进而可以提高多晶硅晶粒大小。
本发明通过在非晶硅薄膜30中形成籽晶,则多晶硅形成时即会以籽晶为起点开始生长变大,从而可控制多晶硅形成时的生长方向,进而可以提高多晶硅晶粒大小。生长多晶硅前,可以根据所欲定义的所形成的多晶硅的生长方向来预先设置非晶硅凸起部40在该非晶硅薄膜30表面的分布,例如,非晶硅凸起部40可以设置为以相同的形状在非晶硅薄膜30表面均匀分布。换句话说,可以通过改变非晶硅凸起部40的形状和位置等条件来改变多晶硅形成时的生长方向。
而且,在该基板10和该缓冲层20之间还可以形成有绝缘层。该绝缘层的材料可以为氮化铝,氮化硼,氧化铝或氧化镁,或者其它适合的材料。该绝缘层可以通过磁控溅射或化学气相沉积法或其它适合的制程形成。进而,本发明的定义多晶硅生长方向的方法可以应用于薄膜晶体管,阵列基板,平板显示装置等的制备。
综上所述,本发明定义多晶硅生长方向的方法能够控制多晶硅形成时的生长方向,进而可以提高多晶硅晶粒大小。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (8)

1.一种定义多晶硅生长方向的方法,其特征在于,包括:
步骤1、在基板上形成缓冲层;
步骤2、在该缓冲层上形成非晶硅薄膜;
步骤3、使该非晶硅薄膜表面形成多个规律的非晶硅凸起部;
步骤4、经由准分子镭射退火使该非晶硅薄膜形成多晶硅;
利用激光扫描进行准分子镭射退火的过程中,非晶硅薄膜受到高温,薄区的非晶硅薄膜变成完全熔融状态,非晶硅凸起部因厚度偏厚,所以处于部分熔融状态,能量偏低,非晶硅凸起部未熔融的非晶硅则作为多晶硅生长的籽晶控制多晶硅向四周生长;
该步骤3包括:
步骤3.1、根据欲形成的非晶硅凸起部光刻该非晶硅薄膜;
步骤3.2、干法蚀刻该非晶硅薄膜;
步骤3.3、剥离光阻;
根据所欲定义的该步骤4中所形成的多晶硅的生长方向来预先设置所述非晶硅凸起部在该非晶硅薄膜表面的分布,通过改变非晶硅凸起部的形状和位置条件来改变多晶硅形成时的生长方向。
2.如权利要求1所述的定义多晶硅生长方向的方法,其特征在于,该步骤4中进行准分子镭射退火前,对该非晶硅薄膜进行高温去氢和HF预清洗处理。
3.如权利要求1所述的定义多晶硅生长方向的方法,其特征在于,该缓冲层的材料为氮化硅或二氧化硅。
4.如权利要求1所述的定义多晶硅生长方向的方法,其特征在于,该基板为玻璃。
5.如权利要求1所述的定义多晶硅生长方向的方法,其特征在于,该缓冲层和非晶硅薄膜分别经由化学气相沉积法形成。
6.如权利要求1所述的定义多晶硅生长方向的方法,其特征在于,在该基板和该缓冲层之间还形成有绝缘层。
7.如权利要求6所述的定义多晶硅生长方向的方法,其特征在于,该绝缘层的材料为氮化铝,氮化硼,氧化铝或氧化镁。
8.如权利要求6所述的定义多晶硅生长方向的方法,其特征在于,该绝缘层通过磁控溅射或化学气相沉积法形成。
CN201310747070.9A 2013-12-30 2013-12-30 定义多晶硅生长方向的方法 Active CN103745916B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201310747070.9A CN103745916B (zh) 2013-12-30 2013-12-30 定义多晶硅生长方向的方法
US14/348,873 US9589796B2 (en) 2013-12-30 2014-01-21 Method of defining poly-silicon growth direction
PCT/CN2014/070963 WO2015100817A1 (zh) 2013-12-30 2014-01-21 定义多晶硅生长方向的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310747070.9A CN103745916B (zh) 2013-12-30 2013-12-30 定义多晶硅生长方向的方法

Publications (2)

Publication Number Publication Date
CN103745916A CN103745916A (zh) 2014-04-23
CN103745916B true CN103745916B (zh) 2017-07-28

Family

ID=50502927

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310747070.9A Active CN103745916B (zh) 2013-12-30 2013-12-30 定义多晶硅生长方向的方法

Country Status (3)

Country Link
US (1) US9589796B2 (zh)
CN (1) CN103745916B (zh)
WO (1) WO2015100817A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104064451A (zh) * 2014-07-10 2014-09-24 深圳市华星光电技术有限公司 低温多晶硅的制作方法及使用该方法的tft基板的制作方法与tft基板结构
CN105097669B (zh) * 2015-07-13 2019-05-03 深圳市华星光电技术有限公司 一种显示面板及其制造方法
CN105088336B (zh) * 2015-07-24 2018-05-18 深圳市华星光电技术有限公司 一种多晶硅制备装置及方法
CN110875171A (zh) * 2018-08-31 2020-03-10 北京北方华创微电子装备有限公司 多晶硅功能层的制备方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6432758B1 (en) * 2000-08-09 2002-08-13 Huang-Chung Cheng Recrystallization method of polysilicon film in thin film transistor

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100291971B1 (ko) * 1993-10-26 2001-10-24 야마자끼 순페이 기판처리장치및방법과박막반도체디바이스제조방법
US7294535B1 (en) * 1998-07-15 2007-11-13 Semiconductor Energy Laboratory Co., Ltd. Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same
US6933527B2 (en) * 2001-12-28 2005-08-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor device production system
US7235466B2 (en) * 2002-10-31 2007-06-26 Au Optronics Corporation Method of fabricating a polysilicon layer
CN1307690C (zh) 2002-11-12 2007-03-28 友达光电股份有限公司 多晶硅层的制作方法
WO2005001921A1 (ja) * 2003-06-27 2005-01-06 Nec Corporation 薄膜トランジスタ、薄膜トランジスタ基板、電子機器及び多結晶半導体薄膜の製造方法
CN1300825C (zh) * 2004-07-21 2007-02-14 友达光电股份有限公司 制造多晶硅层的方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6432758B1 (en) * 2000-08-09 2002-08-13 Huang-Chung Cheng Recrystallization method of polysilicon film in thin film transistor

Also Published As

Publication number Publication date
US9589796B2 (en) 2017-03-07
WO2015100817A1 (zh) 2015-07-09
US20150249006A1 (en) 2015-09-03
CN103745916A (zh) 2014-04-23

Similar Documents

Publication Publication Date Title
TWI310059B (en) Method for fabricating single crystal silicon film
US20160351602A1 (en) Low temperature polycrystalline silicon thin film and method of producing the same, array substrate and display apparatus
US20070065998A1 (en) Polysilicon thin film fabrication method
CN103745916B (zh) 定义多晶硅生长方向的方法
JP2005117001A (ja) ポリシリコン薄膜トランジスタの製造方法
WO2015096174A1 (zh) 低温多晶硅薄膜及其制备方法、晶体管
WO2014139291A1 (zh) 多晶硅层的制作方法和多晶硅薄膜晶体管及其制造方法
WO2015188594A1 (zh) 多晶硅层及显示基板的制备方法、显示基板
TWI302997B (en) Method of fabricating tft array substrate
JP2004214615A (ja) 非晶質シリコン膜の結晶化方法及び非晶質シリコンの結晶化用マスク、並びにアレイ基板の製造方法
JP2004349699A (ja) 多結晶シリコンの製造方法及びこれを利用したスイッチング素子
WO2015131495A1 (zh) 薄膜晶体管及其制备方法、阵列基板及其制备方法、显示装置
CN103730336B (zh) 定义多晶硅生长方向的方法
JP4784955B2 (ja) 薄膜半導体装置の製造方法
JP2009081433A (ja) 結晶化方法および活性半導体膜構造体
US20160240377A1 (en) Method of defining poly-silicon growth direction
WO2015192558A1 (zh) 低温多晶硅薄膜晶体管、其制备方法及阵列基板与显示装置
CN101414564A (zh) 低温多晶硅薄膜晶体管的制造方法
WO2018145515A1 (zh) 薄膜晶体管及其制作方法、显示基板和显示装置
TW200426950A (en) Laser re-crystallization method of low temperature polysilicon thin film transistor
KR100660814B1 (ko) 박막트랜지스터의 반도체층 형성방법
WO2016138715A1 (zh) 低温多晶硅薄膜及薄膜晶体管的制备方法、薄膜晶体管、显示面板及显示装置
CN106783532B (zh) 一种低温多晶硅薄膜的制备方法、薄膜晶体管、阵列基板以及液晶显示面板
WO2019205569A1 (zh) 多晶硅层及其制造方法、薄膜晶体管及阵列基板的制造方法
JPH0629212A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant