WO2015089826A1 - 半导体器件和制备半导体器件的方法 - Google Patents

半导体器件和制备半导体器件的方法 Download PDF

Info

Publication number
WO2015089826A1
WO2015089826A1 PCT/CN2013/090099 CN2013090099W WO2015089826A1 WO 2015089826 A1 WO2015089826 A1 WO 2015089826A1 CN 2013090099 W CN2013090099 W CN 2013090099W WO 2015089826 A1 WO2015089826 A1 WO 2015089826A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
dielectric layer
silicon
semiconductor
semiconductor device
Prior art date
Application number
PCT/CN2013/090099
Other languages
English (en)
French (fr)
Inventor
皇甫幼睿
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to KR1020167017473A priority Critical patent/KR20160089519A/ko
Priority to EP13899857.0A priority patent/EP3070751A4/en
Priority to CN201380004030.3A priority patent/CN105264674B/zh
Priority to JP2016541187A priority patent/JP2017511596A/ja
Priority to CN201811378239.7A priority patent/CN109860022B/zh
Priority to PCT/CN2013/090099 priority patent/WO2015089826A1/zh
Priority to EP18160118.8A priority patent/EP3428957B1/en
Publication of WO2015089826A1 publication Critical patent/WO2015089826A1/zh
Priority to US15/186,681 priority patent/US20160291248A1/en
Priority to US15/975,496 priority patent/US10234629B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0232—Optical elements or arrangements associated with the device
    • H01L31/02325—Optical elements or arrangements associated with the device the optical elements not being integrated nor being directly associated with the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/103—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN homojunction type
    • H01L31/1035—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN homojunction type the devices comprising active layers formed only by AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/021—Silicon based substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0218—Substrates comprising semiconducting materials from different groups of the periodic system than the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0225—Out-coupling of light
    • H01S5/02257—Out-coupling of light using windows, e.g. specially adapted for back-reflecting light to a detector inside the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/3013—AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12083—Constructional arrangements
    • G02B2006/12123—Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers

Definitions

  • the present invention relates to the field of information technology and, more particularly, to semiconductor devices and methods of fabricating semiconductor devices. Background technique
  • Silicon is the cornerstone of microelectronics platforms and is also indispensable for optoelectronic integration. It has the advantages of high integration and low cost. Its oxides are excellent insulating materials, and their high refractive index difference makes them available. Conduct light guide.
  • silicon is an indirect bandgap semiconductor, and the efficiency of light absorption and emission is low, and the carrier mobility of silicon is not high, which is limited in high-speed applications.
  • III-V compound semiconductors have a direct band gap structure and high electron mobility, and their low-dimensional systems such as multiple quantum wells, quantum dots, etc. also bring excellent performance to optical gain, and adjustment of material composition.
  • the optimization of the low-dimensional structure brings various changes to the performance parameters of the device, and can be used to prepare electronic devices such as lasers, solar cells, and the like, and high electron mobility transistors.
  • a monolithic integration technique for fabricating m-v semiconductor devices is to epitaxially grow m-v materials on a silicon substrate to prepare devices.
  • mv family materials such as gallium arsenide, indium phosphide, etc. and silicon
  • direct growth of mv-type materials on silicon introduces high-density line dislocations, resulting in Device performance is degraded and reliability is reduced.
  • Embodiments of the present invention provide a semiconductor device and a method of fabricating the same, which are capable of providing an m-v semiconductor device free of line dislocations.
  • a semiconductor device comprising:
  • First silicon layer a first dielectric layer, the first dielectric layer is located above the first silicon layer, the first dielectric layer has a window, the horizontal dimension of the bottom of the window of the first dielectric layer does not exceed 20 nm;
  • An m-v semiconductor layer is distributed over the first dielectric layer and deep into the window of the first dielectric layer, and is connected to the first silicon layer in a window of the first dielectric layer.
  • the window of the first dielectric layer is inverted or cylindrical.
  • the first silicon layer is a silicon substrate
  • the semiconductor device further includes:
  • the second silicon layer includes a waveguide, the second silicon layer is located above the first dielectric layer, and a portion of the first dielectric layer between the second silicon layer and the first silicon layer has no window,
  • the second silicon layer is directly or indirectly connected to the mv semiconductor layer.
  • the first silicon layer includes a waveguide, and a window of the first dielectric layer is located above the waveguide;
  • the semiconductor device also includes:
  • the third silicon layer is a silicon substrate, and the second dielectric layer is located below the first silicon layer, above the third silicon layer.
  • the semiconductor device is a laser
  • the m-v semiconductor layer includes a buffer layer, an active region, a spacer layer, an N-type doped transition layer, and a P-type doped transition layer;
  • the semiconductor device further includes an N electrode and a P electrode, the N electrode being connected to the N-type doped transition layer, the P electrode being connected to the P-type doped transition layer.
  • the semiconductor device is an optical amplifier;
  • the semiconductor layer includes a buffer layer, an active region, a spacer layer, an N-type doped transition layer, and a P-type doped transition layer;
  • the semiconductor device further includes an N electrode, a P electrode, and an anti-reflection film, the N electrode being connected to the N-type doped transition layer, the p electrode being connected to the p-type doped transition layer, the anti-reflection film being located in the mv-type semiconductor The end face of the layer.
  • the semiconductor device is a photodetector;
  • the mv semiconductor layer includes an N region, a p region, and an intrinsic region;
  • the semiconductor device further includes an N electrode and a P electrode, the N electrode being connected to the N region, the P electrode being connected to the P region.
  • the semiconductor device is a transistor
  • the m-v semiconductor layer is a channel material of the transistor
  • the semiconductor device further includes a source, a drain, a gate, and a gate dielectric layer, the source, the drain, and the gate dielectric layer being coupled to the m-v semiconductor layer, the gate being coupled to the gate dielectric layer.
  • a method of fabricating a semiconductor device comprising:
  • the silicon layer of the SOI is etched by using a graphic template as a mask.
  • the SOI includes a silicon substrate, a dielectric layer on the silicon substrate, and a silicon layer on the dielectric layer. When the dielectric layer is exposed, the etching is stopped, and the pattern is removed. Template, obtaining a silicon layer with a window;
  • the dielectric layer is etched by using a silicon layer having a window as a template.
  • the etching is stopped, and the silicon layer having the window is removed to obtain a dielectric layer having a window, wherein the bottom of the window of the dielectric layer is laterally
  • the size does not exceed 20nm;
  • a semiconductor material is grown in the window of the dielectric layer to form a buffer layer, and the semiconductor material is grown on the buffer layer to obtain a semiconductor layer.
  • the graphic template is a porous alumina film or a photoresist after extreme ultraviolet exposure development.
  • the semiconductor material is a m-v semiconductor material.
  • the semiconductor material comprises a predetermined amount of dopant material.
  • the silicon layer of the SOI is patterned by using the graphic template as a mask Before performing the etching, the method further includes:
  • the photoresist is blocked on a portion of the pattern template so that the silicon layer under the occlusion region is not etched.
  • the method further includes: The waveguide is prepared in a silicon layer that is not etched.
  • a method of fabricating a semiconductor device comprising:
  • the SOI comprises a silicon substrate, a first dielectric layer on the silicon substrate and a silicon layer on the first dielectric layer;
  • the second dielectric layer is etched by using the graphic template as a mask.
  • the etching is stopped, and the graphic template is removed to obtain a second dielectric layer having a window, wherein the bottom of the window of the second dielectric layer is laterally
  • the size does not exceed 20nm;
  • a semiconductor material is grown in the window of the second dielectric layer to form a buffer layer, and the semiconductor material is continuously grown on the buffer layer to obtain a semiconductor layer.
  • the graphic template is a porous alumina film or a photoresist after extreme ultraviolet exposure development.
  • the semiconductor material is a m-v semiconductor material.
  • the semiconductor material comprises a predetermined amount of dopant material.
  • the waveguide is fabricated in a silicon layer of silicon SOI on the insulator , including:
  • a ridge waveguide is prepared in the silicon layer.
  • the method before the second dielectric layer is etched by using the graphic template as a mask, the method further includes:
  • a photoresist is masked over a portion of the pattern template, wherein the region where the photoresist is not blocked corresponds to the position of the ridge waveguide.
  • the semiconductor device of the embodiment of the present invention employs a group III-V semiconductor material, and the m-v group semiconductor material in the semiconductor device of the embodiment of the invention has no line dislocations and thus has high performance.
  • FIG. 1 is a schematic structural view of a semiconductor device in accordance with one embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a semiconductor device in accordance with another embodiment of the present invention.
  • FIG 3 is a schematic structural view of a laser according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of an optical amplifier according to an embodiment of the present invention.
  • Figure 5 is a block diagram showing the structure of a detector in accordance with one embodiment of the present invention.
  • FIG. 6 is a schematic structural view of a probe according to another embodiment of the present invention.
  • Figure 7 is a block diagram showing the structure of a transistor in accordance with one embodiment of the present invention.
  • Figure 8 is a block diagram showing the integration of a transistor on a single chip in accordance with one embodiment of the present invention.
  • 9 is a schematic structural view of a semiconductor device in accordance with another embodiment of the present invention.
  • FIG. 10 is a schematic structural view of a laser according to another embodiment of the present invention.
  • FIG. 11 is a schematic structural view of an optical amplifier according to another embodiment of the present invention.
  • Figure 12 is a block diagram showing the structure of a detector in accordance with another embodiment of the present invention.
  • Figure 13 is a schematic view showing the structure of a detector according to another embodiment of the present invention.
  • Figure 14 is a schematic flow diagram of a method of fabricating a semiconductor device in accordance with one embodiment of the present invention.
  • Figure 15 is a schematic illustration of a semiconductor device at various stages of a method of fabricating a semiconductor device in accordance with one embodiment of the present invention.
  • Figure 16 is a schematic flow chart of a method of fabricating a semiconductor device in accordance with another embodiment of the present invention.
  • Figure 17 is a schematic illustration of a semiconductor device at various stages of a method of fabricating a semiconductor device in accordance with another embodiment of the present invention.
  • FIG. 1 shows a schematic structural view of a semiconductor device 100 in accordance with one embodiment of the present invention.
  • the semiconductor device loo includes a first silicon layer no, a first dielectric layer 120 and an mv semiconductor layer 130.
  • the first silicon layer 110 is a silicon substrate.
  • the first dielectric layer 120 is over the first silicon layer 110.
  • the material of the first dielectric layer 120 may be silicon oxide or silicon nitride or a mixture thereof.
  • the first dielectric layer 120 has a window 121, and the lateral dimension of the bottom of the window 121 does not exceed 20 nm.
  • the number of the windows 121 is not limited and may vary depending on the size of the semiconductor device 100.
  • the III-V semiconductor layer 130 is distributed over the first dielectric layer 120 and penetrates into the window 121 of the first dielectric layer 120.
  • the III-V semiconductor layer 130 is connected to the first silicon layer 110 in the window 121 of the first dielectric layer 120.
  • the III-V semiconductor layer 130 can be obtained by first growing a m-v semiconductor material in the window 121 and continuing to grow the m-v semiconductor material over the first dielectric layer 120.
  • the m-v semiconductor material may include one or more of the following:
  • Aluminum phosphide ( ⁇ 1 ⁇ ), gallium phosphide (GaP), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), indium arsenide (InAs), aluminum telluride (AlSb), germanium Gallium (GaSb), indium antimonide (InSb), aluminum nitride (A1N), gallium nitride (GaN), indium nitride (InN), and their ternary and quaternary compounds.
  • the lateral dimension of the bottom of the window 121 of the first dielectric layer 120 does not exceed 20 nm, that is, the size of the contact surface of the III-V semiconductor layer 130 and the first silicon layer 110 is not in any direction. More than 20 nm, such that the III-V semiconductor material in the window 121 (i.e., the mv semiconductor material at the contact surface) has no line dislocations. That is, the semiconductor device of the embodiment of the present invention is an m-v semiconductor device having no line dislocations. Since the m-v group semiconductor material has a direct band gap structure and a high electron mobility, the semiconductor device performance can be improved, and therefore, the semiconductor device of the embodiment of the present invention has high crystal quality and device performance.
  • the semiconductor device of the embodiment of the present invention employs a m-v group semiconductor material, and the m-v group semiconductor material has no line dislocations and thus has high performance.
  • the window 121 of the first dielectric layer 120 may be inverted or cylindrical.
  • the embodiment of the present invention only defines that the lateral dimension of the bottom of the window 121 does not exceed 20 nm, and does not limit the shape of the window 121, that is, it may be other shapes.
  • the semiconductor device 100 optionally, as shown in FIG. 2, the semiconductor device 100 further includes: a second silicon layer 140.
  • the second silicon layer 140 is over the first dielectric layer 120, and the portion of the first dielectric layer 120 between the second silicon layer 140 and the first silicon layer 110 has no window. That is, the second silicon layer 140 is located above the windowless portion of the first dielectric layer 120.
  • the second silicon layer 140 is directly or indirectly connected to the III-V semiconductor layer 130.
  • the second silicon layer 140 includes a waveguide through which light output from the III-V semiconductor layer 130 can be coupled.
  • the semiconductor device 100 may further include a filling layer 150.
  • the filling layer 150 is used to fill the gap between the III-V semiconductor layer 130 and the second silicon layer 140.
  • it may be filled with a material such as amorphous silicon.
  • the semiconductor device 100 of the embodiment of the present invention may specifically be a laser, an optical amplifier, a photodetector, a transistor or a solar cell or the like.
  • FIG. 3 is a schematic structural view of a laser according to an embodiment of the present invention.
  • the semiconductor device 100 is a laser.
  • the III-V semiconductor layer 130 constitutes a main structure of the laser, and includes a buffer layer 131, an active region 134, a spacer 133, an N-type doped transition layer 132, and a P-type doped transition layer 135.
  • the III-V semiconductor material in the window 121 forms a buffer layer 131, and the semiconductor material in the buffer layer 131 has no line dislocations.
  • the laser light is generated and amplified in the active region 134.
  • Active region 134 may comprise multiple quantum wells or quantum dots to enhance optical gain.
  • the semiconductor device 100 further includes an N electrode 160 and a P electrode 170.
  • the N electrode 160 is connected to the N-type doped transition layer 132
  • the P electrode 170 is connected to the P-type doped transition layer 135.
  • a grating structure may also be included.
  • Light output from the main structure of the laser is coupled into the waveguide in the second silicon layer 140.
  • the laser in this embodiment uses the III-V semiconductor material to form the main structure of the laser, and the III-V semiconductor material has no line dislocations and thus has high performance.
  • FIG. 4 is a schematic structural view of an optical amplifier according to an embodiment of the present invention.
  • the semiconductor device 100 is an optical amplifier, also referred to as a Semiconductor Optical Amplifier (SOA).
  • SOA Semiconductor Optical Amplifier
  • the mv-type semiconductor layer 130 constitutes the main body of the optical amplifier.
  • the bulk structure includes a buffer layer 131, an active region 134, a spacer layer 133, an N-type doped transition layer 132, and a P-type doped transition layer 135.
  • the III-V semiconductor material in the window 121 forms a buffer layer 131, and the semiconductor material in the buffer layer 131 has no line dislocations.
  • the active region 134 may comprise bulk materials, multiple quantum wells, quantum dots or quantum stubs, and the like.
  • the semiconductor device 100 further includes an N electrode 160, a P electrode 170, and an anti-reflection film 180.
  • the N electrode 160 is connected to the N-type doped transition layer 132
  • the P electrode 170 is connected to the P-type doped transition layer 135.
  • the anti-reflection film 180 is located on the end face of the III-V semiconductor layer 130, and the anti-reflection film is also referred to as an anti-reflection film.
  • the main structure of the optical amplifier is formed using the m-v semiconductor material, and the m-v semiconductor material has no line dislocations and thus has high performance.
  • 5 and 6 are schematic structural views of a photodetector according to an embodiment of the present invention.
  • the semiconductor device 100 is a photodetector.
  • the III-V semiconductor layer 130 includes an N region 136, a P region 137, and an intrinsic region 138.
  • N region 136 and P region 137 are doped regions.
  • N-zone 136 and P-zone 137 may be vertically distributed (as shown in Figure 5) or distributed on the surface of the device (as shown in Figure 6).
  • the semiconductor device 100 further includes an N electrode 160 and a P electrode 170.
  • the 136 is connected, and the P electrode 170 is connected to the P zone 137.
  • Light is coupled into the detector from the waveguide in the second silicon layer 140 to be detected.
  • the photodetector in this embodiment employs a m-v group semiconductor material, and the m-v group semiconductor material has no line dislocations and thus has high performance.
  • FIG. 7 is a schematic structural view of a transistor according to an embodiment of the present invention.
  • the semiconductor device 100 is a transistor.
  • the III-V semiconductor layer 130 is a channel material of a transistor, that is, the transistor of the embodiment of the present invention is an m-v semiconductor transistor. Quantum wells or quantum dots can be included in the channel material.
  • the semiconductor device 100 further includes a source 181, a drain 182, a gate 183, and a gate dielectric layer 184.
  • the source 181, the drain 182, and the gate dielectric layer 184 are connected to the III-V semiconductor layer 130, and the gate 183 is connected to the gate dielectric layer 184.
  • the mv semiconductor transistor of the embodiment of the present invention can be monolithically integrated with the Si transistor, as shown in FIG.
  • a variety of transistors can be obtained by using different m-v semiconductor materials as the channel material.
  • a high electron mobility transistor HMT
  • a metal-semiconductor field effect transistor Metal-Semiconductor Field Effect Transistor
  • MESFET Metal-Semiconductor Field Effect Transistor
  • FinFET Fin Field Effect Transistor
  • MODFET Modulation Doped Field Effect Transistor
  • the transistor in this embodiment employs a m-v group semiconductor material, and the m-v group semiconductor material has no line dislocations and thus has high performance.
  • FIG. 9 is a block diagram showing the structure of a semiconductor device 200 in accordance with another embodiment of the present invention.
  • the semiconductor device 200 includes a first silicon layer 210, a first dielectric layer 220, and a III-V semiconductor layer 230.
  • the first dielectric layer 220 is located above the first silicon layer 210.
  • the material of the first dielectric layer 220 may be silicon oxide or silicon nitride or a mixture thereof.
  • the first dielectric layer 220 has a window 221, and the lateral dimension of the bottom of the window 221 does not exceed 20 nm.
  • the number of the windows 221 is not limited and may vary depending on the size of the semiconductor device 200.
  • the III-V semiconductor layer 230 is distributed over the first dielectric layer 220 and penetrates into the window 221 of the first dielectric layer 220.
  • the III-V semiconductor layer 230 is connected to the first silicon layer 210 in the window 221 of the first dielectric layer 220.
  • the III-V semiconductor layer 230 can be obtained by first growing a III-V semiconductor material in the window 221 and continuing to grow a III-V semiconductor material over the first dielectric layer 220.
  • the III-V semiconductor material may include one or more of the following:
  • Aluminum phosphide ( ⁇ 1 ⁇ ), gallium phosphide (GaP), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), indium arsenide (InAs), aluminum telluride (AlSb), germanium Gallium (GaSb), indium antimonide (InSb), aluminum nitride (A1N), gallium nitride (GaN), indium nitride (InN), and their ternary and quaternary compounds.
  • the first silicon layer 210 comprises a waveguide, such as a ridge waveguide.
  • the window 221 of the first dielectric layer 220 is located above the waveguide.
  • the semiconductor device 200 further includes:
  • the second dielectric layer 240 and the third silicon layer 250 are identical to the second dielectric layer 240 and the third silicon layer 250.
  • the third silicon layer 250 is a silicon substrate.
  • the second dielectric layer 240 is located below the first silicon layer 210 and above the third silicon layer 250.
  • the material of the second dielectric layer 240 is similar to the first dielectric layer 220 and may be silicon oxide or silicon nitride or a mixture thereof.
  • the lateral dimension of the bottom of the window 221 of the first dielectric layer 220 does not exceed 20 nm, that is, the size of the contact surface of the III-V semiconductor layer 230 and the first silicon layer 210 is not in any direction. More than 20 nm, such that the III-V semiconductor material in the window 221 (i.e., the III-V semiconductor material at the contact surface) has no line dislocations. That is, the semiconductor device of the embodiment of the present invention is an m-v semiconductor device having no line dislocations. Since the m-v group semiconductor material has a direct band gap structure and a high electron mobility, the semiconductor device performance can be improved, and therefore, the semiconductor device of the embodiment of the present invention has high crystal quality and device performance.
  • the window 221 of the first dielectric layer 220 may be an inverted cone or a cylinder.
  • the embodiment of the present invention only defines that the lateral dimension of the bottom of the window 221 is not more than 20 nm, and the shape of the window 221 is not limited, that is, it may be other shapes. Specifically, when the window 221 is inverted or cylindrical, the diameter of the bottom portion thereof does not exceed 20 nm; and when the window 221 has other shapes, the lateral dimension of the bottom portion does not exceed 20 nm in any direction.
  • the semiconductor device 200 of the embodiment of the present invention may specifically be a laser, an optical amplifier, a photodetector, a transistor or a solar cell or the like.
  • FIG. 10 is a schematic structural view of a laser according to another embodiment of the present invention.
  • the semiconductor device 200 is a laser.
  • the III-V semiconductor layer 230 constitutes a main structure of the laser, and includes a buffer layer 231, an active region 234, a spacer 233, an N-type doped transition layer 232, and a P-type doped transition layer 235.
  • the III-V semiconductor material in the window 221 forms a buffer layer 231, and the semiconductor material in the buffer layer 231 has no line dislocations.
  • the light of the laser is generated and amplified in the active region 234.
  • Active region 234 may comprise multiple quantum wells or quantum dots to enhance optical gain.
  • the semiconductor device 200 further includes an N electrode 260 and a P electrode 270.
  • the N electrode 260 is connected to the N-type doped transition layer 232
  • the P electrode 270 is connected to the P-type doped transition layer 235.
  • a grating structure may also be included.
  • Light output from the main structure of the laser is coupled into the waveguide in the first silicon layer 210.
  • the laser in this embodiment uses a mv group semiconductor material to form a main structure of the laser. Moreover, the i ⁇ - ⁇ semiconductor materials have no line dislocations and therefore have high performance.
  • FIG. 11 is a schematic structural diagram of an optical amplifier according to another embodiment of the present invention.
  • the semiconductor device 200 is an optical amplifier, also referred to as a semiconductor optical amplifier SOA.
  • the ⁇ -V semiconductor layer 230 constitutes a main structure of the optical amplifier, and includes a buffer layer 231, an active region 234, a spacer 233, a erbium-doped transition layer 232, and a erbium-doped transition layer 235.
  • the III-V semiconductor material in the window 221 forms a buffer layer 231, and the semiconductor material in the buffer layer 231 has no line dislocations.
  • the active region 234 may comprise bulk material, multiple quantum wells, quantum dots or quantum stubs, and the like.
  • the semiconductor device 200 further includes an N electrode 260 and a P electrode 270.
  • the N electrode 260 is connected to the N-type doped transition layer 232
  • the P electrode 270 is connected to the P-type doped transition layer 235.
  • An antireflection film is also included, which is located on the end face of the III-V semiconductor layer.
  • the main structure of the optical amplifier is formed using the m-v semiconductor material, and the m-v semiconductor material has no line dislocations and thus has high performance.
  • FIGS. 12 and 13 are schematic structural views of a photodetector according to another embodiment of the present invention.
  • the semiconductor device 200 is a photodetector.
  • the III-V semiconductor layer 230 includes an N region 236, a P region 237, and an intrinsic region 238.
  • N region 236 and P region 237 are doped regions.
  • N-zone 236 and P-zone 237 may be vertically distributed (as shown in Figure 12) or distributed on the surface of the device (as shown in Figure 13).
  • the semiconductor device 200 further includes an N electrode 260 and a P electrode 270.
  • the N electrode 260 is connected to the N region 236, and the P electrode 270 is connected to the P region 237.
  • Light is coupled into the detector from a waveguide in the first silicon layer 210 to be detected.
  • the photodetector in this embodiment employs a m-v group semiconductor material, and the m-v group semiconductor material has no line dislocations and thus has high performance.
  • the semiconductor device of the embodiment of the present invention has been described in detail above, and a method of manufacturing a semiconductor device of an embodiment of the present invention will be described in detail below.
  • Figure 14 shows a schematic flow diagram of a method 300 of fabricating a semiconductor device in accordance with one embodiment of the present invention.
  • the method 300 includes: S310, etching a silicon layer of SOI (Silicon On Insulator) by using a graphic template as a mask, the SOI includes a silicon substrate, a dielectric layer on the silicon substrate, and a silicon layer on the dielectric layer. When the dielectric layer is exposed, the etching is stopped, and the graphic template is removed to obtain a silicon layer having a window;
  • SOI Silicon On Insulator
  • the dielectric layer is etched by using a silicon layer having a window as a template, and when the silicon substrate is exposed, the etching is stopped, and the silicon layer having the window is removed to obtain a dielectric layer having a window, wherein the bottom of the window of the dielectric layer The lateral dimension does not exceed 20 nm;
  • the Silicon On Insulator includes a silicon substrate 410, a dielectric layer 420, and a silicon layer 440.
  • the thickness of dielectric layer 420 and silicon layer 440 can be selected to vary depending on the needs and applications of the device.
  • the silicon layer of the SOI is first etched using the pattern template 490.
  • the pattern template 490 is a porous aluminum oxide film or a photoresist after extreme ultraviolet exposure development. If a porous alumina film is used, the porous alumina film is directly attached to the silicon layer 440 of the SOI (as shown by a in Fig. 15). A thin oxide layer may be formed on the silicon layer 440 to facilitate subsequent removal of the porous aluminum oxide film. If the photoresist after development by extreme ultraviolet exposure is used, the photoresist is first coated on the silicon layer 440, and the photoresist is exposed by an extreme ultraviolet lithography source, and then developed to obtain a pattern template 490.
  • the photoresist may be masked over a portion of the pattern template 490 (shown as b in Figure 15) so that the silicon layer under the occlusion region is not etched.
  • the silicon layer 440 can be selectively etched by controlling the etch parameters without etching the dielectric layer 420 under the silicon layer 440. When the dielectric layer 420 is exposed, the etching is stopped.
  • a window 441 with a decreasing aperture is formed in the silicon layer 440, i.e., the top lateral dimension of the window 441 is larger than the bottom lateral dimension (shown as b in Figure 15).
  • the graphic template 490 is removed, resulting in a patterned silicon layer 440 having a window 441.
  • the removal method can be chemically applied.
  • the dielectric layer 420 is etched using the patterned silicon layer 440 having the window 441 as a template.
  • a window 421 is formed in the dielectric layer 420 (shown as c in Fig. 15). Due to the shadow effect, the lateral dimension of the bottom of the window 421 will be smaller than the top lateral dimension, that is, the dielectric layer 420 The horizontal dimension of the bottom of the window 421 is much smaller than the window size of the graphic template 490.
  • the unobstructed silicon layer is then removed (as indicated by d in Figure 15).
  • the semiconductor material is selectively grown in the window 421 of the dielectric layer 420, the buffer layer is formed first, and the semiconductor material is further grown on the buffer layer to obtain the semiconductor layer 430 (shown as e in Fig. 15).
  • the remaining portion of the silicon layer 440 is protected prior to growth of the semiconductor material, for example, by forming a dielectric protective layer 155 by silicon oxide or silicon nitride.
  • the semiconductor material is a III-V semiconductor material, for example, one or more of the following:
  • Chemical Vapor Deposition CVD
  • Atomic Layer Deposition ALD
  • CVD may include Metal-Organic Chemical Vapor Deposition (MOCVD).
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • UHVCVD Ultra High Vacuum Chemical Vapor Deposition
  • RPCVD reaction Reactive Plasma Chemical Vapor Deposition
  • the semiconductor material may also include a predetermined amount of dopant material to form a PN or PIN structure.
  • the grown semiconductor material can form an active region, and the active region can include structures such as multiple quantum wells or quantum dots.
  • the method 300 further includes:
  • the waveguide is prepared in a silicon layer that is not etched.
  • a waveguide is prepared in the remaining portion of the silicon layer 440.
  • the dielectric protective layer 155 it is also necessary to remove the dielectric protective layer 155 to fill the remaining voids to form the filling layer 150.
  • it may be filled with a material such as amorphous silicon.
  • the size of the window template is much smaller than the size of the graphic template, so you can control the window of the graphic template.
  • the port size forms a smaller window in the dielectric layer to achieve the condition of dislocation growth of different mv semiconductor materials.
  • the lateral dimension of the bottom of the window formed in the dielectric layer does not exceed 20 nm, and may be less than 10 nm, and may even not exceed 2 nm.
  • the lateral dimension does not exceed the window of 20 nm, and therefore, the III-V semiconductor material in the semiconductor device prepared by the method for fabricating the semiconductor device of the embodiment of the present invention has no line dislocations, and therefore, the method for fabricating the semiconductor device of the embodiment of the present invention It is possible to prepare semiconductor devices of higher performance.
  • the semiconductor device 100 and in particular, in conjunction with the specific structure of the laser, optical amplifier, photodetector or transistor given in the foregoing embodiments, a corresponding semiconductor device can be fabricated.
  • Figure 16 shows a schematic flow diagram of a method 400 of fabricating a semiconductor device in accordance with another embodiment of the present invention. As shown in Figure 16, the method 400 includes:
  • S410 preparing a waveguide in a silicon layer of the SOI, wherein the SOI comprises a silicon substrate, a first dielectric layer on the silicon substrate and a silicon layer on the first dielectric layer;
  • the SOI includes a silicon substrate 510, a first dielectric layer 520, and a silicon layer 540.
  • a waveguide is prepared in the silicon layer 540 of the SOI, for example, a ridge waveguide is prepared, as shown by a in Fig. 17.
  • a second dielectric layer 550 is formed on the silicon layer 540 having a waveguide.
  • the pattern template 590 is a porous alumina film or a photoresist after extreme ultraviolet exposure development. Prior to etching, the photoresist may be masked over a portion of the pattern template 590, wherein the area not masking the photoresist corresponds to the position of the waveguide (as indicated by b in Figure 17).
  • the second dielectric layer 550 is etched to expose the silicon layer 540, and a window 551 is formed on the second dielectric layer 550 (shown as c in FIG. 17). Due to the shadow effect of the graphic template 590 on the etched beam, the bottom lateral dimension of the window 551 formed on the second dielectric layer 550 is smaller than the top lateral dimension, and thus, the second dielectric layer can be controlled by controlling the window size of the graphic template 590. A smaller window is formed in 550, for example, a window having a lateral dimension of no more than 20 nm is formed.
  • the photoresist and pattern template 590 are then removed.
  • the semiconductor material is selectively grown in the window 551 of the second dielectric layer 550, a buffer layer is formed first, and the semiconductor material is further grown on the buffer layer to obtain a semiconductor layer 530 (shown as d in Fig. 17).
  • the semiconductor material is a III-V semiconductor material, for example, one or more of the following:
  • the semiconductor material may further comprise a predetermined amount of dopant material.
  • the lateral dimension does not exceed the window of 20 nm, and therefore, the III-V semiconductor material in the semiconductor device prepared by the method for fabricating the semiconductor device of the embodiment of the present invention has no line dislocations, and therefore, the method for fabricating the semiconductor device of the embodiment of the present invention It is possible to prepare semiconductor devices of higher performance.
  • the semiconductor device 200 and in particular, in conjunction with the specific structure of the laser, optical amplifier, photodetector or transistor given in the foregoing embodiment, a corresponding semiconductor device can be fabricated.
  • the size of the sequence numbers of the above processes does not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not be taken to the embodiments of the present invention.
  • the implementation process constitutes any limitation.
  • the disclosed systems, devices, and methods may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention contributes in essence or to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and the like, which can store program codes. .

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Light Receiving Elements (AREA)
  • Recrystallisation Techniques (AREA)
  • Optical Integrated Circuits (AREA)
  • Drying Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Semiconductor Lasers (AREA)

Abstract

一种半导体器件和制备半导体器件的方法。该半导体器件包括：第一硅层（110；210）；第一介质层（120；220），位于第一硅层（110；210）上面，该第一介质层（120；220）包含窗口（121；221），该第一介质层（120；220）的窗口（121；221）底部的横向尺寸不超过20nm；III-V族半导体层（130；230），位于第一介质层（120；220）上面以及该第一介质层（120；220）的窗口（120；220）的窗口（121；221）内，并在该第一介质层（120；220）的窗口（121；221）内与该第一硅层（110；210）相连。半导体器件中的III-V族半导体材料没有线位错，具有较高的性能。

Description

半导体器件和制备半导体器件的方法 技术领域
本发明涉及信息技术领域， 并且更具体地， 涉及半导体器件和制备半导 体器件的方法。 背景技术
为了提高微处理器的性能， 集成电路一直保持小型化和多样化的高速发 展， 然而缩小的器件尺寸、 增加的器件密度也带来了一些不可避免的问题， 如信号延迟、 互连串扰等。 使用电互连介质导致的高功耗和能量浪费逐渐不 能满足半导体工业对器件高性能低成本的要求。 人们发现， 光互连可以有效 的解决这些问题并给传统集成电路带来许多新的功能， 因此， 硅光子学成为 了未来光电集成电路的重要研究课题。
硅是微电子平台的基石， 在光电集成上也是不可或缺的， 它具有高集成 度、 低成本的优势， 它的氧化物是优异的绝缘材料， 它们的折射率差较高使 得可以利用它们进行导光。 但是， 硅是间接带隙半导体， 光吸收和发射的效 率很低，同时硅的载流子迁移率也不高，在高速应用上受到限制。相反， III-V 族化合物半导体则具有直接带隙结构和高的电子迁移率， 其低维系统如多量 子阱、 量子点等也给光增益带来^艮多优良性能， 对材料成分的调节和低维结 构的优化给器件性能参数带来了多样的变化， 可以用来制备激光器、 太阳能 电池等光电器件， 高电子迁移率晶体管等电子器件。
制备 m-v族半导体器件的单片集成技术是在硅村底上外延生长 m-v族 材料， 进而制备成器件。 然而， 由于 m-v族材料如砷化镓、 磷化铟等和硅 之间存在很大的晶格失配和热失配， 在硅上直接生长 m-v族材料会引入高 密度的线位错， 致使器件性能恶化， 可靠性降低。 发明内容
本发明实施例提供了一种半导体器件和制备半导体器件的方法， 能够提 供没有线位错的 m-v族半导体器件。
第一方面， 提供了一种半导体器件， 包括：
第一硅层； 第一介质层， 该第一介质层位于该第一硅层上面， 该第一介质层具有窗 口， 该第一介质层的窗口底部的横向尺寸不超过 20nm;
m-v族半导体层， 该 m-v族半导体层分布于该第一介质层上面并深入 到该第一介质层的窗口内， 并在该第一介质层的窗口内与该第一硅层相连。
结合第一方面， 在第一种可能的实现方式中， 该第一介质层的窗口为倒 锥形或圓柱形。
结合第一方面或第一方面的第一种可能的实现方式，在第二种可能的实 现方式中， 该第一硅层为硅村底；
该半导体器件还包括：
第二硅层， 该第二硅层包含波导， 该第二硅层位于该第一介质层上面， 并且该第二硅层与该第一硅层之间的第一介质层的部分无窗口，该第二硅层 与该 m-v族半导体层直接或间接相连。
结合第一方面或第一方面的第一种可能的实现方式，在第三种可能的实 现方式中， 该第一硅层包含波导， 该第一介质层的窗口位于波导的上面； 该半导体器件还包括：
第二介质层和第三硅层， 该第三硅层为硅村底， 该第二介质层位于该第 一硅层下方， 该第三硅层上方。
结合第一方面或第一方面的第一至三种可能的实现方式中的任一种可 能的实现方式， 在第四种可能的实现方式中， 该半导体器件为激光器；
该 m-v族半导体层包括緩沖层、 有源区、 隔层、 N型掺杂过渡层和 P 型掺杂过渡层；
该半导体器件还包括 N电极和 P电极， 该 N电极与该 N型掺杂过渡层 相连， 该 P电极与该 P型掺杂过渡层相连。
结合第一方面或第一方面的第一至三种可能的实现方式中的任一种可 能的实现方式， 在第五种可能的实现方式中， 该半导体器件为光放大器； 该 III-V族半导体层包括緩沖层、 有源区、 隔层、 N型掺杂过渡层和 P 型掺杂过渡层；
该半导体器件还包括 N电极、 P电极和增透膜， 该 N电极与该 N型掺 杂过渡层相连， 该 p电极与该 p型掺杂过渡层相连， 该增透膜位于该 m-v 族半导体层的端面。
结合第一方面或第一方面的第一至三种可能的实现方式中的任一种可 能的实现方式， 在第六种可能的实现方式中， 该半导体器件为光探测器； 该 m-v族半导体层包括 N区、 p区和本征区；
该半导体器件还包括 N电极和 P电极， 该 N电极与该 N区相连， 该 P 电极与该 P区相连。
结合第一方面或第一方面的第一种可能的实现方式，在第七种可能的实 现方式中， 该半导体器件为晶体管；
该 m-v族半导体层为该晶体管的沟道材料；
该半导体器件还包括源极、 漏极、 栅极和栅介质层， 该源极、 该漏极和 该栅介质层与该 m-v族半导体层相连， 该栅极与该栅介质层相连。
第二方面， 提供了一种制备半导体器件的方法， 包括：
以图形模板为掩膜对 SOI的硅层进行刻蚀，该 SOI包括硅村底，硅村底 上的介质层和介质层上的硅层， 在暴露出介质层时， 停止刻蚀， 去除图形模 板， 得到具有窗口的硅层；
以具有窗口的硅层为模板对介质层进行刻蚀， 在暴露出硅村底时， 停止 刻蚀， 去除具有窗口的硅层， 得到具有窗口的介质层， 其中， 介质层的窗口 底部的横向尺寸不超过 20nm;
在介质层的窗口内生长半导体材料， 形成緩沖层， 在緩沖层上继续生长 半导体材料， 得到半导体层。
结合第二方面， 在第一种可能的实现方式中， 该图形模板为多孔氧化铝 膜或者极紫外曝光显影后的光刻胶。
结合第二方面或第二方面的第一种可能的实现方式，在第二种可能的实 现方式中， 该半导体材料为 m-v族半导体材料。
结合第二方面或第二方面的第一或二种可能的实现方式，在第三种可能 的实现方式中， 该半导体材料包含预设量的掺杂材料。
结合第二方面或第二方面的第一至三种可能的实现方式中的任一种可 能的实现方式， 在第四种可能的实现方式中， 在以图形模板为掩膜对 SOI 的硅层进行刻蚀之前， 该方法还包括：
在该图形模板的部分区域上遮挡光刻胶， 以便于遮挡区域下的硅层不被 刻蚀。
结合第二方面的第四种可能的实现方式， 在第五种可能的实现方式中， 该方法还包括： 在没有被刻蚀的硅层中制备波导。
第三方面， 提供了一种制备半导体器件的方法， 包括：
在 SOI的硅层中制备波导， 其中， 该 SOI包括硅村底， 硅村底上的第一 介质层和第一介质层上的硅层；
在硅层上形成第二介质层；
以图形模板为掩膜对第二介质层进行刻蚀，在暴露出硅层时，停止刻蚀， 去除图形模板， 得到具有窗口的第二介质层， 其中， 第二介质层的窗口底部 的横向尺寸不超过 20nm;
在第二介质层的窗口内生长半导体材料， 形成緩沖层， 在緩沖层上继续 生长半导体材料， 得到半导体层。
结合第三方面， 在第一种可能的实现方式中， 该图形模板为多孔氧化铝 膜或者极紫外曝光显影后的光刻胶。
结合第三方面或第三方面的第一种可能的实现方式，在第二种可能的实 现方式中， 该半导体材料为 m-v族半导体材料。
结合第三方面或第三方面的第一或二种可能的实现方式，在第三种可能 的实现方式中， 该半导体材料包含预设量的掺杂材料。
结合第三方面或第三方面的第一至三种可能的实现方式中的任一种可 能的实现方式， 在第四种可能的实现方式中， 在绝缘体上的硅 SOI的硅层中 制备波导， 包括：
在硅层中制备脊形波导。
结合第三方面的第四种可能的实现方式， 在第五种可能的实现方式中， 在以图形模板为掩膜对第二介质层进行刻蚀之前， 该方法还包括：
在该图形模板的部分区域上遮挡光刻胶， 其中， 没有遮挡光刻胶的区域 对应脊形波导的位置。
基于上述技术方案， 本发明实施例的半导体器件， 采用 III-V族半导体 材料，并且本发明实施例的半导体器件中的 m-v族半导体材料没有线位错， 因而具有较高的性能。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对本发明实施例中 所需要使用的附图作筒单地介绍， 显而易见地， 下面描述中的附图仅仅是本 发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动的 前提下， 还可以根据这些附图获得其他的附图。
图 1是根据本发明一个实施例的半导体器件的结构示意图。
图 2是根据本发明另一实施例的半导体器件的结构示意图。
图 3是根据本发明一个实施例的激光器的结构示意图。
图 4是根据本发明一个实施例的光放大器的结构示意图。
图 5是根据本发明一个实施例的探测器的结构示意图。
图 6是根据本发明另一实施例的探测器的结构示意图。
图 7是根据本发明一个实施例的晶体管的结构示意图。
图 8是根据本发明一个实施例的晶体管在单片上集成的结构示意图。 图 9是根据本发明另一实施例的半导体器件的结构示意图。
图 10是根据本发明另一实施例的激光器的结构示意图。
图 11是根据本发明另一实施例的光放大器的结构示意图。
图 12是根据本发明另一实施例的探测器的结构示意图。
图 13是根据本发明另一实施例的探测器的结构示意图。
图 14是根据本发明一个实施例的制备半导体器件的方法的示意性流程 图。
图 15是根据本发明一个实施例的制备半导体器件的方法的不同阶段的 半导体器件的示意图。
图 16是根据本发明另一实施例的制备半导体器件的方法的示意性流程 图。
图 17是根据本发明另一实施例的制备半导体器件的方法的不同阶段的 半导体器件的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例是本发明的一部分实施例， 而不 是全部实施例。 基于本发明中的实施例， 本领域普通技术人员在没有作出创 造性劳动的前提下所获得的所有其他实施例， 都应属于本发明保护的范围。
应理解， 本发明实施例中的术语 "第一" 和 "第二" 仅仅是为了区分不 同的内容， 不对本发明实施例做其他限定。 图 1示出了根据本发明一个实施例的半导体器件 100的结构示意图。如 图 1所示，该半导体器件 loo包括第一硅层 no,第一介质层 120和 m-v族 半导体层 130。
第一硅层 110为硅村底。
第一介质层 120位于第一硅层 110上面。 第一介质层 120的材料可以为 氧化硅或氮化硅或它们的混合物。
第一介质层 120具有窗口 121 , 窗口 121底部的横向尺寸不超过 20nm。 窗口 121的数量不限定， 可以随半导体器件 100的尺寸的大小而不同。
III-V族半导体层 130分布于第一介质层 120上面并深入到第一介质层 120的窗口 121内。 III-V族半导体层 130在第一介质层 120的窗口 121内与 第一硅层 110相连。
III-V族半导体层 130可以通过先在窗口 121内生长 m-v族半导体材料， 再继续在第一介质层 120上面生长 m-v族半导体材料得到。 m-v族半导体 材料可以包括以下的一种或多种：
磷化铝 (Α1Ρ)、磷化镓 (GaP)、磷化铟 (InP)、砷化铝 (AlAs)、砷化镓 (GaAs)、 砷化铟 (InAs)、 锑化铝 (AlSb)、 锑化镓 (GaSb)、 锑化铟 (InSb)、 氮化铝 (A1N)、 氮化镓 (GaN)、 氮化铟 (InN)以及它们三元和四元的化合物。
在本发明实施例中， 第一介质层 120的窗口 121底部的横向尺寸不超过 20nm, 也就是说， III-V族半导体层 130与第一硅层 110的接触面在任意方 向上的尺寸不超过 20nm, 这样， 窗口 121内的 III-V族半导体材料（即接触 面处的 m-v族半导体材料）没有线位错。 也就是说， 本发明实施例的半导 体器件是没有线位错的 m-v族半导体器件。由于 m-v族半导体材料具有直 接带隙结构和较高的电子迁移率， 能够提高半导体器件性能， 因此， 本发明 实施例的半导体器件具有较高的晶体质量和器件性能。
因此，本发明实施例的半导体器件，采用 m-v族半导体材料，并且 m-v 族半导体材料没有线位错， 因而具有较高的性能。
在本发明实施例中， 可选地， 该第一介质层 120的窗口 121可以为倒锥 形或圓柱形。 换句话说， 本发明实施例只限定窗口 121底部的横向尺寸不超 过 20nm, 不限定窗口 121的形状， 即还可以为其他形状。 具体地， 在窗口 121为倒锥形或圓柱形时，其底部直径不超过 20nm;在窗口 121为其他形状 时， 其底部的横向尺寸在任意方向上不超过 20nm。 在本发明实施例中， 可选地， 如图 2所示， 该半导体器件 100还包括： 第二硅层 140。
第二硅层 140位于第一介质层 120上面， 并且第二硅层 140与第一硅层 110之间的第一介质层 120的部分无窗口。 也就是说， 第二硅层 140位于第 一介质层 120的无窗口的部分的上面。第二硅层 140与 III-V族半导体层 130 直接或间接相连。 第二硅层 140包含波导， 从 III-V族半导体层 130中输出 的光可以耦合进波导中。
可选地， 该半导体器件 100还可以包括填充层 150。 填充层 150用于填 充 III-V族半导体层 130与第二硅层 140之间的空隙。 例如， 可以使用非晶 硅等材料填充。
可选地，本发明实施例的半导体器件 100具体可以为激光器、光放大器、 光探测器、 晶体管或太阳能电池等。
图 3为本发明一个实施例的激光器的结构示意图。
如图 3所示， 在本实施例中， 半导体器件 100为激光器。
在本实施例中， III-V族半导体层 130构成激光器的主体结构， 包括緩 沖层 131、 有源区 134、 隔层 133、 N型掺杂过渡层 132和 P型掺杂过渡层 135。
窗口 121 内的 III-V族半导体材料形成緩沖层 131 , 緩沖层 131 内的半 导体材料没有线位错。
激光器的光在有源区 134产生并放大。有源区 134可以包含多量子阱或 量子点， 以增强光增益。
在本实施例中， 该半导体器件 100还包括 N电极 160和 P电极 170, N 电极 160与 N型掺杂过渡层 132相连， P电极 170与 P型掺杂过渡层 135相 连。 可选地， 还可以包括光栅结构。
从激光器的主体结构中输出的光耦合进第二硅层 140中的波导中。
本实施例中的激光器，采用 III-V族半导体材料形成激光器的主体结构， 并且 III-V族半导体材料没有线位错， 因此具有较高的性能。
图 4为本发明一个实施例的光放大器的结构示意图。
如图 4所示， 在本实施例中， 半导体器件 100为光放大器， 也称为半导 体光放大器（ Semiconductor Optical Amplifier, SOA )。
与前述激光器的实施例类似， m-v族半导体层 130构成光放大器的主 体结构， 包括緩沖层 131、 有源区 134、 隔层 133、 N型掺杂过渡层 132和 P 型掺杂过渡层 135。
窗口 121 内的 III-V族半导体材料形成緩沖层 131 , 緩沖层 131 内的半 导体材料没有线位错。
外部进入光放大器的光在有源区 134内放大。有源区 134可以包含体材 料、 多量子阱、 量子点或量子短线等。
在本实施例中， 该半导体器件 100还包括 N电极 160、 P电极 170和增 透膜 180。 N电极 160与 N型掺杂过渡层 132相连， P电极 170与该 P型掺 杂过渡层 135相连。 增透膜 180位于 III-V族半导体层 130的端面， 增透膜 也称为减反膜。
从光放大器的主体结构中输出的光耦合进第二硅层 140中的波导中。 本实施例中的光放大器， 采用 m-v族半导体材料形成光放大器的主体 结构， 并且 m-v族半导体材料没有线位错， 因此具有较高的性能。
图 5和图 6为本发明实施例的光探测器的结构示意图。
在本实施例中， 半导体器件 100为光探测器。
如图 5和图 6所示， III-V族半导体层 130包括 N区 136、 P区 137和本 征区 138。
N区 136和 P区 137为掺杂区域。 N区 136和 P区 137可以垂直分布（如 图 5所示）， 也可以分布于器件表面 （如图 6所示）。
半导体器件 100还包括 N电极 160和 P电极 170。 N电极 160与 N区
136相连， P电极 170与 P区 137相连。
光从第二硅层 140中的波导耦合进探测器， 从而被探测。
本实施例中的光探测器， 采用 m-v族半导体材料， 并且 m-v族半导体 材料没有线位错， 因此具有较高的性能。
图 7为本发明一个实施例的晶体管的结构示意图。
如图 7所示， 在本实施例中， 半导体器件 100为晶体管。
III-V族半导体层 130为晶体管的沟道材料， 即本发明实施例的晶体管 为 m-v族半导体晶体管。 沟道材料中可以包含量子阱或量子点。
半导体器件 100还包括源极 181、 漏极 182、 栅极 183和栅介质层 184。 源极 181、 漏极 182和栅介质层 184与 III-V族半导体层 130相连， 栅极 183 与栅介质层 184相连。 本发明实施例的 m-v族半导体晶体管可以与 si晶体管单片集成， 如图 8所示。
通过选用不同的 m-v族半导体材料作为沟道材料， 可以得到多种晶体 管。 例如， 用两种不同带隙材料组成的结作为沟道材料， 可以得到高电子迁 移率晶体管（ High Electron Mobility Transistor, HEMT ), 另外还可以得到金 属半导体场效应晶体管 （ Metal-Semiconductor Field Effect Transistor , MESFET )、 鳍式场效应晶体管（Fin Field Effect Transistor, FinFET )和调制 掺杂场效应晶体管（ Modulation Doped Field Effect Transistor, MODFET )等。
本实施例中的晶体管， 采用 m-v族半导体材料， 并且 m-v族半导体材 料没有线位错， 因此具有较高的性能。
图 9示出了根据本发明另一实施例的半导体器件 200的结构示意图。如 图 2所示， 该半导体器件 200包括第一硅层 210, 第一介质层 220和 III-V 族半导体层 230。
第一介质层 220位于第一硅层 210上面。 第一介质层 220的材料可以为 氧化硅或氮化硅或它们的混合物。
第一介质层 220具有窗口 221 , 窗口 221底部的横向尺寸不超过 20nm。 窗口 221的数量不限定， 可以随半导体器件 200的尺寸的大小而不同。
III- V族半导体层 230分布于第一介质层 220上面并深入到第一介质层 220的窗口 221内。 III-V族半导体层 230在第一介质层 220的窗口 221内与 第一硅层 210相连。
III- V族半导体层 230可以通过先在窗口 221内生长 III-V族半导体材料， 再继续在第一介质层 220上面生长 III-V族半导体材料得到。 III-V族半导体 材料可以包括以下的一种或多种：
磷化铝 (Α1Ρ)、磷化镓 (GaP)、磷化铟 (InP)、砷化铝 (AlAs)、砷化镓 (GaAs)、 砷化铟 (InAs)、 锑化铝 (AlSb)、 锑化镓 (GaSb)、 锑化铟 (InSb)、 氮化铝 (A1N)、 氮化镓 (GaN)、 氮化铟 (InN)以及它们三元和四元的化合物。
在本发明实施例中， 可选地， 第一硅层 210包含波导， 例如， 脊形波导。 第一介质层 220的窗口 221位于波导的上面。
可选地， 半导体器件 200还包括：
第二介质层 240和第三硅层 250。
第三硅层 250为硅村底。 第二介质层 240位于第一硅层 210下方， 第三硅层 250上方。 第二介质 层 240的材料与第一介质层 220类似， 可以为氧化硅或氮化硅或它们的混合 物。
在本发明实施例中， 第一介质层 220的窗口 221底部的横向尺寸不超过 20nm, 也就是说， III-V族半导体层 230与第一硅层 210的接触面在任意方 向上的尺寸不超过 20nm, 这样， 窗口 221内的 III-V族半导体材料（即接触 面处的 III-V族半导体材料）没有线位错。 也就是说， 本发明实施例的半导 体器件是没有线位错的 m-v族半导体器件。由于 m-v族半导体材料具有直 接带隙结构和较高的电子迁移率， 能够提高半导体器件性能， 因此， 本发明 实施例的半导体器件具有较高的晶体质量和器件性能。
在本发明实施例中， 可选地， 该第一介质层 220的窗口 221可以为倒锥 形或圓柱形。 换句话说， 本发明实施例只限定窗口 221底部的横向尺寸不超 过 20nm, 不限定窗口 221的形状， 即还可以为其他形状。 具体地， 在窗口 221为倒锥形或圓柱形时，其底部直径不超过 20nm;在窗口 221为其他形状 时， 其底部的横向尺寸在任意方向上不超过 20nm。
与前述半导体器件 100类似， 本发明实施例的半导体器件 200具体可以 为激光器、 光放大器、 光探测器、 晶体管或太阳能电池等。
图 10为本发明另一实施例的激光器的结构示意图。
如图 10所示， 在本实施例中， 半导体器件 200为激光器。
在本实施例中， III-V族半导体层 230构成激光器的主体结构， 包括緩 沖层 231、 有源区 234、 隔层 233、 N型掺杂过渡层 232和 P型掺杂过渡层 235。
窗口 221 内的 III-V族半导体材料形成緩沖层 231 , 緩沖层 231 内的半 导体材料没有线位错。
激光器的光在有源区 234产生并放大。有源区 234可以包含多量子阱或 量子点， 以增强光增益。
在本实施例中， 半导体器件 200还包括 N电极 260和 P电极 270, N电 极 260与 N型掺杂过渡层 232相连， P电极 270与 P型掺杂过渡层 235相连。 可选地， 还可以包括光栅结构。
从激光器的主体结构中输出的光耦合进第一硅层 210中的波导中。
本实施例中的激光器，采用 m-v族半导体材料形成激光器的主体结构， 并且 ιπ-ν族半导体材料没有线位错， 因此具有较高的性能。
图 11为本发明另一实施例的光放大器的结构示意图。
如图 11所示， 在本实施例中， 半导体器件 200为光放大器， 也称为半 导体光放大器 SOA。
ΙΠ-V族半导体层 230构成光放大器的主体结构， 包括緩沖层 231、 有源 区 234、 隔层 233、 Ν型掺杂过渡层 232和 Ρ型掺杂过渡层 235。
窗口 221 内的 III-V族半导体材料形成緩沖层 231 , 緩沖层 231 内的半 导体材料没有线位错。
外部进入光放大器的光在有源区 234内放大。有源区 234可以包含体材 料、 多量子阱、 量子点或量子短线等。
在本实施例中， 该半导体器件 200还包括 N电极 260和 P电极 270。 N 电极 260与 N型掺杂过渡层 232相连， P电极 270与该 P型掺杂过渡层 235 相连。 还包括增透膜， 位于 III-V族半导体层的端面。
从光放大器的主体结构中输出的光耦合进第一硅层 210中的波导中。 本实施例中的光放大器， 采用 m-v族半导体材料形成光放大器的主体 结构， 并且 m-v族半导体材料没有线位错， 因此具有较高的性能。
图 12和图 13为本发明另一实施例的光探测器的结构示意图。
在本实施例中， 半导体器件 200为光探测器。
如图 12和图 13所示， III-V族半导体层 230包括 N区 236、 P区 237和 本征区 238。
N区 236和 P区 237为掺杂区域。 N区 236和 P区 237可以垂直分布（如 图 12所示）， 也可以分布于器件表面 （如图 13所示）。
半导体器件 200还包括 N电极 260和 P电极 270。 N电极 260与 N区 236相连， P电极 270与 P区 237相连。
光从第一硅层 210中的波导耦合进探测器， 从而被探测。
本实施例中的光探测器， 采用 m-v族半导体材料， 并且 m-v族半导体 材料没有线位错， 因此具有较高的性能。
以上详细描述了本发明实施例的半导体器件， 下面详细描述本发明实施 例的制备半导体器件的方法。
图 14示出了本发明一个实施例的制备半导体器件的方法 300的示意性 流程图。 如图 14所示， 该方法 300包括： S310, 以图形模板为掩膜对 SOI ( Silicon On Insulator, 绝缘体上的硅） 的硅层进行刻蚀，该 SOI包括硅村底，硅村底上的介质层和介质层上的硅层， 在暴露出介质层时， 停止刻蚀， 去除图形模板， 得到具有窗口的硅层；
S320,以具有窗口的硅层为模板对介质层进行刻蚀，在暴露出硅村底时， 停止刻蚀， 去除具有窗口的硅层， 得到具有窗口的介质层， 其中， 介质层的 窗口底部的横向尺寸不超过 20nm;
S330, 在介质层的窗口内生长半导体材料， 形成緩沖层， 在緩沖层上继 续生长半导体材料， 得到半导体层。
图 15是方法 300的不同阶段的半导体器件的示意图。 如图 15所示， 绝 缘体上的硅（Silicon On Insulator, SOI ) 包括硅村底 410, 介质层 420和硅 层 440。 介质层 420和硅层 440的厚度可根据器件的需要和应用不同而选择 不同的厚度。
在 S310中， 先利用图形模板 490对 SOI的硅层进行刻蚀。
可选地， 该图形模板 490为多孔氧化铝膜或者极紫外曝光显影后的光刻 胶。若使用多孔氧化铝膜，则直接将多孔氧化铝膜贴在 SOI的硅层 440上（如 图 15中的 a所示）。 硅层 440上面可预先形成一层薄的氧化层， 方便后续多 孔氧化铝膜的去除。 若使用极紫外曝光显影后的光刻胶， 则先将光刻胶涂覆 在硅层 440上， 再利用极紫外光刻光源对光刻胶曝光， 再经过显影得到图形 模板 490。
在刻蚀前，可在图形模板 490的部分区域上遮挡光刻胶（如图 15中的 b 所示）， 以便于遮挡区域下的硅层不被刻蚀。
通过控制刻蚀参数，可以选择性的对硅层 440进行刻蚀，不刻蚀硅层 440 下面的介质层 420。 在暴露出介质层 420时， 停止刻蚀。
由于图形模板 490对刻蚀束流的阴影效应，在硅层 440中会形成孔径逐 渐缩小的窗口 441 , 即窗口 441的顶部横向尺寸大于底部横向尺寸（如图 15 中的 b所示）。
接下来去除图形模板 490, 得到具有窗口 441的图形化硅层 440。 去除 方法可以采用化学方法。
在 S320中， 以具有窗口 441的图形化硅层 440为模板对介质层 420进 行刻蚀。 在介质层 420中形成窗口 421 (如图 15中的 c所示）。 由于阴影效 应， 窗口 421底部横向尺寸会小于顶部横向尺寸， 也就是说， 介质层 420的 窗口 421底部横向尺寸相比图形模板 490的窗口尺寸会小很多。 然后去除未 遮挡的硅层（如图 15中的 d所示）。
在 S330中， 在介质层 420的窗口 421 内选择性生长半导体材料， 先形 成緩沖层， 再在緩沖层上继续生长半导体材料， 得到半导体层 430 (如图 15 中的 e所示）。
在生长半导体材料前， 先对硅层 440剩余的部分进行保护， 例如， 通过 氧化硅或氮化硅等形成介质保护层 155。
优选地， 半导体材料为 III-V族半导体材料， 例如， 可以为以下的一种 或多种：
磷化铝 (A1P)、磷化镓 (GaP)、磷化铟 (InP)、砷化铝 (AlAs)、砷化镓 (GaAs)、 砷化铟 (InAs)、 锑化铝 (AlSb)、 锑化镓 (GaSb)、 锑化铟 (InSb)、 氮化铝 (A1N)、 氮化镓 (GaN)、 氮化铟 (InN)以及它们三元和四元的化合物。 化学气相沉积（ Chemical Vapor Deposition, CVD ),原子层沉积（ Atomic Layer Deposition , ALD )和它们的各种变化， 例如， CVD可以包括金属有机化合 物化学气相淀积（Metal-Organic Chemical Vapor Deposition, MOCVD )、 等 离子体增强化学气相沉积 ( Plasma Enhanced Chemical Vapor Deposition, PECVD )、 低压力化学气相沉积（ Low Pressure Chemical Vapor Deposition, LPCVD )、 超高真空化学气相沉积 （Ultra High Vacuum Chemical Vapor Deposition , UHVCVD ) , 反应等离子体化学汽相淀积 （ Reactive Plasma Chemical Vapor Deposition , RPCVD )等。
可选地， 半导体材料还可以包含预设量的掺杂材料， 以形成 PN或 PIN 结构。 生长的半导体材料可以形成有源区， 有源区中可以包含多量子阱或量 子点等结构。
可选地， 该方法 300还包括：
在没有被刻蚀的硅层中制备波导。
如图 15中的 f所示， 在硅层 440剩余的部分中制备波导。 另外， 还需 要去除介质保护层 155 , 对留下的空隙进行填充， 形成填充层 150。 例如， 可以使用非晶硅等材料填充。 尺寸相比图形模板的窗口尺寸会小很多， 因此， 可以通过控制图形模板的窗 口尺寸在介质层中形成较小的窗口， 以达到不同 m-v族半导体材料无位错 生长的条件。 例如， 在介质层中形成的窗口底部的横向尺寸不超过 20nm, 还可以小于 10nm, 甚至可以不超过 2nm。 的横向尺寸不超过 20nm的窗口， 因此， 本发明实施例的制备半导体器件的 方法制备的半导体器件中的 III-V族半导体材料没有线位错， 因此， 本发明 实施例的制备半导体器件的方法能够制备较高性能的半导体器件。 的半导体器件 100, 并且具体地， 结合该前述实施例给出的激光器、 光放大 器、 光探测器或晶体管的具体结构， 可以制备相应的半导体器件。
图 16示出了本发明另一实施例的制备半导体器件的方法 400的示意性 流程图。 如图 16所示， 该方法 400包括：
S410, 在 SOI的硅层中制备波导， 其中， 该 SOI包括硅村底， 硅村底上 的第一介质层和第一介质层上的硅层；
S420, 在硅层上形成第二介质层；
S430, 以图形模板为掩膜对第二介质层进行刻蚀， 在暴露出硅层时， 停 止刻蚀， 去除图形模板， 得到具有窗口的第二介质层， 其中， 第二介质层的 窗口底部的横向尺寸不超过 20nm;
S440, 在第二介质层的窗口内生长半导体材料， 形成緩沖层， 在緩沖层 上继续生长半导体材料， 得到半导体层。
图 17是方法 400的不同阶段的半导体器件的示意图。如图 17所示， SOI 包括硅村底 510, 第一介质层 520和硅层 540。
在 S410中， 在 SOI的硅层 540中制备波导， 例如， 制备脊形波导， 如 图 17中的 a所示。
在 S420中， 在具有波导的硅层 540上形成第二介质层 550。
S430, 利用图形模板 590对第二介质层 550进行刻蚀。
可选地， 该图形模板 590为多孔氧化铝膜或者极紫外曝光显影后的光刻 胶。 在刻蚀前， 可在图形模板 590的部分区域上遮挡光刻胶， 其中， 没有遮 挡光刻胶的区域对应波导的位置（如图 17中的 b所示）。
对第二介质层 550进行刻蚀， 暴露出硅层 540, 在第二介质层 550上形 成窗口 551 (如图 17中的 c所示）。 由于图形模板 590对刻蚀束流的阴影效应 ,在第二介质层 550上形成的 窗口 551的底部横向尺寸小于顶部横向尺寸大于， 因此， 可以通过控制图形 模板 590的窗口尺寸在第二介质层 550中形成较小的窗口， 例如， 形成底部 的横向尺寸不超过 20nm的窗口。
接下来除去光刻胶和图形模板 590。
在 S440中， 在第二介质层 550的窗口 551 内选择性生长半导体材料， 先形成緩沖层， 再在緩沖层上继续生长半导体材料， 得到半导体层 530 (如 图 17中的 d所示）。
优选地， 半导体材料为 III-V族半导体材料， 例如， 可以为以下的一种 或多种：
磷化铝 (A1P)、磷化镓 (GaP)、磷化铟 (InP)、砷化铝 (AlAs)、砷化镓 (GaAs)、 砷化铟 (InAs)、 锑化铝 (AlSb)、 锑化镓 (GaSb)、 锑化铟 (InSb)、 氮化铝 (A1N)、 氮化镓 (GaN)、 氮化铟 (InN)以及它们三元和四元的化合物。
可选地， 该半导体材料还可以包含预设量的掺杂材料。 的横向尺寸不超过 20nm的窗口， 因此， 本发明实施例的制备半导体器件的 方法制备的半导体器件中的 III-V族半导体材料没有线位错， 因此， 本发明 实施例的制备半导体器件的方法能够制备较高性能的半导体器件。 的半导体器件 200, 并且具体地， 结合该前述实施例给出的激光器、 光放大 器、 光探测器或晶体管的具体结构， 可以制备相应的半导体器件。
应理解， 在本发明的各种实施例中， 上述各过程的序号的大小并不意味 着执行顺序的先后， 各过程的执行顺序应以其功能和内在逻辑确定， 而不应 对本发明实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到， 结合本文中所公开的实施例描述的各 示例的单元及算法步骤， 能够以电子硬件、 计算机软件或者二者的结合来实 现， 为了清楚地说明硬件和软件的可互换性， 在上述说明中已经按照功能一 般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执 行， 取决于技术方案的特定应用和设计约束条件。 专业技术人员可以对每个 特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超 出本发明的范围。 所属领域的技术人员可以清楚地了解到， 为了描述的方便和筒洁， 上述 描述的系统、 装置和单元的具体工作过程， 可以参考前述方法实施例中的对 应过程， 在此不再赘述。
在本申请所提供的几个实施例中， 应该理解到， 所揭露的系统、 装置和 方法， 可以通过其它的方式实现。 例如， 以上所描述的装置实施例仅仅是示 意性的， 例如， 所述单元的划分， 仅仅为一种逻辑功能划分， 实际实现时可 以有另外的划分方式， 例如多个单元或组件可以结合或者可以集成到另一个 系统， 或一些特征可以忽略， 或不执行。 另外， 所显示或讨论的相互之间的 耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或 通信连接， 也可以是电的， 机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作 为单元显示的部件可以是或者也可以不是物理单元， 即可以位于一个地方， 或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或 者全部单元来实现本发明实施例方案的目的。
另外， 在本发明各个实施例中的各功能单元可以集成在一个处理单元 中， 也可以是各个单元单独物理存在， 也可以是两个或两个以上单元集成在 一个单元中。 上述集成的单元既可以采用硬件的形式实现， 也可以采用软件 功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销 售或使用时， 可以存储在一个计算机可读取存储介质中。 基于这样的理解， 本发明的技术方案本质上或者说对现有技术做出贡献的部分， 或者该技术方 案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在 一个存储介质中， 包括若干指令用以使得一台计算机设备（可以是个人计算 机， 服务器， 或者网络设备等）执行本发明各个实施例所述方法的全部或部 分步骤。 而前述的存储介质包括： U盘、 移动硬盘、 只读存储器（ROM, Read-Only Memory )、 随机存取存储器 ( RAM, Random Access Memory )、 磁碟或者光盘等各种可以存储程序代码的介质。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到各种等效的修改或替换， 这些修改或替换都应涵盖在本发明的保护范围 之内。 因此， 本发明的保护范围应以权利要求的保护范围为准。

Claims

权利要求
1. 一种半导体器件， 其特征在于， 包括：
第一硅层 ( 110; 210);
第一介质层（120; 220), 所述第一介质层（120; 220)位于所述第一 硅层（110; 210)上面， 所述第一介质层（120; 220)具有窗口 （121; 221), 所述第一介质层（ 120; 220)的窗口（ 121; 221 )底部的横向尺寸不超过 20nm;
III-V族半导体层（ 130; 230), 所述 III-V族半导体层（ 130; 230)分 布于所述第一介质层（ 120; 220 )上面并深入到所述第一介质层（ 120; 220 ) 的窗口 （121; 221 ) 内， 并在所述第一介质层（120; 220) 的窗口 （121; 221 ) 内与所述第一硅层（ 110; 210)相连。
2. 根据权利要求 1所述的半导体器件， 其特征在于， 所述第一介质层 ( 120; 220) 的窗口 （121; 221 ) 为倒锥形或圓柱形。
3. 根据权利要求 1或 2所述的半导体器件， 其特征在于， 所述第一硅 层（ 110) 为硅村底；
所述半导体器件还包括：
第二硅层（ 140 ), 所述第二硅层（ 140 )包含波导， 所述第二硅层（ 140 ) 位于所述第一介质层（120)上面， 并且所述第二硅层（140)与所述第一硅 层（ 110 )之间的所述第一介质层（ 120 )的部分无窗口， 所述第二硅层（ 140 ) 与所述 III-V族半导体层（130)直接或间接相连。
4. 根据权利要求 1或 2所述的半导体器件， 其特征在于， 所述第一硅 层（210) 包含波导， 所述第一介质层（220) 的窗口 （221)位于所述波导 的上面；
所述半导体器件还包括：
第二介质层（ 240 )和第三硅层（ 250 ), 所述第三硅层（ 250 )为硅村底， 所述第二介质层（ 240 )位于所述第一硅层（ 210 )下方，所述第三硅层（ 250 ) 上方。
5. 根据权利要求 1至 4中任一项所述的半导体器件， 其特征在于， 所 述半导体器件为激光器；
所述 III-V族半导体层（ 130; 230), 包括緩沖层（131; 231)、 有源区 ( 134; 234)、 隔层（ 133; 233 )、 N型掺杂过渡层（ 132; 232)和 P型掺杂 过渡层（135; 235 ); 所述半导体器件还包括 N电极 ( 160; 260 )和 P电极 ( 170; 270 ), 所 述 N电极（ 160; 260 )与所述 N型掺杂过渡层（ 132; 232 )相连， 所述 P 电极（170; 270 )与所述 P型掺杂过渡层（135; 235 )相连。
6. 根据权利要求 1至 4中任一项所述的半导体器件， 其特征在于， 所 述半导体器件为光放大器；
所述 III-V族半导体层（ 130; 230 ), 包括緩沖层（131; 231 )、 有源区 ( 134; 234 )、 隔层（133; 233 )、 N型掺杂过渡层（132; 232 )和 P型掺杂 过渡层（135; 235 );
所述半导体器件还包括 N电极 ( 160; 260 )、 P电极 ( 170; 270 )和增 透膜， 所述 N电极（160; 260 )与所述 N型掺杂过渡层（ 132; 232 )相连， 所述 P电极（170; 270 )与所述 P型掺杂过渡层（135; 235 )相连， 所述增 透膜位于所述 III-V族半导体层（130; 230 ) 的端面。
7. 根据权利要求 1至 4中任一项所述的半导体器件， 其特征在于， 所 述半导体器件为光探测器；
所述 III-V族半导体层（130; 230 ) 包括 N区 （136; 236 )、 P区 （137;
237 )和本征区 ( 138; 238 );
所述半导体器件还包括 N电极 ( 160; 260 )和 P电极 ( 170; 270 ) , 所 述 N电极（160; 260 )与所述 N区 （ 136; 236 )相连， 所述 P电极（170;
270 ) 与所述 P区 （137; 237 )相连。
8. 根据权利要求 1或 2所述的半导体器件， 其特征在于， 所述半导体 器件为晶体管；
所述 m-v族半导体层（130 ) 为所述晶体管的沟道材料；
所述半导体器件还包括源极（ 181 )、 漏极（ 182 )、 栅极（ 183 )和栅介 质层（ 184 ) , 所述源极（ 181 )、 所述漏极（ 182 )和所述栅介质层（ 184 )与 所述 III-V族半导体层（ 130 )相连， 所述栅极 ( 183 )与所述栅介质层（ 184 ) 相连。
9. 一种制备半导体器件的方法， 其特征在于， 包括：
以图形模板为掩膜对绝缘体上的硅 SOI的硅层进行刻蚀，所述 SOI包括 硅村底， 硅村底上的介质层和介质层上的硅层， 在暴露出介质层时， 停止刻 蚀， 去除图形模板， 得到具有窗口的硅层；
以具有窗口的硅层为模板对介质层进行刻蚀， 在暴露出硅村底时， 停止 刻蚀， 去除具有窗口的硅层， 得到具有窗口的介质层， 其中， 介质层的窗口 底部的横向尺寸不超过 20nm;
在介质层的窗口内生长半导体材料， 形成緩沖层， 在所述緩沖层上继续 生长半导体材料， 得到半导体层。
10. 根据权利要求 9所述的方法， 其特征在于， 所述图形模板为多孔氧 化铝膜或者极紫外曝光显影后的光刻胶。
11. 根据权利要求 9或 10所述的方法， 其特征在于， 所述半导体材料 为 m-v族半导体材料。
12. 根据权利要求 9至 11 中任一项所述的方法， 其特征在于， 所述半 导体材料包含预设量的掺杂材料。
13. 根据权利要求 9至 12中任一项所述的方法， 其特征在于， 在所述 以图形模板为掩膜对绝缘体上的硅 SOI的硅层进行刻蚀之前，所述方法还包 括：
在所述图形模板的部分区域上遮挡光刻胶， 以便于遮挡区域下的硅层不 被刻蚀。
14. 根据权利要求 13所述的方法， 其特征在于， 所述方法还包括： 在没有被刻蚀的硅层中制备波导。
15. 一种制备半导体器件的方法， 其特征在于， 包括：
在绝缘体上的硅 SOI的硅层中制备波导， 其中， 所述 SOI包括硅村底， 硅村底上的第一介质层和第一介质层上的硅层；
在硅层上形成第二介质层；
以图形模板为掩膜对第二介质层进行刻蚀，在暴露出硅层时，停止刻蚀， 去除图形模板， 得到具有窗口的第二介质层， 其中， 第二介质层的窗口底部 的横向尺寸不超过 20nm;
在第二介质层的窗口内生长半导体材料， 形成緩沖层， 在所述緩沖层上 继续生长半导体材料， 得到半导体层。
16. 根据权利要求 15所述的方法， 其特征在于， 所述图形模板为多孔 氧化铝膜或者极紫外曝光显影后的光刻胶。
17. 根据权利要求 15或 16所述的方法， 其特征在于， 所述半导体材料 为 III-V族半导体材料。
18. 根据权利要求 15至 17中任一项所述的方法， 其特征在于， 所述半 导体材料包含预设量的掺杂材料。
19. 根据权利要求 15至 18中任一项所述的方法， 其特征在于， 所述在 绝缘体上的硅 SOI的硅层中制备波导， 包括：
在硅层中制备脊形波导。
20. 根据权利要求 19所述的方法， 其特征在于， 在所述以图形模板为 掩膜对第二介质层进行刻蚀之前， 所述方法还包括：
在所述图形模板的部分区域上遮挡光刻胶， 其中， 没有遮挡光刻胶的区 域对应脊形波导的位置。
PCT/CN2013/090099 2013-12-20 2013-12-20 半导体器件和制备半导体器件的方法 WO2015089826A1 (zh)

Priority Applications (9)

Application Number Priority Date Filing Date Title
KR1020167017473A KR20160089519A (ko) 2013-12-20 2013-12-20 반도체 디바이스 및 반도체 디바이스 제조 방법
EP13899857.0A EP3070751A4 (en) 2013-12-20 2013-12-20 Semiconductor device and method for manufacturing same
CN201380004030.3A CN105264674B (zh) 2013-12-20 2013-12-20 半导体器件和制备半导体器件的方法
JP2016541187A JP2017511596A (ja) 2013-12-20 2013-12-20 半導体デバイスおよび半導体デバイスの製造方法
CN201811378239.7A CN109860022B (zh) 2013-12-20 2013-12-20 半导体器件和制备半导体器件的方法
PCT/CN2013/090099 WO2015089826A1 (zh) 2013-12-20 2013-12-20 半导体器件和制备半导体器件的方法
EP18160118.8A EP3428957B1 (en) 2013-12-20 2013-12-20 Method for producing semiconductor device
US15/186,681 US20160291248A1 (en) 2013-12-20 2016-06-20 Semiconductor device and method for producing semiconductor device
US15/975,496 US10234629B2 (en) 2013-12-20 2018-05-09 Method for reducing threading dislocation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2013/090099 WO2015089826A1 (zh) 2013-12-20 2013-12-20 半导体器件和制备半导体器件的方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/186,681 Continuation US20160291248A1 (en) 2013-12-20 2016-06-20 Semiconductor device and method for producing semiconductor device

Publications (1)

Publication Number Publication Date
WO2015089826A1 true WO2015089826A1 (zh) 2015-06-25

Family

ID=53401994

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/090099 WO2015089826A1 (zh) 2013-12-20 2013-12-20 半导体器件和制备半导体器件的方法

Country Status (6)

Country Link
US (2) US20160291248A1 (zh)
EP (2) EP3428957B1 (zh)
JP (1) JP2017511596A (zh)
KR (1) KR20160089519A (zh)
CN (2) CN109860022B (zh)
WO (1) WO2015089826A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3060772B1 (fr) * 2016-12-20 2022-12-30 Thales Sa Circuit photonique integre optimise
CN108054182B (zh) * 2017-12-19 2024-04-12 苏州矩阵光电有限公司 一种化合物半导体硅基混合器件及其制备方法
US11257672B2 (en) * 2018-05-14 2022-02-22 Globalfoundries U.S. Inc. Semiconductor devices including active regions in RAM areas with deposition determined pitch
JP7139960B2 (ja) * 2019-01-10 2022-09-21 株式会社デンソー 半導体装置
GB2586889B (en) * 2019-08-26 2022-11-02 Rockley Photonics Ltd Method of manufacturing a III-V based optoelectronic device
JP7287495B2 (ja) * 2019-12-03 2023-06-06 日本電信電話株式会社 半導体層の形成方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060077807A (ko) * 2004-12-31 2006-07-05 엘지전자 주식회사 측면 성장된 발광 다이오드 및 그의 제조 방법
CN1983656A (zh) * 2005-12-15 2007-06-20 Lg电子株式会社 具有垂直结构的发光二极管及其制造方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US187018A (en) * 1877-02-06 Improvement in harrows
US4806996A (en) 1986-04-10 1989-02-21 American Telephone And Telegraph Company, At&T Bell Laboratories Dislocation-free epitaxial layer on a lattice-mismatched porous or otherwise submicron patterned single crystal substrate
JP3838718B2 (ja) * 1996-12-13 2006-10-25 京セラ株式会社 光デバイス実装基板の作製方法および光モジュールの作製方法
KR100413792B1 (ko) * 1997-07-24 2004-02-14 삼성전자주식회사 질화갈륨 층과 공기층이 반복 적층된 분산브래그 반사기를구비한 단파장 면발광 반도체 레이저장치 및 그 제조 방법
US6372599B1 (en) * 1999-01-14 2002-04-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US6730588B1 (en) * 2001-12-20 2004-05-04 Lsi Logic Corporation Method of forming SiGe gate electrode
JP3946062B2 (ja) * 2002-03-18 2007-07-18 シャープ株式会社 表示装置およびその製造方法
US7029959B1 (en) * 2003-05-06 2006-04-18 Advanced Micro Devices, Inc. Source and drain protection and stringer-free gate formation in semiconductor devices
JP4457576B2 (ja) 2003-05-08 2010-04-28 住友電気工業株式会社 Ｉｉｉ−ｖ族化合物結晶およびその製造方法
US7638842B2 (en) 2005-09-07 2009-12-29 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
DE602006008256D1 (de) * 2005-12-15 2009-09-17 Lg Electronics Inc LED mit vertikaler Struktur und deren Herstellungsverfahren
WO2008051503A2 (en) * 2006-10-19 2008-05-02 Amberwave Systems Corporation Light-emitter-based devices with lattice-mismatched semiconductor structures
FR2910700B1 (fr) * 2006-12-21 2009-03-20 Commissariat Energie Atomique PROCEDE DE FABRICATION D'UN SUBSTRAT SOI ASSOCIANT DES ZONES A BASE DE SILICIUM ET DES ZONES A BASE DE GaAs
US7893798B2 (en) * 2007-05-09 2011-02-22 Innovative Micro Technology Dual substrate MEMS plate switch and method of manufacture
WO2009020433A1 (en) * 2007-08-08 2009-02-12 Agency For Science, Technology And Research A semiconductor arrangement and a method for manufacturing the same
US8686472B2 (en) * 2008-10-02 2014-04-01 Sumitomo Chemical Company, Limited Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate
DE102009051520B4 (de) * 2009-10-31 2016-11-03 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung von Siliziumhalbleiterscheiben mit Schichtstrukturen zur Integration von III-V Halbleiterbauelementen
CN102107852B (zh) * 2009-12-24 2013-05-22 中国科学院微电子研究所 半导体纳米结构和制造方法及其应用
US8119494B1 (en) * 2010-07-29 2012-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Defect-free hetero-epitaxy of lattice mismatched semiconductors
CN102332423B (zh) 2011-05-25 2013-11-06 湖南红太阳光电科技有限公司 一种减少埋层空洞型soi晶片化学机械研磨破裂的工艺
CN103390698A (zh) * 2012-05-08 2013-11-13 华夏光股份有限公司 发光二极管及其制造方法
CN102882129A (zh) * 2012-10-25 2013-01-16 中国科学院半导体研究所 改变硅波导宽度制备多波长硅基混合激光器阵列的方法
US9287115B2 (en) * 2014-03-12 2016-03-15 International Business Machines Corporation Planar III-V field effect transistor (FET) on dielectric layer
US9704958B1 (en) * 2015-12-18 2017-07-11 International Business Machines Corporation III-V field effect transistor on a dielectric layer
US9837302B1 (en) * 2016-08-26 2017-12-05 Qualcomm Incorporated Methods of forming a device having semiconductor devices on two sides of a buried dielectric layer
US10090409B2 (en) * 2016-09-28 2018-10-02 Monolithic Power Systems, Inc. Method for fabricating LDMOS with self-aligned body

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060077807A (ko) * 2004-12-31 2006-07-05 엘지전자 주식회사 측면 성장된 발광 다이오드 및 그의 제조 방법
CN1983656A (zh) * 2005-12-15 2007-06-20 Lg电子株式会社 具有垂直结构的发光二极管及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3070751A4 *

Also Published As

Publication number Publication date
EP3070751A4 (en) 2017-01-11
EP3070751A1 (en) 2016-09-21
CN105264674B (zh) 2019-01-18
CN105264674A (zh) 2016-01-20
US20160291248A1 (en) 2016-10-06
EP3428957B1 (en) 2021-12-08
CN109860022A (zh) 2019-06-07
US10234629B2 (en) 2019-03-19
EP3428957A1 (en) 2019-01-16
JP2017511596A (ja) 2017-04-20
KR20160089519A (ko) 2016-07-27
CN109860022B (zh) 2022-09-23
US20180259708A1 (en) 2018-09-13

Similar Documents

Publication Publication Date Title
US10234629B2 (en) Method for reducing threading dislocation of semiconductor device
US9496379B2 (en) Method and structure for III-V FinFET
US20140203243A1 (en) Three-dimensional quantum well transistor and fabrication method
US20130264609A1 (en) Semiconductor Structure of Hybrid of Coplanar Ge and III-V and Preparation Method Thereof
TWI692107B (zh) 具有逆行半導體源/汲極之高遷移率的場效電晶體
TWI656638B (zh) 用於ｉｉｉ－ｖ族奈米線穿隧ｆｅｔ之方法及結構
US9589791B2 (en) Compound finFET device including oxidized III-V fin isolator
WO2015109456A1 (zh) Soi衬底制备方法和soi衬底
US20180315591A1 (en) Hetero-integration of iii-n material on silicon
KR102125324B1 (ko) 단파장을 위한 이종 집적회로
CN110600549A (zh) 一种增强型AlGaN/GaN MOS-HEMT器件结构及其制备方法
WO2022041674A1 (zh) 低热阻硅基氮化镓微波毫米波器件材料结构及制备方法
US11164939B2 (en) Tunnel field-effect transistor and method for forming the same
US11728448B2 (en) Fabrication of a semiconductor device including a quantum dot structure
CN209843716U (zh) 一种增强型AlGaN/GaN MOS-HEMT器件结构
US9401583B1 (en) Laser structure on silicon using aspect ratio trapping growth
US9087775B2 (en) Planar semiconductor growth on III-V material
US20230033374A1 (en) Fabrication of a semiconductor device
JP2005150136A (ja) 窒化物系化合物からなる半導体素子の製造方法
JP2014225681A (ja) ハニカムヘテロエピタキシーを含む半導体装置
WO2018094711A1 (zh) 隧穿场效应晶体管及其制作方法
WO2016168995A1 (zh) 隧穿晶体管及隧穿晶体管的制造方法
JP2003234358A (ja) 半導体装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201380004030.3

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13899857

Country of ref document: EP

Kind code of ref document: A1

REEP Request for entry into the european phase

Ref document number: 2013899857

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2013899857

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2016541187

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20167017473

Country of ref document: KR

Kind code of ref document: A