WO2018094711A1 - 隧穿场效应晶体管及其制作方法 - Google Patents

隧穿场效应晶体管及其制作方法 Download PDF

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WO2018094711A1
WO2018094711A1 PCT/CN2016/107378 CN2016107378W WO2018094711A1 WO 2018094711 A1 WO2018094711 A1 WO 2018094711A1 CN 2016107378 W CN2016107378 W CN 2016107378W WO 2018094711 A1 WO2018094711 A1 WO 2018094711A1
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region
type
dopant
substrate
layer
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PCT/CN2016/107378
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English (en)
French (fr)
Inventor
徐挽杰
蔡皓程
张臣雄
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华为技术有限公司
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Priority to CN201680064132.8A priority Critical patent/CN108369954B/zh
Priority to PCT/CN2016/107378 priority patent/WO2018094711A1/zh
Publication of WO2018094711A1 publication Critical patent/WO2018094711A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a tunneling field effect transistor and a method of fabricating the same.
  • TFET Tunnel Field-Effect Transistors
  • subthreshold swing is the amount of change in gate voltage required when the drain current changes by an order of magnitude in the subthreshold state. The smaller the subthreshold swing, the drain current follows the gate The faster the pole voltage changes, the better the switching characteristics of the transistor.), so that the supply voltage of the transistor is lowered, thereby significantly reducing the power consumption of the transistor.
  • the in-line tunneling TFET In the in-line tunneling TFET, there is a large overlap between the gate and the source region. When a certain voltage is applied to the gate, inter-band tunneling occurs in the source region perpendicular to the gate (referred to as line tunneling). Wear) Because of the small distance of this tunneling, the line tunneling TFET can achieve a small subthreshold swing and a large tunneling current.
  • the embodiment of the invention discloses a tunneling field effect transistor and a manufacturing method thereof, which can reduce the subthreshold swing of the tunneling field effect transistor.
  • a first aspect of the embodiments of the present invention discloses a tunneling field effect transistor, including:
  • a source region and a drain region disposed on the substrate, a region between the source region and the drain region is a channel, and a source region and the channel form a pocket-shaped region, the source
  • the region and the pocket region each comprise a first type of dopant, the drain region comprising a second type of dopant;
  • the gate stack layer being disposed on the source region and the pocket region and the channel;
  • the generation of point tunneling in the tunneling field effect transistor is delayed, and the subthreshold swing of the tunneling field effect transistor can be reduced.
  • the tunneling field effect transistor further includes:
  • An epitaxial layer disposed on the source region, the pocket region, the channel, and the drain region;
  • the gate stack layer is disposed on the epitaxial layer.
  • the use of an epitaxial layer can increase the energy band bending in the overlap region of the gate source, thereby reducing the subthreshold swing and increasing the tunneling current.
  • the gate stack layer includes a gate dielectric layer and a gate region, the gate dielectric layer is disposed on the epitaxial layer, and the gate region is disposed on the gate dielectric layer.
  • a gate dielectric layer and a gate region are disposed on the epitaxial layer, and the gate bias is transmitted through the gate dielectric layer to change the degree of band bending in the epitaxial layer, thereby affecting the tunneling current.
  • an electrode correspondingly connecting the source region, the drain region and the gate region to form a source, a drain and a gate.
  • the first doping concentration of the first type of dopant included in the source region is greater than the second doping concentration of the first type of dopant included in the pocket region.
  • the doping concentration of the source region is greater than the doping concentration of the pocket region, tunneling between the source region and the channel can be suppressed, and since the doping concentration of the pocket region is small, the pocket region and the channel can be avoided. Tunneling occurs between them.
  • the first type of dopant is a P type dopant
  • the second type of dopant is an N type dopant
  • the first type of dopant is an N-type dopant and the second type of dopant is a P-type dopant.
  • a second aspect of the embodiments of the present invention discloses a method for fabricating a tunneling field effect transistor, including:
  • the source region and the pocket-type region each comprise a first type of dopant, and the drain region comprises a second type of dopant;
  • a low dielectric constant material is filled around the gate stack layer and the sidewalls.
  • a pocket type region is formed between the source region and the channel, and a pocket type is used for delaying the generation of point tunneling in the tunneling field effect transistor, and the tunneling field effect transistor can be reduced. Threshold swing.
  • the method further includes:
  • the gate stack layer is formed on the epitaxial layer.
  • the use of an epitaxial layer can increase the energy band bending in the overlap region of the gate source, thereby reducing the subthreshold swing and increasing the tunneling current.
  • the gate stack layer includes a gate dielectric layer and a gate region
  • the step of “forming a gate stack layer on the epitaxial layer” includes:
  • the method further includes:
  • the step of “forming a source region on one side of the substrate” includes:
  • Patterning the first mask layer removing one side of the first mask layer, to obtain a patterned first mask layer, so that the substrate is exposed to the first predetermined region;
  • the step of “forming a source region on one side of the substrate” includes:
  • Patterning the first mask layer removing one side of the first mask layer, to obtain a patterned first mask layer, so that the substrate is exposed to the first predetermined region;
  • a material comprising the first type of dopant is epitaxially grown in the first etched region to form the source region.
  • the step of “forming a pocket type on a side of the substrate adjacent to the source region” includes:
  • the first type of dopant doping is performed at a second doping concentration in a region of the first predetermined region adjacent to the patterned first mask layer to form the pocket region.
  • the step of “forming a drain region on the other side of the substrate” includes:
  • Patterning the second mask layer removing a side of the second mask layer away from the source region, and obtaining a patterned second mask layer to expose the substrate to a second preset a region, the second preset area does not overlap the first preset area;
  • a second type of dopant doping is performed in the second predetermined region to form the drain region.
  • the step of “forming a drain region on the other side of the substrate” includes:
  • Patterning the second mask layer removing a side of the second mask layer away from the source region, and obtaining a patterned second mask layer to expose the substrate to a second preset a region, the second preset area does not overlap the first preset area;
  • a material containing the second type of dopant is epitaxially grown in the second etched region to form the drain region.
  • the step of “forming an epitaxial layer on the source region, the pocket region, the channel, and the drain region” includes:
  • the source region includes a first concentration of the first type of dopant that is greater than a second concentration of the first type of dopant included in the pocket region.
  • the doping concentration of the source region is greater than the doping concentration of the pocket region, tunneling between the source region and the channel can be suppressed, and since the doping concentration of the pocket region is small, the pocket region and the channel can be avoided. Tunneling wear.
  • the first type of dopant is a P type dopant
  • the second type of dopant is an N type dopant
  • the first type of dopant is an N-type dopant and the second type of dopant is a P-type dopant.
  • the tunneling path length of the point tunneling is increased, thereby reducing the point tunneling current, thereby reducing the tunneling field effect transistor. Subthreshold swing.
  • FIG. 1 is a cross-sectional view of a tunneling field effect transistor disclosed in an embodiment of the present invention
  • FIG. 2 is a schematic diagram of energy band distribution in a tunneling field effect transistor according to an embodiment of the invention
  • FIG. 3 is a cross-sectional view of another tunneling field effect transistor disclosed in an embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a method for fabricating a tunneling field effect transistor according to an embodiment of the invention.
  • FIG. 5 is a schematic diagram of a substrate provided in a flow of a method for fabricating a tunneling field effect transistor according to an embodiment of the invention
  • FIG. 6 is a schematic diagram of forming a source region in a flow of a method for fabricating a tunneling field effect transistor according to an embodiment of the invention
  • FIG. 7 is a schematic diagram of forming a pocket type region in a flow of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of forming a drain region in a flow of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention
  • FIG. 9 is a flow chart of a method for fabricating a tunneling field effect transistor according to an embodiment of the invention. a schematic diagram of a gated stacked layer and sidewalls;
  • FIG. 10 is a schematic diagram of filling a low dielectric constant material in a flow of a method for fabricating a tunneling field effect transistor according to an embodiment of the invention.
  • FIG. 11 is a schematic diagram of forming a source, a gate, and a drain in a flow of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention
  • FIG. 12 is a schematic flow chart of another method for fabricating a tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram of forming an epitaxial layer in a flow of another method for fabricating a tunneling field effect transistor according to an embodiment of the present invention
  • FIG. 14 is a schematic diagram of forming a gate stack layer and sidewalls in a flow of another method of fabricating a tunneling field effect transistor according to an embodiment of the invention.
  • FIG. 15 is a schematic diagram of filling a low dielectric constant material in a flow of another method for fabricating a tunneling field effect transistor according to an embodiment of the invention.
  • 16 is a schematic diagram of forming a source, a gate, and a drain in a flow of another method of fabricating a tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 1 is a cross-sectional view of a tunneling field effect transistor disclosed in an embodiment of the present invention.
  • the tunneling field effect transistor 1 includes a substrate 10, a source region 20, a drain region 30, a channel 40, a pocket type region 50, a gate stack layer 60, and sidewalls 70, wherein the source region 20, the drain region 30, and the channel 40.
  • the pocket-type region 50, the gate stack layer 60, and the sidewalls 70 are disposed directly or indirectly on the substrate 10.
  • the source region 20 and the drain region 30 are disposed on the substrate 10, the region between the source region 20 and the drain region 30 is the channel 40, and the pocket region 50 is formed between the source region 20 and the channel 40, and the source region 20 and the pocket
  • the pattern regions 50 each comprise a first type of dopant and the drain region 30 comprises a second type of dopant;
  • the gate stack layer 60 is disposed on the source region 20, the pocket region 50, and the channel 40; the sidewalls 70 are disposed on both sides of the gate stack layer 60.
  • the substrate 10 may be a silicon (Si) substrate.
  • the substrate 10 may also be a germanium (Ge) or silicon germanium, gallium arsenide or the like group IV, or a group III-V, or a group IV-VI binary or ternary compound semiconductor, on an insulating substrate. Any of silicon (Silicon on Insulator, SOI) or silicon germanium on an insulating substrate.
  • a pocket 50 is used to delay the generation of point tunneling in a Tunnel Field-Effect Transistor (TFET), which can reduce the subthreshold swing of the TFFT.
  • TFET Tunnel Field-Effect Transistor
  • the volume of the pocket region 50 is much smaller than the volume of the source region 20.
  • FIG. 2 is a schematic diagram of energy band distribution in a tunneling field effect transistor according to an embodiment of the present invention.
  • the solid line in FIG. 2 is a source region of a tunneling field effect transistor when there is no pocket region 50.
  • Schematic diagram of the energy band distribution in (Source), channel, and drain; the dotted line in FIG. 2 is the source region (channel) and channel of the field effect transistor when there is a pocket region 50.
  • the abscissa is the position, the ordinate is the energy, Ec is the conduction band energy, and Ev is the valence band energy.
  • Fig. 2 the abscissa is the position, the ordinate is the energy, Ec is the conduction band energy, and Ev is the valence band energy.
  • the channel is close to The energy band bending at the position of the source region is reduced, and the tunneling path length of the point tunneling is increased (d2>d1), thereby reducing the point tunneling current, thereby reducing the subthreshold pendulum of the tunneling field effect transistor. Width.
  • the material of the channel 40 is the same as the material of the substrate 10.
  • the source region 20 may be formed by forming a first hard mask on one surface of the substrate 10, and exposing on one surface of the substrate 10 without being first masked The first predetermined area covered by the film layer.
  • the mask layer has a function of protecting the surface region of the substrate covered by it from being doped, and therefore, the surface and surface of the substrate covered by the mask layer when doping the surface of the substrate on which the mask layer is disposed The following portions are not doped, and the surface of the substrate not covered by the mask layer is doped due to no protection.
  • the source region 20 can be formed by doping the first type dopant at the first doping concentration in the first predetermined region.
  • the pocket region 50 may be formed by incorporating the first region at a second doping concentration in a region of the first predetermined region close to the first mask layer.
  • the dopants are doped to form pocket-type regions 50.
  • the drain region 30 may be formed by forming a second mask layer on one surface of the substrate 10 on one surface of the substrate 10. Exposing a second preset region not covered by the second mask layer, wherein the second preset region does not overlap with the first preset region, and the second type of dopant doping is performed in the second predetermined region, A drain region 30 is formed.
  • the gate stack layer 60 may include a gate dielectric layer 601 and a gate region 602.
  • the gate dielectric layer 601 is disposed on the source region 20, the pocket region 50, and the channel 40.
  • the gate region 602 is disposed on the gate dielectric layer 601.
  • the gate dielectric layer 601 may include a high dielectric constant dielectric such as silicon dioxide or hafnium oxide.
  • the sidewalls 70 can be used to isolate the gate region 602 from the source region 20, the drain region 30.
  • source region 20 includes a first dopant concentration of the first type of dopant that is greater than a second dopant concentration of the first type of dopant included in pocket region 50.
  • the doping concentration of the source region 20 is greater than the doping concentration of the pocket region 50, tunneling between the source region 20 and the channel 40 can be suppressed, and since the doping concentration of the pocket region 50 is small, the pocket type can be avoided. Tunneling occurs between region 50 and channel 40.
  • the tunneling field effect transistor further includes an electrode corresponding to the source region 20, the drain region 30, and the gate region 602 to form a source 80, a drain 90, and a gate 100.
  • the source 80 and the drain 90 are filled with a low dielectric constant material 110.
  • the first type of dopant is a P type dopant
  • the second type of dopant is an N type dopant
  • the first type of dopant is an N-type dopant and the second type of dopant is a P-type dopant.
  • the P-type dopant may include at least one of boron ions and BF 2 ; the N-type dopant may include at least one of phosphorus ions, arsenic ions, and cerium ions.
  • the first type of dopant is a P-type dopant and the second type of dopant is an N-type dopant, that is, the source region 20 is P-type doped, and the drain region 30 is N-type doped.
  • the field effect transistor 1 is an N-type tunneling field effect transistor (NTFFT); when the first type of dopant is an N type dopant and the second type of dopant is a P type dopant, that is, the source region 20 is N-type doping, the drain region 30 is P-type doped, and the tunneling field effect transistor 1 is a P-type tunneling field effect transistor (PTFFT).
  • NTFFT N-type tunneling field effect transistor
  • the voltage signal loaded when the drain region 30 operates is a forward bias voltage
  • the voltage signal loaded when the source region 20 operates is a negative bias voltage
  • the voltage signal loaded during operation of the drain region 30 is a negative bias voltage
  • the voltage signal loaded during operation of the source region 20 is a forward bias voltage.
  • the tunneling path length of the point tunneling is increased, thereby reducing the point tunneling current, thereby reducing the tunneling effect.
  • the subthreshold swing of the transistor is formed by forming the pocket type region 50 between the source region 20 and the channel 40.
  • FIG. 3 is a cross-sectional view of another tunneling field effect transistor disclosed in the embodiment of the present invention.
  • FIG. 3 is further optimized on the basis of FIG. 1, and the tunneling field effect transistor is shown in FIG. 1 includes a substrate 10, a source region 20, a drain region 30, a channel 40, a pocket-type region 50, a gate stack layer 60, sidewalls 70, and an epitaxial layer 120, wherein the source region 20, the drain region 30, the channel 40, The pocket region 50, the gate stack layer 60, the sidewalls 70, and the epitaxial layer 120 are disposed directly or indirectly on the substrate 10.
  • the source region 20 and the drain region 30 are disposed on the substrate 10, the region between the source region 20 and the drain region 30 is the channel 40, and the pocket region 50 is formed between the source region 20 and the channel 40, and the source region 20 and the pocket
  • the pattern regions 50 each comprise a first type of dopant
  • the drain region 30 comprises a second type of dopant
  • the epitaxial layer 120 is disposed over the source region 20, the pocket region 50, the channel 40, and the drain region 30
  • the gate stack layer 60 The sidewalls 70 are disposed on both sides of the gate stack layer 60.
  • the substrate 10 may be a silicon (Si) substrate.
  • the substrate 10 may also be a germanium (Ge) or silicon germanium, gallium arsenide or the like group IV, or a group III-V, or a group IV-VI binary or ternary compound semiconductor, on an insulating substrate. Any of silicon (Silicon on Insulator, SOI) or silicon germanium on an insulating substrate.
  • SOI silicon on Insulator
  • the sidewalls 70 can be used to protect the gate stack layer 60.
  • a pocket 50 is used to delay the generation of point tunneling in a Tunnel Field-Effect Transistor (TFET), which can reduce the subthreshold swing of the TFFT (far less than 60 mV/dec).
  • TFET Tunnel Field-Effect Transistor
  • the epitaxial layer 120 may be a chemical vapor deposition (CVD), an atomic layer deposition (ALD), or a molecular beam epitaxy (Molecular Beam). Epitaxy, MBE, etc. may be formed, and the epitaxial layer 120 may be undoped or doped with a second type of dopant (the same type of dopant as the drain region 30 is doped).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • Molecular Beam molecular beam epitaxy
  • Epitaxy, MBE, etc. may be formed, and the epitaxial layer 120 may be undoped or doped with a second type of dopant (the same type of dopant as the drain region 30 is doped).
  • the use of an epitaxial layer can increase the energy band bending in the overlap region of the gate source, thereby reducing the subthreshold swing and increasing the tunneling current.
  • the gate stack layer 60 may include a gate dielectric layer 601 and a gate region 602.
  • the gate dielectric layer 601 is disposed on the epitaxial layer 120, and the gate region 602 is disposed on the gate dielectric layer 601.
  • the tunneling field effect transistor further includes an electrode corresponding to the source region 20, the drain region 30, and the gate region 602 to form a source 80, a drain 90, and a gate 100.
  • the source 80 and the drain 90 are filled with a low dielectric constant material 110.
  • source region 20 includes a first dopant concentration of the first type of dopant that is greater than a second dopant concentration of the first type of dopant included in pocket region 50.
  • the doping concentration of the source region 20 is greater than the doping concentration of the pocket region 50, tunneling between the source region 20 and the channel 40 can be suppressed, and since the doping concentration of the pocket region 50 is small, the pocket type can be avoided. Tunneling occurs between region 50 and channel 40.
  • the first type of dopant is a P type dopant
  • the second type of dopant is an N type dopant
  • the first type of dopant is an N-type dopant and the second type of dopant is a P-type dopant.
  • the P-type dopant may include at least one of boron ions BF 2 ; the N-type dopant may include at least one of phosphorus ions, arsenic ions, and cerium ions.
  • the method of forming the source region 20, the drain region 30, and the pocket type region 50 in FIG. 3 is the same as that of FIG. 1, and details are not described herein again.
  • the tunneling path length of the point tunneling is increased, thereby reducing the point tunneling current, thereby reducing the tunneling field.
  • the subthreshold swing of the effect transistor is formed by forming the pocket type region 50 between the source region 20 and the channel 40.
  • FIG. 4 is a schematic flow chart of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention. As shown in FIG. 4, the method includes the following steps.
  • a substrate 10 is provided.
  • the substrate 10 may be a silicon (Si) substrate.
  • the substrate 10 may also be a germanium (Ge) or silicon germanium, gallium arsenide or the like group IV, or a group III-V, or a group IV-VI binary or ternary compound semiconductor, on an insulating substrate. Any of silicon (Silicon on Insulator, SOI) or silicon germanium on an insulating substrate.
  • a source region 20 is formed on one side of the substrate 10.
  • the doping may be performed by ion implantation.
  • the source region 20 is formed on one side of the substrate 10 in a specific manner: a first mask layer is formed on one surface of the substrate 10; Patterning the first mask layer, removing one side of the first mask layer, and obtaining a patterned first mask layer (a in FIG. 6) to expose the substrate 10 to the first predetermined region;
  • the first predetermined region is doped with the first type of dopant according to the first doping concentration to form the source region 20.
  • the position of the first predetermined area may be defined by photolithography to facilitate doping the first predetermined area to form the source region 20.
  • the source region may also be formed by etching, for example, forming a first mask layer on one surface of the substrate 10; patterning the first mask layer, removing one side of the first mask layer, and obtaining a pattern a first mask layer (a in FIG. 6) to expose the substrate 10 to the first predetermined region; etching the substrate 10 in the first predetermined region to form a first etch region, An etched region epitaxially grows a material containing a first type of dopant (wherein the material of the source region may be the same as or different from the substrate, for example, the material of the substrate is Si, and the material of the source region may be Si, also It may be SiGe) to form the source region 20.
  • etching for example, forming a first mask layer on one surface of the substrate 10; patterning the first mask layer, removing one side of the first mask layer, and obtaining a pattern a first mask layer (a in FIG. 6) to expose the substrate 10 to the first predetermined region; etching the substrate 10 in
  • In-situ doping is performed while epitaxial growth, for example, when epitaxial growth is performed by chemical vapor deposition, a first type of dopant is added to the reaction gas to form a source region.
  • the position of the first predetermined area may be defined by photolithography to facilitate doping the first predetermined area to form the source region 20.
  • a pocket-shaped region 50 is formed on the substrate 10 on a side close to the source region 20.
  • the manner of forming the pocket-shaped region 50 on the side of the substrate 10 adjacent to the source region 20 is specifically: after performing step 402, approaching the patterned first mask layer in the first predetermined region.
  • the region (a in Figure 7) is doped with a first type of dopant in accordance with a second doping concentration to form a pocket-type region.
  • a first type of dopant can be implanted at the interface of source region 20 and channel 40 with a certain angle of inclination to form a pocket-type region.
  • a drain region 30 is formed on the other side of the substrate 10, and a region between the source region 20 and the drain region 30 is a channel 40; wherein the source region 20 and the pocket region 50 each comprise a first type of dopant
  • the drain region 30 contains a second type of dopant.
  • the drain region may be doped by ion implantation.
  • the manner of forming the drain region 30 on the other side of the substrate 10 is specifically: after performing step 403, after patterning is removed a first mask layer, forming a second mask layer on one surface of the substrate 10; patterning the second mask layer, removing a side of the second mask layer away from the source region, and obtaining a patterned pattern a second mask layer (b in FIG. 8) to expose the substrate 10 to the second predetermined region, the second predetermined region does not overlap the first predetermined region; and the second type of blending is performed in the second predetermined region
  • the impurities are doped to form a drain region 30.
  • the position of the second predetermined area may be defined by photolithography to facilitate doping the second predetermined area to form the drain region 30.
  • the drain region can also be formed by etching.
  • the drain region 30 is formed on the other side of the substrate 10, specifically: after performing step 403, the patterned first mask layer is removed. Forming a second mask layer on one surface of the substrate 10; patterning the second mask layer, removing a side of the second mask layer away from the source region, to obtain a patterned second mask layer (in FIG.
  • the b) is such that the substrate 10 is exposed to the second predetermined area, the second predetermined area does not overlap with the first predetermined area; and the substrate 10 is etched in the second predetermined area to form a second Etching region; epitaxially growing a material containing a second type of dopant in the second etch region (wherein the material of the source region may be the same as or different from the substrate, for example, the material of the substrate is Si, the material of the source region It may be Si or SiGe) to form the drain region 30.
  • In-situ doping is performed while epitaxial growth, for example, when epitaxial growth is performed by chemical vapor deposition, a second type of dopant is added to the reaction gas to form a drain region.
  • the position of the second predetermined area may be defined by photolithography to facilitate doping the second predetermined area to form the drain region 30.
  • the first doping concentration of the first type dopants included in the source region 20 is greater than the second doping concentration of the first type dopants included in the pocket region 50.
  • the doping concentration of the source region 20 is greater than the doping concentration of the pocket region 50, tunneling between the source region 20 and the channel 40 can be suppressed, and since the doping concentration of the pocket region 50 is small, the pocket can be avoided. Tunneling occurs between the pattern 50 and the channel 40.
  • the first type of dopant is a P type dopant
  • the second type of dopant is an N type dopant
  • the first type of dopant is an N-type dopant and the second type of dopant is a P-type dopant.
  • source region 20 and pocket region 50 are both doped with a P-type dopant, and drain region 30 is doped with an N-type dopant; or source region 20 and pocket-type region 50 are both doped with an N-type dopant, Zone 30 incorporates a P-type dopant.
  • the P-type dopant may include at least one of boron ions and BF 2 ; the N-type dopant may include at least one of phosphorus ions, arsenic ions, and cerium ions.
  • a gate stack layer 60 is formed over the source region 20, the pocket region 50, and the channel 40.
  • a gate stack layer 60 may be deposited over the source region 20, the pocket region 50, and the channel 40.
  • the gate stack layer 60 includes a gate dielectric layer 601 and a gate region 602. Specifically, a gate dielectric layer 601 and a gate region 602 may be sequentially deposited on the source region 20, the pocket region 50, and the channel 40.
  • the gate region 602 is disposed on the gate dielectric layer 601, and then the gate is defined by photolithography. The location where the stack layer is located.
  • sidewalls 70 are formed on both sides of the gate stack layer 60.
  • sidewalls 70 are formed on both sides of the gate stack layer 60, and the sidewalls 70 may be used to isolate the gate region 602 from the source region 20 and the drain region 30.
  • a low dielectric constant material 110 is filled around the gate stack layer 60 and the sidewalls 90.
  • step 408 the following steps may also be performed:
  • the source region 20, the drain region 30, and the gate region 602 form a source 80, a drain 90, and a gate 100, respectively.
  • the source 80, the drain 90, and the gate 100 are respectively connected to the source region 20, the drain region 30, and the gate electrode. Area 602 is connected.
  • a first through hole corresponding to the source region 20 may be formed on the low dielectric constant material 110, and the source electrode 80 is connected to the source region 20 through the first through hole; and a corresponding correspondence is formed on the low dielectric constant material 110.
  • the second via of the drain region 30, the drain 90 is connected to the drain region 30 through the second via hole; and the gate electrode 100 is formed on the gate region 602.
  • FIG. 12 is a schematic flow chart of another method for fabricating a tunneling field effect transistor according to an embodiment of the present invention. As shown in FIG. 12, the method includes the following steps.
  • a substrate 10 is provided.
  • a source region 20 is formed on one side of the substrate 10.
  • a pocket-shaped region 50 is formed on the side of the substrate 10 adjacent to the source region 20.
  • a drain region 30 is formed on the other side of the substrate 10, and a region between the source region 20 and the drain region 30 is a channel 40; wherein the source region 20 and the pocket region 50 each comprise a first type of dopant
  • the drain region 30 contains a second type of dopant.
  • an epitaxial layer 120 is formed on the source region 20, the pocket region 50, the channel 40, and the drain region 30.
  • an epitaxial layer can be formed on the source region 20, the pocket region 50, the channel 40, and the drain region 30. 120.
  • a thin oxide layer may be formed on the surfaces of the source region 20, the pocket region 50, and the drain region 30. If a thin oxide layer is formed, the thin oxide layer needs to be removed first, and then the epitaxial layer 120 is formed.
  • the epitaxial layer 120 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), etc., and the material of the epitaxial layer 120 may be undoped.
  • the substrate is either a substrate doped with a second type of dopant (the same type of dopant as the drain region 30 is doped).
  • the use of an epitaxial layer can increase the energy band bending in the overlap region of the gate source, thereby reducing the subthreshold swing and increasing the tunneling current.
  • a gate stack layer 60 is formed on the epitaxial layer 120.
  • sidewalls 70 are formed on both sides of the gate stack layer 60.
  • a gate stack layer 60 may be formed over the epitaxial layer 120, wherein the gate stack layer 60 includes a gate dielectric layer 601 and a gate region 602. Specifically, a gate dielectric layer 601 and a gate region 602 may be sequentially deposited on the epitaxial layer 120. The gate region 602 is disposed on the gate dielectric layer 601, and then the gate stack layer coverage region is defined by photolithography. As shown in FIG. 14, sidewalls 70 are formed on both sides of the gate stack layer 60, and the sidewalls 70 may be used to protect the gate stack layer 60.
  • a low dielectric constant material 110 is filled around the gate stack layer 60 and sidewalls 70.
  • step 1208 the following steps may also be performed:
  • the source region 20, the drain region 30, and the gate region 602 form a source 80, a drain 90, and a gate 100, respectively.
  • the source 80, the drain 90, and the gate 100 are respectively connected to the source region 20, the drain region 30, and the gate electrode. Area 602 is connected.
  • a first via hole corresponding to the source region 20 may be formed on the low dielectric constant material 110, and the source electrode 80 is connected to the source region 20 through the first via hole; a corresponding correspondence is formed on the low dielectric constant material 110.
  • Leakage zone 30 The second via, the drain 90 is connected to the drain region 30 through the second via; and the gate 100 is formed on the gate region 602.
  • Steps 1201 to 1204 in FIG. 12 may refer to step 401 to step 404 described in FIG. 4, and steps 1207 and 1208 may refer to step 406 and step 407 described in FIG. 4, and details are not described herein again.

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Abstract

一种隧穿场效应晶体管及其制作方法，该隧穿场效应晶体管包括衬底（10）；设置于衬底（10）上的源区（20）和漏区（30），源区（20）与漏区（30）之间的区域为沟道（40），源区（20）与沟道（40）之间形成口袋型区（50），源区（20）和口袋型区（50）均包含第一类掺杂物，漏区（30）包含第二类掺杂物；栅堆叠层（60），栅堆叠层（60）设置于源区（20）、口袋型区（50）以及沟道（40）上；侧壁（70），侧壁（70）设置于栅堆叠层（60）的两侧。该隧穿场效应晶体管，能够减小隧穿场效应晶体管的亚阈值摆幅。

Description

隧穿场效应晶体管及其制作方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种隧穿场效应晶体管及其制作方法。
背景技术
随着金属-氧化物-半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)尺寸的不断缩小，器件的功耗问题和可靠性性问题成为制约集成电路发展的重要因素。为了降低集成电路的功耗，隧穿场效应晶体管(Tunnel Field-Effect Transistor，TFET)得到了广泛的研究，在TFET中，载流子以带间隧穿的机制注入沟道中，可以实现比MOSFET更小的亚阈值摆幅(亚阈值摆幅是指晶体管在亚阈值状态下，漏极电流变化一个数量级时所需要的栅极电压的变化量。亚阈值摆幅越小，漏极电流随栅极电压变化越快，晶体管的开关特性越好。)，以使晶体管的供电电压降低，进而显著减小晶体管的功耗。
在线隧穿TFET中，栅极和源区之间有较大的重叠区域，在栅极上施加一定的电压时，在源区区内垂直于栅极的方向发生带间隧穿(称作线隧穿)由于这种隧穿的距离很小，因而线隧穿TFET可以实现较小的亚阈值摆幅和较大的隧穿电流。
然而，由于沟道中的掺杂浓度较小，在一定的栅极偏压下会产生比栅源重叠区更大的能带弯折，因此源区和沟道之间在较小的栅极电压下就会发生能带交叠，产生带间隧穿(称作点隧穿)。虽然点隧穿电流较小，但是点隧穿的开启电压更小，会导致亚阈值区内TFET的隧穿电流随栅极电压变化缓慢，导致亚阈值摆幅增大。
发明内容
本发明实施例公开了一种隧穿场效应晶体管及其制作方法，能够减小隧穿场效应晶体管的亚阈值摆幅。
本发明实施例第一方面公开一种隧穿场效应晶体管，包括：
衬底；
设置于所述衬底上的源区和漏区，所述源区与所述漏区之间的区域为沟道，所述源区与所述沟道之间形成口袋型区，所述源区和所述口袋型区均包含第一类掺杂物，所述漏区包含第二类掺杂物；
栅堆叠层，所述栅堆叠层设置于所述源区以及所述口袋型区以及所述沟道上；
侧壁，所述侧壁设置于所述栅堆叠层的两侧。
本发明实施例通过在源区与沟道之间形成口袋型区(pocket)，从而延缓隧穿场效应晶体管中的点隧穿的产生，可以减小隧穿场效应晶体管的亚阈值摆幅。
可选的，所述隧穿场效应晶体管还包括：
外延层，所述外延层设置于所述源区、所述口袋型区、所述沟道以及所述漏区上；
所述栅堆叠层设置于所述外延层上。
采用外延层可以增大栅源重叠区内的能带弯折，从而减小亚阈值摆幅，增大隧穿电流。
可选的，所述栅堆叠层包括栅介质层和栅极区，所述栅介质层设置于所述外延层上，所述栅极区设置于所述栅介质层上。
在外延层上设置栅介质层和栅极区，栅极偏压透过栅介质层改变外延层中的能带弯折程度，进而影响隧穿电流的大小。
其中，所述隧穿场效应晶体管还包括：
电极，所述电极对应连接所述源区、所述漏区以及所述栅极区，以形成源极、漏极以及栅极。
可选的，所述源区包含的第一类掺杂物的第一掺杂浓度大于所述口袋型区包含的第一类掺杂物的第二掺杂浓度。
当源区的掺杂浓度大于口袋型区的掺杂浓度时，可以抑制源区和沟道之间的隧穿，由于口袋型区的掺杂浓度较小，可以避免口袋型区与沟道之间发生隧穿。
可选的，所述第一类掺杂物为P型掺杂物，所述第二类掺杂物为N型掺杂物；或者，
所述第一类掺杂物为N型掺杂物，所述第二类掺杂物为P型掺杂物。
本发明实施例第二方面公开一种隧穿场效应晶体管的制作方法，包括：
提供衬底；
在所述衬底上的一侧形成源区；
在所述衬底上靠近所述源区的一侧形成口袋型区；
在所述衬底上的另一侧形成漏区，其中，所述源区与所述漏区之间的区域为沟道；
所述源区和所述口袋型区均包含第一类掺杂物，所述漏区包含第二类掺杂物；
在所述源区、所述口袋型区以及所述沟道上形成栅堆叠层；
在所述栅堆叠层的两侧形成侧壁；
在所述栅堆叠层和所述侧壁周围填充低介电常数材料。
本发明实施例通过在源区与沟道之间形成口袋型区，口袋型区(pocket)用于延缓隧穿场效应晶体管中的点隧穿的产生，可以减小隧穿场效应晶体管的亚阈值摆幅。
可选的，在所述“在所述衬底上的另一侧形成漏区”步骤之后，并且在所述“在所述源区、所述口袋型区以及所述沟道上形成栅堆叠层”步骤之前，所述方法还包括：
在所述源区、所述口袋型区、所述沟道以及所述漏区上形成外延层；
在所述外延层上形成所述栅堆叠层。
采用外延层可以增大栅源重叠区内的能带弯折，从而减小亚阈值摆幅，增大隧穿电流。
可选的，所述栅堆叠层包括栅介质层和栅极区，所述“在所述外延层上形成栅堆叠层”步骤包括：
在所述外延层上形成所述栅介质层，在所述栅介质层上形成所述栅极区，并通过光刻定义所述栅堆叠层所在的区域。
其中，所述方法还包括：
对应所述源区、所述漏区以及所述栅极区分别形成源极、漏极以及栅极，所述源极、所述漏极以及所述栅极分别与所述源区、所述漏区以及所述栅极区连接。
可选的，所述“在所述衬底上的一侧形成源区”步骤包括：
在所述衬底上的一个表面形成第一掩膜层；
图案化所述第一掩膜层，移除所述第一掩膜层的一侧，得到图案化后的第一掩膜层，以使所述衬底露出第一预设区域；
在所述第一预设区域按照第一掺杂浓度进行第一类掺杂物掺杂，以形成所述源区。
可选的，所述“在所述衬底上的一侧形成源区”步骤包括：
在所述衬底上的一个表面形成第一掩膜层；
图案化所述第一掩膜层，移除所述第一掩膜层的一侧，得到图案化后的第一掩膜层，以使所述衬底露出第一预设区域；
在所述第一预设区域对所述衬底进行刻蚀，形成第一刻蚀区域；
在所述第一刻蚀区域外延生长包含所述第一类掺杂物的材料，以形成所述源区。
可选的，所述“在所述衬底上靠近所述源区的一侧形成口袋型区”步骤包括：
在所述第一预设区域靠近所述图案化后的第一掩膜层的区域按照第二掺杂浓度进行所述第一类掺杂物掺杂，以形成所述口袋型区。
可选的，所述“在所述衬底上的另一侧形成漏区”步骤包括：
移除所述图案化后的第一掩膜层，在所述衬底上的所述一个表面形成第二掩膜层；
图案化所述第二掩膜层，移除所述第二掩膜层远离所述源区的一侧，得到图案化后的第二掩膜层，以使所述衬底露出第二预设区域，所述第二预设区域与所述第一预设区域没有交叠；
在所述第二预设区域进行第二类掺杂物掺杂，以形成所述漏区。
可选的，所述“在所述衬底上的另一侧形成漏区”步骤包括：
移除所述图案化后的第一掩膜层，在所述衬底上的所述一个表面形成第二掩膜层；
图案化所述第二掩膜层，移除所述第二掩膜层远离所述源区的一侧，得到图案化后的第二掩膜层，以使所述衬底露出第二预设区域，所述第二预设区域与所述第一预设区域没有交叠；
在所述第二预设区域进行对所述衬底进行刻蚀，形成第二刻蚀区域；
在所述第二刻蚀区域外延生长包含所述第二类掺杂物的材料，以形成所述漏区。
可选的，所述“在所述源区、所述口袋型区、所述沟道以及所述漏区上形成外延层”步骤包括：
移除所述图案化后的第二掩膜层，去除所述衬底上的所述一个表面的氧化层，在所述源区、所述口袋型区、所述沟道以及所述漏区上形成所述外延层。
可选的，所述源区包含的第一类掺杂物的第一浓度大于所述口袋型区包含的第一类掺杂物的第二浓度。
当源区的掺杂浓度大于口袋型区的掺杂浓度时，可以抑制源区和沟道之间的隧穿，由于口袋型区的掺杂浓度较小，可以避免口袋型区与沟道之间发生隧 穿。
可选的，所述第一类掺杂物为P型掺杂物，所述第二类掺杂物为N型掺杂物；或者，
所述第一类掺杂物为N型掺杂物，所述第二类掺杂物为P型掺杂物。
本发明实施例中，通过在源区与沟道之间形成口袋型区，造成点隧穿的隧穿路径长度增加，从而减小了点隧穿电流，进而可以减小隧穿场效应晶体管的亚阈值摆幅。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例公开的一种隧穿场效应晶体管的剖视图；
图2是本发明实施例公开的一种隧穿场效应晶体管中的能带分布示意图；
图3是本发明实施例公开的另一种隧穿场效应晶体管的剖视图；
图4是本发明实施例公开的一种隧穿场效应晶体管的制作方法的流程示意图；
图5是本发明实施例公开的一种隧穿场效应晶体管的制作方法的流程中提供衬底的示意图；
图6是本发明实施例公开的一种隧穿场效应晶体管的制作方法的流程中形成源区的示意图；
图7是本发明实施例公开的一种隧穿场效应晶体管的制作方法的流程中形成口袋型区的示意图；
图8是本发明实施例公开的一种隧穿场效应晶体管的制作方法的流程中形成漏区的示意图；
图9是本发明实施例公开的一种隧穿场效应晶体管的制作方法的流程中形 成栅堆叠层以及侧壁的示意图；
图10是本发明实施例公开的一种隧穿场效应晶体管的制作方法的流程中填充低介电常数材料的示意图；
图11是本发明实施例公开的一种隧穿场效应晶体管的制作方法的流程中形成源极、栅极以及漏极的示意图；
图12是本发明实施例公开的另一种隧穿场效应晶体管的制作方法的流程示意图；
图13是本发明实施例公开的另一种隧穿场效应晶体管的制作方法的流程中形成外延层的示意图；
图14是本发明实施例公开的另一种隧穿场效应晶体管的制作方法的流程中形成栅堆叠层以及侧壁的示意图；
图15是本发明实施例公开的另一种隧穿场效应晶体管的制作方法的流程中填充低介电常数材料的示意图；
图16是本发明实施例公开的另一种隧穿场效应晶体管的制作方法的流程中形成源极、栅极以及漏极的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1是本发明实施例公开的一种隧穿场效应晶体管的剖视图。隧穿场效应晶体管1包括衬底10、源区20、漏区30、沟道40、口袋型区50、栅堆叠层60、以及侧壁70，其中，源区20、漏区30、沟道40、口袋型区50、栅堆叠层60、以及侧壁70直接或间接设置在衬底10上。源区20和漏区30设置于衬底10上，源区20与漏区30之间的区域为沟道40，源区20与沟道40之间形成口袋型区50，源区20和口袋型区50均包含第一类掺杂物，漏区30包含第二类掺杂物； 栅堆叠层60设置于源区20、口袋型区50以及沟道40上；侧壁70设置于栅堆叠层60的两侧。
本发明实施例中，衬底10可以为硅(Si)衬底。在其他实施方式中，衬底10也可以为锗(Ge)或者硅锗、镓砷等IV族、或者III-V族、或者IV-VI族的二元或三元化合物半导体、绝缘衬底上的硅(Silicon on Insulator，SOI)、或者绝缘衬底上的硅锗中的任意一种。
口袋型区(pocket)50用于延缓隧穿场效应晶体管(Tunnel Field-Effect Transistor，TFET)中的点隧穿的产生，可以减小TFFT的亚阈值摆幅。一般而言，口袋型区50的体积远小于源区20的体积。
以下结合图2阐述口袋型区50的工作原理。请参阅图2，图2是本发明实施例公开的一种隧穿场效应晶体管中的能带分布示意图，图2中的实线为没有口袋型区50时，隧穿场效应晶体管的源区(Source)、沟道(Channel)和漏区(Drain)内的能带分布示意图；图2中的虚线为有口袋型区50时，隧穿场效应晶体管的源区(Source)、沟道(Channel)和漏区(Drain)内的能带分布示意图。图2中，横坐标为位置(position)，纵坐标为能量(Energy)，Ec为导带能量，Ev为价带能量，从图2中可以看出，增加口袋型区50之后，沟道内靠近源区的位置的能带弯折减小，造成点隧穿的隧穿路径长度增加(d2>d1)，从而减小了点隧穿电流，进而可以减小隧穿场效应晶体管的亚阈值摆幅。
在一种实施方式中，沟道40的材质与衬底10的材质相同。
在一种实施方式中，源区20可以由以下方式形成：在衬底10上的一个表面上形成第一掩膜层(hard mask)，在衬底10的一个表面上露出未被第一掩膜层覆盖的第一预设区域。掩膜层具有保护其所覆盖的衬底的表面区域不被掺杂的作用，因此，对设置掩膜层的衬底的表面进行掺杂时，被掩膜层覆盖的衬底的表面以及表面以下的部分不会被掺杂，而未被掩膜层覆盖的衬底的表面则由于没有保护而被掺杂。在上述第一预设区域按照第一掺杂浓度掺入第一类型掺杂物，即可形成源区20。
在一种实施方式中，在形成源区20的基础上，口袋型区50可以由以下方式形成：在第一预设区域靠近第一掩膜层的区域按照第二掺杂浓度掺入第一类掺杂物掺杂，以形成口袋型区50。
在一种实施方式中，在形成口袋型区50的基础上，漏区30可以由以下方式形成：在衬底10上的一个表面上形成第二掩膜层，在衬底10的一个表面上露出未被第二掩膜层覆盖的第二预设区域，其中，第二预设区域与第一预设区域没有交叠，在第二预设区域进行第二类掺杂物掺杂，以形成漏区30。
其中，栅堆叠层60可以包括栅介质层601和栅极区602，栅介质层601设置于源区20、口袋型区50以及沟道40上，栅极区602设置于栅介质层601上。栅介质层601可以包括二氧化硅以及氧化铪等高介电常数的电介质。侧壁70可以用于将栅极区602与源区20、漏区30隔离。
在一种实施方式中，源区20包含的第一类掺杂物的第一掺杂浓度大于口袋型区50包含的第一类掺杂物的第二掺杂浓度。当源区20的掺杂浓度大于口袋型区50的掺杂浓度时，可以抑制源区20和沟道40之间的隧穿，由于口袋型区50的掺杂浓度较小，可以避免口袋型区50与沟道40之间发生隧穿。
隧穿场效应晶体管还包括电极，电极对应连接源区20、漏区30以及栅极区602，以形成源极80、漏极90以及栅极100。栅极100和源区20之间有较大的重叠面积，在栅极100上施加一定的偏压，源区20中在垂直于栅极方向会发生带间隧穿。其中，源极80和漏极90周围填充有低介电常数材料110。
可选的，第一类掺杂物为P型掺杂物，第二类掺杂物为N型掺杂物；或者，
第一类掺杂物为N型掺杂物，第二类掺杂物为P型掺杂物。
其中，P型掺杂物可以包括硼离子、BF2中的至少一种；N型掺杂物可以包括磷离子、砷离子、锑离子中的至少一种。当第一类掺杂物为P型掺杂物，第二类掺杂物为N型掺杂物时，即源区20为P型掺杂，漏区30为N型掺杂，此时隧穿场效应晶体管1为N型隧穿场效应晶体管(NTFFT)；当第一类掺杂物为N型掺杂物，第二类掺杂物为P型掺杂物时，即源区20为N型掺杂，漏区30为P型掺 杂，此时隧穿场效应晶体管1为P型隧穿场效应晶体管(PTFFT)。对于NTFFT来说，漏区30工作时加载的电压信号为正向偏置电压，源区20工作时加载的电压信号为负向偏置电压。对于PTFFT来说，漏区30工作时加载的电压信号为负向偏置电压，源区20工作时加载的电压信号为正向偏置电压。
本发明实施例中，通过在源区20与沟道40之间形成口袋型区50，造成点隧穿的隧穿路径长度增加，从而减小了点隧穿电流，进而可以减小穿场效应晶体管的亚阈值摆幅。
请参阅图3，图3是本发明实施例公开的另一种隧穿场效应晶体管的剖视图，图3是在图1的基础上进一步优化得到的，如图3所示，隧穿场效应晶体管1包括衬底10、源区20、漏区30、沟道40、口袋型区50、栅堆叠层60、侧壁70以及外延层120，其中，源区20、漏区30、沟道40、口袋型区50、栅堆叠层60、侧壁70以及外延层120直接或间接设置在衬底10上。源区20和漏区30设置于衬底10上，源区20与漏区30之间的区域为沟道40，源区20与沟道40之间形成口袋型区50，源区20和口袋型区50均包含第一类掺杂物，漏区30包含第二类掺杂物；外延层120设置于源区20、口袋型区50、沟道40以及漏区30上；栅堆叠层60设置于外延层120上；侧壁70设置于栅堆叠层60的两侧。
本发明实施例中，衬底10可以为硅(Si)衬底。在其他实施方式中，衬底10也可以为锗(Ge)或者硅锗、镓砷等IV族、或者III-V族、或者IV-VI族的二元或三元化合物半导体、绝缘衬底上的硅(Silicon on Insulator，SOI)、或者绝缘衬底上的硅锗中的任意一种。侧壁70可以用于保护栅堆叠层60。
口袋型区(pocket)50用于延缓隧穿场效应晶体管(Tunnel Field-Effect Transistor，TFET)中的点隧穿的产生，可以减小TFFT的亚阈值摆幅(远小于60mV/dec)。口袋型区50的工作原理请参见上述图2的描述。
外延层120可以采用化学气相沉积(Chemical Vapor Deposition，CVD)、原子层沉积(Atomic layer deposition，ALD)、分子束外延(Molecular Beam  Epitaxy，MBE)等形成，外延层120可以是不掺杂的或者是掺有第二类掺杂物(与漏区30掺入的掺杂物类型相同)。采用外延层可以增大栅源重叠区内的能带弯折，从而减小亚阈值摆幅，增大隧穿电流。
其中，栅堆叠层60可以包括栅介质层601和栅极区602，栅介质层601设置于外延层120上，栅极区602设置于栅介质层601上。
隧穿场效应晶体管还包括电极，电极对应连接源区20、漏区30以及栅极区602，以形成源极80、漏极90以及栅极100。栅极100和源区20之间有较大的重叠面积，在栅极100上施加一定的偏压，源区20和外延层120之间会发生带间隧穿。其中，源极80和漏极90周围填充有低介电常数材料110。
在一种实施方式中，源区20包含的第一类掺杂物的第一掺杂浓度大于口袋型区50包含的第一类掺杂物的第二掺杂浓度。当源区20的掺杂浓度大于口袋型区50的掺杂浓度时，可以抑制源区20和沟道40之间的隧穿，由于口袋型区50的掺杂浓度较小，可以避免口袋型区50与沟道40之间发生隧穿。
可选的，第一类掺杂物为P型掺杂物，第二类掺杂物为N型掺杂物；或者，
第一类掺杂物为N型掺杂物，第二类掺杂物为P型掺杂物。
其中，P型掺杂物可以包括硼离子BF2中的至少一种；N型掺杂物可以包括磷离子、砷离子、锑离子中的至少一种。
图3中的源区20、漏区30和口袋型区50的形成方法与图1相同，此处不再赘述。
本发明实施例中，通过在源区20与沟道40之间形成口袋型区50，造成点隧穿的隧穿路径长度增加，从而减小了点隧穿电流，进而可以减小隧穿场效应晶体管的亚阈值摆幅。
请参阅图4，图4是本发明实施例公开的一种隧穿场效应晶体管的制作方法的流程示意图，如图4所示，该方法包括如下步骤。
401，提供衬底10。
如图5所示，衬底10可以为硅(Si)衬底。在其他实施方式中，衬底10也可以为锗(Ge)或者硅锗、镓砷等IV族、或者III-V族、或者IV-VI族的二元或三元化合物半导体、绝缘衬底上的硅(Silicon on Insulator，SOI)、或者绝缘衬底上的硅锗中的任意一种。
402，在衬底10上的一侧形成源区20。
如图6所示，可以通过离子注入的方式进行掺杂，例如，在衬底10上的一侧形成源区20的方式具体为：在衬底10上的一个表面形成第一掩膜层；图案化第一掩膜层，移除第一掩膜层的一侧，得到图案化后的第一掩膜层(图6中的a)，以使衬底10露出第一预设区域；在第一预设区域按照第一掺杂浓度进行第一类掺杂物掺杂以形成源区20。可以利用光刻定义出第一预设区域的位置，方便对第一预设区域进行掺杂，以形成源区20。
还可以通过刻蚀的方式形成源区，例如，在衬底10上的一个表面形成第一掩膜层；图案化第一掩膜层，移除第一掩膜层的一侧，得到图案化后的第一掩膜层(图6中的a)，以使衬底10露出第一预设区域；在第一预设区域对衬底10进行刻蚀，形成第一刻蚀区域，在第一刻蚀区域外延生长包含第一类掺杂物的材料(其中，源区的材料可以和衬底相同，也可以不同，例如，衬底的材料是Si，源区的材料可以是Si，也可以是SiGe)，以形成源区20。外延生长的同时进行原位掺杂，例如，用化学气相沉积进行外延生长时，则在反应气体中加入第一类掺杂物，形成源区。可以利用光刻定义出第一预设区域的位置，方便对第一预设区域进行掺杂，以形成源区20。
403，在衬底10上靠近源区20的一侧形成口袋型区50。
如图7所示，在衬底10上靠近源区20的一侧形成口袋型区50的方式具体为：在执行步骤402之后，在第一预设区域靠近图案化后的第一掩膜层(图7中的a)的区域按照第二掺杂浓度进行第一类掺杂物掺杂，以形成口袋型区。如图7所示，可以采用一定的倾角在源区20与沟道40的交界处注入第一类掺杂物，以形成口袋型区。
404，在衬底10上的另一侧形成漏区30，源区20与漏区30之间的区域为沟道40；其中，源区20和口袋型区50均包含第一类掺杂物，漏区30包含第二类掺杂物。
如图8所示，可以通过离子注入的方式对漏区进行掺杂，例如，在衬底10上的另一侧形成漏区30的方式具体为：在执行步骤403之后，移除图案化后的第一掩膜层，在衬底10上的一个表面形成第二掩膜层；图案化第二掩膜层，移除第二掩膜层远离源区的一侧，得到图案化后的第二掩膜层(图8中的b)，以使衬底10露出第二预设区域，第二预设区域与第一预设区域没有交叠；在第二预设区域进行第二类掺杂物掺杂，以形成漏区30。可以利用光刻定义出第二预设区域的位置，方便对第二预设区域进行掺杂，以形成漏区30。
还可以通过刻蚀的方式形成漏区，例如，在衬底10上的另一侧形成漏区30的方式具体为：在执行步骤403之后，移除图案化后的第一掩膜层，在衬底10上的一个表面形成第二掩膜层；图案化第二掩膜层，移除第二掩膜层远离源区的一侧，得到图案化后的第二掩膜层(图8中的b)，以使衬底10露出第二预设区域，第二预设区域与第一预设区域没有交叠；在第二预设区域进行对衬底10进行刻蚀，形成第二刻蚀区域；在第二刻蚀区域外延生长包含第二类掺杂物的材料(其中，源区的材料可以和衬底相同，也可以不同，例如，衬底的材料是Si，源区的材料可以是Si，也可以是SiGe)以形成漏区30。外延生长的同时进行原位掺杂，例如，用化学气相沉积进行外延生长时，则在反应气体中加入第二类掺杂物，形成漏区。可以利用光刻定义出第二预设区域的位置，方便对第二预设区域进行掺杂，以形成漏区30。
其中，源区20包含的第一类掺杂物的第一掺杂浓度大于口袋型区50包含的第一类掺杂物的第二掺杂浓度。当源区20的掺杂浓度大于口袋型区50的掺杂浓度时，可以抑制源区20和沟道40之间的隧穿，同时由于口袋型区50的掺杂浓度较小，可以避免口袋型区50与沟道40之间发生隧穿。
其中，第一类掺杂物为P型掺杂物，第二类掺杂物为N型掺杂物；或者，
第一类掺杂物为N型掺杂物，第二类掺杂物为P型掺杂物。
例如，源区20和口袋型区50均掺入P型掺杂物，漏区30掺入N型掺杂物；或者，源区20和口袋型区50均掺入N型掺杂物，漏区30掺入P型掺杂物。
P型掺杂物可以包括硼离子、BF2的至少一种；N型掺杂物可以包括磷离子、砷离子、锑离子中的至少一种。
405，在源区20、口袋型区50以及沟道40上形成栅堆叠层60。
如图9所示，可以在源区20、口袋型区50以及沟道40上沉积形成栅堆叠层60。其中，栅堆叠层60包括栅介质层601和栅极区602。具体的，可以在源区20、口袋型区50以及沟道40上依次沉积栅介质层601和栅极区602，栅极区602设置于栅介质层601上，然后利用光刻的方法定义栅堆叠层所在的位置。
406，在栅堆叠层60的两侧形成侧壁70。
如图9所示，在栅堆叠层60的两侧形成侧壁70，侧壁70可以用于将栅极区602与源区20、漏区30隔离。
407，在栅堆叠层60和侧壁90周围填充低介电常数材料110。
可选的，在执行步骤408之后，还可以执行如下步骤：
对应源区20、漏区30以及栅极区602分别形成源极80、漏极90以及栅极100，源极80、漏极90以及栅极100分别与源区20、漏区30以及栅极区602连接。
如图11所示，可以在低介电常数材料110上开设对应源区20的第一贯孔，源极80穿过第一贯孔连接源区20；在低介电常数材料110上开设对应漏区30的第二贯孔，漏极90穿过第二贯孔连接漏区30；在栅极区602上形成栅极100。
请参阅图12，图12是本发明实施例公开的另一种隧穿场效应晶体管的制作方法的流程示意图，如图12所示，该方法包括如下步骤。
1201，提供衬底10。
1202，在衬底10上的一侧形成源区20。
1203，在衬底10上靠近源区20的一侧形成口袋型区50。
1204，在衬底10上的另一侧形成漏区30，源区20与漏区30之间的区域为沟道40；其中，源区20和口袋型区50均包含第一类掺杂物，漏区30包含第二类掺杂物。
1205，在源区20、口袋型区50、沟道40以及漏区30上形成外延层120。
如图13所示，在源区20、漏区30、沟道40以及口袋型区50都制作完毕后，可以在源区20、口袋型区50、沟道40以及漏区30上形成外延层120。在执行步骤406之前，在源区20、口袋型区50以及漏区30的表面可能会形成薄氧化层，如果形成了薄氧化层，需要先去除薄氧化层，然后形成外延层120。
外延层120可以采用化学气相沉积(Chemical Vapor Deposition，CVD)、原子层沉积(Atomic layer deposition，ALD)、分子束外延(Molecular Beam Epitaxy，MBE)等形成，外延层120的材料可以是不掺杂的衬底或者是掺有第二类掺杂物(与漏区30掺入的掺杂物类型相同)的衬底。采用外延层可以增大栅源重叠区内的能带弯折，从而减小亚阈值摆幅，增大隧穿电流。
1206，在外延层120上形成栅堆叠层60。
1207，在栅堆叠层60的两侧形成侧壁70。
如图14所示，可以在外延层120上形成栅堆叠层60，其中，栅堆叠层60包括栅介质层601和栅极区602。具体的，可以在外延层120上依次沉积栅介质层601和栅极区602，栅极区602设置于栅介质层601上，然后利用光刻定义出栅堆叠层覆盖区域。如图14所示，在栅堆叠层60的两侧形成侧壁70，侧壁70可以用于保护栅堆叠层60。
1208，在栅堆叠层60和侧壁70周围填充低介电常数材料110。
可选的，在执行步骤1208之后，还可以执行如下步骤：
对应源区20、漏区30以及栅极区602分别形成源极80、漏极90以及栅极100，源极80、漏极90以及栅极100分别与源区20、漏区30以及栅极区602连接。
如图16所示，可以在低介电常数材料110上开设对应源区20的第一贯孔，源极80穿过第一贯孔连接源区20；在低介电常数材料110上开设对应漏区30的 第二贯孔，漏极90穿过第二贯孔连接漏区30；在栅极区602上形成栅极100。
图12中的步骤1201至步骤1204可以参见图4所描述的步骤401至步骤404，步骤1207和步骤1208可以参见图4所描述的步骤406和步骤407，此处不再赘述。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此本发明的保护范围应该以权利要求的保护范围为准。

Claims (18)

  1. 一种隧穿场效应晶体管，其特征在于，包括：
    衬底；
    设置于所述衬底上的源区和漏区，所述源区与所述漏区之间的区域为沟道，所述源区与所述沟道之间形成口袋型区，所述源区和所述口袋型区均包含第一类掺杂物，所述漏区包含第二类掺杂物；
    栅堆叠层，所述栅堆叠层设置于所述源区、所述口袋型区以及所述沟道上；
    侧壁，所述侧壁设置于所述栅堆叠层的两侧。
  2. 根据权利要求1所述的隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管还包括：
    外延层，所述外延层设置于所述源区、所述口袋型区、所述沟道以及所述漏区上；
    所述栅堆叠层设置于所述外延层上。
  3. 根据权利要求2所述的隧穿场效应晶体管，其特征在于，所述栅堆叠层包括栅介质层和栅极区，所述栅介质层设置于所述外延层上，所述栅极区设置于所述栅介质层上。
  4. 根据权利要求3所述的隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管还包括：
    电极，所述电极对应连接所述源区、所述漏区以及所述栅极区，以形成源极、漏极以及栅极。
  5. 根据权利要求1-4任一项所述的隧穿场效应晶体管，其特征在于，
    所述源区包含的第一类掺杂物的第一掺杂浓度大于所述口袋型区包含的 第一类掺杂物的第二掺杂浓度。
  6. 根据权利要求1-5任一项所述的隧穿场效应晶体管，其特征在于，
    所述第一类掺杂物为P型掺杂物，所述第二类掺杂物为N型掺杂物；或者，
    所述第一类掺杂物为N型掺杂物，所述第二类掺杂物为P型掺杂物。
  7. 一种隧穿场效应晶体管的制作方法，其特征在于，包括：
    提供衬底；
    在所述衬底上的一侧形成源区；
    在所述衬底上靠近所述源区的一侧形成口袋型区；
    在所述衬底上的另一侧形成漏区，其中，所述源区与所述漏区之间的区域为沟道；
    所述源区和所述口袋型区均包含第一类掺杂物，所述漏区包含第二类掺杂物；
    在所述源区、所述口袋型区以及所述沟道上形成栅堆叠层；
    在所述栅堆叠层的两侧形成侧壁；
    在所述栅堆叠层和所述侧壁周围填充低介电常数材料。
  8. 根据权利要求7所述的方法，其特征在于，在所述“在所述衬底上的另一侧形成漏区”步骤之后，并且在所述“在所述源区、所述口袋型区以及所述沟道上形成栅堆叠层”步骤之前，所述方法还包括：
    在所述源区、所述口袋型区、所述沟道以及所述漏区上形成外延层；
    在所述外延层上形成所述栅堆叠层。
  9. 根据权利要求8所述的方法，其特征在于，所述栅堆叠层包括栅介质层和栅极区，所述“在所述外延层上形成栅堆叠层”步骤包括：
    在所述外延层上形成所述栅介质层，在所述栅介质层上形成所述栅极区，并通过光刻定义所述栅堆叠层所在的区域。
  10. 根据权利要求9所述的方法，其特征在于，所述方法还包括：
    对应所述源区、所述漏区以及所述栅极区分别形成源极、漏极以及栅极，所述源极、所述漏极以及所述栅极分别与所述源区、所述漏区以及所述栅极区连接。
  11. 根据权利要求8-10任一项所述的方法，其特征在于，所述“在所述衬底上的一侧形成源区”步骤包括：
    在所述衬底上的一个表面形成第一掩膜层；
    图案化所述第一掩膜层，移除所述第一掩膜层的一侧，得到图案化后的第一掩膜层，以使所述衬底露出第一预设区域；
    在所述第一预设区域按照第一掺杂浓度进行第一类掺杂物掺杂，以形成所述源区。
  12. 根据权利要求8-10任一项所述的方法，其特征在于，所述“在所述衬底上的一侧形成源区”步骤包括：
    在所述衬底上的一个表面形成第一掩膜层；
    图案化所述第一掩膜层，移除所述第一掩膜层的一侧，得到图案化后的第一掩膜层，以使所述衬底露出第一预设区域；
    在所述第一预设区域对所述衬底进行刻蚀，形成第一刻蚀区域；
    在所述第一刻蚀区域外延生长包含所述第一类掺杂物的材料，以形成所述源区。
  13. 根据权利要求11或12所述的方法，其特征在于，所述“在所述衬底上 靠近所述源区的一侧形成口袋型区”步骤包括：
    在所述第一预设区域靠近所述图案化后的第一掩膜层的区域按照第二掺杂浓度进行所述第一类掺杂物掺杂，以形成所述口袋型区。
  14. 根据权利要求13所述的方法，其特征在于，所述“在所述衬底上的另一侧形成漏区”步骤包括：
    移除所述图案化后的第一掩膜层，在所述衬底上的所述一个表面形成第二掩膜层；
    图案化所述第二掩膜层，移除所述第二掩膜层远离所述源区的一侧，得到图案化后的第二掩膜层，以使所述衬底露出第二预设区域，所述第二预设区域与所述第一预设区域没有交叠；
    在所述第二预设区域进行第二类掺杂物掺杂，以形成所述漏区。
  15. 根据权利要求13所述的方法，其特征在于，所述“在所述衬底上的另一侧形成漏区”步骤包括：
    移除所述图案化后的第一掩膜层，在所述衬底上的所述一个表面形成第二掩膜层；
    图案化所述第二掩膜层，移除所述第二掩膜层远离所述源区的一侧，得到图案化后的第二掩膜层，以使所述衬底露出第二预设区域，所述第二预设区域与所述第一预设区域没有交叠；
    在所述第二预设区域进行对所述衬底进行刻蚀，形成第二刻蚀区域；
    在所述第二刻蚀区域外延生长包含所述第二类掺杂物的材料，以形成所述漏区。
  16. 根据权利要求14或15所述的方法，其特征在于，所述“在所述源区、所述口袋型区、所述沟道以及所述漏区上形成外延层”步骤包括：
    移除所述图案化后的第二掩膜层，去除所述衬底上的所述一个表面的氧化层，在所述源区、所述口袋型区、所述沟道以及所述漏区上形成所述外延层。
  17. 根据权利要求7-16任一项所述的方法，其特征在于，所述源区包含的第一类掺杂物的第一浓度大于所述口袋型区包含的第一类掺杂物的第二浓度。
  18. 根据权利要求7-17任一项所述的方法，其特征在于，
    所述第一类掺杂物为P型掺杂物，所述第二类掺杂物为N型掺杂物；或者，
    所述第一类掺杂物为N型掺杂物，所述第二类掺杂物为P型掺杂物。
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CN102623495B (zh) * 2012-04-09 2014-04-30 北京大学 一种多掺杂口袋结构的隧穿场效应晶体管及其制备方法
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