WO2015085825A1 - Procédés et appareil d'étalonnage de fréquence - Google Patents

Procédés et appareil d'étalonnage de fréquence Download PDF

Info

Publication number
WO2015085825A1
WO2015085825A1 PCT/CN2014/088791 CN2014088791W WO2015085825A1 WO 2015085825 A1 WO2015085825 A1 WO 2015085825A1 CN 2014088791 W CN2014088791 W CN 2014088791W WO 2015085825 A1 WO2015085825 A1 WO 2015085825A1
Authority
WO
WIPO (PCT)
Prior art keywords
control word
calibrated
clock
hopping
count value
Prior art date
Application number
PCT/CN2014/088791
Other languages
English (en)
Chinese (zh)
Inventor
许应新
Original Assignee
炬芯（珠海）科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 炬芯（珠海）科技有限公司 filed Critical 炬芯（珠海）科技有限公司
Publication of WO2015085825A1 publication Critical patent/WO2015085825A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the present application relates to the field of integrated circuit technologies, and in particular, to a frequency calibration method and apparatus.
  • Automatic frequency control is an automatic control method that keeps the output signal frequency in a certain relationship with a given frequency. It is widely used in electronic equipment for frequency stabilization or phase locking. Specifically used in the Phase Locked Loop (PLL), the PLL output clock with little deviation from the reference clock is frequency-calibrated, so that the PLL outputs a more accurate clock.
  • PLL Phase Locked Loop
  • a common automatic frequency control method in PLL is to digitally control the oscillator capacitance to adjust the oscillation frequency of the oscillator.
  • a counter can be used to compare the clock frequency to be calibrated (ie, the oscillation frequency of the oscillator) with the reference clock frequency, and accordingly adjust the output control word for controlling the oscillator capacitance according to the comparison result, thereby adjusting the oscillation frequency.
  • the reference clock and the clock to be calibrated are counted simultaneously for a period of time.
  • the clock to be calibrated is considered to be slow, and the output control word is adjusted to decrement the control word by 1, thereby speeding up the calibration.
  • the frequency of the clock Conversely, if the clock counter to be calibrated reaches the preset value first, the clock to be calibrated is considered to be faster, and the output control word is adjusted to increase the control word by one. Repeat the calibration according to this method until the calibration clock is equal to the reference clock.
  • the existing automatic frequency control has the following problems:
  • the counting time of the counter is relatively long: the output control word is adjusted when one of the counters counts to a predetermined value, and the analysis from the circuit shows that the predetermined value is not well determined, because if the predetermined value is set too small, the accuracy of the frequency adjustment will be affected. degree. If the preset value is set too large, the frequency adjustment time is increased.
  • the control word can only be jumped by adding 1 or subtracting 1.
  • the jump mode is not flexible, and the frequency adjustment efficiency is low.
  • the purpose of the present application is to provide a frequency calibration method and apparatus to solve the problem that the counter has a long counting time.
  • a frequency calibration method comprising:
  • the method provided by the embodiment of the present application compares two count values in real time. As long as the count values of the two counters are different, the control word can be output to adjust the frequency of the clock to be calibrated without affecting the accuracy of the frequency adjustment. Improve the efficiency of frequency adjustment.
  • the count value of the clock counter to be calibrated is compared with the count value of the reference clock counter in real time in the reference clock domain.
  • the format of the count value of the clock counter to be calibrated is converted from a binary number to a Gray code; in the reference clock domain, the count value of the clock counter to be calibrated converted to the Gray code is performed.
  • the delay for canceling the metastable state is converted into a binary number; in the reference clock domain, after the delay value of the clock counter to be calibrated converted to a binary number is used to control the timing delay, the same delay is performed.
  • the count value of the reference clock counter is compared.
  • the same delay refers to the delay performed by the count value of the reference clock counter, and the delay for canceling the metastable state and the delay for controlling the timing are the same as the count value of the clock counter to be calibrated.
  • the specific implementation manner of outputting the control word for adjusting the clock frequency to be calibrated according to the comparison result may be, but is not limited to: When the count value of the reference clock counter is greater than the count value of the clock counter to be calibrated but less than the preset count threshold, outputting a control word for raising the clock frequency to be calibrated; when the count value of the clock counter to be calibrated is When the count value of the reference clock counter is greater than the preset count threshold, the control word for lowering the clock frequency to be calibrated is output.
  • condition for outputting the control word for increasing the clock frequency to be calibrated further comprises: the count value of the reference clock counter is greater than the count value +1 of the clock counter to be calibrated; and the output is used to lower the clock to be calibrated
  • condition of the frequency control word further includes: the count value of the clock counter to be calibrated is greater than the count value +1 of the reference clock counter.
  • control word for adjusting the clock frequency to be calibrated when the control word for adjusting the clock frequency to be calibrated is output according to the comparison result, the control word for adjusting the clock frequency to be calibrated may be output by using a binary method according to the comparison result; or According to the comparison result, the control word for adjusting the clock frequency to be calibrated is output by using the 1/4 hopping method; or, according to the comparison result, the control word for adjusting the clock frequency to be calibrated is output by adding 2 minus 1 hopping method.
  • a plurality of control word hopping modes are set in advance, preferably, before outputting the control word for adjusting the clock frequency to be calibrated according to the comparison result, the following operations may be included: when the cumulative number of hops of the control word does not reach the maximum When the number of transitions is changed, according to the difference between the clock frequency to be calibrated and the reference clock frequency, the control word hopping mode adopted by the output control word is selected from the preset N kinds of control word hopping modes, wherein the larger the difference is The longer the jump step of the selected control word hopping mode, N is not small An integer of 2; correspondingly, outputting a control word for adjusting a clock frequency to be calibrated according to the comparison result may be: outputting a control for adjusting a clock frequency to be calibrated by using a selected control word hopping manner according to the comparison result word.
  • the clock stability waiting time corresponding to the selected control word hopping mode may be determined according to the corresponding relationship between the preset control word hopping mode and the clock stability waiting time to be calibrated, as This output control word adjusts the clock to be calibrated and waits for the clock to be calibrated to stabilize.
  • the longer the hopping step of the selected control word hopping mode, the longer the waiting time of the corresponding clock to be calibrated, or the longer the hopping step of the selected control word hopping mode, the corresponding clock to be calibrated The shorter the stabilization wait time.
  • the embodiment of the present application further provides a frequency calibration apparatus, including:
  • the control word output module is configured to output a control word for adjusting a clock frequency to be calibrated according to the comparison result when the count value of the clock counter to be calibrated is different from the reference clock counter.
  • the device provided by the embodiment of the present application can output a control word to adjust the frequency of the clock to be calibrated as long as the count values of the two counters are different, and improve the efficiency of the frequency adjustment without affecting the accuracy of the frequency adjustment.
  • the counting real-time comparison module is specifically configured to: compare the count value of the clock counter to be calibrated with the count value of the reference clock counter in real time in a reference clock domain.
  • the counting real-time comparison module is specifically configured to:
  • the count value of the clock counter to be calibrated converted to Gray code is used to cancel the metastable delay and then convert to a binary number
  • the delay value of the clock counter to be calibrated converted to a binary number is used to control the timing delay, it is compared with the count value of the reference clock counter that has performed the same delay.
  • the same delay refers to the delay performed by the count value of the reference clock counter, and the delay for canceling the metastable state and the delay for controlling the timing are the same as the count value of the clock counter to be calibrated.
  • control word output module is specifically configured to:
  • condition for outputting the control word for increasing the clock frequency to be calibrated further comprises: the count value of the reference clock counter is greater than the count value +1 of the clock counter to be calibrated; and the output is used to lower the Describe the calibration clock
  • the condition of the frequency control word further includes: the count value of the clock counter to be calibrated is greater than the count value +1 of the reference clock counter.
  • control word output module is configured to: output a control word for adjusting a clock frequency to be calibrated by using a binary method according to the comparison result; or output a 1/4 hop method according to the comparison result.
  • a control word for adjusting the clock frequency to be calibrated; or, according to the comparison result, a control word for adjusting the clock frequency to be calibrated is output by adding 2 minus 1 hopping.
  • the control word output module may be further configured to: when the cumulative number of jumps of the control word is not When the maximum number of jumps is reached, the control word hopping mode used for outputting the control word is selected from the preset N kinds of control word hopping manners according to the difference between the clock frequency to be calibrated and the reference clock frequency, wherein The larger the difference is, the longer the hopping step of the selected control word hopping mode is, and the N is an integer not less than 2; correspondingly, when the control word for adjusting the clock frequency to be calibrated is output according to the comparison result, The control word output module is configured to: output a control word for adjusting a clock frequency to be calibrated by using a selected control word hopping manner according to the comparison result.
  • a waiting time determining module may be further included, after the control word output module selects the control word hopping mode, according to a preset control word hopping manner and a clock stability waiting time to be calibrated Determining the clock stabilization waiting time to be calibrated corresponding to the selected control word hopping mode, as the output control word adjusts the clock frequency to be calibrated and waits for the clock to be calibrated to be stable; wherein, the selected control word hopping mode jumps The longer the step size is, the longer the corresponding clock stabilization wait time is to be calibrated, or the longer the jump step size of the selected control word hopping mode, the shorter the waiting time for the corresponding clock to be calibrated.
  • Another object of the present application is to provide a frequency calibration method and apparatus to solve the problem that the control word hopping mode is inflexible and the frequency adjustment efficiency is low.
  • a frequency calibration method comprising:
  • a control word hopping mode is selected from the preset N control word hopping modes.
  • N is an integer not less than 2;
  • the control word for adjusting the clock frequency to be calibrated is outputted by using the selected control word hopping mode.
  • the method provided by the embodiment of the present application flexibly selects an appropriate control word hopping mode according to the difference between the clock frequency to be calibrated and the reference clock frequency.
  • the difference is larger, the longer the jump step of the selected control word hopping mode, the number of adjustments of the clock to be calibrated can be reduced, and the adjustment efficiency is improved.
  • the clock to be calibrated corresponding to the selected control word hopping mode is determined according to the corresponding relationship between the preset control word hopping mode and the clock stability waiting time to be calibrated. Waiting time As the output control word adjusts the clock frequency to be calibrated and waits for the clock to be calibrated to stabilize; wherein the longer the hopping step of the selected control word hopping mode, the longer the waiting time of the corresponding clock to be calibrated is. Alternatively, the longer the jump step of the selected control word hopping mode, the shorter the waiting time for the corresponding clock to be calibrated.
  • the embodiment of the present application further provides a frequency calibration apparatus, including:
  • a counting comparison module configured to compare a count value of the clock counter to be calibrated with a count value of the reference clock counter
  • the control word hopping mode selection module is configured to hop from the preset N kinds of control words according to the difference between the clock frequency to be calibrated and the reference clock frequency when the number of accumulated hops of the control word does not reach the maximum hopping number Selecting a control word hopping mode, wherein the larger the difference, the longer the hopping step of the selected control word hopping mode, and the N is an integer not less than 2;
  • the control word output module is configured to output a control word for adjusting the clock frequency to be calibrated by using a selected control word hopping manner according to a comparison result between the count value of the clock counter to be calibrated and the count value of the reference clock counter.
  • the device provided in the embodiment of the present application flexibly selects an appropriate control word hopping mode according to the difference between the clock frequency to be calibrated and the reference clock frequency.
  • the difference is larger, the longer the jump step of the selected control word hopping mode, the number of adjustments of the clock to be calibrated can be reduced, and the adjustment efficiency is improved.
  • the method further includes a waiting time determining module, configured to, after the control word hopping mode selection module selects the control word hopping mode, according to a preset control word hopping manner and a clock stability waiting time to be calibrated Relationship, determining the clock stabilization waiting time to be calibrated corresponding to the selected control word hopping mode, as the output control word adjusts the clock frequency to be calibrated and waits for the clock to be calibrated to be stable; wherein, the selected control word hopping mode The longer the hopping step is, the longer the waiting time for the clock to be calibrated is stable, or the longer the hopping step of the selected control word hopping mode, and the shorter the waiting time for the corresponding clock to be calibrated.
  • a waiting time determining module configured to, after the control word hopping mode selection module selects the control word hopping mode, according to a preset control word hopping manner and a clock stability waiting time to be calibrated Relationship, determining the clock stabilization waiting time to be calibrated corresponding to the selected control word hopping mode, as the
  • FIG. 1 is a schematic diagram of a frequency calibration method according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a real-time comparison processing process provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a dichotomy hopping provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a first frequency calibration apparatus according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a frequency calibration circuit according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of another frequency calibration method according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of another frequency calibration apparatus according to an embodiment of the present application.
  • a frequency calibration method provided by the embodiment of the present application is as shown in FIG. 1 , and specifically includes the following operations:
  • Step 100 Compare the count value of the clock counter to be calibrated with the count value of the reference clock counter in real time.
  • Step 110 When the count value of the clock counter to be calibrated is different from the reference clock counter, output a control word for adjusting the clock frequency to be calibrated according to the comparison result.
  • the control word can be output to adjust the frequency of the clock to be calibrated, and the efficiency of the frequency adjustment is improved without affecting the accuracy of the frequency adjustment.
  • the two clocks are asynchronous clocks.
  • asynchronous clocks need to be compared in real time in the same clock domain.
  • the two clocks are preferably compared in real time in the reference clock domain.
  • the two clocks can also be compared in real time in the clock domain to be calibrated.
  • the same delay refers to the delay performed by the count value of the reference clock counter, and the delay for canceling the metastable state and the delay for controlling the timing are the same as the count value of the clock counter to be calibrated.
  • the count value of the clock counter to be calibrated converted to the Gray code is subjected to two beat delays, and the count value of the clock counter to be calibrated converted to a binary number is subjected to one beat delay.
  • the processing of the above real-time comparison is as shown in FIG. 2.
  • the purpose of converting the binary number into the Gray code is to avoid a state error after converting the count value of the clock to be calibrated to the reference clock domain.
  • the delay is realized by the flip-flop. After the first-level flip-flop and the second-level flip-flop, the count value of the clock counter to be calibrated realizes two beat delays, and the purpose is to eliminate metastability.
  • the count value of the clock counter to be calibrated is converted to a binary number for comparison with the count value of the reference clock counter.
  • the purpose of implementing a beat delay via a three-level flip-flop is for timing considerations.
  • the count value of the reference clock counter is also subjected to three-shot delay processing.
  • the specific implementation manner of outputting the control word for adjusting the clock frequency to be calibrated according to the comparison result may be, but is not limited to, when the reference clock counter is used.
  • the count value is greater than the count value of the clock counter to be calibrated, but is smaller than the preset count threshold, and the output is used.
  • the embodiment of the present application introduces a counting threshold. When the counting threshold has not been determined, the real-time comparison will be terminated (ie, the frequency calibration is stopped).
  • the accuracy of the real-time comparison result is affected.
  • the control word is output according to the comparison result, the count value of the slow clock counter is incremented by one.
  • the condition for outputting the control word for increasing the clock frequency to be calibrated further includes: the count value of the reference clock counter is greater than the count value +1 of the clock counter to be calibrated; and the output is used to lower the clock frequency to be calibrated.
  • the condition of the control word further includes: the count value of the clock counter to be calibrated is greater than the count value +1 of the reference clock counter.
  • control word for adjusting the clock frequency to be calibrated when the control word for adjusting the clock frequency to be calibrated is output according to the comparison result, the control word for adjusting the clock frequency to be calibrated may be output by using a binary method according to the comparison result; or According to the comparison result, the control word for adjusting the clock frequency to be calibrated is output by using the 1/4 hopping method; or, according to the comparison result, the control word for adjusting the clock frequency to be calibrated is output by adding 2 minus 1 hopping method.
  • control word hopping mode when the cumulative number of hops of the control word does not reach the maximum When the number of hops is changed, according to the difference between the clock frequency to be calibrated and the reference clock frequency, the control word hopping mode adopted by the output control word is selected from the preset N kinds of control word hopping modes, wherein the difference is Large, the longer the hopping step of the selected control word hopping mode, N is an integer not less than 2; correspondingly, the specific implementation manner of outputting the control word for adjusting the clock frequency to be calibrated according to the comparison result may be:
  • the comparison result uses the selected control word hopping mode to output a control word for adjusting the clock frequency to be calibrated.
  • the control word hopping mode may be a dichotomy hop, a 1/4 hopping method, a plus 2 minus one hopping method, a hopping method with a fixed step size of 1, and the like.
  • the value range of the difference value may be divided, and each value range corresponds to a control word hopping manner.
  • the selection order of the control word hopping mode may be: dichotomy hopping -> 1/4 hopping method -> adding 2 minus 1 hopping method -> hopping method with step length fixed to 1 .
  • the reference clock frequency is fixed, for example, 24 megahertz (MHz). Since the sampling times of the two count values of the real-time comparison are the same, the total duration of the two clocks is the same from the initial sampling time to the current sampling time.
  • the clock frequency to be calibrated can be obtained by the following formula:
  • Clock frequency to be calibrated reference clock frequency ⁇ count value of reference clock counter ⁇ count value of clock counter to be calibrated
  • the so-called dichotomy means that the control word jump step size outputted each time is 1/2 of the control word jump step size of the previous output.
  • the initial value of the control word is 5'b10000, and the initial jump step size is 8. If it is required to output a control word for raising the clock frequency to be calibrated, the control word jumps to a large value. If it is necessary to output a control word for lowering the clock frequency to be calibrated, the control word jumps to a small value.
  • Figure 3 shows the control word hopping process for two frequency calibrations completed with 4 hops. The so-called one jump, that is, the control word is output once.
  • the 1/4 hopping method means that the control word hopping step size outputted each time is 1/4 of the control word hopping step size of the previous output.
  • the so-called plus 2 minus 1 hopping method means that the control word hopping step size of each output is 2. For example, if the current control word is word, the next control word will be word+2 or word-2. If the control word is incremented or decremented by 2 or more, the count value of the clock counter to be calibrated is greater than (or less than). The count value of the reference clock counter becomes less than (or greater than) the count value of the reference clock counter, then the control word is decremented by 1 (or incremented by 1).
  • the jump step size of the control word refers to the difference between the control word outputted this time and the control word outputted last time.
  • the relationship between the stable latency of the PLL and the output clock span is not considered. Take the PLL with a larger output clock span and a longer stable wait time as an example. For scenarios where the output clock span changes, the existing stable wait time setting is not flexible enough.
  • the control word hopping may be determined according to the corresponding relationship between the preset control word hopping mode and the clock stability waiting time to be calibrated.
  • the clock stabilization waiting time corresponding to the variable mode is used as the time when the output control word adjusts the clock frequency to be calibrated and waits for the clock to be calibrated to be stable.
  • the PLL output clock span is larger, the stable waiting time is longer. Then, the longer the hopping step of the selected control word hopping mode, the longer the waiting time for the corresponding clock to be calibrated is stable. Since the conventional PLL has the larger span and the longer the stable waiting time in the same adjustment gear position, the implementation can not only effectively reduce the number of transitions, but also adjust the stable waiting time for this characteristic of the PLL, further reducing Adjust the total time used by the clock to improve regulation efficiency.
  • the embodiment of the present application further provides a frequency calibration device, as shown in FIG. 4, specifically including:
  • the control word output module 402 is configured to output a control word for adjusting the clock frequency to be calibrated according to the comparison result when the clock counter to be calibrated is different from the count value of the reference clock counter.
  • the device provided in the embodiment of the present application can output a control word to adjust the waiting value as long as the count values of the two counters are different. Calibrating the frequency of the clock improves the efficiency of the frequency adjustment without affecting the accuracy of the frequency adjustment.
  • the counting real-time comparison module 401 is specifically configured to: compare the count value of the clock counter to be calibrated with the count value of the reference clock counter in real time in the reference clock domain.
  • the counting real-time comparison module 401 is specifically configured to:
  • the format of the count value of the clock counter to be calibrated is converted from a binary number to a Gray code; in the reference clock domain, the count value of the clock counter to be calibrated converted to Gray code is used. Converting to a binary number after canceling the metastable delay; in the reference clock domain, the count value of the clock counter to be calibrated converted to a binary number is used to control the timing delay, and is performed the same The count value of the delayed reference clock counter is compared.
  • the same delay refers to the delay performed by the count value of the reference clock counter, and the delay for canceling the metastable state and the delay for controlling the timing are the same as the count value of the clock counter to be calibrated.
  • control word output module 402 is specifically configured to:
  • condition for outputting the control word for increasing the clock frequency to be calibrated further comprises: the count value of the reference clock counter is greater than the count value +1 of the clock counter to be calibrated; and the output is used to lower the
  • the condition of the control word for calibrating the clock frequency further includes: the count value of the clock counter to be calibrated is greater than the count value +1 of the reference clock counter.
  • control word output module 402 is configured to: use a binary method to output a control word for adjusting a clock frequency to be calibrated according to the comparison result; or, according to the comparison result, adopt a 1/4 hopping method according to the comparison result.
  • the control word for adjusting the clock frequency to be calibrated is output; or, according to the comparison result, the control word for adjusting the clock frequency to be calibrated is output by adding 2 minus 1 hopping method.
  • the control word output module may be further configured to: when the cumulative number of jumps of the control word is not When the maximum number of jumps is reached, the control word hopping mode used for outputting the control word is selected from the preset N kinds of control word hopping manners according to the difference between the clock frequency to be calibrated and the reference clock frequency, wherein The larger the difference is, the longer the hopping step of the selected control word hopping mode is, and the N is an integer not less than 2; correspondingly, when the control word for adjusting the clock frequency to be calibrated is output according to the comparison result, The control word output module is configured to: output a control word for adjusting a clock frequency to be calibrated by using a selected control word hopping manner according to the comparison result.
  • a waiting time determining module may be further included, after the control word output module selects the control word hopping mode, according to a preset control word hopping manner and a clock stability waiting time to be calibrated Determining the clock stabilization waiting time to be calibrated corresponding to the selected control word hopping mode, as the output control word is adjusted Waiting for the clock to be calibrated to stabilize after the clock frequency is calibrated; wherein the longer the hopping step of the selected control word hopping mode, the longer the waiting time of the corresponding clock to be calibrated, or the selected control word hopping mode The longer the jump step, the shorter the waiting time for the corresponding clock to be calibrated.
  • FIG. 5 is a schematic structural diagram of a preferred frequency calibration circuit according to an embodiment of the present application.
  • T1 ⁇ T4 clock stabilization waiting times to be calibrated
  • T1 is the waiting time before the frequency calibration is performed to ensure that the clock to be calibrated is stable
  • T2 is the waiting time corresponding to the dichotomy hopping
  • T3 It is the waiting time corresponding to the 1/4 hopping method
  • T4 is the waiting time corresponding to the addition of 2 minus 1 hopping method. If the PLL output clock span is larger and the required settling time is longer, T2>T3>T4; if the PLL output clock span is larger, the required settling time is shorter, then T2 ⁇ T3 ⁇ T4.
  • the counter control circuit After waiting for the clock stabilization circuit to be calibrated to control the clock to be calibrated to be stable, the counter control circuit triggers the reference clock counter and the clock counter to be calibrated to start counting.
  • the reference clock counter and the clock counter to be calibrated transmit the count value to the count value real-time comparison circuit in real time, and the two count values of the input are compared by the count value real-time comparison circuit.
  • the control word hopping mode selection circuit determines the difference between the two clock frequencies according to the received two count values, and then selects one of the above three control word hopping modes according to the difference of the clock frequency, and selects the selected one.
  • the word hopping mode is notified to the control word output circuit.
  • the control word hopping mode selection circuit first determines whether the number of accumulated jumps of the control word reaches the maximum number of hops, and only when the mode is not reached, the control word hopping mode is performed. The selection, otherwise the counter control circuit stops counting and ends the frequency calibration process.
  • the corresponding state machine in the control word output circuit outputs the corresponding control word according to the indication of the real-time comparison circuit of the count value to adjust the oscillator capacitance, thereby adjusting the oscillation frequency of the oscillator (ie, the clock frequency to be calibrated); if the control word is output If a jump occurs, the number of accumulated jumps of the control word is incremented by one; if the control word jump mode selection circuit does not judge the number of accumulated jumps of the control word, the control word output circuit implements the determination, and only the number of jumps of the control word is accumulated. When the maximum number of jumps is not reached, the corresponding state machine is notified to work.
  • the correspondence between the difference between the clock frequency and the control word hopping manner is preset.
  • the value range x1 ⁇ x2 corresponds to the dichotomy hopping
  • the value range x2 ⁇ x3 corresponds to the 1/4 hopping method
  • the value range x3 ⁇ x4 corresponds to the plus 2 minus one hopping method.
  • control word hopping mode selection circuit selects the binary method hopping mode
  • the control word output The circuit notifies the dichotomy state machine to work. If the 1/4 hopping method is selected, the control word output circuit notifies the 1/4 state machine to operate. If the add 2 minus 1 hopping method is selected, the control word output circuit notifies the adding 2 minus 1 state machine. jobs.
  • control word hopping mode selection circuit selects the binary method hopping mode
  • the selected control word hopping mode is notified to the waiting clock stabilization circuit, and waits for the clock stabilization circuit to determine that the clock stabilization waiting time to be calibrated is T2
  • the word hopping mode selection circuit selects the 1/4 hopping method
  • the selected control word hopping mode is notified to the waiting clock stabilization circuit, waiting for the clock stabilization circuit to determine that the clock stabilization waiting time to be calibrated is T3
  • the control word hopping mode is selected The circuit selection plus 2 minus 1 hopping method notifies the waiting clock stabilization circuit of the selected control word hopping mode, and waits for the clock stabilization circuit to determine that the clock stabilization waiting time to be calibrated is T4.
  • the specific working principle of the binary method state machine is as follows: if the count value real-time comparison circuit instructs the control word output circuit to increase the value of the control word or reduce the value of the control word, the dichotomy state machine correspondingly increases or decreases The value of the control word, and the jump step of the control word output this time is 1/2 of the jump step of the control word of the previous jump, if the count value real-time comparison circuit indicates that the control word output circuit does not change the control word.
  • the value of the binary method state machine can either output the control word or output the control word without change.
  • the initial value of the control word is preset.
  • control word hopping mode selection circuit as shown in FIG. 5, the embodiment of the present application can still be implemented, that is, a fixed control word hopping mode is adopted.
  • control word output circuit can be implemented by a fixed control word state machine.
  • FIG. 6 Another frequency calibration method provided by the embodiment of the present application is as shown in FIG. 6 , and specifically includes the following operations:
  • Step 600 Compare the count value of the clock counter to be calibrated with the count value of the reference clock counter.
  • the real-time comparison mode provided by the foregoing embodiment of the present application can be used to compare the count values of the two counters. It can also be implemented by using an existing comparison method. For example, the calibration clock and the reference clock are counted simultaneously for a period of time, and the count values of the two counters are compared by determining which clock counter count value first reaches a predetermined value.
  • Step 610 When the cumulative number of jumps of the control word does not reach the maximum number of jumps, select a control word from the preset N control word hopping manner according to the difference between the clock frequency to be calibrated and the reference clock frequency.
  • the hopping mode wherein the larger the difference, the longer the hopping step of the selected control word hopping mode, and N is an integer not less than 2.
  • the clock frequency to be calibrated and the reference clock frequency can be compared in real time according to the method provided in the foregoing embodiment, or can be compared according to the existing manner. If the comparison is made in the existing manner, the difference between the two clock frequencies is further calculated when it is determined that the count value of the counter reaches the predetermined value first.
  • Step 620 Output a control word for adjusting a clock frequency to be calibrated by using a selected control word hopping manner according to a comparison result between the count value of the clock counter to be calibrated and the count value of the reference clock counter.
  • the method provided by the embodiment of the present application flexibly selects according to the difference between the clock frequency to be calibrated and the reference clock frequency. Appropriate control word jump mode. When the difference is larger, the longer the jump step of the selected control word hopping mode, the number of adjustments of the clock to be calibrated can be reduced, and the adjustment efficiency is improved.
  • the clock to be calibrated corresponding to the selected control word hopping mode is determined according to the corresponding relationship between the preset control word hopping mode and the clock stability waiting time to be calibrated. Waiting time, as the output control word adjusts the clock frequency to be calibrated and waits for the clock to be calibrated to stabilize; wherein the longer the hopping step of the selected control word hopping mode, the longer the waiting time of the corresponding clock to be calibrated Or, the longer the jump step of the selected control word hopping mode, the shorter the waiting time for the corresponding clock to be calibrated.
  • the embodiment of the present application further provides a frequency calibration device, as shown in FIG.
  • a counting comparison module 701 configured to compare a count value of the clock counter to be calibrated with a count value of the reference clock counter
  • the control word hopping mode selection module 702 is configured to: when the number of accumulated hops of the control word does not reach the maximum number of hops, according to the difference between the clock frequency to be calibrated and the reference clock frequency, jump from the preset N control words.
  • a control word hopping mode is selected in the variable mode, wherein the larger the difference is, the longer the hopping step of the selected control word hopping mode is, and the N is an integer not less than 2;
  • the control word output module 703 is configured to output a control word for adjusting the clock frequency to be calibrated by using a selected control word hopping manner according to a comparison result between the count value of the clock counter to be calibrated and the count value of the reference clock counter.
  • the device provided in the embodiment of the present application flexibly selects an appropriate control word hopping mode according to the difference between the clock frequency to be calibrated and the reference clock frequency.
  • the difference is larger, the longer the jump step of the selected control word hopping mode, the number of adjustments of the clock to be calibrated can be reduced, and the adjustment efficiency is improved.
  • the method further includes a waiting time determining module, configured to, after the control word hopping mode selection module selects the control word hopping mode, according to a preset control word hopping manner and a clock stability waiting time to be calibrated Relationship, determining the clock stabilization waiting time to be calibrated corresponding to the selected control word hopping mode, as the output control word adjusts the clock frequency to be calibrated and waits for the clock to be calibrated to be stable; wherein, the selected control word hopping mode The longer the hopping step is, the longer the waiting time for the clock to be calibrated is stable, or the longer the hopping step of the selected control word hopping mode, and the shorter the waiting time for the corresponding clock to be calibrated.
  • a waiting time determining module configured to, after the control word hopping mode selection module selects the control word hopping mode, according to a preset control word hopping manner and a clock stability waiting time to be calibrated Relationship, determining the clock stabilization waiting time to be calibrated corresponding to the selected control word hopping mode, as the
  • embodiments of the present application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne des procédés et un appareil d'étalonnage de fréquence. Un procédé consiste à: comparer une valeur de comptage d'un compteur d'une horloge à étalonner à une valeur de comptage d'un compteur d'une horloge de référence en temps réel; et lorsque les valeurs de comptage des deux compteurs d'horloge sont différentes, émettre un mot de commande utilisé pour ajuster une fréquence de l'horloge à étalonner en fonction d'un résultat de la comparaison. Un autre procédé consiste à: lorsqu'un nombre d'occurrences de sauts accumulés d'un mot de commande n'atteint pas un nombre maximal d'occurrences permis, choisir une manière de saut de mot de commande parmi N manières de saut de mot de commande prédéterminées en fonction d'une différence entre la valeur de comptage du compteur de l'horloge à étalonner et la valeur de comptage du compteur d'horloge de référence, dans lequel plus la différence est importante, plus l'étape de saut de la manière de saut de mot de commande choisie est longue; et utiliser la manière de saut de mot de commande choisie pour émettre un mot de commande servant à ajuster la fréquence de l'horloge à étalonner. A la différence des systèmes d'étalonnage de fréquence de l'art antérieur, les modes de réalisation de la présente invention offrent une solution technique qui améliore l'efficacité d'ajustement de fréquence.
PCT/CN2014/088791 2013-12-10 2014-10-17 Procédés et appareil d'étalonnage de fréquence WO2015085825A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310671766.8A CN104702278A (zh) 2013-12-10 2013-12-10 一种频率校准方法及装置
CN201310671766.8 2013-12-10

Publications (1)

Publication Number Publication Date
WO2015085825A1 true WO2015085825A1 (fr) 2015-06-18

Family

ID=53349093

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/088791 WO2015085825A1 (fr) 2013-12-10 2014-10-17 Procédés et appareil d'étalonnage de fréquence

Country Status (2)

Country Link
CN (1) CN104702278A (fr)
WO (1) WO2015085825A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111541450A (zh) * 2020-06-19 2020-08-14 华大半导体有限公司 时钟自动校准电路及方法
CN113641214A (zh) * 2021-08-24 2021-11-12 维沃移动通信有限公司 时钟校准电路、时钟校准方法及相关设备
CN116318120A (zh) * 2023-03-30 2023-06-23 归芯科技(深圳)有限公司 Rc振荡时钟的校准电路、校准方法、芯片和电子设备

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105738695A (zh) * 2016-04-14 2016-07-06 杭州中科微电子有限公司 一种时钟频率跟踪测量及误差估计实现方法和模块
CN106656173B (zh) * 2016-12-26 2020-01-24 上海迦美信芯通讯技术有限公司 一种振荡器的频率校准电路及其频率校准方法
CN107066030B (zh) * 2016-12-30 2020-01-14 深圳市鼎阳科技股份有限公司 一种信号源及其多频率输出补偿方法、系统
CN107103144B (zh) * 2017-05-08 2020-06-26 北京化工大学 基于fpga的仲裁型puf的布线延迟偏差快速校准方法
CN107682010A (zh) * 2017-11-07 2018-02-09 杭州城芯科技有限公司 基于脉冲吞咽多模分频器的低功耗全数字的快速自动频率校准电路
CN108230660B (zh) * 2018-01-09 2020-08-25 广东美的制冷设备有限公司 控制方法及控制装置、存储介质及遥控器
CN109211946B (zh) * 2018-08-29 2021-08-27 苏州瑞迈斯医疗科技有限公司 校正X-ray探测器中的探测通道的方法
CN111431526B (zh) * 2020-04-17 2023-06-06 珠海泰特微电子股份有限公司 一种高精度振荡器校准系统及其快速校准方法
CN111665431B (zh) * 2020-04-26 2023-07-25 江西联智集成电路有限公司 芯片内部时钟源校准方法、装置、设备及介质
CN112051889A (zh) * 2020-08-27 2020-12-08 海光信息技术有限公司 I2c总线的时钟频率自适应调整方法、主设备及设备系统
CN112269424A (zh) * 2020-11-19 2021-01-26 珠海零边界集成电路有限公司 一种芯片时钟频率校准方法、装置、设备和介质
CN112636752A (zh) * 2020-12-29 2021-04-09 北京奕斯伟计算技术有限公司 一种振荡器装置及振荡器频率校准方法
CN112332834B (zh) * 2021-01-04 2021-04-13 南京芯视界微电子科技有限公司 激光雷达的时间数字转换器避免亚稳态的矫正方法及装置
CN113031695B (zh) * 2021-03-19 2024-04-12 维沃移动通信有限公司 控制电路装置、电子设备、控制方法和可读存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2339753A1 (fr) * 2009-12-24 2011-06-29 Nxp B.V. Boucle numérique à verrouillage de phase
CN102195646A (zh) * 2010-03-18 2011-09-21 上海华虹Nec电子有限公司 时钟振荡器自动校准方法及电路
CN102201801A (zh) * 2010-03-23 2011-09-28 三星半导体(中国)研究开发有限公司 高精度振荡器及其自校准方法
CN102761332A (zh) * 2012-06-29 2012-10-31 深圳市九洲电器有限公司 一种时钟产生电路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10049531C2 (de) * 2000-10-06 2002-07-18 Texas Instruments Deutschland Taktgenerator
CN102820885B (zh) * 2012-07-13 2015-10-21 电子科技大学 一种时钟恢复控制器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2339753A1 (fr) * 2009-12-24 2011-06-29 Nxp B.V. Boucle numérique à verrouillage de phase
CN102195646A (zh) * 2010-03-18 2011-09-21 上海华虹Nec电子有限公司 时钟振荡器自动校准方法及电路
CN102201801A (zh) * 2010-03-23 2011-09-28 三星半导体(中国)研究开发有限公司 高精度振荡器及其自校准方法
CN102761332A (zh) * 2012-06-29 2012-10-31 深圳市九洲电器有限公司 一种时钟产生电路

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111541450A (zh) * 2020-06-19 2020-08-14 华大半导体有限公司 时钟自动校准电路及方法
CN111541450B (zh) * 2020-06-19 2024-01-30 小华半导体有限公司 时钟自动校准电路及方法
CN113641214A (zh) * 2021-08-24 2021-11-12 维沃移动通信有限公司 时钟校准电路、时钟校准方法及相关设备
CN116318120A (zh) * 2023-03-30 2023-06-23 归芯科技(深圳)有限公司 Rc振荡时钟的校准电路、校准方法、芯片和电子设备
CN116318120B (zh) * 2023-03-30 2024-05-03 归芯科技(深圳)有限公司 Rc振荡时钟的校准电路、校准方法、芯片和电子设备

Also Published As

Publication number Publication date
CN104702278A (zh) 2015-06-10

Similar Documents

Publication Publication Date Title
WO2015085825A1 (fr) Procédés et appareil d'étalonnage de fréquence
WO2016095679A1 (fr) Procédé de commande de boucle verrouillée en phase à fréquence à demi-débit numérique et boucle verrouillée en phase
US20100260242A1 (en) Time digital converter, digital pll frequency synthesizer, transceiver, and receiver
US9564885B2 (en) Event-driven clock duty cycle control
KR101051944B1 (ko) 듀티 감지 회로 및 이를 포함하는 듀티 보정 회로
US20100295590A1 (en) Time to digital converter
KR102123901B1 (ko) 완전 디지털 위상 고정 루프 회로, 반도체 장치 및 휴대 정보 기기
US9778676B2 (en) Power distribution network (PDN) droop/overshoot mitigation in dynamic frequency scaling
US7636001B2 (en) Digital DLL circuit
TWI470937B (zh) 鎖相迴路之頻率校正裝置及頻率校正方法
US11095291B2 (en) Time measurement circuit, system having a PWM signal generator circuit and a time measurement circuit, and corresponding integrated circuit
US11469670B2 (en) Methods and apparatus to improve power converter on-time generation
US10411683B2 (en) Information processing device, information processing method, and computer-readable recording medium
CN114868337A (zh) 用于同步两个系统的方法和装置
WO2011161737A1 (fr) Dispositif de détection de déphasage numérique et synthétiseur de fréquence équipé dudit dispositif
US10018970B2 (en) Time-to-digital system and associated frequency synthesizer
TWI613890B (zh) 數位控制振盪器的頻率校正方法及其頻率校正裝置
US20240056084A1 (en) Digital phase locked loop and methods of operating same
KR101297413B1 (ko) 적응형 클럭 생성 장치 및 방법
EP4350999A1 (fr) Procédé et appareil de commutation d'horloge, dispositif électronique, et support de stockage lisible par ordinateur
TW201316150A (zh) 多相位時脈產生系統及其時脈校準方法
JP2010200064A (ja) Ｐｌｌ回路、ｐｌｌ回路無線通信機、及びｐｌｌ回路のロック検出方法
KR20120126242A (ko) 반도체 장치의 데이터 출력 타이밍 제어 회로
JP5638376B2 (ja) Ｐｌｌ回路
JP2022188629A (ja) 電子回路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14869074

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14869074

Country of ref document: EP

Kind code of ref document: A1