WO2015062867A1 - Elektronisches bauelement und verfahren zum herstellen eines elektronischen bauelements - Google Patents
Elektronisches bauelement und verfahren zum herstellen eines elektronischen bauelements Download PDFInfo
- Publication number
- WO2015062867A1 WO2015062867A1 PCT/EP2014/072180 EP2014072180W WO2015062867A1 WO 2015062867 A1 WO2015062867 A1 WO 2015062867A1 EP 2014072180 W EP2014072180 W EP 2014072180W WO 2015062867 A1 WO2015062867 A1 WO 2015062867A1
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- WIPO (PCT)
- Prior art keywords
- layer
- chip
- adhesive layer
- substrate
- electrically conductive
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010410 layer Substances 0.000 claims abstract description 149
- 239000012790 adhesive layer Substances 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000010292 electrical insulation Methods 0.000 claims abstract description 13
- 238000000465 moulding Methods 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 21
- 238000009413 insulation Methods 0.000 claims description 14
- 150000001875 compounds Chemical class 0.000 claims description 10
- 238000009987 spinning Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 3
- 238000005507 spraying Methods 0.000 claims description 3
- 238000003856 thermoforming Methods 0.000 claims description 3
- 239000002861 polymer material Substances 0.000 claims description 2
- 241001465754 Metazoa Species 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 13
- 239000012778 molding material Substances 0.000 description 8
- 229920001296 polysiloxane Polymers 0.000 description 8
- 230000005693 optoelectronics Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 5
- 238000000926 separation method Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000005670 electromagnetic radiation Effects 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 2
- 239000004810 polytetrafluoroethylene Substances 0.000 description 2
- 206010053567 Coagulopathies Diseases 0.000 description 1
- 101100346656 Drosophila melanogaster strat gene Proteins 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 235000010678 Paulownia tomentosa Nutrition 0.000 description 1
- 240000002834 Paulownia tomentosa Species 0.000 description 1
- 229920001774 Perfluoroether Polymers 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000000181 anti-adherent effect Effects 0.000 description 1
- 239000012876 carrier material Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000035602 clotting Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000012050 conventional carrier Substances 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 108090000623 proteins and genes Proteins 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 230000000284 resting effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/54—Encapsulations having a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
- H01L33/60—Reflective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
Definitions
- the present invention relates to an electronic component in which a chip is embedded in a molding and a method for producing a corresponding electronic component.
- the carrier substrate may be, for example, a silicon or ceramic substrate, a leadframe or a so-called metal core board.
- the carrier substrate can be provided as a mechanical support, for electrical contacting, for wiring with further components, for example protective diodes, for heat spreading and / or for heat dissipation.
- the carrier substrate may also be provided as a support for an optical lens.
- conventional carrier substrates are relatively expensive. Due to a required minimum size of the carrier substrates, these contribute a significant share of the total manufacturing costs.
- molding compound is therefore increasingly being used to form mechanical supports for the chips.
- an optoelectronic semiconductor component is known, in which from the molding material a side surface is formed of the chip-covering moldings, wherein only one side surface of the chip remains free or is released ⁇ .
- connection contacts On the exposed side surface of the embedded chip, a light-emitting region and one or more connection contacts may be provided.
- electrically conductive structures may be arranged on or in the molded body.
- insulation structures can be formed, for example, by the application of an insulating material. The application of the insulating material al ⁇ lerdings comprises several sub-steps, so that the application of the insulating material is relatively time consuming and costly.
- an adhesive layer is applied to a carrier.
- the adhesive layer applied to the carrier is hardened.
- a chip is provided.
- the chip has a substrate and a layer sequence arranged on the substrate.
- the chip comes up with a first top of the layer sequence placed the cured adhesive layer.
- the chip resting on the adhesive layer is embedded in a shaped body, wherein the upper side of the layer sequence and a first side of the shaped body lie substantially in one plane.
- the chip embedded in the molded body is separated from the adhesive layer and the carrier.
- an electrically conductive structure is attached, wherein the form ⁇ body forms a vertical electrical insulation between the electrically conductive structure and the substrate.
- the viscosity and / or the tack of the adhesive layer can set the ⁇ that the chip will not sink when placed on the adhesive layer or very little into the adhesive layer. Furthermore, the viscosity and / or the stickiness of the adhesive layer can be adjusted so that the adhesive layer seals the edge of the adhesive layer
- the vertical electrical insulation forming region of the molded body may surround the layer sequence laterally. Furthermore, the region of the shaped body forming the vertical electrical insulation can cover an edge region of the substrate. A separate electrical insulation of the substrate or the edge region of the substrate is thus not required. Since the vertical insulation is formed as part of the molded body, the number of process ⁇ steps can be reduced. While the molded body is formed, that during the on ⁇ Bettens of the chip, the chip is situated with the top of
- the electronic component includes egg ⁇ NEN embedded in a molding die, said chip comprises a substrate and, disposed on a first side of the substrate layer sequence.
- the molded body has a first side. The first side of the molding and a
- Top of the layer sequence are essentially in one plane.
- the top of the layer sequence is free of Formmas ⁇ se.
- an electrically conductive structure is disposed on the first side of the mold body. Between the electrically conductive structure and the substrate, a region of the shaped body forms a vertical electrical insulation.
- partial curing can refer to a defined curing the adhesive layer here.
- the stickiness and / or the viscosity of the adhesive layer can be set before application of the chip by the partial curing.
- the tackiness of the adhesive layer by the partial curing can thus be ⁇ represents the stickiness is sufficient to fix a chip on the carrier, the viscosity of the adhesive layer n
- the viscosity and the tackiness of the adhesive layer can be so turned ⁇ provides that when the molded body form the upper side of the layer sequence and the first side of the molded body substantially in one plane. Can mean lie substantially in a plane that is defined by the jeweili ⁇ gen pages levels have an offset of less than 2 ym.
- the adhesive layer can be applied to the carrier by, for example, spinning, spraying, laminating, jetting or thermoforming.
- a polymer material having non-stick properties may be provided.
- a silicone can be provided as material for the Kle ⁇ be harsh. The silicone can be applied to the carrier in the non-crosslinked state.
- the adhesive layer After placing the chip on the adhesive layer and before embedding the chip in the molding, the adhesive layer can be cured. After curing, the material of the adhesive layer may be crosslinked. The hardening can Kle ⁇ be Mrs lose their stickiness. By the complete curing of the adhesive layer can, for example, prevents the ⁇ that when embedding the chip combines the molding material with the adhesive layer. This may make it easier to separate the molded article from the carrier after embedding the chip enable. The adhesive film can thus be cured in two separate steps. Where in the first step, the
- Curing may depend on the material of the adhesive layer and / or on the properties of the adhesive layer to be set by the curing.
- the adhesive layer may be cured at a temperature less than or equal to 175 ° C.
- the curing of the adhesive layer may be for a period of less than or equal to 15 minutes.
- at equal tempering temperatures at most half of the time required to completely cure the adhesive layer may be provided.
- a maximum of one quarter of the time required for complete curing of the adhesive layer can be provided for the curing.
- connection contact On the substrate, a connection contact may be arranged.
- the connection contact can be configured to a
- an electrically conductive intermediate layer can be arranged on the terminal contact.
- the intermediate layer may be because ⁇ set to compensate for a difference in height between the top of the layer sequence and the upper side of the connection contact.
- the terminal contact can be exposed after the separation of the carrier and the molded body.
- the connection contact can be exposed by means of laser drilling, for example. Releasing the terminal may require removal of one over the Terminal contact arranged portion of the molding umfas ⁇ sen.
- An edge region can be arranged between the layer sequence and a side edge of the first side of the substrate.
- the vertical electrical insulation may be arranged between the edge region arranged on the substrate and the electrically conductive structure.
- the shaped body can at least partially laterally surround the layer sequence. At least in part, it may mean that at least 50% of the lateral edge of the layer sequence is covered by molding compound. Furthermore, the molded body, the
- a via can be arranged.
- the plated-through hole can be designed to electrically conductively connect electrically conductive structures on the first side of the molded body to electrically conductive structures on the second side of the molded body.
- the arranged on the first side of the molded body electrically conductive structure, the layer sequence with the
- the electrically conductive structure can contact the layer sequence directly or indirectly.
- Direct contacting can mean that the electrically conductive structure rests on the layer of the layer sequence to be contacted. Indirect contact may be signified ⁇ th that the electrically conductive structure rests on a connection contact, and the sequence of layers for the buying Closing contact with the electrically conductive structure is connected.
- a recess filled with molding compound can be arranged.
- the recess is filled with molding compound can be filled during the embedding of the chip with the molding composition, that may be part of the mold ⁇ body.
- a reflector layer can be arranged between a lateral edge of the layer sequence and the shaped body.
- the reflector layer can surround the layer sequence.
- Reflector layer may be adapted to reflect light emitted from the layer sequence in the direction of the shaped body.
- Reflector layer may be a transparent insulation layer ⁇ ordered.
- the transparent insulation layer can be provided in particular when the reflector layer is electrically conductive.
- Fig. 1 is a schematic representation of a cross section of a first embodiment
- Fig. 2 is a schematic representation of a plan view of the embodiment shown in Figure 1;
- 3a-3f are schematic representations of a cross section of an embodiment for different process steps
- Fig. 4 is a schematic representation of a cross section of a second embodiment
- Fig. 5 is a schematic representation of a cross section of a third embodiment.
- the term "electronic component” may include, for example, optoelectronic devices, logic devices and Leis ⁇ tung components. Subsequently, the pre schla ⁇ generic solution illustrated by the example of an optoelectronic component, which for the optoelectronic component he ⁇ läuterten features for other Component types are suitable.
- Fig. 1 shows a first embodiment of a elekt ⁇ tronic device 10.
- the illustrated in Fig. 1 Bauele ⁇ ment may for example be a light emitting diode (LED).
- the construction ⁇ element 10 includes a chip 12 and a molding 20.
- the chip 12 illustrated includes a substrate 13, an on ⁇ circuit contact 14 and a series of layers 16.
- the substrate 13 may for example be made of a semiconductor material or on ⁇ whose carrier material for optoelectronic devices, such as sapphire, is formed.
- the terminal contact 14 and the layer sequence 16 are arranged on a first side of the substrate 13.
- the on ⁇ terminal contact 14 may be an ohmic contact.
- the terminal ⁇ contact 14 is a metallic layer.
- the material for the on-circuit terminal 14 can, for example, aluminum or gold ge ⁇ selected.
- the connection contact 14 is arranged to one layer of the layer sequence electrically conductively to kon taktieren ⁇ sixteenth
- the terminal contact 14 is arranged directly on a layer of the layer sequence 16 to be electrically contacted.
- the layer sequence 16 a plurality of layers umfas ⁇ sen which have been applied for example by epitaxy on the first side of the substrate. 13 Between the
- Layer sequence 16 and the terminal contact 14 may be provided a Ver ⁇ depression 18.
- the depression 18 is filled with molding material.
- the layer sequence 16 is set up to emit electromagnetic radiation.
- the electromagnetic radiation emitted by the layer sequence can also be referred to as light in a simplified manner, in which case the term "light” also includes electromagnetic radiation for humans should denote non-visible ultraviolet and infrared wavelengths.
- the terminal contact 14 and the sequence of layers 16 do not reach the edge of the substrate 13. Rather, it is on the first side of the substrate 13 between the on ⁇ circuit contact 14, an edge portion 17 provided to the edge of the sub ⁇ strats 13 and the layer sequence 16 respectively.
- the edge region 17 may be a circumferential region disposed along the edges of the first side of the substrate 13.
- the edge region 17 can be electrically insulating.
- the edge region 17 can be provided, for example, to separate the layer sequence 16 and the connection contact 14 from the-undefined electrical potential of the side surfaces of the chip 12-as a result of the dicing of the chip 12.
- the chip 12 is embedded in a shaped body 20 of molding material.
- the molded body 20 may be provided as a support ⁇ structure for the chip 12.
- the molded body 20 may be provided as a mechanical support for the chip 12.
- the molded body 20 can ver greater ⁇ the surface of the component 10 relative to the base surface of the chip 12th This may be, for example in regard to réellesprei ⁇ -cutting and / or removal of heat desired.
- the molded body 20 can be used for mechanical, electrical and / or thermal arrival bond the chip 12 to an electronic assembly vorgese ⁇ hen be.
- the molded body 20 can facilitate the electrical contacting of the chip 12.
- electrically conductive structures can be provided on and / or in the shaped body 20, electrically conductive structures can be provided. Electrically conductive structures can, for example, vias, layers of electrically conductive Material and bonding include.
- a plurality of chips 12 can also be embedded in a shaped body.
- the upper side of the chip 12 is usually through the upper side of the
- the phrase "the sides lie ⁇ gen substantially in a plane” may mean having that defined by the respective sides of planes offset is less than or equal to 2 .mu.m, in particular the offset is less than or equal to 1 ym may be.
- the first side the shaped body 20 are flush with the top of Schich ⁇ ten tile sixteenth the molded body 20 extends to the lateral edge of the terminal 14 and / or the sequence of layers 16.
- the top of the Rankon ⁇ clock 14 and / or the sequence of layers 16 is not covered with the form ⁇ masse. the top is free from molding material.
- the upper sides of the terminal 14 and / or the sequence of layers 16 is not embedded in the mold body 20.
- the underside of the molded body 20 referred to also as two ⁇ te side of the molded body 20 is 12, hereinafter also referred to as the second side of the chip 12 in a plane with the underside of the chip.
- the height of the shaped body 20 shown thus corresponds substantially to the height of the chip 12.
- the second side of the chip can be incorporated in the form of mass ⁇ embeds 12th
- the material for the molded body 20 for example epoxy ⁇ resin, silicone, epoxy-silicone hybrid material, glass or glass ceramic ⁇ may be provided.
- the shaped body 20 can be highly filled, for example, with quartz glass, titanium oxide, converter particles and / or scattering particles. By choosing suitable filler particles, a white, black, converting or transparent molding can be provided with regard to the respective application.
- the material of the molded body 20 is electrically insulating. Or in other words, the molded body 20 forms an electrical insulation.
- molded body 20 is in addition to the chip 12 a
- the via 22 is electrically conductive.
- the via 22 may be, for example, a metal molded cylinder.
- Through-connection 22 can be embedded in the molded body 20 simultaneously with the embedding of the chip 12.
- Through-connection 22 can, however, also be introduced into the molded body 20 independently of the embedment of the chip 12.
- the via 22 can be provided, for example, to connect the disposed on the first side of the substrate 13 with terminal contact on the underside of molded body 20 is arranged ⁇ contacts.
- Solder terminals 26, 27 have been arranged ⁇ .
- the on the second side of the molded body 20 ordered solder terminals 26, 27 may be provided for surface mounting of the device 10.
- an electrically conductive structure 24 is arranged on the first side of the molded body 20.
- the electrically conductive structure 24 is formed as an electrically conductive layer.
- the electrically conductive layer 24 connects the connecting terminal 14 with the via 22.
- nickel, gold or silver may, for example, aluminum, can be selected.
- the electrically conductive layer 24 may be strip-shaped, for example. A part of the electrically conductive layer 24 rests directly on the first side of the molded body 20.
- the molding body 20 and the rim portion 17 of the substrate 13 covers the the edge portion 17 covering the area of the shaped body 20 forms an electrical insulation 19 between the elekt ⁇ driven conductive layer 24 and the edge region 17 of the substrate 13. Since this electrical insulation 19 is located at the position representation of FIG. 1 with the electrically conductive layer 24 and over the edge of region 17, this portion of the mold body can be referred to as a vertical electric Iso-regulation ⁇ 19th
- the vertical insulation 19 may, for example, have a height which corresponds approximately to the height of the layer sequence 16. In the Darge ⁇ presented in Fig.
- the terminal contact 14 is conductively connected electrically via the electroconductive layer 24 and the via 22 with a first solder connection 26th
- a second solder connection 27 is arranged on the second side of the substrate 13.
- the first and / or the second solder connection 27 can be used for electrical contacting, for mechanical connection of the component 10 and / or for heat dissipation. drove to be set up.
- the second solder connection 27 may be via electrically conductive regions in the substrate 13 a layer of the layer sequence 16 in an electrically conductive PLEASE CONTACT ⁇ ren.
- the second solder connection 27 can be performed relatively large off so that ent ⁇ stationary during operation of the device 10 heat loss via the substrate 13 and the second solder terminal 27 can be derived.
- the optoelectronic component 10 further comprises a coupling-out element 28.
- the coupling-out element 28 may be formed, for example, from a silicone or epoxy resin.
- the decoupling element may for example have the shape of a lens.
- the decoupling element 28 is transparent to the light emitted by the layer sequence 16.
- FIG. 2 is a schematic plan view of that shown in Fig. 1 embodiment, the Darge ⁇ presented in Fig. 2 line 1-1 indicates the position of shown in FIG. 1 ⁇ cross-section.
- the shaped body 20 has a rectangular structure.
- the chip 12 is laterally surrounded by the shaped body 20.
- the upper side of the layer sequence 16 and the connection contacts 14, 15 are not covered with molding compound.
- the substrate 13 is covered by the molded body 20.
- the dimensions of the substrate 13 are indicated in Fig. 2 by the dashed right ⁇ eck.
- the area covered by the molding 20 Randbe ⁇ rich 17 is tet angedeu- in Fig. 2 by the hatched area.
- Fig. 2 are two electrically conductive structures and two vias shown.
- the first electrically conductive layer 24 connects the first connection contact 14 to the first through-connection 22.
- a second electrically conductive layer 25 connects a second connection contact 15 to a second through-connection 23.
- the recess 18 arranged laterally between the connection contacts 14, 15 and the layer sequence 16 filled with potting compound.
- the decoupling element 28 is indicated in Fig. 2 by the illustrated circle.
- FIGS. 3a-3f show a schematic representation of a cross section of the first embodiment for different process steps.
- a carrier 32 is shown.
- the carrier 32 serves as a support during the embedding of the chip 12.
- the carrier 32 may be provided, for example, a semiconductor wafer, a ceramic, a glass or a metal plate.
- the adhesive layer 34 may be applied to the carrier 32 by, for example, spinning, spraying, thermoforming or laminating.
- the adhesive layer is approximately, for example, in the illustrated execution brought to 34 by spinning ⁇ .
- a rotational speed in a range of 2500 to 4000 rpm and a duration in a range of 30 to 120 sec may be provided.
- the applied adhesive layer 34 may have a thickness of 1 .mu.m to 50 .mu.m. INS In particular, the adhesive layer 34 may have a thickness of 10 ym to 20 ym.
- polymers with anti-adhesive properties such as, for example, silicones, can be used.
- Perfluoroalkoxy polymers PFA
- PTFE polytetrafluoroethylene
- A-stage A-stage
- a hardening of the adhesive layer 34 is indicated by the arrows shown.
- the partial curing can for In ⁇ play by a controlled supply of thermal energy ⁇ SUC gene.
- the adhesive layer may be cured, for example, 34 at a temperature of 150 ° C for 6 minutes.
- it is additionally and / or alternatively also possible to supply energy in the form of electromagnetic radiation. Due to the partial curing of a partial crosslinking of the Kle ⁇ be harsh 34.
- the partially crosslinked state takes place of silicone may be referred to as a B-stage.
- Fig. 3d with a predetermined sequence of layers 16 on the adhesive layer 34 ⁇ chip 12 is shown. Due to the properties of the adhesive layer 34 set by the hardening, the chip 12 does not sink into the adhesive layer 34, or only very slightly.
- the permissible sinking depth depends on but may for example be less than 2 ym. In particular, the permissible sinking depth can be less than or equal to 1 ym.
- the viscosity of the adhesive layer 34 can be increased. Due to the increased viscosity of the adhesive layer 34 decreases
- Chip 12 is not or only very little in the adhesive layer 34 a.
- the tackiness of the adhesive layer 34 can be reduced.
- the tackiness of the adhesive layer 34 after curing is still so great that the chip 12 can be fixed on the adhesive layer 34.
- the adhesive layer 34 wets the Be ⁇ ten Chemistry of the chip 12 and particularly the side surfaces of the layer sequence sixteenth
- the adhesive layer 34 is cured. This is indicated in Fig. 3d by the arrows.
- the carrier 32 can be stored with the chip 12, for example for 60 min at 150 ° C.
- substantially more heat energy is supplied during curing than during curing.
- the duration of curing may exceed the duration of hardening.
- the material of the adhesive layer 34 can be largely or completely crosslinked.
- the fully crosslinked state can be referred to as C-stage.
- the material of the adhesive layer 34 may lose its stickiness.
- the surface of the adhesive layer 34 may be smooth after curing.
- Fig. 3e embedded in the molding 20 chip 12 is shown.
- a transfer molding process or a molding process can be provided.
- electrically conductive structures such as the via 22, may be embedded in the molding 20. The embedding of the chip 12 and the electrically conductive structures can take place simultaneously.
- the molding material does not combine with the adhesive layer during the embedding. Rather, after curing, the non-stick properties of the material come to the fore. This facilitates the subsequent separation of the embedded chips 12 from the adhesive layer 34 and the carrier 32.
- the second side of the chip may be covered with mold ⁇ mass 12, so as, for example, in Fig. 3e represents is set ⁇ , or be free of molding material, so as For example, in Fig. 3f is shown. If the second side of the chip 12 is not covered with molding compound, the second side of the molding 20 and the second side of the
- Chips 12 lie substantially in a plane. Starting from the state shown in Fig. 3e, for example, the second side of the molding 20 can be removed until the second side of the chip 12 is exposed. Alternatively, the embedding of the chip 12 may already be designed such that the second side of the chip 12 is not covered with molding compound during embedding. This can be achieved for example by a ge ⁇ suitable embodiment of a molding tool.
- Fig. 3f the molded body 20 with the embedded chip 12 after separation from the adhesive layer 34 and the carrier 32 is shown. After separation, electrically conductive structures are applied to the first and / or second side of the molded body 20. For example, electrically conductive
- Structures in the form of electrically conductive layers 24, 25 are attached to the first side of the molded body 20.
- the electrically conductive layers 24, 25 respectively connect the terminal contacts 14, 15 with the plated-through holes 22, 23.
- solder terminals connected to the plated-through holes may be attached to the second side of the molded body 20 and / or to the second side of the chip 12, for example , which are provided for electrical contacting and surface mounting of the device 10.
- the solder terminals provided for surface mounting may also be disposed on the first side of the molded body 20.
- electrically conductive structure 24 mounted on the first side of the molded body 20 is electrically conductive structure 24 may be a solder connection or can be connected electrically conductively to a 20 are arrange ⁇ th on the first side of the molding solder connection.
- LötanInstitut can be, for example, a Lotperle, a solder ball and / or a pad of a device with BGA housing form.
- a decoupling element 28 can be attached via the shaped body.
- the Auskoppelement 28 can be applied for example in egg nem separate molding on the already embedded chip 12.
- 4 is a schematic cross-sectional view of a second embodiment.
- the second embodiment differs from the first embodiment, for example, in that the layer sequence 46 is higher than the terminal contact 44.
- the distance may be 6 ym, for example.
- the distance can be compensated by an electrically conductive intermediate layer 48.
- the intermediate layer 48 can already be applied to the connection contact 44 during the front-end production, ie before the singulation of the chips 12.
- the material for the intermediate layer 48 for example, aluminum can be selected.
- the intermediate layer 48 can also be applied after the dicing of the chips 12 or after the embedding of the chips 12 on the terminal contact 44. If after the embedding of the chip is to be applied intermediate layer 48 ⁇ 12, the surface of the terminal 44 must be exposed after embedding. In particular, a formed during embedding to the connection contact 44 Be ⁇ area of the mold body 20 must be removed. For example, a laser can be used to drill a hole reaching the connection contact 44 into the molding 20. But it is also possible to dispense with the application of an intermediate layer. In this case, the exposed after embedding terminal contact 44 is contacted directly by an electrically conductive structure.
- FIG. 4 shows a shaped body 20 which also covers the second side of the chip 12. Shown is whether the second side of the chip 12 is exposed, as for example in Fig. 1 Darge ⁇ , or is embedded in the mold body 20, as shown in Fig. 4, depends on the particular application of the
- FIG. 5 schematically shows a cross section of a third exemplary embodiment.
- the chip 52 is embedded in a shaped body 20. At least a portion of the sub ⁇ strats 53 of the chip 52 is electrically conductive. On the sub ⁇ strat 53 is a sequence of layers 56 is disposed.
- the Schich ⁇ tenier 56 has a mirror layer on the 55th
- the mirror layer 55 can be arranged as the lowermost layer of the layer sequence 56 directly on the substrate 53.
- the material for the reflective layer 55 can be selected as silver ⁇ to.
- the mirror layer 55 is configured to reflect the light emitted by the layer sequence 56 in the direction of the substrate 53.
- the mirror layer 55 may be provided for electrical contacting of the layer sequence 56.
- the mirror layer 55 may be connected to an electrically conductive region of the substrate 53. This electrically conductive region of the substrate 53 can extend vertically through the substrate 53 and Layer 55 electrically connected to a mounted on the second side of the substrate 53 first contact 66.
- an electrically conductive structure 64 is arranged on the first side of the molded body 20 for electrical contacting of the layer sequence 56.
- the electrically conductive structural ⁇ structure 64 rests on the layer sequence 56, and thus contacted them directly.
- indirect contacting may also be provided.
- the electrically conductive structure 64 is electrically conductively connected via a through-connection 62 to a second contact 67 arranged on the second side of the shaped body 20. Between the first side of the substrate 53 and the electrically conductive structure 64, a region of the molded body 20 forms a vertical insulation 19.
- a trans ⁇ parente insulation layer 58 is disposed at the lateral edge of the layer sequence 56.
- the transparent insulation layer 58 is transparent to the light emitted by the layer sequence 56.
- Insulation layer 58 an electrical insulation.
- Materi ⁇ al for the insulating layer 58 can, for example
- Reflector layer 60 is arranged. As material for the
- Reflector layer 60 may be selected, for example, silver or aluminum. Furthermore, the reflector layer 60 can also be constructed as a Bragg mirror. When the reflector layer 60 is formed of an electrically insulating material, can be dispensed with the transparent insulating layer 56. The reflector layer 60 is configured to reflect the light emitted laterally by the layer sequence 56. Thereby, the reflector layer 60 protects the form ⁇ body 20 before the light emitted from the layer sequence 56
- the light-induced aging of the molded body 20 can thus be slowed down.
- Reflector layer 60 may be part of the layer sequence 56.
- Reflector layer 60 may be applied to chip 12 during front-end fabrication.
- the mirror layer 55, the transparent insulating layer 58 and the reflective layer 60 are independent of the clocking of described in United ⁇ connection with Fig. 5 variant of the electrical Kon. Accordingly, these features may be provided individually or in combination also in the embodiments explained in connection with FIGS. 1, 2, 3 and 4.
- a method for producing an electronic component is specified.
- one of many possibilities for producing the electronic component described here can be realized by means of the method described here. That is to say that all features described for the electrostatic ⁇ African device are also disclosed for the procedural ⁇ ren and vice versa.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Led Device Packages (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/033,157 US20160276545A1 (en) | 2013-10-31 | 2014-10-16 | Electronic component and method for producing an electronic component |
DE112014005022.9T DE112014005022A5 (de) | 2013-10-31 | 2014-10-16 | Elektronisches Bauelement und Verfahren zum Herstellen eines elektronischen Bauelements |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102013222200.9A DE102013222200A1 (de) | 2013-10-31 | 2013-10-31 | Elektronisches Bauelement und Verfahren zum Herstellen eines elektronischen Bauelements |
DE102013222200.9 | 2013-10-31 |
Publications (1)
Publication Number | Publication Date |
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WO2015062867A1 true WO2015062867A1 (de) | 2015-05-07 |
Family
ID=51842494
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2014/072180 WO2015062867A1 (de) | 2013-10-31 | 2014-10-16 | Elektronisches bauelement und verfahren zum herstellen eines elektronischen bauelements |
Country Status (3)
Country | Link |
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US (1) | US20160276545A1 (de) |
DE (2) | DE102013222200A1 (de) |
WO (1) | WO2015062867A1 (de) |
Cited By (3)
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DE102015108056A1 (de) * | 2015-05-21 | 2016-11-24 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauteil, optoelektronische Anordnung und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils |
WO2016198502A1 (de) * | 2015-06-11 | 2016-12-15 | Osram Opto Semiconductors Gmbh | Optoelektronisches bauelement und herstellungsverfahren dafür |
WO2018024705A1 (de) * | 2016-08-02 | 2018-02-08 | Osram Opto Semiconductors Gmbh | Multichipmodul |
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DE102014116079A1 (de) * | 2014-11-04 | 2016-05-04 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement und Verfahren zu seiner Herstellung |
US10825974B2 (en) | 2016-06-07 | 2020-11-03 | Plessey Semiconductors Limited | Light-emitting diode package and method of manufacture |
US10439114B2 (en) * | 2017-03-08 | 2019-10-08 | Cree, Inc. | Substrates for light emitting diodes and related methods |
US10407298B2 (en) * | 2017-07-28 | 2019-09-10 | Advanced Semiconductor Engineering Korea, Inc. | Microelectromechanical systems and method of manufacturing the same |
DE102019118543B4 (de) * | 2019-07-09 | 2023-02-16 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Anordnung von elektronischen halbleiterbauelementen und verfahren zum betrieb einer anordnung von elektronischen halbleiterbauelementen |
DE102022102494A1 (de) | 2022-02-02 | 2023-08-03 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronisches bauelementepackage und verfahren |
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- 2014-10-16 WO PCT/EP2014/072180 patent/WO2015062867A1/de active Application Filing
- 2014-10-16 US US15/033,157 patent/US20160276545A1/en not_active Abandoned
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Also Published As
Publication number | Publication date |
---|---|
DE112014005022A5 (de) | 2016-08-11 |
DE102013222200A1 (de) | 2015-08-27 |
US20160276545A1 (en) | 2016-09-22 |
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