WO2015055005A1 - 电平转移电路、栅极驱动电路及显示装置 - Google Patents

电平转移电路、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2015055005A1
WO2015055005A1 PCT/CN2014/077707 CN2014077707W WO2015055005A1 WO 2015055005 A1 WO2015055005 A1 WO 2015055005A1 CN 2014077707 W CN2014077707 W CN 2014077707W WO 2015055005 A1 WO2015055005 A1 WO 2015055005A1
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Prior art keywords
transistor
circuit
bias
gate
terminal
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English (en)
French (fr)
Inventor
刘宝玉
张亮
许益祯
孙志华
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US14/430,016 priority Critical patent/US9646554B2/en
Publication of WO2015055005A1 publication Critical patent/WO2015055005A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit

Definitions

  • the present disclosure relates to a level shifting circuit, a gate driving circuit, and a display device. Background technique
  • the function of the gate driving circuit is to generate a scanning signal required for the liquid crystal display panel such that each scanning line is sequentially turned on in order.
  • the gate drive circuit is mainly composed of circuits such as a shift register, a level shift circuit, and a buffer. Among them, the level shifting circuit is particularly important, and it directly supplies the voltage required for each gate of the liquid crystal display panel to be turned on.
  • the level shift circuit is a typical amplifying circuit. Generally, a differential amplifying circuit is used to improve the anti-interference ability against environmental noise.
  • the level shift circuit shown in FIG. 1 includes a P-type transistor. M3 and M4, N-type transistors M0, M1 and M2; the sources of P-type transistors M3 and M4 are respectively connected to the power supply V DD , and the gates of the P-type transistors M3 and M4 are respectively connected to the output V Bias of the bias circuit, P
  • the drain of the transistor M3 serves as the first output terminal OUTi; the drain of the P-type transistor M4 serves as the second output terminal OUT 2 ; the drain of the N-type transistor M1 is connected to the first output terminal OU, and the drain of the N-type transistor M2 Connected to the second output terminal OUT 2 ; the gates of the NMOS transistors M1 and M2 are connected to the input signal V In ; the sources of the N-type transistors M1 and M2 are
  • the differential amplifying circuit since the gain of the differential amplifying circuit is inversely proportional to the transconductance of the load transistor, and the transconductance is proportional to the load transistor, the differential amplifying circuit is usually reduced in order to obtain a larger gain.
  • the aspect ratio of the load transistor is to reduce the transconductance of the load transistor, thereby achieving the purpose of increasing the gain of the differential amplifying circuit.
  • to reduce the width to length ratio of load transistor will reduce the common mode voltage between a first output terminal of the differential amplifier circuit and a second output terminal of the power source ground V ss. Summary of the invention
  • At least one embodiment of the present invention provides a level shifting circuit, a gate driving circuit, and a display device.
  • the level shifting circuit is configured to solve the known problem of increasing the amplification gain by reducing the aspect ratio of the load transistor. problems first output terminal and a common mode voltage between the output terminal and a second power source V ss polar reduced differential amplifier circuit.
  • At least one embodiment of the present invention provides a level shifting circuit including a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M0. ;
  • the sources of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are respectively connected to the DC power source V DD , and the gates are respectively connected to the bias voltage terminal V Bias ;
  • the drains of the third transistor M3 and the fifth transistor M5 are connected as a first output terminal OUTi; the drains of the fourth transistor M4 and the sixth transistor M6 are connected as a second output terminal OUT 2 ;
  • a drain of the first transistor M1 is connected to the first output terminal OU, a drain of the second transistor M2 is connected to the second output terminal OUT 2 ; the first transistor M1 and the second The gate of the transistor M2 is connected to the input signal terminal V In , the source is connected to the drain of the seventh transistor M0 , and the input signal terminal V In provides a signal to be level-converted; the seventh transistor M0 The source is connected to the source power source V ss , and the gate is connected to the bias voltage terminal V Bias .
  • the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are P-type transistors, and the first transistor M1, the second transistor M2, and The seventh transistor M0 is an N-type transistor.
  • the first transistor M1 and the second transistor M2 have the same width to length ratio.
  • the signal to be level-converted provided by the input signal terminal V In is an analog signal.
  • the beneficial effects of at least one embodiment of the present invention are as follows: For a wide aspect ratio of a load transistor in a given level shifting circuit, the transconductance of the load transistor is reduced by subtracting d, the current flowing through the load transistor, and the level shift is improved. The gain of the circuit; since the aspect ratio of the load transistor is not reduced, the common mode voltage between the two output terminals of the level shifting circuit and the source power source is not lowered.
  • At least one embodiment of the present invention provides a gate driving circuit including a bias circuit including a bias voltage terminal V Bias and a level shifting circuit as described in the above embodiments.
  • the gates of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 of the level shift circuit are respectively connected to the bias voltage terminal V Bias provided by the bias circuit; the seventh of the level shift circuit
  • the gate of the transistor M0 is connected to the bias voltage terminal V Bias .
  • the beneficial effects of at least one embodiment of the present invention are as follows:
  • the level shifting circuit included in the gate driving circuit reduces the width to length ratio of the load transistor in a given level shifting circuit by reducing the current flowing through the load transistor
  • the transconductance of the small load transistor increases the gain of the level shifting circuit. Since the aspect ratio of the load transistor is not reduced, the common mode voltage between the two output terminals of the level shifting circuit and the source power source is not lowered, ensuring The driving capability of the gate drive circuit.
  • At least one embodiment of the present invention provides a display device including an array substrate on which a pixel array and a gate signal line for driving the pixel array are disposed, and a gate including the above embodiment a driving circuit, the first output terminal OU and the second output terminal ⁇ 2 of the level shifting circuit included in the gate driving circuit are simultaneously connected to the gate signal line.
  • the beneficial effects of at least one embodiment of the present invention are as follows:
  • the level shifting circuit included in the gate driving circuit reduces the width to length ratio of the load transistor in a given level shifting circuit by reducing the current flowing through the load transistor
  • the transconductance of the small load transistor increases the gain of the level shifting circuit. Since the aspect ratio of the load transistor is not reduced, the common mode voltage between the two output terminals of the level shifting circuit and the source power source is not lowered, ensuring The ability of the gate drive circuit to drive the pixel array ensures the display effect.
  • FIG. 2 is a level shift circuit according to an embodiment of the present invention. detailed description
  • the level shifting circuit includes a first transistor M1, a second transistor ⁇ 2, a third transistor ⁇ 3, and a fourth transistor. M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M0.
  • the sources of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are respectively connected to the DC power source V DD , and the gates are respectively connected to the bias voltage terminal V Bias ; the third transistor M3 and the fifth transistor the drain terminal of M5 is connected to a first output 017 as ⁇ ; the fourth transistor M4 and the drain of the sixth transistor M6 is connected to the second output terminal OUT 2.
  • the drain of the first transistor M1 is connected to the first output terminal OUT, the drain of the second transistor M2 is connected to the second output terminal OUT 2 ; the gates of the first transistor M1 and the second transistor M2 are both connected to the input signal terminal V In
  • the source is connected to the drain of the seventh transistor M0, the input signal terminal Vin provides a signal to be level-converted; the source of the seventh transistor M0 is connected to the source power source V ss , and the gate and the bias voltage terminal V Bias connection.
  • the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are P-type transistors, and the first transistor M1, the second transistor M2, and the seventh transistor M0 are N-type transistors.
  • the fifth transistor M5 and the sixth transistor M6 at the load end, the current flowing through the third transistor M3 and the fourth transistor M4 as the load transistor is reduced, thereby reducing as shown in FIG. Transconductance of the level shifting circuit.
  • the level shifting circuit of the known technical solution shown in FIG. 1 is a typical differential amplifying circuit, and the gain calculating formula of the differential amplifying circuit is as shown in the formula (1).
  • gmN is the transconductance of the differential pair of the N-type transistor
  • g is the transconductance of the differential pair of the P-type transistor
  • p is the internal resistance of the ⁇ -type transistor.
  • the gain of the differential amplifier circuit depends on the ratio of the transconductance of the N-type transistor and the P-type transistor.
  • the gain " ⁇ needs to be adjusted, it is usually ⁇
  • the transconductance of the load transistor ⁇ i.e., P-type transistor M3 in FIG adjusting the transconductance and M4 shown in FIG 1 ⁇ m P
  • the transconductance gm is shown in equation (2): Equation (2) where V DS is the source-drain voltage of the transistor, V GS is the gate-to-source voltage of the transistor, VTH is the threshold voltage of the transistor, is the oxide layer capacitance, is the mobility of the transistor, and W is the channel width of the transistor L is the channel length of the transistor, which is biased, and the bias current ⁇ is as shown in equation (3):
  • the transconductance gmP of the W_tubes M3 and M4 is usually achieved by reducing the aspect ratio of the P-type transistors M3 and M4. But for a given bias current ⁇ , when reducing the width W_ of the ⁇ -type transistors ⁇ 3 and ⁇ 4
  • the fifth transistor connected in parallel with the third transistor M3 is added to the load terminal.
  • M5 the sixth transistor M6 connected in parallel with the fourth transistor M4, the bias current flowing through each P-type transistor flowing as a load is reduced without changing the width-to-length ratio W/L of the given load transistor, thereby reducing The transconductance of the differential pair of P-type transistors.
  • the width ratios of the first transistor M1 and the second transistor M2 are equal.
  • the signal to be level-converted provided by the input signal terminal V In is an analog signal.
  • the beneficial effects of at least one embodiment of the present invention are as follows: For a wide aspect ratio of a load transistor in a given level shifting circuit, the transconductance of the load transistor is reduced by reducing the current flowing through the load transistor, and the level shifting circuit is improved Gain; Since the aspect ratio of the load transistor is not reduced, the common mode voltage between the two output terminals of the level shifting circuit and the source power source does not decrease.
  • At least one embodiment of the present invention provides a gate driving circuit including a bias circuit including a bias voltage terminal V Bias , the gate driving circuit further including level shifting as described in the above embodiments a gate of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 of the level shift circuit is respectively connected to a bias voltage terminal V Bias provided by the bias circuit; The gate of the seven transistor M0 is connected to the bias voltage terminal V Bias .
  • the beneficial effects of at least one embodiment of the present invention are as follows:
  • the level shifting circuit included in the gate driving circuit reduces the width to length ratio of the load transistor in a given level shifting circuit by reducing the current flowing through the load transistor
  • the transconductance of the small load transistor increases the gain of the level shifting circuit. Since the aspect ratio of the load transistor is not reduced, the two output terminals of the level shifting circuit and the source power source The common mode voltage between them does not decrease, ensuring the driving capability of the gate drive circuit.
  • At least one embodiment of the present invention provides a display device including an array substrate on which an array of pixels and a gate signal line for driving the pixel array are disposed, and a gate driving circuit including the above-described embodiment, the gate The first output terminal OU and the second output terminal OUT 2 of the level shift circuit included in the pole drive circuit are simultaneously connected to the gate signal line.
  • the beneficial effects of at least one embodiment of the present invention are as follows:
  • the level shifting circuit included in the gate driving circuit reduces the width to length ratio of the load transistor in a given level shifting circuit by reducing the current flowing through the load transistor
  • the transconductance of the small load transistor increases the gain of the level shifting circuit. Since the aspect ratio of the load transistor is not reduced, the common mode voltage between the two output terminals of the level shifting circuit and the source power source is not lowered, ensuring The ability of the gate drive circuit to drive the pixel array ensures the display effect.

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Abstract

一种电平转移电路、栅极驱动电路及显示装置。该电平转移电路包括：第三晶体管（M3）、第四晶体管（M4）、第五晶体管（M5）和第六晶体管（M6），源极分别与直流电源（VDD）连接，栅极分别与偏置电压端（VBias）连接，其中，第三晶体管（M3）和第五晶体管（M5）的漏极连接作为第一输出端（OUT1），第四晶体管（M4）和第六晶体管（M6）的漏极连接作为第二输出端（OUT2）；第一晶体管（M1）和第二晶体管（M2），栅极均与输入信号端（VIn）连接，源极均与第七晶体管（M0）的漏极连接，其中，第一晶体管（M1）的漏极与第一输出端（OUT1）连接，第二晶体管（M2）的漏极与第二输出端（OUT2）连接；第七晶体管（M0），其源极与源极地电源（VSS）连接，栅极与偏置电压端（VBias）连接。电平转移电路的两输出端与源极地电源之间的共模电压不会降低。

Description

电平转移电路、 栅极驱动电路及显示装置 技术领域
本公开涉及一种电平转移电路、 栅极驱动电路及显示装置。 背景技术
在许多集成电路中， 为满足集成电路中不同半导体器件的耐压要求， 需 要将较低的电平信号转换成较高的电平信号， 或者将较高的电平信号转换成 较低的电平信号， 电平转移电路即用于实现这种功能。
液晶显示技术中， 栅极驱动电路的功能是产生液晶显示面板所需要的扫 描信号， 使得每一扫描行按照次序依次导通。 栅极驱动电路主要由移位寄存 器、 电平转移电路和緩冲器等电路组成。 其中电平转移电路尤为重要， 它直 接提供液晶显示面板中各栅极开启所需要的电压。
在栅极驱动电路中， 电平转移电路是一个典型的放大电路， 一般釆用差 动放大电路来提高对环境噪声的抗干扰能力， 如图 1所示的电平转移电路， 包括 P型晶体管 M3和 M4， N型晶体管 M0、 Ml和 M2; P型晶体管 M3 和 M4的源极分别与电源 VDD连接， P型晶体管 M3和 M4的栅极分别与偏 置电路的输出 VBias连接， P型晶体管 M3的漏极作为第一输出端 OUTi; P型 晶体管 M4的漏极作为第二输出端 OUT2; N型晶体管 Ml的漏极与第一输出 端 OU 连接， N型晶体管 M2的漏极与第二输出端 OUT2连接； Ν型晶体管 Ml和 M2栅极与输入信号 VIn连接； N型晶体管 Ml和 M2的源极与 N型晶 体管 M0的漏极连接； N型晶体管 M0的源极与源极地电源 Vss连接， N型 晶体管 M0栅极与偏置电路的输出 VBias连接。 对于差动放大电路， 由于差动 放大电路的增益与负载晶体管的跨导成反比， 而且跨导又与该负载晶体管成 正比， 因此， 为了获取更大的增益， 通常减小该差动放大电路的负载晶体管 的宽长比以减小负载晶体管的跨导，实现提高该差动放大电路的增益的目的。 但是， 负载晶体管的宽长比的减小会降低差动放大电路的第一输出端和第二 输出端与源极地电源 Vss之间的共模电压。 发明内容
本发明的至少一个实施例提供一种电平转移电路、 栅极驱动电路及显示 装置， 电平转移电路用于解决已知的通过减小负载晶体管的宽长比来提高提 高放大增益时， 会降低差动放大电路的第一输出端和第二输出端与源极地电 源 Vss之间的共模电压的问题。
本发明的至少一个实施例提供一种电平转移电路， 包括第一晶体管 Ml、 第二晶体管 M2、 第三晶体管 M3、 第四晶体管 M4、 第五晶体管 M5、 第六 晶体管 M6和第七晶体管 M0;
所述第三晶体管 M3、 所述第四晶体管 M4、 所述第五晶体管 M5和所述 第六晶体管 M6的源极分别与直流电源 VDD连接，栅极分别与偏置电压端 VBias 连接； 所述第三晶体管 M3和所述第五晶体管 M5的漏极连接作为第一输出 端 OUTi;所述第四晶体管 M4和所述第六晶体管 M6的漏极连接作为第二输 出端 OUT2;
所述第一晶体管 Ml的漏极与所述第一输出端 OU 连接， 所述第二晶 体管 M2的漏极与所述第二输出端 OUT2连接； 所述第一晶体管 Ml和所述 第二晶体管 M2栅极均与输入信号端 VIn连接， 源极均与所述第七晶体管 M0 的漏极连接， 所述输入信号端 VIn提供待进行电平转换的信号； 所述第七晶 体管 M0的源极与源极地电源 Vss连接， 栅极与所述偏置电压端 VBias连接。
可替换地， 所述第三晶体管 M3、 所述第四晶体管 M4、 所述第五晶体管 M5和所述第六晶体管 M6为 P型晶体管， 所述第一晶体管 Ml、 所述第二晶 体管 M2和所述第七晶体管 M0为 N型晶体管。
可替换地， 所述第一晶体管 Ml和所述第二晶体管 M2的宽长比相等。 可替换地， 所述输入信号端 VIn提供的待进行电平转换的信号为模拟信 号。
本发明的至少一个实施例的有益效果如下： 对于给定电平转移电路中负 载晶体管的宽长比， 通过减 d、流经负载晶体管的电流来减小负载晶体管的跨 导， 提高电平转移电路的增益； 由于未减小负载晶体管的宽长比， 因此电平 转移电路的两输出端与源极地电源之间的共模电压不会降低。
本发明的至少一个实施例提供一种栅极驱动电路， 包括偏置电路， 所述 偏置电路包括偏置电压端 VBias， 还包括如上述实施例所述的电平转移电路， 该电平转移电路的第三晶体管 M3、 第四晶体管 M4、 第五晶体管 M5和第六 晶体管 M6的栅极分别与偏置电路提供的偏置电压端 VBias连接； 电平转移电 路的第七晶体管 M0的栅极与偏置电压端 VBias连接。
本发明的至少一个实施例的有益效果如下： 栅极驱动电路所包括的电平 转移电路， 对于给定电平转移电路中负载晶体管的宽长比， 通过减小流经负 载晶体管的电流来减小负载晶体管的跨导从而提高电平转移电路的增益， 由 于未减小负载晶体管的宽长比， 因此电平转移电路的两输出端与源极地电源 之间的共模电压不会降低， 确保了栅极驱动电路的驱动能力。
本发明的至少一个实施例提供一种显示装置， 包括阵列基板， 所述阵列 基板上设置像素阵列和用于驱动所述像素阵列的栅极信号线； 以及包括如上 述实施例所述的栅极驱动电路， 所述栅极驱动电路所包括的电平转移电路的 第一输出端 OU 和第二输出端 ουτ2同时连接所述栅极信号线。
本发明的至少一个实施例的有益效果如下： 栅极驱动电路所包括的电平 转移电路， 对于给定电平转移电路中负载晶体管的宽长比， 通过减小流经负 载晶体管的电流来减小负载晶体管的跨导从而提高电平转移电路的增益， 由 于未减小负载晶体管的宽长比， 因此电平转移电路的两输出端与源极地电源 之间的共模电压不会降低， 确保了栅极驱动电路的驱动像素阵列的能力， 从 而保证显示效果。 附图说明
图 1为已知的技术方案的电平转移电路；
图 2为本发明实施例提供的一种电平转移电路。 具体实施方式
下面结合说明书附图对本发明实施例的实现过程进行详细说明。 需要注 意的是， 附图中相同或类似的标号表示相同或类似的元件。 下面通过参考附 图描述的实施例是示例性的， 仅用于解释本发明， 而不能理解为对本发明的 限制。
图 2是本发明实施例提供的一种电平转移电路。 如图 2所示， 该电平转 移电路 包括第一晶体管 Ml、 第二晶体管 Μ2、 第三晶体管 Μ3、 第四晶体管 M4、 第五晶体管 M5、 第六晶体管 M6和第七晶体管 M0。
第三晶体管 M3、 第四晶体管 M4、 第五晶体管 M5和第六晶体管 M6的 源极分别与直流电源 VDD连接，栅极分别与偏置电压端 VBias连接； 第三晶体 管 M3和第五晶体管 M5的漏极连接作为第一输出端 017^; 第四晶体管 M4 和第六晶体管 M6的漏极连接作为第二输出端 OUT2。
第一晶体管 Ml的漏极与第一输出端 OUT连接， 第二晶体管 M2的漏 极与第二输出端 OUT2连接； 第一晶体管 Ml和第二晶体管 M2栅极均与输 入信号端 VIn连接， 源极均与第七晶体管 M0的漏极连接， 输入信号端 Vin提 供待进行电平转换的信号； 第七晶体管 M0的源极与源极地电源 Vss连接， 栅极与偏置电压端 VBias连接。
可替换地， 第三晶体管 M3、 第四晶体管 M4、 第五晶体管 M5和第六晶 体管 M6为 P型晶体管， 第一晶体管 Ml、 第二晶体管 M2和第七晶体管 M0 为 N型晶体管。
本发明实施例中， 通过在负载端增加第五晶体管 M5和第六晶体管 M6， 使流经作为负载晶体管的第三晶体管 M3和第四晶体管 M4的电流减小， 从 而减小如图 2所示电平转移电路的跨导。
详细原理及推导过程如下：
图 1 所示的已知的技术方案的电平转移电路是一个典型的差动放大电 路， 差动放大电路增益计算公式如公式（ 1 )
Figure imgf000006_0001
gmP 公式（ 1 ) 其中， gmN 为 N型晶体管差分对的跨导， g 为 P型晶体管差分对的 跨导， 为N型晶体管的内阻， p为卩型晶体管的内阻。
A
在 N型晶体管和 P型晶体管同时工作时， 差动放大电路的增益 取决 于 N型晶体管和 P型晶体管的跨导的比值， 在需要调整增益" ^时， 通常釆 用调整负载晶体管的跨导^^， 即调整如图 1所示 P型晶体管 M3和 M4的 跨导 ^ mP 因此，为了使增益 A 增大，通常减小 Ρ型晶体管 Μ3和 Μ4的跨导 gmP， 而跨导 gm如公式（ 2 )所示：
Figure imgf000007_0001
公式（2 ) 其中， VDS为晶体管的源漏电压， VGS为晶体管的栅源电压， VTH为晶体 管的阔值电压， 为氧化层电容， 为晶体管的迁移率， W为晶体管的 沟道宽度， L为晶体管的沟道长度， 为偏置 其中， 偏置电流 β如公式（3 )所示：
Figure imgf000007_0002
公式（3 ) 对于如图 1所示的差动放大电路， 根据公式 (2 ) ， 为了减小 P型晶体
W_ 管 M3和 M4的跨导 gmP， 通常通过减小 P型晶体管 M3和 M4的宽长比 来实现。 但是对于给定的偏置电流 β， 当减小 Ρ型晶体管 Μ3和 Μ4的宽长 W_
比 时， 造成 gs _ ?^增大。 因此对于整个差动放大电路而言， 由于电路 的电源 VDD保持一定值，负载晶体管的 P型晶体管 M3和 M4的 Vgs ~ V™增 大， 也就意味着输出信号对地的共模电压将减小， 使得如图 1所示的电平转 移电路的驱动能力受限。 为了解决上述问题， 根据公式（2 )和公式（3 )推导出表示跨导 ^∞的 另一公式（4 ) ， 如下：
Figure imgf000008_0001
公式（4 ) 由公式（4 )可知， 在不改变给定负载晶体管的尺寸的情况下， 可以改变 偏置电流7 以实现减小跨导 gm。 相比如图 1所示的电平转移电路， 根据上述原理， 在本发明实施例提供 的如图 2所示的电平转移电路中， 在负载端增加了与第三晶体管 M3并联的 第五晶体管 M5， 与第四晶体管 M4并联的第六晶体管 M6， 在不改变给定负 载晶体管的宽长比 W/L的情况下，流经作为负载的各 P型晶体管偏置电流减 小， 从而减小了 P型晶体管差分对的跨导。
可替换地， 第一晶体管 Ml和第二晶体管 M2的宽长比相等。
可替换地， 输入信号端 VIn提供的待进行电平转换的信号为模拟信号。 本发明的至少一个实施例的有益效果如下： 对于给定电平转移电路中负 载晶体管的宽长比， 通过减小流经负载晶体管的电流来减小负载晶体管的跨 导， 提高电平转移电路的增益； 由于未减小负载晶体管的宽长比， 因此电平 转移电路的两输出端与源极地电源之间的共模电压不会降低。
本发明的至少一个实施例提供一种栅极驱动电路， 包括偏置电路， 所述 偏置电路包括偏置电压端 VBias， 该栅极驱动电路还包括如上述实施例所述的 电平转移电路； 电平转移电路的第三晶体管 M3、 第四晶体管 M4、 第五晶体 管 M5和第六晶体管 M6的栅极分别与偏置电路提供的偏置电压端 VBias连接； 电平转移电路的第七晶体管 M0的栅极与偏置电压端 VBias连接。
本发明的至少一个实施例的有益效果如下： 栅极驱动电路所包括的电平 转移电路， 对于给定电平转移电路中负载晶体管的宽长比， 通过减小流经负 载晶体管的电流来减小负载晶体管的跨导从而提高电平转移电路的增益， 由 于未减小负载晶体管的宽长比， 因此电平转移电路的两输出端与源极地电源 之间的共模电压不会降低， 确保了栅极驱动电路的驱动能力。
本发明的至少一个实施例提供一种显示装置， 包括阵列基板， 阵列基板 上设置像素阵列和用于驱动像素阵列的栅极信号线； 以及包括如上述实施例 所述的栅极驱动电路， 栅极驱动电路所包括的电平转移电路的第一输出端 OU 和第二输出端 OUT2同时连接所述栅极信号线。
本发明的至少一个实施例的有益效果如下： 栅极驱动电路所包括的电平 转移电路， 对于给定电平转移电路中负载晶体管的宽长比， 通过减小流经负 载晶体管的电流来减小负载晶体管的跨导从而提高电平转移电路的增益， 由 于未减小负载晶体管的宽长比， 因此电平转移电路的两输出端与源极地电源 之间的共模电压不会降低， 确保了栅极驱动电路的驱动像素阵列的能力， 从 而保证显示效果。 发明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。
本申请要求于 2013年 10月 15日递交的中国专利申请第 201310482290.3 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1.一种电平转移电路， 包括第一晶体管 （Ml) 、 第二晶体管 （M2) 、 第三晶体管（M3) 、 第四晶体管 （M4) 、 第五晶体管 （M5) 、 第六晶体管 (M6)和第七晶体管 （M0) ；
其中， 所述第三晶体管 （M3) 、 所述第四晶体管 （M4) 、 所述第五晶 体管 （M5)和所述第六晶体管 （M6) 的源极分别与直流电源 （VDD)连接， 栅极分别与偏置电压端（VBias)连接； 所述第三晶体管（M3)和所述第五晶 体管 （M5) 的漏极连接作为第一输出端 （OUTJ ； 所述第四晶体管 （M4) 和所述第六晶体管 （M6) 的漏极连接作为第二输出端 （OUT2) ；
并且其中， 所述第一晶体管 （Ml) 的漏极与所述第一输出端 （OUTJ 连接， 所述第二晶体管 （M2) 的漏极与所述第二输出端 （OUT2)连接； 所 述第一晶体管 （Ml)和所述第二晶体管 （M2)栅极均与输入信号端 （VIn) 连接， 源极均与所述第七晶体管（M0)的漏极连接， 所述输入信号端（VIn) 提供待进行电平转换的信号； 所述第七晶体管 （M0) 的源极与源极地电源 (Vss)连接， 栅极与所述偏置电压端 （VBias)连接。
2.如权利要求 1所述的电平转移电路， 其中， 所述第三晶体管 （M3) 、 所述第四晶体管 （M4) 、 所述第五晶体管 （M5)和所述第六晶体管 （M6) 为 P型晶体管， 所述第一晶体管 （Ml) 、 所述第二晶体管 （M2)和所述第 七晶体管 （M0) 为 N型晶体管。
3.如权利要求 1至 2中任一项所述的电平转移电路， 其中， 所述第一晶 体管 （Ml)和所述第二晶体管 （M2) 的宽长比相等。
4.如权利要求 1至 3中任一项所述的电平转移电路， 其中， 所述输入信 号端 （VIn)提供的待进行电平转换的信号为模拟信号。
5.—种栅极驱动电路， 包括偏置电路， 所述偏置电路包括偏置电压端
( VBias ) ， 其中， 所述栅极驱动电路还包括如权利要求 1至 4任一项所述的 电平转移电路， 该电平转移电路的第三晶体管（M3)、 第四晶体管（M4)、 第五晶体管 （M5)和第六晶体管 （M6) 的栅极分别与偏置电路提供的偏置 电压端（VBias)连接； 电平转移电路的第七晶体管（M0)的栅极与偏置电路 提供的偏置电压端 （VBias)连接。
6.—种显示装置， 包括阵列基板， 所述阵列基板上设置像素阵列和用于 驱动所述像素阵列的栅极信号线； 其中， 所述显示装置包括如权利要求 5所 述的栅极驱动电路， 所述栅极驱动电路所包括的电平转移电路的第一输出端
( OUTj )和第二输出端 （ ουτ2 ) 同时连接所述栅极信号线。
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CN103338015A (zh) * 2013-05-28 2013-10-02 南京邮电大学 一种提高增益的放大器及其设计方法
CN103532539A (zh) * 2013-10-15 2014-01-22 京东方科技集团股份有限公司 一种电平转移电路、栅极驱动电路及显示装置

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