WO2015040662A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2015040662A1 WO2015040662A1 PCT/JP2013/074964 JP2013074964W WO2015040662A1 WO 2015040662 A1 WO2015040662 A1 WO 2015040662A1 JP 2013074964 W JP2013074964 W JP 2013074964W WO 2015040662 A1 WO2015040662 A1 WO 2015040662A1
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- mos transistor
- mosfet
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000001514 detection method Methods 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229910021332 silicide Inorganic materials 0.000 description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 16
- 230000015556 catabolic process Effects 0.000 description 15
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- 239000011229 interlayer Substances 0.000 description 10
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- 230000004913 activation Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Definitions
- the present invention relates to a semiconductor device, and more particularly to a semiconductor device using a wide band gap semiconductor.
- SiC-MOSFET field effect transistor having a wide band gap semiconductor, particularly a metal / oxide / semiconductor junction structure (MOS) using silicon carbide (SiC), a MOSFET (Si) using silicon (Si) (Si Since the forward voltage drop (on voltage) between the drain and the source can be reduced more than (-MOSFET), the number of unit cells can be reduced and the chip size can be reduced as compared with the Si-MOSFET. For example, if the on-resistance can be halved, the number of unit cells can be halved and the chip size can be halved.
- the SiC-MOSFET has a problem that the gate area is reduced, the capacitance component between the gate and the source is reduced, and the electrostatic breakdown resistance (ESD) between the gate and the source is reduced.
- ESD electrostatic breakdown resistance
- a pn junction layer is formed on a polysilicon (Poly-Si) layer as a gate electrode material to form a Zener diode (poly Zener diode), which is connected between the gate and the source.
- a Zener diode is incorporated.
- the polyzener diode Although it is considered effective to incorporate a polyzener diode as a countermeasure against electrostatic breakdown in a wide band gap semiconductor device such as a SiC-MOSFET, the polyzener diode has low controllability in a high temperature environment due to temperature characteristics. Therefore, it is considered unsuitable for a wide band gap semiconductor device expected to be used in a high temperature environment.
- the present invention has been made to solve the above-described problems, and an object thereof is to provide a semiconductor device capable of preventing electrostatic breakdown between a gate and a source of a wide band gap semiconductor device such as a SiC-MOSFET. To do.
- An aspect of a semiconductor device includes a first conductivity type first MOS transistor in which a first main electrode is connected to a first potential and a second main electrode is connected to a second potential; A second conductive type second MOS transistor having a first main electrode connected to a control electrode of the first MOS transistor and a second main electrode connected to the second potential; The control electrode of one MOS transistor and the control electrode of the second MOS transistor are connected in common, and the first and second MOS transistors are formed on a common wide band gap semiconductor substrate, In the first MOS transistor, a main current flows in a direction perpendicular to a main surface of the wide band gap semiconductor substrate, and in the second MOS transistor, a main current flows in the wide band gap semiconductor. It flows in the horizontal direction with respect to the main surface of the plate.
- FIG. 6 is a plan view schematically showing a top surface configuration of the SiC-MOSFET SM according to the second embodiment of the present invention. It is a figure which shows the cross-sectional structure of SiC-MOSFETSM of Embodiment 2 which concerns on this invention.
- FIG. 10 is a plan view schematically showing a top surface configuration of the SiC-MOSFET SM according to the third embodiment of the present invention. It is a figure which shows the cross-sectional structure of SiC-MOSFETSM of Embodiment 3 which concerns on this invention.
- FIG. 10 is a plan view schematically showing a top surface configuration of the SiC-MOSFET SM according to the fourth embodiment of the present invention.
- FIG. 10 is a plan view schematically showing a top surface configuration of the SiC-MOSFET SM according to the fifth embodiment of the present invention. It is a figure which shows the cross-sectional structure of SiC-MOSFETSM of Embodiment 5 which concerns on this invention.
- MOS Metal-Oxide-Semiconductor
- polycrystalline silicon has been adopted instead of metal as a material of a gate electrode mainly from the viewpoint of forming a source / drain in a self-aligned manner.
- a material having a high dielectric constant is adopted as a material for the gate insulating film, but the material is not necessarily limited to an oxide.
- MOS is not necessarily limited to the metal / oxide / semiconductor laminated structure, and this specification does not assume such limitation. That is, in view of the common general knowledge, “MOS” is not only an abbreviation derived from the word source, but also has a meaning including widely a laminated structure of a conductor / insulator / semiconductor.
- FIG. 1 is a diagram showing a circuit configuration of a SiC-MOSFET incorporating a lateral MOSFET for countermeasures against electrostatic breakdown.
- a p-channel lateral MOSFET LM is connected between a gate (G) and a source (S) of an n-channel SiC-MOSFETSM, and the gate of the SiC-MOSFETSM and the gate of the lateral MOSFET LM are commonly used. It is connected. Note that the sources of the SiC-MOSFET SM and the lateral MOSFET LM are grounded.
- the lateral MOSFET LM includes an n + buffer layer 1 obtained by introducing an n-type impurity into a silicon carbide substrate at a relatively high concentration, and an n-type impurity formed on the n + buffer layer 1.
- n + buffer layer 1 obtained by introducing an n-type impurity into a silicon carbide substrate at a relatively high concentration
- n base layer 4 having n-type impurities is selectively formed in the surface of the p base layer 3, and p + having a relatively high concentration of p-type impurities in the surface of the n base layer 4.
- a plurality of layers 5 are selectively formed so as to form a pair. Since n + buffer layer 1, n ⁇ layer 2, p base layer 3, n base layer 4 and p + layer 5 are included in the silicon carbide substrate, they are collectively referred to as substrate portion SB.
- a field oxide film 11 is formed on the substrate portion SB, and contact holes CH1 and CH2 that penetrate the field oxide film 11 in the thickness direction and reach the surface of the p + layer 5 are formed in the field oxide film 11. Yes.
- a polysilicon film 13 is formed on the inner wall of the contact hole CH 1 and the field oxide film 11, and an interlayer insulating film 14 is formed so as to cover the polysilicon film 13.
- a gate electrode 16 is formed on the interlayer insulating film 14, and the gate electrode 16 is a portion corresponding to the contact hole CH 1 in the contact hole CH 11 that penetrates the interlayer insulating film 14 and reaches the surface of the p + layer 5. Is also filled.
- a silicide film 10 made of a silicide such as NiSi is formed on the p + layer 5 at the bottom of the contact hole CH11, and the gate electrode 16 is connected to the silicide film 10.
- a silicide film 10 made of silicide such as NiSi is formed on the p + layer 5 at the bottom of the contact hole CH2, and field oxidation is performed from the inner wall of the contact hole CH2 opposite to the contact hole CH1.
- a source electrode 15 is formed over the film 11, and the source electrode 15 is connected to the edge of the silicide film 10.
- a drain electrode 17 is provided on the main surface of the substrate portion SB on the n + buffer layer 1 side.
- FIG. 3 shows a cross-sectional configuration of the SiC-MOSFET SM.
- the SiC-MOSFET SM shares the lateral MOSFET LM and the substrate part SB, and a plurality of n + source layers 6 having a relatively high concentration of n-type impurities are selectively formed in the surface of the p base layer 3 in pairs.
- a p + layer 5 having a p-type impurity at a relatively high concentration is formed between the n + layers 6 formed and paired.
- a gate oxide film 12 is formed on the substrate portion SB, and a polysilicon film 13 that functions as a gate electrode is formed on the gate oxide film 12.
- the gate oxide film 12 and the polysilicon film 13 are provided from the edge of the n + source layer 6 to the upper portion of the p base layer 3 on the outer side and the n ⁇ layer 2 on the outer side.
- the + layer 5 is not provided.
- a silicide film 10 made of silicide such as NiSi is formed on the p + layer 5 and the n + source layer 6 around it.
- an interlayer insulating film 14 is formed so as to cover the gate oxide film 12 and the polysilicon film 13, and a source electrode 15 is formed on the silicide film 10 and the interlayer insulating film 14 not covered with the interlayer insulating film 14. ing.
- the potential applied to the lateral MOSFET LM will be described with reference to FIG. As shown in FIG. 4, when a negative potential is applied to the gate electrode 16 and the source electrode 15 is grounded, the n base layer 4 becomes floating, but the breakdown voltage between the drain and source becomes higher than the threshold voltage (VGSth). If configured in this way, there is no problem in operation.
- VGSth threshold voltage
- FIG. 5 is a diagram showing a gate current path when a negative overvoltage is applied between the gate and source of the SiC-MOSFET SM in the circuit configuration shown in FIG.
- FIG. 6 is a cross-sectional view showing the flow of the gate current GC when a negative overvoltage is applied between the gate and the source of the SiC-MOSFET.
- the same voltage is also applied between the gate and source of the built-in lateral MOSFET LM.
- a p channel 21 is formed between the formed p + layers 5.
- the field oxide film 11 serves as a gate oxide film, and a p-channel 21 is formed under the gate electrode 16.
- the gate current GC generated by the overvoltage between the gate and the source of the SiC-MOSFET SM flows to the ground via the source and the drain of the lateral MOSFET LM, and the gate between the gate and the source of the SiC-MOSFET SM.
- electrostatic breakdown due to a negative overvoltage between the gate and the source can be prevented.
- the negative maximum rated voltage between the gate and the source of a general SiC-MOSFET is -5 to -20V. Therefore, by setting VGSth of the lateral MOSFET LM to -25V or less (that is, the negative side of the lateral MOSFET LM). Is set lower than the negative threshold voltage of the SiC-MOSFETSM), and a voltage of -5 to -20 V is applied as the gate-source voltage, the lateral MOSFET LM It does not operate and does not affect the normal operation of the SiC-MOSFETSM.
- the lateral MOSFET LM functions as an overvoltage protection element that operates only when a negative overvoltage of ⁇ 25V or less is applied.
- VGSth of the lateral MOSFET LM -25 V or less
- the forward voltage drop (ON voltage) of the lateral MOSFET LM also increases, and the gate current generated by the gate overvoltage can be consumed in the lateral MOSFET LM.
- FIG. 7 is a plan view schematically showing an upper surface configuration of the SiC-MOSFET SM according to the second embodiment.
- the SiC-MOSFET SM is provided with a source pad SP having a square shape in plan view and a gate wiring GL so as to surround the outside of the source pad SP.
- the plan view shape of the source pad SP is a quadrangle in which the central part of one side is recessed inward, and a gate pad GP extending from the surrounding gate wiring GL is provided so as to enter a recessed part inside the source pad SP. It has been.
- a gate wiring GL is also provided around the gate pad GP.
- the gate pad GP is a portion to which a gate voltage is applied through a wire connected by wire bonding from the outside, and the gate voltage applied thereto is a unit that is the minimum unit structure of the SiC-MOSFETSM through the gate wire GL. Applied to the gate electrode of the cell.
- the source pad SP is provided on an active region where a plurality of unit cells are arranged, and the source electrodes (not shown) of the unit cells are connected in parallel.
- a termination junction region GND wiring TG is provided so as to surround the gate wiring GL, and a plurality of field limiting rings FLR are provided concentrically on the outer side thereof.
- the lateral MOSFET LM is provided so as to straddle the gate wiring GL near the gate pad GP and the termination junction region GND wiring TG.
- FIG. 8 is a diagram showing a cross-sectional configuration along the line A-A ′ in FIG.
- FIG. 8 shows an SiC-MOSFET active region, a lateral MOSFET region, and a termination junction region.
- the SiC-MOSFET active region has the same configuration as the SiC-MOSFET described with reference to FIG.
- the same configuration as that of the lateral MOSFET described with reference to FIG. 2 is arranged in the lateral MOSFET region, and the same reference numeral is given to the same configuration, and redundant description is omitted.
- a termination junction region a plurality of p layers 31 containing p-type impurities constituting the field limiting ring FLR are arranged in the surface of the n ⁇ layer 2 at intervals.
- the upper portion of the p layer 31 is covered with the field oxide film 11.
- a termination junction region GND wiring TG is connected via a contact hole CH3 penetrating the field oxide film 11 in the thickness direction. It is connected.
- the termination junction region GND wiring TG is connected to the source electrode 15.
- the termination junction region and the lateral MOSFET region are covered with a termination junction region protective film 20.
- the gate current generated by the overvoltage between the gate and the source of the SiC-MOSFET SM flows to the termination junction region GND wiring TG via the source and the drain of the lateral MOSFET LM. Does not affect the normal activation operation (unit cell operation).
- FIG. 9 is a plan view schematically showing an upper surface configuration of the SiC-MOSFET SM according to the third embodiment.
- symbol is attached
- the gate wiring GL is provided so as to surround the outside of the source pad SP, and a plurality of field limiting rings FLR are provided concentrically so as to surround the gate wiring GL.
- the lateral MOSFET LM is provided so as to straddle the gate wiring GL in the vicinity of the gate pad GP.
- FIG. 10 is a diagram showing a cross-sectional configuration along the line A-A ′ in FIG. 9.
- FIG. 9 shows an SiC-MOSFET active region, a lateral MOSFET region, and a termination junction region, and the same configuration as the SiC-MOSFET described with reference to FIG. 3 is arranged in the SiC-MOSFET active region.
- symbol is attached
- contact holes CH4 and CH5 that penetrate the field oxide film 11 in the thickness direction and reach the surface of the p + layer 5 are formed in the field oxide film 11, and SiC-MOSFET active
- the inner wall of the contact hole CH4 opposite to the terminal junction region on the region side is covered with the source electrode 15, and the source electrode 15 is connected to the silicide film 10 at the bottom of the contact hole CH4.
- a polysilicon film 13 is formed on the field oxide film 11, and the polysilicon film 13 extends to the gate oxide film 12 provided in the SiC-MOSFET active region.
- the silicon film 13 and the gate oxide film 12 are covered with an interlayer insulating film 14.
- the source electrode 15 of the lateral MOSFET LM is also formed on the interlayer insulating film 14 and is connected to the source electrode 15 of the SiC-MOSFETSM.
- the inner wall of the contact hole CH5 on the side opposite to the SiC-MOSFET active region on the terminal junction region side is covered with the polysilicon film 13, and the polysilicon film 13 is formed on the p + layer 5 at the bottom of the contact hole CH5. It is connected.
- the polysilicon film 13 extends to the field oxide film 11, and a gate electrode 16 is formed so as to cover the field oxide film 11 and the polysilicon film 13 in the contact hole CH5.
- the gate current generated by the gate-source overvoltage of the SiC-MOSFETSM flows from the gate electrode 16 to the source electrode 15 of the SiC-MOSFETSM via the source-drain of the lateral MOSFET LM. It becomes.
- the termination junction region GND wiring TG of the SiC-MOSFET which is necessary in the second embodiment, is unnecessary, and an increase in the invalid region of the SiC-MOSFET chip can be suppressed.
- the lateral MOSFET LM can be incorporated without increasing the chip area, and the increase in chip cost can be suppressed.
- FIG. 11 is a plan view schematically showing a top surface configuration of the SiC-MOSFET SM according to the fourth embodiment.
- symbol is attached
- a termination junction region GND wiring TG is provided so as to surround the gate wiring GL, and a plurality of field limiting rings FLR are provided concentrically on the outer side thereof.
- the lateral MOSFET LM is provided so as to straddle the gate wiring GL in the vicinity of the termination junction region GND wiring TG and the termination junction region GND wiring TG of the gate pad GP.
- FIG. 12 is a diagram showing a cross-sectional configuration along the line A-A ′ in FIG. 11.
- FIG. 12 shows a gate pad region, a lateral MOSFET region, and a termination junction region.
- the n ⁇ layer 2 is covered with the field oxide film 11, and the field oxide film 11 is covered with the gate electrode 16.
- contact holes CH1 and CH2 that penetrate the field oxide film 11 in the thickness direction and reach the surface of the p + layer 5 are formed in the field oxide film 11, and gate pads are formed.
- a polysilicon film 13 is formed on the inner wall of the contact hole CH1 opposite to the gate pad region on the region side and the field oxide film 11, and an interlayer insulating film 14 is formed so as to cover the polysilicon film 13. Yes.
- a gate electrode 16 is formed on the interlayer insulating film 14, and the gate electrode 16 is also filled in the remaining portion of the contact hole CH1.
- a silicide film 10 made of silicide such as NiSi is formed on the p + layer 5 at the bottom of the contact hole CH1, and the gate electrode 16 is connected to the silicide film 10.
- a silicide film 10 made of silicide such as NiSi is formed on the p + layer 5 at the bottom of the contact hole CH2, and the field oxide film 11 is formed from the inner wall of the contact hole CH2 on the terminal junction region side.
- a source electrode 15 is formed over the source electrode 15, and the source electrode 15 is connected to the edge of the silicide film 10.
- a termination junction region a plurality of p layers 31 containing p-type impurities constituting the field limiting ring FLR are arranged in the surface of the n ⁇ layer 2 at intervals. The upper portion of the p layer 31 is covered with the field oxide film 11.
- a termination junction region GND wiring TG is connected via a contact hole CH3 penetrating the field oxide film 11 in the thickness direction. It is connected.
- the termination junction region GND wiring TG is connected to the source electrode 15.
- the gate current GC generated by the gate-source overvoltage of the SiC-MOSFETSM flows to the termination junction region GND wiring TG via the source-drain of the lateral MOSFET LM.
- the normal activation operation (unit cell operation) of the MOSFET is not affected.
- the lateral MOSFET LM in the gate pad GP, it is possible to suppress an increase in the ineffective area of the SiC-MOSFET chip.
- the lateral MOSFET LM can be incorporated without increasing the chip area, and the increase in chip cost can be suppressed.
- the lateral MOSFET LM is configured to be connected between the gate and the source of the SiC-MOSFETSM as described with reference to FIG.
- a lateral MOSFET LM may be connected between the gate and source of the MOSFET serving as a current sense element.
- the current sense element is built in an IGBT chip or a MOSFET chip used for IPM (Intelligent Power Module) or the like, and is provided for detection and protection when an overcurrent flows through these chips.
- IPM Intelligent Power Module
- a MOSFET serving as a current sense element has an active region capable of flowing a current that is approximately 1 / 10,000 of the current flowing in the active region of an IGBT chip or MOSFET chip. Since the area of the region is small and the gate-source capacitance is small, the gate-source electrostatic breakdown resistance is low.
- FIG. 13 shows the circuit configuration of a SiC-MOSFET with a built-in lateral MOSFET as a countermeasure against electrostatic breakdown of the current sensing element.
- an n-channel type current sense MOSFET CSM is connected in parallel with the n-channel type SiC-MOSFET SM, and a p-channel type lateral MOSFET LM is connected between the gate and source thereof.
- the gates of the SiC-MOSFET SM, the lateral MOSFET LM, and the current sense MOSFET CSM are connected in common.
- the sources CS of the SiC-MOSFET SM, the lateral MOSFET LM, and the current sense MOSFET CSM are grounded.
- FIG. 14 is a plan view schematically showing a top surface configuration of the SiC-MOSFET SM according to the fifth embodiment.
- symbol is attached
- the gate wiring GL is provided so as to surround the outside of the source pad SP, and a plurality of field limiting rings FLR are provided concentrically so as to surround the gate wiring GL.
- a square current sense pad CSP is provided so that one corner of the source pad SP is recessed inside and enters a recessed portion inside the source pad SP, and the current sense pad CSP is surrounded by the gate wiring GL. It is.
- the current sense pad CSP is a part from which a sense current is derived to the outside through a wire connected by wire bonding, and is electrically connected to the current sense MOSFET CSM.
- the lateral MOSFET LM is provided adjacent to the current sense MOSFET CSM in the current sense pad CS.
- FIG. 15 is a diagram showing a cross-sectional configuration along the line A-A ′ in FIG. 14.
- FIG. 15 shows a current sense MOSFET region, a lateral MOSFET region, and a termination junction region.
- the same configuration as that of the SiC-MOSFET described with reference to FIG. 3 is disposed, and in the lateral MOSFET region, the same configuration as that of the lateral MOSFET LM described with reference to FIG. 10 is disposed. Further, in the termination junction region, the same configuration as that of the termination junction region described with reference to FIG. 10 is arranged. In each case, the same configuration is denoted by the same reference numeral, and redundant description is omitted.
- the gate current generated by the overvoltage between the gate and source of the current sense MOSFET CSM flows to the source electrode 15 of the current sense MOSFET CSM via the source and drain of the lateral MOSFET LM. It is possible to prevent the gate current from flowing between the gate and the source of the MOSFET CSM, and to prevent electrostatic breakdown due to a negative overvoltage between the gate and the source.
- the lateral MOSFET LM in the current sense pad CSP, it is possible to suppress an increase in the ineffective region of the SiC-MOSFET chip.
- the lateral MOSFET LM can be incorporated without increasing the chip area, and the increase in chip cost can be suppressed.
- ⁇ Threshold voltage setting> In the lateral MOSFET LM described above, by setting VGSth between the gate and the source to be ⁇ 25 V or less, the lateral MOSFET LM can be prevented from affecting the operation of the current sense MOSFET CSM. The reason is the same as that in the case where the lateral MOSFET LM is connected between the gate and source of the SiC-MOSFET.
- the field oxide film 11 is used as the gate oxide film.
- 11 is formed in the same process as the field oxide film 11 formed in the termination junction region shown in FIG.
- the field oxide film formed in the termination junction region of the SiC-MOSFET is thicker than the gate oxide film used in the active region (unit cell). For this reason, by using the field oxide film as the gate oxide film of the lateral MOSFET LM, VGSth of the lateral MOSFET LM can be made higher than VGSth of the SiC-MOSFET without increasing the number of steps.
- the SiC-MOSFET and the current sense MOSFET are described as an n-channel type, and the lateral MOSFET is described as a p-channel type.
- the SiC-MOSFET and the current sense MOSFET are configured as a p-channel type.
- the MOSFET may be an n-channel type.
- the wide band gap semiconductor is not limited to SiC, and the present invention can be applied even to a semiconductor device using another wide band gap semiconductor such as GaN, and the same effect can be obtained. .
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Abstract
Description
「MOS」という用語は、古くは金属/酸化物/半導体の接合構造に用いられており、Metal-Oxide-Semiconductorの頭文字を採ったものとされている。しかしながら特にMOS構造を有する電界効果トランジスタ(以下、単に「MOSトランジスタ」と称す)においては、近年の集積化や製造プロセスの改善などの観点からゲート絶縁膜やゲート電極の材料が改善されている。
図1は、静電破壊対策のための横型MOSFETを内蔵したSiC-MOSFETの回路構成を示す図である。
以上説明した横型MOSFETLMにおいては、ゲート-ソース間のVGSthを-25V以下とすることで、横型MOSFETLMが、SiC-MOSFETSMの通常の動作に影響を与えることを防ぐことができる。
実施の形態1においては、図6を用いて、SiC-MOSFETSMのゲート-ソース間の過電圧によって発生するゲート電流GCは、横型MOSFETLMのソース-ドレイン間を介して接地に流れることを説明したが、横型MOSFETLMのソース電極15を、SiC-MOSFETSMの終端接合領域のグランド(GND)配線に接続した構成を採ることができる。
実施の形態1においては、図6を用いて、SiC-MOSFETSMのゲート-ソース間の過電圧によって発生するゲート電流GCは、横型MOSFETLMのソース-ドレイン間を介して接地に流れることを説明したが、横型MOSFETLMのソース電極15を、SiC-MOSFETSMのソース電極に接続した構成を採ることができる。
実施の形態2および3においては、横型MOSFETLMをゲートパッドGPの近傍に設けた構成を示したが、横型MOSFETLMの形成箇所はこれに限定されるものではなく、例えば、ゲートパッドGPの領域内に設けても良い。
以上説明した実施の形態1~4においては、横型MOSFETLMは、図1を用いて説明したように、SiC-MOSFETSMのゲート-ソース間に接続された構成を示したが、電流センス素子が内蔵されたSiC-MOSFETにおいて、電流センス素子となるMOSFETのゲート-ソース間に、横型MOSFETLMを接続しても良い。
以上説明した横型MOSFETLMにおいては、ゲート-ソース間のVGSthを-25V以下とすることで、横型MOSFETLMが、電流センスMOSFETCSMの動作に影響を与えることを防ぐことができる。その理由は、SiC-MOSFETのゲート-ソース間に横型MOSFETLMを接続する場合と同様である。
横型MOSFETLMをSiC-MOSFETのゲート-ソース間に接続した構成および電流センスMOSFETCSMのゲート-ソース間に接続した構成においては、何れもフィールド酸化膜11をゲート酸化膜として使用するが、このフィールド酸化膜11は、例えば、図8に示した終端接合領域に形成するフィールド酸化膜11と同時に同じ工程で形成することになる。
以上説明した実施の形態1~5においては、SiC-MOSFETおよび電流センスMOSFETをnチャネル型とし、横型MOSFETをpチャネル型として説明したが、SiC-MOSFETおよび電流センスMOSFETをpチャネル型とし、横型MOSFETをnチャネル型としても良い。
Claims (11)
- 第1の主電極(D)が第1の電位に接続され、第2の主電極(S)が第2の電位に接続された第1導電型の第1のMOSトランジスタ(SM)と、
第1の主電極(D)が前記第1のMOSトランジスタの制御電極(G)に接続され、第2の主電極(S)が前記第2の電位に接続された第2導電型の第2のMOSトランジスタ(LM)と、を備え、
前記第1のMOSトランジスタの前記制御電極と、前記第2のMOSトランジスタの制御電極(G)とが共通に接続され、
前記第1および第2のMOSトランジスタは、共通のワイドバンドギャップ半導体基板上に形成され、
前記第1のMOSトランジスタは、主電流が前記ワイドバンドギャップ半導体基板の主面に対して垂直方向に流れ、
前記第2のMOSトランジスタは、主電流が前記ワイドバンドギャップ半導体基板の主面に対して水平方向に流れる、半導体装置。 - 前記第1導電型はnチャネル型であり、
前記第2導電型はpチャネル型であり、
前記第2のMOSトランジスタの負側のしきい値電圧は、
前記第1のMOSトランジスタの負側のしきい値電圧よりも低く設定される、請求項1記載の半導体装置。 - 前記ワイドバンドギャップ半導体基板は、
前記第1のMOSトランジスタをユニットセルとして複数有する平面視四角形状のユニットセル領域と、
前記ユニットセル領域を囲む終端接合領域と、を有し、
前記終端接合領域は、
前記ユニットセル領域の直近において前記ユニットセル領域を囲むグランド配線(GL)を含み、
前記第2のMOSトランジスタの前記第2の主電極は、前記グランド配線に接続される、請求項1記載の半導体装置。 - 前記第2のMOSトランジスタの前記第2の主電極は、前記第1のMOSトランジスタの前記第2の主電極を介して前記第2の電位に接続される、請求項1記載の半導体装置。
- 前記ワイドバンドギャップ半導体基板は、
前記第1のMOSトランジスタをユニットセルとして複数有する平面視四角形状のユニットセル領域と、
前記ユニットセル領域を囲む終端接合領域と、を有し、
前記ユニットセル領域は、その一部が内側に凹み、その凹み部分に配設されるワイヤボンディングのパッド領域を含み、
前記パッド領域は、前記第1のMOSトランジスタの前記制御電極が電気的に接続され、
前記第2のMOSトランジスタは、前記パッド領域に形成される、請求項1記載の半導体装置。 - 前記終端接合領域は、
前記ユニットセル領域の直近において前記ユニットセル領域を囲むグランド配線(GL)を含み、
前記第2のMOSトランジスタの前記第2の主電極は、前記グランド配線に接続される、請求項5記載の半導体装置。 - 第1の主電極(D)が第1の電位に接続され、第2の主電極(S)が第2の電位に接続された第1導電型の第1のMOSトランジスタ(SM)と、
第1の主電極(D)が前記第1の電位に接続され、第2の主電極(S)が前記第2の電位に接続された第1導電型の電流検出MOSトランジスタ(CSM)と、
第1の主電極(D)が前記電流検出MOSトランジスタの制御電極(G)に接続され、第2の主電極(S)が前記第2の電位に接続された第2導電型の第2のMOSトランジスタ(LM)と、を備え、
前記電流検出MOSトランジスタの前記制御電極と、前記第2のMOSトランジスタの制御電極(G)とが共通に接続され、
前記第1、第2のMOSトランジスタおよび前記電流検出MOSトランジスタは、共通のワイドバンドギャップ半導体基板上に形成され、
前記第1のMOSトランジスタおよび前記電流検出MOSトランジスタは、主電流が前記ワイドバンドギャップ半導体基板の主面に対して垂直方向に流れ、
前記第2のMOSトランジスタは、主電流が前記ワイドバンドギャップ半導体基板の主面に対して水平方向に流れる、半導体装置。 - 前記ワイドバンドギャップ半導体基板は、
前記第1のMOSトランジスタをユニットセルとして複数有する平面視四角形状のユニットセル領域と、
前記ユニットセル領域を囲む終端接合領域と、を有し、
前記ユニットセル領域は、その一部が内側に凹み、その凹み部分に配設されるワイヤボンディングのパッド領域を含み、
前記パッド領域は、前記電流検出MOSトランジスタの前記第2の主電極が電気的に接続され、
前記第2のMOSトランジスタは、前記パッド領域に形成される、請求項7記載の半導体装置。 - 前記第1導電型はnチャネル型であり、
前記第2導電型はpチャネル型であり、
前記第2のMOSトランジスタの負側のしきい値電圧は、
前記電流検出MOSトランジスタの負側のしきい値電圧よりも低く設定される、請求項7記載の半導体装置。 - 前記第2のMOSトランジスタのゲート酸化膜は、
前記第1のMOSトランジスタのフィールド酸化膜と同じ厚さに形成される、請求項1または請求項7記載の半導体装置。 - 前記ワイドバンドギャップ半導体基板は、
ワイドバンドギャップ半導体として、SiCまたはGaNを用いる、請求項1または請求項7記載の半導体装置。
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JP2000223705A (ja) * | 1999-01-29 | 2000-08-11 | Nissan Motor Co Ltd | 半導体装置 |
JP2007299862A (ja) * | 2006-04-28 | 2007-11-15 | Nissan Motor Co Ltd | 半導体装置およびその製造方法 |
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JP2020526914A (ja) * | 2017-07-06 | 2020-08-31 | ゼネラル・エレクトリック・カンパニイ | 半導体電力変換デバイスのための正の抵抗温度係数(ptc)を有するゲートネットワーク |
JP7317425B2 (ja) | 2017-07-06 | 2023-07-31 | ゼネラル・エレクトリック・カンパニイ | 半導体電力変換デバイスのための正の抵抗温度係数(ptc)を有するゲートネットワーク |
JP2020205319A (ja) * | 2019-06-14 | 2020-12-24 | 富士電機株式会社 | 半導体装置 |
JP7310343B2 (ja) | 2019-06-14 | 2023-07-19 | 富士電機株式会社 | 半導体装置 |
JP2021005664A (ja) * | 2019-06-27 | 2021-01-14 | 富士電機株式会社 | 半導体装置 |
JP7310356B2 (ja) | 2019-06-27 | 2023-07-19 | 富士電機株式会社 | 半導体装置 |
Also Published As
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DE112013007439T5 (de) | 2016-06-16 |
JP5968548B2 (ja) | 2016-08-10 |
KR101742447B1 (ko) | 2017-05-31 |
CN105556669A (zh) | 2016-05-04 |
JPWO2015040662A1 (ja) | 2017-03-02 |
US9627383B2 (en) | 2017-04-18 |
DE112013007439B4 (de) | 2021-09-30 |
US20160163703A1 (en) | 2016-06-09 |
CN105556669B (zh) | 2019-06-28 |
KR20160044008A (ko) | 2016-04-22 |
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