WO2015037335A1 - 炭化珪素半導体装置およびその製造方法 - Google Patents

炭化珪素半導体装置およびその製造方法 Download PDF

Info

Publication number
WO2015037335A1
WO2015037335A1 PCT/JP2014/069515 JP2014069515W WO2015037335A1 WO 2015037335 A1 WO2015037335 A1 WO 2015037335A1 JP 2014069515 W JP2014069515 W JP 2014069515W WO 2015037335 A1 WO2015037335 A1 WO 2015037335A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon carbide
region
main surface
semiconductor device
carbide semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2014/069515
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
透 日吉
増田　健良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to US14/911,678 priority Critical patent/US20160211332A1/en
Publication of WO2015037335A1 publication Critical patent/WO2015037335A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H10D10/441—Vertical BJTs having an emitter-base junction ending at a main surface of the body and a base-collector junction ending at a lateral surface of the body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/133—Emitter regions of BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/231—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/281—Base electrodes for bipolar transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10P50/242—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes

Definitions

  • the present invention relates to a silicon carbide semiconductor device and a manufacturing method thereof, and more particularly, to a silicon carbide semiconductor device having a bipolar transistor and a manufacturing method thereof.
  • Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices.
  • silicon carbide as a material constituting the semiconductor device, it is possible to achieve high breakdown voltage of the semiconductor device, reduction of on-resistance, and the like.
  • a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.
  • SiC power semiconductors are mainly classified into a junction type device and a MOS (Metal Oxide Semiconductor) type device.
  • a typical example of the junction type device is a bipolar transistor (also called a bipolar junction transistor (BJT)).
  • Current gain is defined as the ratio of collector current to base current.
  • the cause of the low current amplification factor is considered to be recombination of holes in the base region and electrons injected from the emitter region through the interface state on the surface of the base region. The higher the density of electrons and holes, the greater the recombination current. Alternatively, the recombination current increases as the interface state increases.
  • Patent Document 1 discloses a bipolar silicon carbide semiconductor device for the purpose of improving the current gain.
  • This semiconductor device has a recombination suppressing semiconductor layer.
  • the recombination suppressing semiconductor layer is a layer containing a low-concentration p-type impurity, and is disposed near the surface of the semiconductor crystal between the base contact region and the emitter region.
  • the recombination suppressing semiconductor layer the surface of the semiconductor having a large number of interface states is separated from the portion where mainly hole current or electron current flows. This suppresses recombination of holes and electrons.
  • An object of the present invention is to provide a silicon carbide semiconductor device capable of achieving a high current gain with a simple configuration and a method for manufacturing the same.
  • a silicon carbide semiconductor device includes a silicon carbide layer having a hexagonal single crystal structure.
  • the silicon carbide layer has a first main surface, a second main surface located opposite to the first main surface, and a collector region having the first conductivity type and defining the second main surface And having a second conductivity type different from the first conductivity type and having a base region disposed on the surface of the collector region opposite to the second main surface, and the first conductivity type And an emitter region disposed on the base region and spaced apart from the collector region and defining a first main surface.
  • the silicon carbide layer is provided with a trench having a side wall surface extending from the first main surface through the emitter region to the base region.
  • the side wall surface includes a region having a macroscopic angle of 50 ° or more and 70 ° or less with respect to the ⁇ 000-1 ⁇ plane.
  • a method for manufacturing a silicon carbide semiconductor device has a hexagonal single-crystal structure, and a first main surface and a second main surface located on the opposite side of the first main surface.
  • the step of preparing the silicon carbide layer includes a step of forming a collector region having the first conductivity type and defining the second main surface, and a surface of the collector region opposite to the second main surface, Forming a base region having a second conductivity type different from the first conductivity type, and forming an emitter region having the first conductivity type and defining the first main surface on the base region; Including the step of.
  • the manufacturing method further includes a step of forming a trench having a side wall surface penetrating the emitter region and reaching the base region.
  • the first main surface of the silicon carbide layer is chemically formed to form a region having a macroscopic angle of 50 ° to 70 ° with respect to the ⁇ 000-1 ⁇ plane.
  • the process of processing is included.
  • a silicon carbide semiconductor device capable of achieving a high current gain with a simple configuration can be realized.
  • FIG. 1 is a plan view showing a schematic configuration of a silicon carbide semiconductor device according to a first embodiment of the present invention.
  • FIG. FIG. 2 is a sectional view taken along line II-II in FIG. Is a diagram for explaining the direction a 11 and a direction a 21 shown in FIGS. 1 is a partial cross sectional view schematically showing a first step of a method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • FIG. 6 is a partial cross sectional view schematically showing a second step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • FIG. 6 is a partial cross sectional view schematically showing a third step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • FIG. 6 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • FIG. 6 is a partial cross sectional view schematically showing a fifth step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • 7 is a partial cross sectional view schematically showing a sixth step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • FIG. FIG. 11 is a partial cross sectional view schematically showing a seventh step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • FIG. 11 is a partial cross sectional view schematically showing an eighth step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • FIG. 16 is a sectional view taken along line XVI-XVI in FIG. 15.
  • FIG. 11 is a partial cross sectional view schematically showing a first process performed in a fourth step (step of forming a trench) of the method for manufacturing silicon carbide semiconductor device 1A according to the second embodiment.
  • FIG. 21 is a sectional view taken along line XXI-XXI in FIG. 20.
  • FIG. 11 is a partial cross sectional view schematically showing a first process performed in a fourth step (step of forming a trench) of the method for manufacturing silicon carbide semiconductor device 1B according to the third embodiment. It is sectional drawing which shows schematically the 2nd process performed at the 4th process (process of forming a trench) of the manufacturing method of silicon carbide semiconductor device 1B which concerns on 3rd Embodiment. It is sectional drawing which shows schematically the 5th and 6th process of the manufacturing method of the silicon carbide semiconductor device 1B which concerns on 3rd Embodiment. It is the figure which showed the depletion layer extended from the junction surface of a pn junction. It is another figure which showed the depletion layer extended from the junction surface of a pn junction.
  • a silicon carbide semiconductor device (1, 1A, 1B) includes a silicon carbide layer (10) having a hexagonal single crystal structure.
  • the silicon carbide layer (10) has a first main surface (10a), a second main surface (10b) located on the opposite side of the first main surface (10a), and a first conductivity type.
  • the collector region (11, 12) that defines the second main surface (10b), the second conductivity type different from the first conductivity type, and the second main surface (10b)
  • a base region (13) disposed on the surface of the collector region on the opposite side, and having a first conductivity type, disposed on the base region (13), separated from the collector region (11, 12), And an emitter region (14) defining one main surface (10a).
  • the silicon carbide layer (10) is provided with a trench (TR) having a side wall surface extending from the first main surface (10a) through the emitter region (14) to the base region (13).
  • the side wall surface includes a first region (SW1) having an angle of 50 ° to 70 ° macroscopically with respect to the ⁇ 000-1 ⁇ plane.
  • the silicon carbide layer has a side wall surface extending from the first main surface of the silicon carbide layer to the base region through the emitter region.
  • the side wall surface includes a first region having an angle of 50 ° to 70 ° macroscopically with respect to the ⁇ 000-1 ⁇ plane.
  • This first region is a crystal plane having a low interface state density (hereinafter also referred to as “special plane” in this specification).
  • “Macroscopic” means ignoring microstructures having dimensions on the order of atomic spacing. As such a macroscopic off-angle measurement, for example, a general method using X-ray diffraction can be used.
  • Base current is generated by recombination of holes and electrons.
  • the current amplification factor of the silicon carbide semiconductor device (bipolar transistor) decreases.
  • One of the factors that recombine holes and electrons is the interface state of the silicon carbide layer. Since the first region of the side wall surface is a surface selected as a surface having a low interface state density, the recombination current can be reduced. Thereby, a silicon carbide semiconductor device having a high current gain can be realized.
  • the first region (SW1) includes a plane having a plane orientation ⁇ 0-33-8 ⁇ .
  • the recombination current can be reduced.
  • a silicon carbide semiconductor device having a high current gain can be realized.
  • the side wall surfaces face each other, and two surfaces (SWa, SWa,) that approach each other as they go from the first main surface (10a) to the second main surface (10b) of the silicon carbide layer (10). SWb).
  • the trench may have a bottom surface, and two surfaces may be connected to the bottom surface.
  • the two surfaces of the trench may be connected. In the latter case, the width of the trench in the first main surface can be reduced. Thereby, the pitch of the bipolar transistor cell can be reduced.
  • the first region (SW1) is arranged so as to straddle the emitter region (14) and the base region (13).
  • the side wall surface has a depth from the first main surface (10a) of the silicon carbide layer (10) to a position shallower than the bonding surface between the emitter region (14) and the base region (13).
  • the angle ( ⁇ 2) formed by the second region (SW2) with respect to the first main surface (10a) is the angle ( ⁇ 1) formed by the first region (SW1) with respect to the first main surface (10a). Bigger than.
  • the current amplification factor of the silicon carbide semiconductor device can be further increased.
  • a surface having a low interface state density is selected for the first region.
  • the first region spans both the emitter region and the base region. Therefore, the probability of recombination of holes and electrons can be further reduced. Thereby, the current gain of the silicon carbide semiconductor device can be increased.
  • the first region (SW1) is arranged in the base region (13).
  • the side wall surface further includes a second region (SW2) connected from the first main surface (10a) of the silicon carbide layer (10) to the first region (SW1) through the emitter region (14). .
  • the angle ( ⁇ 2) formed by the second region (SW2) with respect to the first main surface (10a) is the angle ( ⁇ 1) formed by the first region (SW1) with respect to the first main surface (10a). Bigger than.
  • the breakdown voltage of the silicon carbide semiconductor device can be secured.
  • the junction surface between the emitter region and the base region intersects with the second region. As the angle formed by the second region with respect to the first main surface becomes smaller, the depletion layer is less likely to spread at the end portion of the joint surface close to the second region.
  • the angle formed by the second region with respect to the first main surface of the silicon carbide layer is larger than the angle formed by the first region with respect to the first main surface. Therefore, the depletion layer can be easily expanded at the end of the joint surface close to the second region. By spreading the depletion layer, the breakdown voltage of the silicon carbide semiconductor device can be secured.
  • the first conductivity type is n-type
  • the second conductivity type is p-type. According to this configuration, an npn-type bipolar transistor can be realized. Furthermore, the ease of manufacturing the silicon carbide semiconductor device can be improved.
  • a method for manufacturing a silicon carbide semiconductor device has a hexagonal single crystal structure, and the first main surface (10a) and the first main surface (10a) are Providing a silicon carbide layer (10) having a second main surface (10b) located on the opposite side.
  • the step of preparing the silicon carbide layer (10) includes the step of forming collector regions (11, 12) having the first conductivity type and defining the second main surface (10b), and the second main surface. Forming a base region (13) having a second conductivity type different from the first conductivity type on the surface of the collector region (11, 12) opposite to (10a); and a base region (13) And forming an emitter region (14) having the first conductivity type and defining the first main surface (10a).
  • the manufacturing method further includes a step of forming a trench (TR) having a side wall surface penetrating the emitter region (14) and reaching the base region (13).
  • the step of forming the trench (TR) includes the step of forming the silicon carbide layer (10) in order to form the first region (SW1) having an angle of 50 ° to 70 ° with respect to the ⁇ 000-1 ⁇ plane.
  • a silicon carbide semiconductor device having a high current gain can be manufactured.
  • the first region (SW1) includes a plane having a plane orientation ⁇ 0-33-8 ⁇ .
  • a silicon carbide semiconductor device having a high current gain can be manufactured.
  • the step of chemically treating the first main surface (10a) includes the step of chemically etching the first main surface (10a) of the silicon carbide layer (10).
  • the step of chemically etching the first main surface (10a) includes a step of thermally etching the first main surface (10a).
  • the step of thermally etching the first main surface (10a) includes a step of heating the silicon carbide layer (10) in an atmosphere containing at least one or more types of halogen atoms.
  • the first region can be exposed more reliably.
  • at least one or more types of halogen atoms include at least one of a chlorine atom and a fluorine atom.
  • the first region can be exposed more reliably.
  • the first main surface (10a) is made reactive before the step of chemically treating the first main surface (10a) of the silicon carbide layer (10). Etching by ion etching is included.
  • the region corresponding to the trench in the first main surface is etched in advance by reactive ion etching.
  • the first main surface is chemically treated.
  • the etching of the silicon carbide layer can proceed smoothly. Therefore, the first region can be exposed more reliably.
  • the emitter region (14) and the base region (13) from the first main surface (10a) of the silicon carbide layer (10).
  • the emitter region (14) is etched to a position shallower than the junction surface with the first surface) to form a second region (SW2) on the side wall surface.
  • the first region extending over both the emitter region and the base region can be formed. Therefore, the probability of recombination of holes and electrons can be further reduced. Thereby, the current gain of the silicon carbide semiconductor device can be increased.
  • the base region extends from the first main surface (10a) of the silicon carbide layer (10) through the emitter region (14).
  • a second region (SW2) on the side wall surface reaching (13) is formed.
  • the angle formed by the second region with respect to the first main surface can be made larger than the angle formed by the first region with respect to the first main surface. Furthermore, the junction surface between the emitter region and the base region intersects with the second region. This makes it easy to spread the depletion layer at the end of the joint surface close to the second region. By spreading the depletion layer, the breakdown voltage of the silicon carbide semiconductor device can be secured.
  • the step of forming the base region (13) includes a step of forming a layer having the second conductivity type on the collector region (11, 12) by epitaxial growth.
  • the crystal defect density can be reduced as compared with the case where the base region is formed by ion implantation into the collector region. Thereby, the current amplification degree of the silicon carbide semiconductor device can be increased.
  • the step of forming the emitter region (14) includes a step of forming a layer having the first conductivity type on the base region (13) by epitaxial growth.
  • the crystal defect density can be reduced as compared with the case where the emitter region is formed by ion implantation into the base region. Thereby, the current amplification degree of the silicon carbide semiconductor device can be increased.
  • the first conductivity type is n-type
  • the second conductivity type is p-type. According to this configuration, an npn-type bipolar transistor can be realized. Furthermore, the ease of manufacturing the silicon carbide semiconductor device can be improved.
  • FIG. 1 is a plan view showing a schematic configuration of the silicon carbide semiconductor device according to the first embodiment of the present invention.
  • 2 is a cross-sectional view taken along line II-II in FIG.
  • silicon carbide semiconductor device 1 according to the first embodiment is a bipolar transistor. More specifically, silicon carbide semiconductor device 1 according to the first embodiment is an npn bipolar transistor.
  • Silicon carbide semiconductor device 1 includes a silicon carbide layer 10, an insulating film 21, an emitter electrode 2 a, a base electrode 3 a, an ohmic electrode 4, and a collector electrode 5. As shown in FIG. 1, in plan view, and the emitter electrode 2a, and the base electrode 3a, as well as extending along the direction of a 11, are arranged alternately along the direction of a 21.
  • the direction a 11 and the direction a 21 are directions orthogonal to each other. The direction a 11 and the direction a 21 will be described in detail later.
  • the silicon carbide layer 10 has a first main surface 10a and a second main surface 10b located on the opposite side to the first main surface 10a.
  • silicon carbide layer 10 has a hexagonal single crystal structure. More preferably, silicon carbide layer 10 has a hexagonal single crystal structure of polytype 4H.
  • Silicon carbide layer 10 includes an n + substrate 11, an n-type layer 12, a p-type layer 13, and an n + -type layer 14.
  • n + substrate 11 and the n-type layer 12 realize the collector region of the bipolar transistor.
  • One surface of n + substrate 11 defines second main surface 10 b of silicon carbide layer 10.
  • N + substrate 11 is made of, for example, polytype 4H hexagonal silicon carbide.
  • the n + substrate 11 contains a high concentration of impurities (donor).
  • the concentration of impurities contained in n + substrate 11 is, for example, about 1.0 ⁇ 10 18 cm ⁇ 3 .
  • the type of impurity is, for example, N (nitrogen).
  • N-type layer 12 is arranged on the other surface (surface opposite to second main surface 10b) of n + substrate 11.
  • N-type layer 12 is a layer formed by, for example, epitaxial growth.
  • N-type layer 12 is made of, for example, polytype 4H hexagonal silicon carbide.
  • the thickness of the n-type layer 12 is, for example, about 5 ⁇ m or more and about 200 ⁇ m or less.
  • the concentration of impurities contained in the n-type layer 12 is, for example, about 1 ⁇ 10 14 cm ⁇ 3 or more and about 3 ⁇ 10 16 cm ⁇ 3 or less.
  • the impurity contained in the n-type layer 12 is, for example, nitrogen (N).
  • the p-type layer 13 realizes a base region of a bipolar transistor.
  • P type layer 13 is arranged on the surface of collector region (n type layer 12) on the opposite side of second main surface 10 b of silicon carbide layer 10.
  • the p-type layer 13 is a layer formed on the collector region (n-type layer 12) by epitaxial growth.
  • the p-type layer 13 is made of, for example, polytype 4H hexagonal silicon carbide.
  • the thickness of the p-type layer 13 is, for example, about 0.1 ⁇ m or more and about 0.8 ⁇ m or less.
  • the concentration of impurities contained in the p-type layer 13 is, for example, about 7 ⁇ 10 16 cm ⁇ 3 or more and about 5 ⁇ 10 18 cm ⁇ 3 or less.
  • the impurity contained in the p-type layer 13 is, for example, aluminum (Al) or boron (B).
  • n + type layer 14 realizes an emitter region of the bipolar transistor.
  • N + -type layer 14 is disposed on the base region (p-type layer 13) separated from the collector region (n + substrate 11 and n-type layer 12).
  • the surface of n + type layer 14 defines first main surface 10 a of silicon carbide layer 10.
  • the n + type layer 14 is a layer formed by epitaxial growth.
  • N + type layer 14 is made of, for example, polytype 4H hexagonal silicon carbide.
  • the thickness of the n + type layer 14 is, for example, about 0.2 ⁇ m or more and about 1 ⁇ m or less.
  • the concentration of impurities contained in the n + -type layer 14 is, for example, about 1 ⁇ 10 19 cm ⁇ 3 or more and about 1 ⁇ 10 20 cm ⁇ 3 or less.
  • the impurity contained in the n + type layer 14 is, for example, phosphorus (P).
  • Trench TR is disposed in the silicon carbide layer 10.
  • Trench TR has side wall surface SWa, side wall surface SWb, and bottom surface BT.
  • the side wall surfaces SWa and Swb face each other.
  • Side wall surface SWa, each SWb leads from the first major surface 10a of the silicon carbide layer 10, p-type layer 13 through the n + -type layer 14 (the emitter region) to (the base region).
  • Sidewall surfaces SWa and SWb are surfaces inclined with respect to first main surface 10a so as to approach each other as they go from first main surface 10a of silicon carbide layer 10 to second main surface 10b. That is, the width of trench TR along direction a 21 decreases as it goes from first main surface 10a of silicon carbide layer 10 to second main surface 10b.
  • the bottom surface BT is a surface connected to the side wall surfaces SWa and SWb.
  • the bottom surface BT is located in the p-type layer 13.
  • the distance from first main surface 10a to bottom surface BT (the depth of bottom surface BT of trench TR from first main surface 10a) is, for example, about 0.3 ⁇ m or more and about 1.5 ⁇ m or less.
  • the side wall surfaces SWa and SWb include the first region SW1.
  • the first region SW1 includes a predetermined crystal plane (also referred to as a special plane).
  • the side wall surfaces SWa and SWb include a region (first region) having an angle of 50 ° to 70 ° macroscopically with respect to the ⁇ 000-1 ⁇ plane. More preferably, this region may include a plane having a plane orientation ⁇ 0-33-8 ⁇ .
  • each of the side wall surfaces SWa and SWb is the first region.
  • each of the side wall surfaces SWa and SWb only needs to include the first region SW1.
  • the p + type region 15 is formed on the bottom surface BT of the trench TR in the p type layer 13.
  • the depth of the p + -type region 15 from the surface of the p-type layer 13 is smaller than the thickness of the p-type layer 13 in that portion.
  • the depth of the p + -type region 15 from the surface of the p-type layer 13 is, for example, about 0.1 ⁇ m to 1 ⁇ m.
  • the concentration of impurities contained in p + -type region 15 is higher than the concentration of impurities contained in p-type layer 13.
  • the impurity concentration of the p + -type region 15 is about 1 ⁇ 10 19 cm ⁇ 3 or more and about 1 ⁇ 10 20 cm ⁇ 3 or less.
  • the impurity contained in p + type region 15 is, for example, aluminum (Al) or boron (B).
  • Insulating film 21 covers first main surface 10a of silicon carbide layer 10 and the inner peripheral surface (sidewall surfaces SWa, SWb and bottom surface BT) of trench TR.
  • the insulating film 21 is an oxide film, and more specifically, a film made of silicon dioxide (SiO 2 ).
  • a contact hole for exposing n + type layer 14 and p + type region 15 is formed in insulating film 21.
  • the ohmic electrode 4 is disposed in a contact hole formed in the insulating film 21 and is in ohmic contact with the n + type layer 14 or the p + type region 15.
  • the ohmic electrode 4 is preferably made of a material having nickel and silicon.
  • the ohmic electrode 4 may be made of a material having titanium, aluminum, and silicon.
  • Collector electrode 5 is formed in contact with second main surface 10 b of silicon carbide layer 10.
  • the collector electrode 5 may be formed of a material capable of ohmic contact with the n + substrate 11.
  • the collector electrode 5 may have the same configuration as that of the ohmic electrode 4, for example, or may be made of another material capable of ohmic contact with the n + substrate 11 such as nickel.
  • Base electrode 3 a is in contact with ohmic electrode 4 disposed on p + -type region 15. Thereby, base electrode 3a is electrically connected to p + type region 15 and p type layer 13.
  • Emitter electrode 2 a is in contact with ohmic electrode 4 disposed on n + -type layer 14. Thereby, the emitter electrode 2a is electrically connected to the n + type layer 14.
  • FIG. 3 is a diagram for explaining the direction a 11 and the direction a 21 shown in FIGS. 1 and 2.
  • direction a 11 is a ⁇ 11-20> direction
  • direction a 21 is a ⁇ 1-100> direction.
  • the off angle ⁇ is preferably an angle of 8 ° or less, for example, 4 ° or 8 °.
  • the main surface 10c of the n-type layer 12 is from the ⁇ 0001 ⁇ plane so that the normal vector z of the main surface 10c has at least one component of ⁇ 11-20> and ⁇ 1-100>. It is a surface that has been turned off.
  • main surface 10c is a surface off from the ⁇ 0001 ⁇ plane so that normal vector z of main surface 10c has a component of ⁇ 11-20>.
  • direction c is the [0001] direction (that is, the c-axis of hexagonal silicon carbide), and direction a 1 is, for example, the ⁇ 11-20> direction.
  • the off direction is a direction in which the normal vector z of the main surface 10c is inclined from the [0001] direction.
  • an off direction is a 1 direction (i.e. ⁇ 11-20> direction).
  • Major surface 10c in FIG. 3 is a surface (0001) plane is turned off in a 1 direction.
  • the plane offset direction is a direction obtained by projecting the offset direction (a 1 direction) to the main surface 10c.
  • the in-plane off direction is a 11 direction.
  • FIG. 4 is a partial cross sectional view schematically showing a first step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • the first step corresponds to a step of forming a collector region having n-type and defining the second main surface 10b.
  • a single crystal n + substrate 11 is prepared.
  • n-type layer 12 is formed on single crystal n + substrate 11 by epitaxial growth of silicon carbide.
  • Epitaxial growth can be performed by a CVD (Chemical Vapor Deposition) method.
  • hydrogen gas may be used as the carrier gas.
  • the source gas for example, a mixed gas of silane (SiH 4 ) and propane (C 3 H 8 ) can be used.
  • nitrogen (N) or phosphorus (P) is preferably introduced as an impurity for imparting n-type to silicon carbide.
  • FIG. 5 is a partial cross-sectional view schematically showing a second step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • the second step corresponds to a step of forming a base region having a p-type different from the n-type on the surface of the collector region opposite to the second main surface 10b.
  • p-type layer 13 is formed on n-type layer 12 by epitaxial growth of silicon carbide.
  • FIG. 6 is a partial cross sectional view schematically showing a third step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • the third step corresponds to a step of forming an emitter region having n-type and defining the first main surface 10a on the base region.
  • n + type layer 14 is formed on p type layer 13 by epitaxial growth of silicon carbide.
  • the p-type layer 13 may be formed by implanting p-type impurity ions into the n-type layer 12.
  • n + -type layer 14 may be formed by implanting n-type impurity ions into p-type layer 13.
  • a p-type layer 13 on the n-type layer 12 may be formed an n + -type layer 14 by implanting n-type impurity ions to the p-type layer 13.
  • the p-type layer 13 and the n + -type layer 14 are formed by epitaxial growth, the density of crystal defects contained in the p-type layer 13 and the n + -type layer 14 can be reduced.
  • FIG. 7 is a partial cross-sectional view schematically showing a fourth step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • the fourth step corresponds to a step of forming trench TR having sidewall surfaces SWa and SWb that penetrate the emitter region and reach the base region.
  • an opening is formed in a region where trench TR is to be formed in first main surface 10a of silicon carbide layer 10 by, for example, P-CVD (Plasma-Chemical Vapor Deposition).
  • a mask layer 90 made of silicon dioxide (SiO 2 ) is formed.
  • first main surface 10a of silicon carbide layer 10 is chemically treated.
  • first main surface 10a of silicon carbide layer 10 is chemically etched. More preferably, thermal etching is performed on first main surface 10a of silicon carbide layer 10.
  • the thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms.
  • the at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom.
  • This atmosphere is, for example, Cl 2 , BCL 3 , SF 6 , or CF 4 .
  • thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and a heat treatment temperature of, for example, 700 ° C. or more and 1000 ° C. or less.
  • the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas.
  • a carrier gas for example, nitrogen (N 2 ) gas, argon gas, helium gas or the like can be used.
  • the step of performing the thermal etching includes forming the first main surface of the silicon carbide layer in order to form a first region having an angle of 50 ° to 70 ° macroscopically with respect to the ⁇ 000-1 ⁇ plane. This is a chemical treatment process. More preferably, the step of performing thermal etching is a step of forming a first region including a plane having a plane orientation ⁇ 0-33-8 ⁇ . Such processing makes it possible to expose the special surface. When the thermal etching is completed, the mask layer 90 is removed.
  • FIG. 8 is a partial cross-sectional view schematically showing a fifth step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • p + type region 15 is formed in p type layer 13.
  • a thermal oxide film is formed on the surface of the p-type layer 13.
  • a photoresist film having an opening corresponding to the p + type region 15 is formed on the thermal oxide film by lithography.
  • the opening pattern is transferred to the thermal oxide film by etching the thermal oxide film and removing the photoresist film. Ion implantation of p-type impurities and activation heat treatment are performed. Thereby, the p + type region 15 is formed.
  • FIG. 9 is a partial cross-sectional view schematically showing a sixth step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • insulating film 21 is formed to cover first main surface 10a, side wall surfaces SWa and SWb, and bottom surface BT.
  • insulating film 21 is formed, for example, by oxidizing the surface of silicon carbide layer 10.
  • the insulating film 21 is made of, for example, silicon dioxide (SiO 2 ).
  • FIG. 10 is a partial cross-sectional view schematically showing a seventh step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • contact hole 16 for exposing n + type layer 14 and p + type region 15 is formed in insulating film 21.
  • the ohmic electrode 4 is disposed in the contact hole 16 formed in the insulating film 21.
  • FIG. 11 is a partial cross-sectional view schematically showing an eighth step of the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment.
  • an electrode material such as aluminum is deposited on the first main surface 10a side of silicon carbide layer 10 by sputtering. Thereby, a conductive film is formed.
  • a photoresist film is formed in a region corresponding to the emitter electrode 2a and the base electrode 3a by a lithography process.
  • the electrode material is removed by etching so that the pattern of the emitter electrode 2a and the base electrode 3a remains. Thereafter, the photoresist film is removed. Thereby, the emitter electrode 2a and the base electrode 3a are formed.
  • the collector electrode 5 may be formed simultaneously with the emitter electrode 2a and the base electrode 3a, or may be formed in a separate process.
  • FIG. 12 is a diagram for explaining the basic operation of the npn transistor. Referring to FIG. 12, a forward bias voltage is applied between the emitter (E) and the base (B), and a reverse bias voltage is applied between the collector (C) and the base.
  • Electrons (e ⁇ ) are injected into the emitter (E). As a result, an emitter current IE is generated.
  • holes (h + ) are injected into the base (B).
  • the base base current I B is caused by the holes and electrons combine. By thinning the base layer, most of the electrons flowing into the base (B) reach the junction between the base and the collector. Electrons diffuse to the collector due to the potential difference between the base and the collector. Thus the collector current I C is generated.
  • the current amplification factor (h FE ) of the bipolar transistor is defined as the ratio of the collector current I C to the base current I B.
  • the collector current I C is generated when electrons injected into the emitter reach the collector. Therefore, in order to increase the current amplification factor, it is necessary to reduce the probability that holes and electrons are combined in the base as much as possible. That is, in order to increase the current amplification factor, it is necessary to reduce the base current I B.
  • the following three methods can be listed as effective methods for reducing the base current.
  • the first technique is to lower the base doping concentration.
  • the second method is to reduce the width of the base.
  • the third method is to lower the crystal defect density or interface state density of the base. It is also conceivable to lower the emitter doping concentration in order to reduce the base current. However, in order to increase the current amplification factor, it is preferable to increase the number of electrons that penetrate the base from the emitter and reach the collector. For this reason, it is desirable that the emitter has a high doping concentration.
  • the base region is formed by epitaxial growth in order to reduce the crystal defect density of the base region.
  • the probability that electrons and holes recombine in the base region can be reduced.
  • the emitter region is formed by epitaxial growth. By reducing the crystal defect density in the emitter region, the probability that electrons are trapped in the emitter region can be reduced. Therefore, the current amplification factor can be increased.
  • the base region In order to form the emitter region on the base region by epitaxial growth, the base region is covered with the emitter region.
  • trench TR is formed from first main surface 10a of silicon carbide layer 10. By the trench TR, the base region can be exposed on the first main surface 10a side. Therefore, electrical connection between the base region and the base electrode can be ensured.
  • FIG. 13 is a diagram showing a configuration of a silicon carbide semiconductor device in which a special surface is not included in the inner peripheral surface of the trench.
  • trench TR ⁇ b> 1 is arranged in silicon carbide semiconductor device 101.
  • p type layer 13 base region
  • n + type layer 14 emitter region
  • the surface of trench TR1 is covered with insulating film 21.
  • the insulating film is generally formed by oxidizing the underlying semiconductor layer. This is because it is difficult to cover the side wall surface of the trench with an oxide film having a uniform and sufficient thickness in the vapor deposition by CVD.
  • an oxide film SiO 2
  • the side wall surface of the trench corresponds to the interface between the oxide film and the silicon carbide layer. Electrons and holes are recombined by the interface states existing at the interface.
  • the region 30 a is an interface at the junction position between the n + -type layer 14 and the p-type layer 13. For example, holes and electrons are likely to be combined in the region 30a.
  • silicon carbide tends to have a higher density of interface states than silicon. This increases the probability that holes and electrons recombine at the interface of the p-type layer 13. That is, the base current increases. For these reasons, it is required to improve the current amplification factor.
  • the side wall surfaces SWa and SWb of the trench TR include special surfaces.
  • the special surface is a surface selected in advance as a surface having a low interface state density. Therefore, the probability that holes and electrons are combined in the region 30 can be reduced. Thereby, since the base current can be reduced, silicon carbide semiconductor device 1 can obtain a high current gain.
  • Sidewall surfaces SWa and SWb of trench TR are surfaces inclined with respect to first main surface 10a of silicon carbide layer 10. Furthermore, the width along the direction a 21 of the trench TR is greater closer to the first major surface 10a.
  • the side wall surface of trench TR ⁇ b> 1 is substantially perpendicular to first main surface 10 a of silicon carbide layer 10. Therefore, as compared to the configuration shown in FIG. 13, FIG. 2, there is a possibility that the interval between the transistor cells along the direction a 21 increases. That is, the cell density may be reduced.
  • silicon carbide semiconductor device 1 can increase the current amplification degree as compared with silicon carbide semiconductor device 101. Therefore, the overall current amplification factor of silicon carbide semiconductor device 1 can be made higher than the entire current amplification factor of silicon carbide semiconductor device 101.
  • the cross-sectional shape of the trench TR is not limited as shown in FIG. It is only necessary that the side wall surfaces SWa and SWb include special surfaces.
  • FIG. 14 is a cross-sectional view showing another configuration of silicon carbide semiconductor device 1 according to the first embodiment.
  • bottom surface BT is omitted from trench TR.
  • the cross-sectional shape of the trench TR has a so-called V-shape. That is, the side wall surfaces SWa and SWb are connected to each other in the p-type layer 13.
  • FIG. 15 is a plan view showing a schematic configuration of the silicon carbide semiconductor device according to the second embodiment of the present invention.
  • 16 is a cross-sectional view taken along line XVI-XVI in FIG.
  • silicon carbide semiconductor device 1A according to the second embodiment is different from silicon carbide semiconductor device 1 according to the first embodiment in the cross-sectional shape of trench TR.
  • Each of the side wall surfaces SWa and SWb includes a first region SW1 and a second region SW2.
  • the first area SW1 is an area including a special surface.
  • Second region SW2 has a depth from first main surface 10a of silicon carbide layer 10 to a position shallower than the junction surface between n + -type layer 14 (emitter region) and p-type layer 13 (base region). It is an area
  • the angle ⁇ 1 is an angle formed by the first region SW1 with respect to the first main surface 10a.
  • the angle ⁇ 2 is an angle formed by the second region SW2 with respect to the first main surface 10a.
  • the angle ⁇ 2 is approximately 90 °.
  • the angle ⁇ 2 is larger than the angle ⁇ 1.
  • the method for manufacturing the silicon carbide semiconductor device according to the second embodiment differs from the method for manufacturing the silicon carbide semiconductor device according to the first embodiment in the step of forming trench TR. Therefore, in the following, the step of forming trench TR in silicon carbide layer 10 (fourth step), the step of forming p + -type region 15 in p-type layer 13 (fifth step), and the surface of trench TR are insulated.
  • the step of covering with a film (sixth step) will be described in detail, and the same steps (first to third, seventh and eighth steps) as the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment will be described. The following detailed description will not be repeated.
  • FIG. 17 is a partial cross-sectional view schematically showing a first process performed in the fourth step (step of forming a trench) of the method for manufacturing silicon carbide semiconductor device 1A according to the second embodiment.
  • mask layer 90 having an opening is formed on first main surface 10a.
  • the portion near the surface of the n + -type layer is removed by etching.
  • etching method for example, reactive ion etching (RIE), particularly inductively coupled plasma (ICP) RIE can be used.
  • RIE reactive ion etching
  • ICP inductively coupled plasma
  • ICP-RIE using SF 6 or a mixed gas of SF 6 and O 2 as a reaction gas can be used.
  • a second region SW2 that is a side wall surface substantially perpendicular to the first main surface 10a is formed in a region where the trench TR is to be formed.
  • the n + type layer 14 emitter region
  • the first main surface 10a of the silicon carbide layer 10 is shallower than the junction surface between the n + type layer 14 and the p type layer 13 (base region). Etched until.
  • FIG. 18 is a cross sectional view schematically showing a second process performed in the fourth step (step of forming a trench) of the method for manufacturing silicon carbide semiconductor device 1A according to the second embodiment.
  • thermal etching is performed in the same manner as in the first embodiment.
  • a first region SW1 connected to the second region SW2 is formed.
  • the angle ⁇ 2 is larger than the angle ⁇ 1.
  • FIG. 19 is a cross sectional view schematically showing fifth and sixth steps of the method for manufacturing silicon carbide semiconductor device 1A according to the second embodiment.
  • p + type region 15 is formed in p type layer 13 in the fifth step.
  • an insulating film 21 that covers the first main surface 10a, the side wall surfaces SWa and SWb, and the bottom surface BT is formed.
  • the current amplification factor of the silicon carbide semiconductor device can be increased as in the first embodiment.
  • the region corresponding to the trench TR in the first main surface 10a is previously etched by reactive ion etching.
  • the etching of the silicon carbide layer can proceed smoothly in the subsequent thermal etching. Therefore, the special surface can be exposed more reliably.
  • the probability of recombination of holes and electrons can be reduced in the base region. Therefore, the current amplification degree of the silicon carbide semiconductor device can be increased.
  • FIG. 20 is a plan view showing a schematic configuration of the silicon carbide semiconductor device according to the third embodiment of the present invention.
  • 21 is a cross-sectional view taken along line XXI-XXI in FIG.
  • silicon carbide semiconductor device 1 ⁇ / b> B according to the third embodiment includes silicon carbide semiconductor device 1 according to the first embodiment and second semiconductor device in terms of the cross-sectional shape of trench TR. Different from silicon carbide semiconductor device 1A according to the embodiment.
  • each of the sidewall surfaces SWa and SWb includes a first region SW1 and a second region SW2.
  • the first area SW1 is an area including a special surface.
  • Second region SW2 is a region connecting from first main surface 10a of silicon carbide layer 10 to first region SW1 through n + -type layer 14 (emitter region).
  • the angle ⁇ 1 is an angle formed by the first region SW1 with respect to the first main surface 10a.
  • the angle ⁇ 2 is an angle formed by the second region SW2 with respect to the first main surface 10a.
  • the angle ⁇ 2 is approximately 90 °.
  • the angle ⁇ 2 is larger than the angle ⁇ 1.
  • a method for manufacturing the silicon carbide semiconductor device according to the third embodiment will be described. Similarly to the description of the second embodiment, the step of forming trench TR in silicon carbide layer 10 (fourth step), the step of forming p + -type region 15 in p-type layer 13 (fifth step). And the step of covering the surface of trench TR with an insulating film (sixth step) will be described in detail, and the same steps (first to third steps) as the method for manufacturing silicon carbide semiconductor device 1 according to the first embodiment will be described. The seventh and eighth steps) will not be described in detail later.
  • FIG. 22 is a partial cross-sectional view schematically showing a first process performed in the fourth step (step of forming a trench) of the method for manufacturing silicon carbide semiconductor device 1B according to the third embodiment.
  • mask layer 90 having an opening is formed on first main surface 10a.
  • the portion near the surface of the n + -type layer 14 is removed by reactive ion etching (RIE), particularly inductively coupled plasma (ICP) RIE.
  • RIE reactive ion etching
  • ICP inductively coupled plasma
  • FIG. 23 is a cross sectional view schematically showing a second treatment executed in the fourth step (step of forming a trench) of the method for manufacturing silicon carbide semiconductor device 1B according to the third embodiment.
  • thermal etching is performed in the same manner as in the first and second embodiments.
  • a first region SW1 connected to the second region SW2 is formed.
  • the angle ⁇ 2 is larger than the angle ⁇ 1.
  • FIG. 24 is a cross sectional view schematically showing fifth and sixth steps of the method for manufacturing silicon carbide semiconductor device 1B according to the third embodiment.
  • p + type region 15 is formed in p type layer 13 in the fifth step.
  • an insulating film 21 that covers the first main surface 10a, the side wall surfaces SWa and SWb, and the bottom surface BT is formed.
  • the current amplification factor of the silicon carbide semiconductor device can be increased as in the first embodiment.
  • the reactive ion etching is performed in the trench TR in the first main surface 10a prior to the formation of the special surface (thermal etching). Corresponding regions are pre-etched. Thereby, the etching of the silicon carbide layer can proceed smoothly in the subsequent thermal etching.
  • the junction surface of the pn junction intersects the second region SW2.
  • Second region SW2 is perpendicular to first main surface 10a of silicon carbide layer 10. Therefore, the junction surface of the pn junction and the interface (second region SW2) of the pn junction intersect perpendicularly. Thereby, the breakdown voltage of the silicon carbide semiconductor device can be secured. In other words, it is possible to avoid a decrease in the breakdown voltage of the silicon carbide semiconductor device.
  • FIG. 25 is a diagram showing a depletion layer extending from the junction surface of the pn junction.
  • power supply 110 applies a reverse bias voltage between n + -type layer 112 and p-type layer 113.
  • the depletion layer 114 extends to both the n + -type layer 112 and the p-type layer 113.
  • the n + type layer 112 corresponds to the emitter region
  • the p type layer 113 corresponds to the base region.
  • the impurity concentration of the p-type layer 113 (base region) is relatively low, the impurity concentration of the n + -type layer 112 (emitter region) is relatively high. For this reason, the depletion layer 114 spreads more on the p-type layer 113 side than on the n + -type layer 112 side.
  • a surface 115 of the semiconductor device including the n + type layer 112 and the p type layer 113 is inclined with respect to the bonding surface 111.
  • the volume of the n + -type layer 112 is reduced.
  • the width of the depletion layer 114 on the p-type layer 113 side at the end of the junction surface 111 is smaller than the central portion of the junction surface 111.
  • the width of the depletion layer 114 on the n + -type layer 112 side is slightly wider at the end of the junction surface 111 than at the center of the junction surface 111.
  • the width of the depletion layer 114 at the center of the junction surface 111 is w1
  • the width of the depletion layer 114 at the end of the junction surface 111 is w2
  • w1> w2 Since the width of the depletion layer is smaller at the end portion of the bonding surface 111 than at the center portion of the bonding surface 111, the electric field strength tends to increase at the end portion of the bonding surface 111. The occurrence of a portion where the strength of the electric field is higher than others tends to reduce the breakdown voltage of the semiconductor device.
  • FIG. 26 is another diagram showing a depletion layer extending from the junction surface of the pn junction.
  • power supply 110 applies a reverse bias voltage between n + -type layer 112 and p-type layer 113.
  • a surface 115 of the semiconductor device including the n + type layer 112 and the p type layer 113 is perpendicular to the bonding surface 111 with respect to the bonding surface 111. Accordingly, the depletion layer 114 extends uniformly in both the n + -type layer 112 and the p-type layer 113.
  • the width of the depletion layer 114 is, for example, the above w1.
  • the junction surface between the n + -type layer 14 (emitter region) and the p-type layer 13 (base region) and the second region SW2 intersect perpendicularly. Therefore, as shown in FIG. 25, the depletion layer includes n + type layer 14 (emitter region) and p type layer 13 (base region). And spreads uniformly in both. Therefore, the breakdown voltage of the silicon carbide semiconductor device can be ensured.
  • the first conductivity type is n-type
  • the second conductivity type different from the first conductivity type is p-type. That is, the silicon carbide semiconductor device according to each embodiment realizes an npn-type bipolar transistor. Thereby, the ease of manufacture of the silicon carbide semiconductor device can be improved.
  • the first conductivity type may be p-type and the second conductivity type may be n-type. That is, the silicon carbide semiconductor device according to each embodiment may realize a pnp bipolar transistor.
  • Silicon carbide semiconductor device 2a emitter electrode, 3a base electrode, 4 ohmic electrode, 5 collector electrode, 10 silicon carbide layer, 10a first main surface, 10b second main surface, 11 n + Substrate, 12,112 n-type layer, 13,113 p-type layer, 14,112 n + -type layer, 15 p + -type region, 16 contact hole, 21 insulating film, 30, 30a region, 90 mask layer, 110 power supply, 111 joint surface 112 114 the depletion layer, 115 surface, BT bottom, I B base current, I C collector current, I E emitter current, SW1 first region, SW2 second region, SWa, Swb sidewall surface, TR, TR1 trench, a 1 , a 11 , a 21 , c direction, w 1, w 2 width (depletion layer), z normal vector, ⁇ off angle, ⁇ 1, ⁇ 2 angle.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
PCT/JP2014/069515 2013-09-12 2014-07-24 炭化珪素半導体装置およびその製造方法 Ceased WO2015037335A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/911,678 US20160211332A1 (en) 2013-09-12 2014-07-24 Silicon carbide semiconductor device and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-189581 2013-09-12
JP2013189581A JP2015056544A (ja) 2013-09-12 2013-09-12 炭化珪素半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
WO2015037335A1 true WO2015037335A1 (ja) 2015-03-19

Family

ID=52665457

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/069515 Ceased WO2015037335A1 (ja) 2013-09-12 2014-07-24 炭化珪素半導体装置およびその製造方法

Country Status (3)

Country Link
US (1) US20160211332A1 (enExample)
JP (1) JP2015056544A (enExample)
WO (1) WO2015037335A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10109724B2 (en) 2017-02-22 2018-10-23 Qualcomm Incorporated Heterojunction bipolar transistor unit cell and power stage for a power amplifier

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303469A (ja) * 2005-03-25 2006-11-02 Shindengen Electric Mfg Co Ltd ＳｉＣ半導体装置
JP2006351621A (ja) * 2005-06-13 2006-12-28 Honda Motor Co Ltd バイポーラ型半導体装置およびその製造方法
JP2011233669A (ja) * 2010-04-27 2011-11-17 Sumitomo Electric Ind Ltd 半導体装置
JP2012209422A (ja) * 2011-03-30 2012-10-25 Sumitomo Electric Ind Ltd Ｉｇｂｔ
JP2013162118A (ja) * 2012-02-01 2013-08-19 Sumitomo Electric Ind Ltd 炭化珪素半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303469A (ja) * 2005-03-25 2006-11-02 Shindengen Electric Mfg Co Ltd ＳｉＣ半導体装置
JP2006351621A (ja) * 2005-06-13 2006-12-28 Honda Motor Co Ltd バイポーラ型半導体装置およびその製造方法
JP2011233669A (ja) * 2010-04-27 2011-11-17 Sumitomo Electric Ind Ltd 半導体装置
JP2012209422A (ja) * 2011-03-30 2012-10-25 Sumitomo Electric Ind Ltd Ｉｇｂｔ
JP2013162118A (ja) * 2012-02-01 2013-08-19 Sumitomo Electric Ind Ltd 炭化珪素半導体装置

Also Published As

Publication number Publication date
US20160211332A1 (en) 2016-07-21
JP2015056544A (ja) 2015-03-23

Similar Documents

Publication Publication Date Title
CN102971853B (zh) 半导体器件及其制造方法
JP5699878B2 (ja) 炭化珪素半導体装置およびその製造方法
CN107068732B (zh) 碳化硅半导体器件
JP2015060859A (ja) 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
WO2012017796A9 (ja) 半導体装置およびその製造方法
JP5564890B2 (ja) 接合型電界効果トランジスタおよびその製造方法
JP2012160485A (ja) 半導体装置とその製造方法
JP2013062397A (ja) 炭化珪素半導体装置の製造方法
JP6357869B2 (ja) 炭化珪素半導体装置の製造方法
WO2013011740A1 (ja) 半導体装置の製造方法
JP2015156429A (ja) 炭化珪素半導体装置およびその製造方法
WO2014199748A1 (ja) 炭化珪素半導体装置
JP6098474B2 (ja) 炭化珪素半導体装置およびその製造方法
KR20180044113A (ko) 실리콘 카바이드 반도체 소자의 제조방법
JP2011091125A (ja) 炭化珪素半導体装置及びその製造方法
CN104584220B (zh) 用于制造碳化硅半导体器件的方法
CN104508828A (zh) 用于制造碳化硅半导体器件的方法
WO2012066820A1 (ja) 炭化珪素半導体装置
JP2015220408A (ja) 炭化珪素半導体装置およびその製造方法
WO2014027520A1 (ja) 炭化珪素半導体装置
JPWO2018096722A1 (ja) 半導体装置
WO2015037335A1 (ja) 炭化珪素半導体装置およびその製造方法
JP5820710B2 (ja) 半導体装置
WO2014041879A1 (ja) 炭化珪素半導体装置
JP5870898B2 (ja) 炭化珪素半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14844934

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 14911678

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14844934

Country of ref document: EP

Kind code of ref document: A1