WO2015019733A1 - 炭化珪素半導体基板およびその製造方法、ならびに炭化珪素半導体装置の製造方法 - Google Patents
炭化珪素半導体基板およびその製造方法、ならびに炭化珪素半導体装置の製造方法 Download PDFInfo
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- silicon carbide
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 256
- 239000000758 substrate Substances 0.000 title claims abstract description 252
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 230
- 239000004065 semiconductor Substances 0.000 title claims abstract description 222
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 63
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims description 49
- 239000012535 impurity Substances 0.000 claims description 43
- 230000001629 suppression Effects 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 22
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 19
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 16
- 239000010936 titanium Substances 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052799 carbon Inorganic materials 0.000 claims description 9
- 239000010931 gold Substances 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 229910052697 platinum Inorganic materials 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
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- 229910052698 phosphorus Inorganic materials 0.000 description 3
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- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 2
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- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
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- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
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- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
- H01L21/047—Making n or p doped regions or layers, e.g. using diffusion using ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
Definitions
- the present invention relates to a silicon carbide semiconductor substrate, a method for manufacturing the same, and a method for manufacturing a silicon carbide semiconductor device, and more particularly, a silicon carbide semiconductor substrate having high flatness even when heat-treated at a high temperature, a method for manufacturing the same, and a silicon carbide semiconductor device. It relates to the manufacturing method.
- SiC silicon carbide
- the silicon carbide semiconductor substrate is being increased in diameter.
- the outer diameter of the silicon carbide semiconductor substrate is, for example, about 6 inches, the flatness of the silicon carbide semiconductor substrate is impaired.
- JP 2012-214376 describes a SiC having a diameter of at least about 75 millimeters (3 inches), a strain of less than about 5 ⁇ m, a warp of less than about 5 mm, and a TTV of less than about 2.0 ⁇ m.
- a wafer is described. Specifically, by slicing the SiC boule into a wafer and starting the lapping process using a downward force that is less than the downward force required to fold the wafer on a double-sided wrapper. It is described that wafers with low distortion, warpage and TTV can be produced.
- the silicon carbide semiconductor substrate whose flatness deteriorates due to heat treatment at a high temperature has been confirmed.
- doping in a method for manufacturing a silicon carbide semiconductor device is performed by ion implantation at a high temperature, but a silicon carbide semiconductor substrate having poor flatness is difficult to be adsorbed on the electrostatic chuck stage of the implantation device. It has been confirmed that problems such as breakage of the substrate may occur depending on the type.
- Such deterioration of flatness at high temperatures is a particularly serious problem in a silicon carbide semiconductor substrate having a large diameter of 100 mm or more. That is, even if a silicon carbide semiconductor substrate having a large diameter (especially 100 mm or more) is used in order to obtain a silicon carbide semiconductor device efficiently, it is difficult to manufacture the silicon carbide semiconductor device with a high yield due to the deterioration of the flatness as described above. Met.
- a main object of the present invention is to provide a silicon carbide semiconductor substrate having high flatness even at high temperatures, a method for manufacturing the same, and a method for manufacturing a silicon carbide semiconductor device.
- Another object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device capable of manufacturing a silicon carbide semiconductor device with a high yield by using a large-diameter silicon carbide semiconductor substrate.
- a silicon carbide semiconductor substrate according to the present invention has a main surface having an outer diameter of 100 mm or more, a base substrate made of single crystal silicon carbide, an epitaxial layer formed on the main surface, and a main substrate. And a deformation suppression layer formed on the back surface located on the opposite side of the surface.
- a method for manufacturing a silicon carbide semiconductor substrate according to the present invention includes a step of preparing a base substrate having a main surface having an outer diameter of 100 mm or more and made of single crystal silicon carbide, and forming an epitaxial layer on the main surface And a step of forming a deformation suppressing layer on a back surface located on the opposite side of the main surface in the base substrate.
- a method for manufacturing a silicon carbide semiconductor device includes a step of preparing a base substrate having a main surface having an outer diameter of 100 mm or more and made of single crystal silicon carbide, and forming an epitaxial layer on the main surface Forming a deformation suppressing layer on a back surface of the base substrate opposite to the main surface to prepare a silicon carbide semiconductor substrate; and implanting impurity ions into the silicon carbide semiconductor substrate.
- a silicon carbide semiconductor substrate having high flatness even at high temperatures can be obtained.
- FIG. 8 is a reference diagram for illustrating the function and effect of the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
- FIG. 8 is a reference diagram for illustrating the function and effect of the method for manufacturing the silicon carbide semiconductor device according to the embodiment.
- silicon carbide semiconductor substrate 10 has a main surface 1A having an outer diameter of 100 mm or more, a base substrate 1 made of single-crystal silicon carbide, and a main surface
- transformation suppression layer 8 formed on the back surface 1B located in the base substrate 1 on the opposite side to 1 A of main surfaces are provided.
- Silicon carbide semiconductor substrate 10 according to the present embodiment is a large-diameter substrate having an outer diameter of 100 mm or more, preferably has an outer diameter of 125 mm or more, and more preferably has an outer diameter of 150 mm or more.
- silicon carbide semiconductor substrate 10 is a large-diameter substrate having an outer diameter of 100 mm or more, and deformation of the substrate by deformation suppression layer 8 (for example, warpage of the substrate during high-temperature processing). Is suppressed.
- produce in the silicon carbide semiconductor substrate 10 during the said manufacturing process can be reduced.
- doping in the method for manufacturing a silicon carbide semiconductor device is performed by ion implantation into silicon carbide semiconductor substrate 10 at a high temperature, and silicon carbide semiconductor substrate 10 is used as an electrostatic chuck stage of the ion implantation device.
- silicon carbide semiconductor substrate 10 is used as an electrostatic chuck stage of the ion implantation device.
- the amount of warpage of silicon carbide semiconductor substrate 10 at a high temperature for example, 400 ° C.
- Large stress is not applied by adsorption. Therefore, the risk of occurrence of abnormalities such as cracks and cracks in silicon carbide semiconductor substrate 10 can be reduced.
- silicon carbide semiconductor substrate 10 is a large-diameter substrate having an outer diameter of 100 mm or more, and exhibits excellent flatness as described above. Therefore, silicon carbide semiconductor substrate 10 is used to form a silicon carbide semiconductor.
- a silicon carbide semiconductor device having a small variation in characteristics can be manufactured on silicon carbide semiconductor substrate 10. Specifically, a process of processing main surface 2A of silicon carbide semiconductor substrate 10 from a specific direction, such as ion implantation for silicon carbide semiconductor substrate 10, is considered.
- main surface 2A of silicon carbide semiconductor substrate 10 since the flatness of main surface 2A of silicon carbide semiconductor substrate 10 is high, the occurrence of a problem that the arrangement and form of a region to be processed (for example, an implantation region) with respect to main surface 2A varies locally within main surface 2A. Can be suppressed. As a result, variations in the processing on the main surface 2A can be reduced.
- silicon carbide semiconductor substrate 10 preferably has, for example, an LTV (Local Thickness Variation) of 1 ⁇ m or less in order to perform high-precision exposure.
- LTV Local Thickness Variation
- the silicon carbide semiconductor substrate 10 according to the present embodiment has a small amount of warpage, the apparent LTV does not increase and high-precision exposure can be performed.
- the silicon carbide semiconductor device can be manufactured with high yield by advancing the manufacturing process of the silicon carbide semiconductor device using silicon carbide semiconductor substrate 10 having a large diameter and high flatness.
- the warpage amount when the substrate temperature is room temperature is -100 ⁇ m or more and 100 ⁇ m or less, and the warpage amount when the substrate temperature is 400 ° C. is -1. It is preferable that it is 5 mm or more and 1.5 mm or less.
- “amount of warpage” of silicon carbide semiconductor substrate 10 is the main surface of silicon carbide semiconductor substrate 10 when silicon carbide semiconductor substrate 10 is placed on plane S ⁇ b> 1. This is the difference in height between the highest position and the lowest position with respect to the plane S1 in 2A.
- FIG. 1 the warpage amount when the substrate temperature is room temperature is -100 ⁇ m or more and 100 ⁇ m or less
- the warpage amount when the substrate temperature is 400 ° C. is -1. It is preferable that it is 5 mm or more and 1.5 mm or less.
- “amount of warpage” of silicon carbide semiconductor substrate 10 is the main surface of silicon carbide semiconductor substrate 10 when silicon carbide semiconductor substrate 10 is placed on plane S ⁇ b> 1. This is the difference
- the amount of warpage is positive or negative when main surface 2A of silicon carbide semiconductor substrate 10 is convex downward (the center position of silicon carbide semiconductor substrate 10 is relative to plane S1 relative to the outer peripheral position).
- the case where it is convex upward is positive.
- “Substrate temperature” is a temperature measured by a radiation thermometer from the main surface 2A side of silicon carbide semiconductor substrate 10, and is measured in a semiconductor manufacturing apparatus such as an ion implantation apparatus, for example.
- the thermal expansion coefficient of the deformation suppressing layer 8 may be 90% or less or 110% or more of the thermal expansion coefficient of the single crystal silicon carbide. In this case, since the thermal expansion coefficient of the deformation suppression layer is sufficiently different from the thermal expansion coefficient of silicon carbide, the deformation suppression effect of the silicon carbide semiconductor substrate by the deformation suppression layer 8 can be reliably obtained.
- the thickness of the deformation suppression layer 8 may be 5 ⁇ m or less. In this case, since the thickness of deformation suppression layer 8 is sufficiently thin, when silicon carbide semiconductor substrate 10 is installed in the processing apparatus, deformation suppression layer 8 is formed, so that silicon carbide semiconductor substrate 10 is placed in a predetermined area in the processing apparatus. It is possible to suppress the occurrence of a problem that the quality of the processing is deteriorated because the optimum processing condition for the silicon carbide semiconductor substrate 10 is different from the case where the deformation suppressing layer 8 is not provided.
- the material constituting the deformation suppression layer 8 is silicon oxide (SiO 2 ), carbon (C), aluminum (Al), titanium (Ti), nickel (Ni ), Platinum (Pt), and gold (Au).
- the above-described material has a thermal expansion coefficient different from that of silicon carbide by 10% or more and has a relatively small influence as an impurity on the silicon carbide semiconductor substrate.
- deformation of silicon carbide semiconductor substrate 10 can be effectively suppressed.
- silicon oxide and carbon for example, diamond, diamond-like carbon: DLC, etc.
- Aluminum, titanium, nickel, platinum, and gold have a relatively large thermal expansion coefficient with respect to the thermal expansion coefficient of silicon carbide.
- a method for manufacturing a silicon carbide semiconductor substrate includes a step (S10) of preparing base substrate 1 having a main surface 1A having an outer diameter of 100 mm or more and made of single-crystal silicon carbide; A step (S20) of forming the epitaxial layer 2 on the main surface 1A and a step (S30) of forming the deformation suppression layer 8 on the back surface 1B located on the opposite side of the main surface 1A in the base substrate 1 are provided.
- the main surface of base substrate 1 is concaved after the step of forming the epitaxial layer (S20).
- the main surface of the base substrate 1 warps in a convex shape after the step (S20) of forming the deformation suppressing layer 8 having a smaller thermal expansion coefficient than that of single crystal silicon carbide and forming the epitaxial layer.
- the deformation suppressing layer 8 having a larger thermal expansion coefficient than that of single crystal silicon carbide may be formed.
- the deformation suppression layer having a smaller thermal expansion coefficient than that of single crystal silicon carbide. 8 is composed of at least one of silicon oxide and carbon, and the deformation suppressing layer 8 having a thermal expansion coefficient larger than that of single crystal silicon carbide is aluminum, titanium, nickel, platinum, and gold. It may be composed of at least one selected from the group consisting of In this case, the silicon carbide semiconductor substrate according to the present embodiment can be easily obtained by using the above-described material having a thermal expansion coefficient different from that of silicon carbide and having a small influence as an impurity on silicon carbide as the material of the deformation suppressing layer 8. Can do.
- the thermal expansion coefficient is 90% or less or 110% of the thermal expansion coefficient of single crystal silicon carbide.
- the deformation suppression layer 8 as described above may be formed. In this case, since the thermal expansion coefficient of deformation suppression layer 8 is sufficiently different from the thermal expansion coefficient of silicon carbide, the deformation suppression effect of silicon carbide semiconductor substrate 10 by deformation suppression layer 8 can be reliably obtained. .
- a method for manufacturing a silicon carbide semiconductor device includes a step (S10) of preparing base substrate 1 having a main surface having an outer diameter of 100 mm or more and made of single crystal silicon carbide, A step of forming epitaxial layer 2 on the surface (S20), and a step of forming silicon carbide semiconductor substrate by forming deformation suppression layer 8 on the back surface of base substrate 1 located on the opposite side of the main surface (S30). And a step (S40) of implanting impurity ions into the silicon carbide semiconductor substrate.
- the method for manufacturing the silicon carbide semiconductor device according to the present embodiment uses silicon carbide semiconductor substrate 10 obtained by the method for manufacturing the silicon carbide semiconductor substrate according to the present embodiment, and carbonizes on silicon carbide semiconductor substrate 10.
- a silicon semiconductor device is manufactured.
- silicon carbide semiconductor substrate 10 obtained by the method for manufacturing a silicon carbide semiconductor substrate according to the present embodiment is a substrate that has an outer diameter of 100 mm or more and is suppressed in warpage and excellent in flatness. That is, in the step of implanting impurity ions into silicon carbide semiconductor substrate 10 (S40), for example, even when the substrate temperature is heated to about 400 ° C., warpage of silicon carbide semiconductor substrate 10 is suppressed and flatness is maintained. can do.
- the angle formed by the impurity implantation direction with respect to main surface 2A of silicon carbide semiconductor substrate 10 is the main surface of silicon carbide semiconductor substrate 10 even if the outer diameter of silicon carbide semiconductor substrate 10 is 100 mm or more. It can be made substantially constant regardless of the in-plane position of the surface 2A.
- the form of the ion implantation region (for example, the shape of the implantation region in the depth direction of the substrate and the ion concentration profile) can be made substantially constant regardless of the in-plane position of the main surface 2A. Therefore, according to the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, the silicon carbide semiconductor device can be manufactured with a high yield.
- Silicon carbide semiconductor substrate 10 includes base substrate 1, epitaxial layer 2 formed on main surface 1A of base substrate 1, and deformation suppression layer 8 formed on back surface 1B of base substrate 1. With.
- Base substrate 1 is made of single crystal silicon carbide and has a main surface 1A having an outer diameter of 6 inches. Silicon carbide constituting base substrate 1 has, for example, a hexagonal crystal structure, and preferably has a crystal polymorph (polytype) of 4H—SiC. Base substrate 1 contains an n-type impurity such as nitrogen (N) at a high concentration, and the conductivity type is n-type.
- the impurity concentration of the base substrate 1 is, for example, about 1.0 ⁇ 10 18 cm ⁇ 3 or more and 1.0 ⁇ 10 18 cm ⁇ 3 or less.
- Main surface 1A may be, for example, a ⁇ 0001 ⁇ plane or a plane having an off angle of 1 ° or more and 10 ° or less with respect to the ⁇ 0001 ⁇ plane.
- the thickness of the base substrate 1 is, for example, about 200 ⁇ m to 700 ⁇ m, preferably 300 ⁇ m to 600 ⁇ m.
- Epitaxial layer 2 is a layer made of silicon carbide formed by epitaxial growth on main surface 1 ⁇ / b> A of base substrate 1.
- Epitaxial layer 2 contains an n-type impurity such as nitrogen (N), for example, and the conductivity type of epitaxial layer 2 is n-type.
- the impurity concentration of the epitaxial layer 2 may be lower than the impurity concentration of the base substrate 1.
- the impurity concentration of the epitaxial layer 2 is, for example, about 7.5 ⁇ 10 15 cm ⁇ 2 .
- the film thickness of the epitaxial layer 2 is, for example, about 5 ⁇ m to 40 ⁇ m.
- deformation suppressing layer 8 made of a material having a thermal expansion coefficient different from that of silicon carbide is formed on back surface 1 ⁇ / b> B located on the opposite side of main surface 1 ⁇ / b> A of base substrate 1. Yes.
- the thickness of the deformation suppressing layer 8 may be 5 ⁇ m or less, and more preferably 3 ⁇ m or less.
- the material constituting the deformation suppression layer 8 is a group consisting of silicon oxide (SiO 2 ), carbon (C), aluminum (Al), titanium (Ti), nickel (Ni), platinum (Pt), and gold (Au). Is at least one selected from.
- the deformation suppression layer 8 may be configured by a single layer including the above-described material, but may have a multilayer structure (laminated structure) including a plurality of layers including at least one of the above-described materials. . Further, the deformation suppressing layer 8 may include a plurality of portions having locally different thicknesses when viewed in plan. For example, in the deformation suppression layer 8, a linear, curved, or circular groove may be formed.
- the silicon carbide semiconductor substrate 10 has a warpage amount of ⁇ 100 ⁇ m or more and 100 ⁇ m or less, preferably 40 ⁇ m or more and 40 ⁇ m or less when the substrate temperature is room temperature. Further, silicon carbide semiconductor substrate 10 has a warpage amount of ⁇ 1.5 mm to 1.5 mm, preferably ⁇ 1.0 mm to 1.0 mm when the substrate temperature is 100 ° C. to 500 ° C. . More preferably, the amount of warpage when the substrate temperature is 200 ° C. or more and 400 ° C. or less is ⁇ 1.5 mm or more and 1.5 mm or less, and more preferably ⁇ 1.0 mm or more and 1.0 mm or less.
- base substrate 1 having a main surface 1A having an outer diameter of 6 inches and made of single crystal silicon carbide is prepared (step (S10)).
- the base substrate 1 having an outer diameter of 6 inches is prepared by an arbitrary method.
- the outer diameter of the base substrate 1 may be 100 mm or more (for example, 5 inches or 8 inches).
- epitaxial layer 2 is formed on main surface 1A of base substrate 1 by an epitaxial growth method (step (S20)).
- Epitaxial growth is performed by a CVD method.
- the source gas for example, a mixed gas of silane (SiH 4 ) and propane (C 3 H 8 ) can be used.
- nitrogen (N) or phosphorus (P) may be introduced as impurities.
- Layer 3 (carbonized layer) may be formed.
- the damaged layer 3 may be formed with a thickness of about 0.001 ⁇ m or more and 10 ⁇ m or less, for example, and when formed with a thickness of 1 ⁇ m or more, it may be visually confirmed as white turbidity on the back surface 1B.
- the surface roughness (Ra) of the back surface 1B of the region where the damage layer 3 is formed is 0.001 ⁇ m or more.
- the laminate 4 of the base substrate 1 and the epitaxial layer 2 on which the damaged layer 3 is formed on the back surface 1B has warpage when the substrate temperature is room temperature, for example, -150 ⁇ m or more and 150 ⁇ m or less.
- a deformation suppression layer 8 is formed on the back surface 1B of the base substrate 1 (step (S30)). Specifically, the deformation suppression layer 8 is formed on the back surface 1 ⁇ / b> B of the base substrate 1 in the stacked body 4.
- a method for forming the deformation suppression layer 8 any method such as a chemical vapor deposition method (CVD method) or a physical vapor deposition method such as a sputtering method can be used.
- the material of the deformation suppression layer 8 can be determined according to the direction of the warp that occurs in the stacked body 4 of the base substrate 1 and the epitaxial layer 2 in the step (S20).
- deformation suppression layer 8 made of a material having a smaller thermal expansion coefficient than that of single crystal silicon carbide is formed. Good.
- a material of the deformation suppression layer 8 for example, at least one of silicon oxide and carbon can be used.
- the deformation suppression layer 8 having a larger thermal expansion coefficient than that of single crystal silicon carbide may be formed.
- a material of the deformation suppressing layer 8 at least one selected from the group consisting of aluminum, titanium, nickel, platinum, and gold can be used.
- the thermal expansion coefficient of the material constituting the deformation suppressing layer 8 is preferably 90% or less or 110% or more of the thermal expansion coefficient of single crystal silicon carbide. Further, the thickness of the deformation suppressing layer 8 may be 5 ⁇ m or less, preferably 3 ⁇ m or less.
- Silicon carbide semiconductor substrate 10 has a back surface of laminate 4 in which base substrate 1 having an outer diameter of 6 inches and epitaxial layer 2 formed on main surface 1A of base substrate 1 are laminated. A deformation suppressing layer 8 is formed on 1B.
- silicon carbide semiconductor substrate 10 has a warp of ⁇ 100 ⁇ m or more and 100 ⁇ m or less when the substrate temperature is room temperature, and a warp amount of ⁇ 1.5 mm or more when the substrate temperature is 100 ° C. or more and 500 ° C. or less. It can be 1.5 mm or less.
- silicon carbide semiconductor substrate 10 has a warp of ⁇ 100 ⁇ m or more and 100 ⁇ m or less when the substrate temperature is room temperature, and a warp amount of ⁇ 1.5 mm or more and 1 or less when the substrate temperature is 200 ° C. or more and 400 ° C. or less. .5 mm or less.
- the warpage amount of silicon carbide semiconductor substrate 10 is described above. The amount can be kept within the range.
- the warp amount can be increased even at high temperatures as described above.
- a small silicon carbide semiconductor substrate 10 can be obtained.
- the amount of warpage is ⁇ 1.5 mm to 1.5 mm.
- silicon carbide semiconductor substrate 10 having a sufficiently small value of ⁇ 1.0 mm or more and 1.0 mm or less can be obtained.
- Silicon carbide semiconductor substrate 10 manufactured by the method for manufacturing a silicon carbide semiconductor substrate according to the present embodiment has an outer diameter of base substrate 1 of 6 inches and a thickness of base substrate 1 of 200 ⁇ m or more and 700 ⁇ m or less. Sometimes, even when the substrate temperature is heated to about 100 ° C. or more and about 500 ° C. or less, the amount of warpage is small and high flatness can be obtained. In other words, silicon carbide semiconductor substrate 10 according to the present embodiment can have high flatness even at a high temperature even if base substrate 1 does not have a thickness exceeding 700 ⁇ m. As a result, according to the method for manufacturing the silicon carbide semiconductor substrate according to the present embodiment, silicon carbide semiconductor substrate 10 having a large diameter and having high flatness even at high temperatures can be obtained at low cost.
- the silicon carbide semiconductor device according to the present embodiment has an element region IR (active region) and a termination region OR (invalid region) surrounding element region IR.
- Termination region OR includes guard ring region 5. That is, the element region IR is surrounded by the guard ring region 5.
- a semiconductor element 7 such as a transistor or a diode is provided in the element region IR.
- the semiconductor element 7 mainly includes, for example, a silicon carbide semiconductor substrate 10 made of hexagonal silicon carbide, a gate insulating film 15, a gate electrode 17, a source electrode 16, and a drain electrode 19.
- Silicon carbide semiconductor substrate 10 includes a base substrate 1 and an epitaxial layer 2, and epitaxial layer 2 mainly includes a drift region 12, a p body region 13, an n + source region 14, and a p + region 18. .
- the drift region 12 is the epitaxial layer 2 where the p body region 13, the n + source region 14, and the p + region 18 are not formed.
- P body region 13 has p type conductivity.
- P body region 13 is formed in drift region 12 including main surface 2 ⁇ / b> A of silicon carbide semiconductor substrate 10.
- the p-type impurity contained in p body region 13 is, for example, aluminum (Al), boron (B), or the like.
- the impurity concentration of aluminum or the like contained in p body region 13 is, for example, about 1 ⁇ 10 17 cm ⁇ 3 .
- N + source region 14 has n type conductivity.
- N + source region 14 is formed inside p body region 13 so as to include main surface 2 A and be surrounded by p body region 13.
- the n-type impurity contained in the n + source region 14 is, for example, P (phosphorus).
- the concentration of impurities such as phosphorus contained in n + source region 14 is higher than that of n-type impurities contained in drift region 12, for example, about 1 ⁇ 10 20 cm ⁇ 3 .
- the p + region 18 has p type conductivity.
- P + region 18 is formed so as to contact main surface 2A and p body region 13 and penetrate the vicinity of the center of n + source region 14.
- the p + region 18 contains p-type impurities such as Al and B at a higher concentration than the p-type impurities contained in the p body region 13, for example, about 1 ⁇ 10 20 cm ⁇ 3 .
- Gate insulating film 15 is formed in contact with drift region 12 so as to extend from the upper surface of one n + source region 14 to the upper surface of the other n + source region 14.
- the gate insulating film 15 is made of, for example, silicon dioxide (SiO 2 ).
- the gate electrode 17 is disposed in contact with the gate insulating film 15 so as to extend from one n + source region 14 to the other n + source region 14.
- the gate electrode 17 is made of a conductor such as polysilicon or Al.
- Source electrode 16 is disposed in contact with the n + source region 14 and the p + region 18 on the main surface 2A.
- Source electrode 16 includes, for example, titanium (Ti) atoms, Al atoms, and silicon (Si) atoms. Thereby, source electrode 16 can make ohmic contact with both n-type silicon carbide region (n + source region 14) and p-type silicon carbide region (p + region 18).
- the drain electrode 19 is formed in contact with the back surface 1B in the silicon carbide semiconductor substrate 10.
- the drain electrode 19 may have the same configuration as the source electrode 16, for example, and is made of another material capable of ohmic contact with the silicon carbide semiconductor substrate 10 (base substrate 1) such as nickel (Ni). It may be. Thereby, the drain electrode 19 is electrically connected to the base substrate 1.
- the guard ring region 5 has an annular planar shape, and is disposed in the termination region OR of the silicon carbide semiconductor substrate 10 so as to surround the element region IR provided with the semiconductor element 7.
- Guard ring region 5 has p-type (second conductivity type).
- the guard ring region 5 is a conductive region that acts as a guard ring.
- the plurality of guard rings 6 in the guard ring region 5 contain impurities such as boron and aluminum.
- the impurity concentration in each of the plurality of guard rings 6 is lower than the impurity concentration in p body region 13.
- the concentration of the impurity in each of the plurality of guard rings 6 is, for example, 1.3 ⁇ 10 13 cm ⁇ 3 , and preferably about 8 ⁇ 10 12 cm ⁇ 3 to 1.4 ⁇ 10 13 cm ⁇ 3 .
- the method for manufacturing the silicon carbide semiconductor device according to the present embodiment is manufactured using the silicon carbide semiconductor substrate according to the present embodiment.
- silicon carbide semiconductor substrate 10 obtained as described above is prepared (step (S10) to step (S30)).
- impurities are implanted into main surface 2 ⁇ / b> A of silicon carbide semiconductor substrate 10, so that p body region 13, n source region 14, p + region 18, and guard are formed in epitaxial layer 2.
- the ring region 5 is formed (step (S40)).
- Al is ion-implanted as a p-type impurity into epitaxial layer 2 having a conductivity type of n to form p body region 13 having a conductivity type of p type.
- P is ion-implanted as an n-type impurity in p body region 13, thereby forming n source region 14 having an n conductivity type.
- Al is ion-implanted as a p-type impurity, whereby p + region 18 having a p-type conductivity is formed.
- Al is ion-implanted as a p-type impurity, whereby a p-type guard ring region 5 is formed.
- ion implantation in this step (S40) is performed, for example, in a state where the substrate temperature of silicon carbide semiconductor substrate 10 is raised to about 100 ° C. or higher and about 500 ° C. or lower (so-called high temperature implantation). Before and after performing this step (S40), warpage of silicon carbide semiconductor substrate 10 is not less than ⁇ 1.5 mm and not more than 1.5 mm.
- step (S50) heat treatment for activating the impurities added by ion implantation is performed (step (S50)).
- the temperature of the heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C.
- the heat treatment time is, for example, about 30 minutes.
- the atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an argon (Ar) atmosphere.
- the warpage amount of silicon carbide semiconductor substrate 10 is not less than ⁇ 1.5 mm and not more than 1.5 mm.
- the gate insulating film 15 is formed (step (S60)). Specifically, first, silicon carbide semiconductor substrate 10 on which a desired impurity region is formed is thermally oxidized. Thermal oxidation can be carried out, for example, by heating to about 1300 ° C. in an oxygen atmosphere and holding for about 40 minutes. Thereby, gate insulating film 15 made of SiO 2 is formed on main surface 2A of silicon carbide semiconductor substrate 10.
- the gate electrode 17 is formed (step (S70)).
- a gate electrode 17 made of polysilicon, Al, or the like, which is a conductor extends from one n + source region 14 to the other n + source region 14 and is formed on the gate insulating film 15. Formed to contact.
- polysilicon is adopted as the material of the gate electrode 17, the polysilicon can be contained at a high concentration of P exceeding 1 ⁇ 10 20 cm ⁇ 3 .
- an insulating film made of, for example, SiO 2 is formed so as to cover gate electrode 17.
- an ohmic electrode is formed (step (S80)). Specifically, for example, a resist pattern having an opening that exposes part of p + region 18 and n + source region 14 is formed, and a metal film containing, for example, Si atoms, Ti atoms, and Al atoms Is formed on the entire surface of the substrate.
- the metal film to be an ohmic electrode is formed by, for example, a sputtering method or a vapor deposition method. Thereafter, the resist pattern is lifted off, for example, to form a metal film in contact with the gate insulating film 15 and in contact with the p + region 18 and the n + source region 14.
- the metal film is heated to about 1000 ° C., for example, to form source electrode 16 in ohmic contact with silicon carbide semiconductor substrate 10.
- drain electrode 19 that is in ohmic contact with base substrate 1 of silicon carbide semiconductor substrate 10 is formed.
- silicon carbide semiconductor device 100 as a MOSFET is completed.
- warpage of silicon carbide semiconductor substrate 10 is considered from the viewpoint of the risk of abnormality such as cracking of silicon carbide semiconductor substrate 10.
- the amount is preferably from ⁇ 1.5 mm to 1.5 mm, and more preferably from ⁇ 1.0 mm to 1.0 mm.
- Silicon carbide semiconductor substrate 10 according to the present embodiment has a warpage amount of ⁇ 1.5 mm or more and 1.5 mm or less even when the substrate temperature is heat-treated at a high temperature of about 100 ° C. or more and 500 ° C. or less.
- silicon carbide semiconductor substrate 10 has a warpage amount of ⁇ 1.5 mm or more and 1.5 mm or less even when the substrate temperature is heated to a high temperature of about 200 ° C. or more and 400 ° C. or less. Therefore, it is possible to reduce the risk of occurrence of abnormality such as cracking of silicon carbide semiconductor substrate 10 due to adsorption by the electrostatic chuck stage.
- the silicon carbide semiconductor substrate 10 has a warpage amount of ⁇ 1.0 mm when the substrate temperature is heated to a high temperature of about 100 ° C. to 500 ° C. It is also possible to suppress it to 1.0 mm or less. Therefore, the risk of occurrence of abnormality such as cracking of silicon carbide semiconductor substrate 10 due to adsorption by the electrostatic chuck stage can be further reduced. Further, in silicon carbide semiconductor substrate 10 in which the conditions such as the material and thickness of deformation suppressing layer 8 are optimized, the warp amount when the substrate temperature is heated to a high temperature of about 200 ° C. to 400 ° C. is ⁇ 1.0 mm. It can be suppressed to 1.0 mm or less. Therefore, the risk of occurrence of abnormality such as cracking of silicon carbide semiconductor substrate 10 due to adsorption by the electrostatic chuck stage can be further reduced.
- the method for manufacturing the silicon carbide semiconductor device according to the present embodiment uses silicon carbide semiconductor substrate 10 having high flatness and high parallelism of main surface 2A, in-plane main surface 2A of silicon carbide semiconductor substrate 10 is used.
- the risk associated with the occurrence of defects such as variations in processing quality can be reduced, and the silicon carbide semiconductor device 100 can be manufactured with high yield.
- silicon carbide semiconductor substrate 10 on which step (S40) is performed has a high flatness of main surface 2A.
- the ion implantation angle formed by the implantation direction 40i see FIG. 10
- the variation in the surface of the main surface 2A is kept low. Therefore, referring to FIG.
- impurity implanted region 30 (p body region 13, n source) formed by implanting impurities from the opening of mask film 20 formed on main surface 2A of silicon carbide semiconductor substrate 10. Regions 14 and the like are formed in the same manner in the central portion and the outer peripheral portion of silicon carbide semiconductor substrate 10. From a different point of view, impurity implantation region 30 in silicon carbide semiconductor device 100 has a side wall portion extending in a direction perpendicular to main surface 2A.
- impurity implantation region 30 (p body region 13, n source region 14, etc.) is formed in silicon carbide semiconductor substrate 10 at the center and the outer periphery of silicon carbide semiconductor substrate 10. The position of the area and the way it expands are different.
- impurity implantation region 30 in silicon carbide semiconductor device 100 has a different main surface 2A in the direction in which the side wall portion extends locally with respect to main surface 2A.
- the impurity implantation region 30 having a side wall portion extending perpendicularly to the main surface 2A can be formed. Therefore, there is no problem that the shape of impurity implantation region 30 (for example, the direction in which the side wall extends) differs locally on main surface 2A, so that silicon carbide semiconductor device 100 can be obtained with high yield.
- the silicon carbide semiconductor device according to the present embodiment may have a field stop region (not shown) so as to surround guard ring region 5.
- the field stop region has n-type conductivity, and may be formed by high-temperature implantation in the impurity implantation step (S40) in the same manner as the source region 14 and the like. Since the silicon carbide semiconductor device according to the present embodiment is manufactured using flat silicon carbide semiconductor substrate 10 even under a high temperature environment, the arrangement and form of guard ring region 5 and field stop region are also principal surface 2A. The occurrence of problems such as local fluctuations can be suppressed. Specifically, for example, it is possible to suppress a change in the distance between the guard ring region 5 and the field stop region in the main surface 2A.
- the present invention is particularly advantageously applied to a large-diameter silicon carbide semiconductor substrate having an outer diameter of 100 mm or more, a method for manufacturing the same, and a method for manufacturing a silicon carbide semiconductor device using the silicon carbide semiconductor substrate.
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Abstract
Description
はじめに、本発明の実施の形態の概要を列挙する。
次に、本発明の実施の形態の詳細について説明する。
図1を参照して、実施の形態1に係る炭化珪素半導体基板10について説明する。本実施の形態に係る炭化珪素半導体基板10は、ベース基板1と、ベース基板1の主面1A上に形成されたエピタキシャル層2と、ベース基板1の裏面1B上に形成された変形抑制層8とを備える。
Claims (10)
- 外径が100mm以上である主面を有し、単結晶炭化珪素からなるベース基板と、
前記主面上に形成されたエピタキシャル層と、
前記ベース基板において前記主面の反対側に位置する裏面上に形成された変形抑制層とを備える、炭化珪素半導体基板。 - 基板温度が室温であるときの反り量は-100μm以上100μm以下であり、基板温度が400℃であるときの反り量は-1.5mm以上1.5mm以下である、請求項1に記載の炭化珪素半導体基板。
- 前記変形抑制層の熱膨張係数は、単結晶炭化珪素の熱膨張係数の90%以下または110%以上である、請求項1または請求項2に記載の炭化珪素半導体基板。
- 前記変形抑制層の厚さは5μm以下である、請求項1~請求項3のいずれか1項に記載の炭化珪素半導体基板。
- 前記変形抑制層を構成する材料は、酸化珪素、炭素、アルミニウム、チタン、ニッケル、白金、および金からなる群から選択される少なくとも1つである、請求項1~請求項4のいずれか1項に記載の炭化珪素半導体基板。
- 外径が100mm以上である主面を有し、単結晶炭化珪素からなるベース基板を準備する工程と、
前記主面上にエピタキシャル層を形成する工程と、
前記ベース基板において前記主面の反対側に位置する裏面上に変形抑制層を形成する工程とを備える、炭化珪素半導体基板の製造方法。 - 前記変形抑制層を形成する工程において、前記エピタキシャル層を形成する工程後に前記ベース基板の前記主面が凹状に反るときには、単結晶炭化珪素の熱膨張係数と比べて小さい熱膨張係数を有する前記変形抑制層を形成し、前記エピタキシャル層を形成する工程後に前記ベース基板の前記主面が凸状に反るときには、単結晶炭化珪素の熱膨張係数と比べて大きい熱膨張係数を有する前記変形抑制層を形成する、請求項6に記載の炭化珪素半導体基板の製造方法。
- 前記変形抑制層を形成する工程において、単結晶炭化珪素の熱膨張係数と比べて小さい熱膨張係数を有する前記変形抑制層は酸化珪素および炭素の少なくともいずれか1つにより構成されており、単結晶炭化珪素の熱膨張係数と比べて大きい熱膨張係数を有する前記変形抑制層はアルミニウム、チタン、ニッケル、白金、および金からなる群から選択される少なくとも1つにより構成されている、請求項7に記載の炭化珪素半導体基板の製造方法。
- 前記変形抑制層を形成する工程は、熱膨張係数が単結晶炭化珪素の熱膨張係数の90%以下または110%以上である前記変形抑制層を形成する、請求項6~請求項8のいずれか1項に記載の炭化珪素半導体基板の製造方法。
- 外径が100mm以上である主面を有し、単結晶炭化珪素からなるベース基板を準備する工程と、
前記主面上にエピタキシャル層を形成する工程と、
前記ベース基板において前記主面の反対側に位置する裏面上に変形抑制層を形成して、炭化珪素半導体基板を準備する工程と、
前記炭化珪素半導体基板に不純物イオンを注入する工程とを備える、炭化珪素半導体装置の製造方法。
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DE112015003483T5 (de) * | 2014-07-30 | 2017-04-20 | Mitsubishi Electric Corporation | Halbleitervorrichtung-herstellungsverfahren und halbleitervorrichtung |
JP6348430B2 (ja) * | 2015-02-23 | 2018-06-27 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
JP6930640B2 (ja) * | 2017-03-08 | 2021-09-01 | 住友電気工業株式会社 | 炭化珪素単結晶基板、炭化珪素エピタキシャル基板および炭化珪素半導体装置の製造方法 |
DE102018111450B4 (de) | 2018-05-14 | 2024-06-20 | Infineon Technologies Ag | Verfahren zum Verarbeiten eines Breiter-Bandabstand-Halbleiterwafers, Verfahren zum Bilden einer Mehrzahl von dünnen Breiter-Bandabstand-Halbleiterwafern und Breiter-Bandabstand-Halbleiterwafer |
JP7259527B2 (ja) * | 2019-04-26 | 2023-04-18 | 富士電機株式会社 | 半導体基板の製造方法および半導体装置の製造方法 |
CN111883648B (zh) * | 2020-07-23 | 2021-05-25 | 中国科学院上海微系统与信息技术研究所 | 一种压电薄膜的制备方法、压电薄膜及带通滤波器 |
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JPH08321445A (ja) * | 1995-05-25 | 1996-12-03 | Sumitomo Electric Ind Ltd | マイクロデバイス基板およびマイクロデバイス基板の製造方法 |
JP2003218031A (ja) * | 2002-01-28 | 2003-07-31 | Toshiba Ceramics Co Ltd | 半導体ウェーハの製造方法 |
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US9818608B2 (en) | 2017-11-14 |
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