WO2015014030A1 - 显示装置 - Google Patents

显示装置 Download PDF

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Publication number
WO2015014030A1
WO2015014030A1 PCT/CN2013/085700 CN2013085700W WO2015014030A1 WO 2015014030 A1 WO2015014030 A1 WO 2015014030A1 CN 2013085700 W CN2013085700 W CN 2013085700W WO 2015014030 A1 WO2015014030 A1 WO 2015014030A1
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WO
WIPO (PCT)
Prior art keywords
gate
control lines
compensation unit
gate control
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2013/085700
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English (en)
French (fr)
Inventor
王峥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Display Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US14/389,138 priority Critical patent/US9773466B2/en
Publication of WO2015014030A1 publication Critical patent/WO2015014030A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display device. Background technique
  • a gate driver is usually integrated on an array substrate, and for a small display (generally a display of less than or equal to 19 inches), a structure of a single-sided integrated gate driver is generally adopted, that is, The gate driver is integrated only at one end of the gate control line of the array substrate.
  • a bilateral integrated gate driver structure is generally used, that is, a gate driver is integrated at both ends of the gate control line of the array substrate because the size of the large panel is large and the wiring is large.
  • the large panels of the prior art all adopt the design of a bilateral integrated gate driver, that is, the same gate driver is integrated at both ends of the gate control line.
  • the gate driver includes a plurality of gate drivers.
  • the input end of the gate driving unit 1 is connected to the gate timing signal lines Ck1, Ck2, Ck 3, and Ck4, respectively, and the output ends are respectively connected to the nl, n, n+1, n+2 row gate control lines.
  • Embodiments of the present invention provide a display device capable of reducing a gate drive footprint and reducing a product size.
  • the display device provided by the embodiment of the present invention includes a plurality of rows of gate control lines and a plurality of gate driving units, and further includes a plurality of compensation units, and any one of the compensation units is connected to the outputs of the two of the gate driving units, and Connect a row of gate control lines.
  • the compensation unit comprises a first thin film transistor and a second thin film crystal a source of the first thin film transistor and a source of the second thin film transistor are connected as a gate timing signal input terminal of the compensation unit; a drain of the first thin film transistor is connected to a drain of the second thin film transistor a driving output end of the compensation unit; a gate of the first thin film transistor as a first control end of the compensation unit; and a gate of the second thin film transistor as a second control end of the compensation unit.
  • the gate timing signal input end of the compensation unit is connected to a row of gate timing signal lines; the driving output end of the compensation unit is connected to a row of gate control lines, and the first control end of the compensation unit
  • the output terminals of one of the two gate drive units are connected to each other, and the second control end of the compensation unit is connected to the output of the other gate drive unit of the two gate drive units.
  • the gate driving unit and the compensation unit are both integrated on the array substrate of the display device.
  • the display device is a liquid crystal display.
  • the first row of gate control lines and the last row of gate control lines of the plurality of rows of gate control lines are connected to the gate driving unit at both ends; except the first row of gate control lines and the last row of gate control lines
  • one end of each of the other gate control lines is connected to the compensation unit, and the other end is connected to the gate driving unit, and the same end of the adjacent two rows of the gate control lines of the other rows of gate control lines are not gate driven at the same time.
  • Unit or compensation unit
  • the compensation unit connected to one end of any one of the other gate control lines is connected to the output end of the gate drive unit connected to the adjacent two rows of gate control lines, the compensation The unit drives the gate control line connected thereto according to the output of the gate driving unit connected to the two rows of gate control lines.
  • the left end of the odd row gate control line is connected to the gate driving unit, the right end is connected to the compensation unit, the left end of the even row gate control line is connected to the compensation unit, and the right end is connected to the gate driving unit.
  • the odd-numbered row gate control lines are connected to the gate driving unit at the right end, the left end is connected to the compensation unit, the even-numbered row gate control lines are connected to the compensation unit at the right end, and the left end is connected to the gate driving unit.
  • the display device of the embodiment of the invention adopts a conventional bilateral double gate driving single
  • the meta-structure becomes a new structure of a double-sided single-gate driving unit plus a compensation unit, which reduces the footprint of the gate drive and effectively reduces the size of the product.
  • FIG. 1 is a schematic structural view of a gate drive of the prior art
  • FIG. 2 is a schematic structural connection diagram of a compensation unit of a display device according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a display device according to an embodiment of the present invention.
  • FIG. 4 is a waveform diagram of a gate timing signal outputted by a gate timing signal line according to an embodiment of the present invention. detailed description
  • Ck l, Ck2, Ck 3 and Ck4 are gate timing signal lines of the display device, and 1 is a gate driving unit.
  • the display device provided by the embodiment of the present invention includes a gate control line and a plurality of gate driving units 1 , and further includes a plurality of compensation units 2 , and the compensation unit 2 is connected to the output ends of the two gate driving units 1 . And connecting the gate control line.
  • the compensation unit 2 drives the gate control line connected thereto according to an output signal of the two gate driving units 1 to shift and transmit a gate signal to the gate control line.
  • the compensation unit 2 includes a first thin film transistor T1 and a second thin film transistor T2; a source of the first thin film transistor T1 and a source of the second thin film transistor T2 are connected as a gate timing signal input end of the compensation unit 2; The drain of the first thin film transistor T1 and the drain of the second thin film transistor T2 are connected as a driving output end of the compensation unit 2; the gate of the first thin film transistor T1 is used as the compensation unit 2 a control terminal; a gate of the second thin film transistor T2 serves as a second control terminal of the compensation unit 2.
  • the gate timing signal input end of the compensation unit 2 is connected to the gate timing signal line; the driving output end of the compensation unit 2 is connected to the gate control line, and the first control end of the compensation unit 2 An output end of one of the gate driving units 1 of the two gate driving units 1 is connected, and a second control end of the compensation unit 2 and another gate driving unit 1 of the two gate driving units 1 The outputs are connected.
  • the source and drain of the thin film transistor used herein are symmetrical, the source and the drain are interchangeable.
  • one of the poles is referred to as a source and the other pole is referred to as a drain. If the source is selected as the signal input, the drain acts as the signal output and vice versa.
  • the gate driving unit 1 and the compensation unit 2 are integrated on the array substrate of the display device, and in this case, the size of the array substrate can also be effectively reduced.
  • the display device can be a liquid crystal display or other display device.
  • the display device includes a plurality of rows of the gate control lines, and the first row of gate control of the plurality of rows of gate control lines of the display device
  • the line and the last row of gate control lines are connected to the gate driving unit 1 at both ends; except for the first row of gate control lines and the last row of gate control lines, one end of each of the other rows of gate control lines is connected to the compensation unit 2, and the other end is connected Connecting the gate driving unit 1 , and the same ends of the adjacent two rows of the gate control lines of the other rows of gate control lines are not the gate driving unit 1 or the compensation unit 2, that is, the other rows of gates are controlled.
  • the gate driving unit 1 and the compensation unit 2 are alternately arranged at the same end of the line.
  • the odd-numbered row gate control lines are connected to the gate driving unit 1 at the left end
  • the compensation unit 2 is connected to the right end
  • the compensation unit 2 is connected to the left end of the even-numbered row gate control lines
  • the gate driving unit is connected to the right end.
  • the odd-line gate control line is connected to the gate driving unit 1 at the right end
  • the compensation unit 2 is connected to the left end
  • the compensation unit 2 is connected to the right end of the even-line gate control line
  • the gate is connected to the left end.
  • Drive unit 1 is connected to the odd-line gate control lines
  • the other rows of gate control lines are
  • the compensation unit 2 connected to one end of any one row of gate control lines is connected to the output end of the gate driving unit 1 connected to the two rows of gate control lines, and the compensation unit 2 is connected according to the gates of the two rows of gate control lines.
  • the output of the pole drive unit 1 drives the gate control line connected thereto.
  • the display device of this embodiment includes six rows of gate control lines, wherein L1 - L6 represent gate lines of the first row to the sixth row, respectively, and Ck l-Ck4 respectively represent four gate timing signals.
  • the gate timing signal waveforms of the line, gate timing signal lines Ck1, Ck2, Ck 3, and Ck4 are as shown in FIG.
  • the gate control unit 1 is connected to both the first row gate control line and the sixth row gate control line of the 6-row gate control line; except for the first row gate control line and the sixth row gate control line
  • the other gates ie, L2-L5 rows
  • the other phases ie, L2-L5 rows
  • the same end of the adjacent two rows of gate control lines is not the gate driving unit 1 or the compensation unit 2 at the same time.
  • the compensation unit 2 connected to one end of the gate control line of any one of the other rows is connected to the output end of the gate drive unit 1 connected to the front and rear rows of gate control lines,
  • the compensation unit 2 drives the gate control line connected thereto according to the output of the gate driving unit 1 connected to the two rows of gate control lines.
  • the compensation unit 2 includes a first thin film transistor T1 and a second thin film transistor
  • the source of the first thin film transistor T1 and the source of the second thin film transistor T2 are connected as a gate timing signal input terminal of the compensation unit 2; the drain of the first thin film transistor T1 and the second thin film transistor T2; The drain of the first thin film transistor T1 serves as the first control terminal of the compensation unit 2; the gate of the second thin film transistor T2 serves as the second of the compensation unit 2; Control terminal.
  • the gate timing signal input end of the compensation unit 2 is connected to the gate timing signal line; the driving output end of the compensation unit 2 is connected to the gate control line, and the first control end of the compensation unit 2 An output end of one of the gate driving units 1 of the two gate driving units 1 is connected, and a second control end of the compensation unit 2 and another gate driving unit 1 of the two gate driving units 1 Output Connected.
  • the compensation unit 2 at the left end of the L2 line is taken as an example to illustrate the working principle of the compensation unit 2.
  • the gate timing signal input line of the compensation unit 2 is connected to the gate timing signal line of the second row.
  • the driving output end is connected to the gate control line of the second row
  • the first control end is connected to the output end of the gate driving unit 1 at the left end of the first row
  • the second control end is connected to the gate driving unit 1 of the left end of the third row
  • the gate driving unit 1 at the left end of the first row and the gate driving unit 1 at the left end of the third row can alternately control the turn-on of T1 and T2, so that Ck2 is connected to the gate control line of the second row, thereby driving the first 2 rows of gate control lines.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示装置包括栅极控制线和多个栅极驱动单元，还包括多个补偿单元（2）。该补偿单元（2）与两个所述栅极驱动单元（1）的输出端相连，且连接所述栅极控制线。该显示装置，通过将传统的双边双栅极驱动单元结构变为新的双边单栅极驱动单元（1）加补偿单元（2）的结构，减少栅极驱动器的占用空间，降低了显示装置的产品尺寸。

Description

显示装置 技术领域
本发明涉及显示技术领域， 尤其涉及一种显示装置。 背景技术
现有的液晶显示器等显示装置的设计中， 通常在阵列基板上 集成栅极驱动器， 对于小型显示器 （一般指小于或等于 19英寸的 显示器）， 通常会采用单边集成栅极驱动器的结构， 即只在阵列基 板的栅极控制线一端集成栅极驱动器。 而对于大型显示器 （一般 指大于 19英寸的显示器）， 通常采用双边集成栅极驱动器的结构， 即在阵列基板的栅极控制线两端均集成栅极驱动器， 原因是大型 面板的尺寸大， 布线长度长， 分辨率高， 所带来的大负载 （包括 大电阻和大的寄生电容）会让栅信号产生延迟， 而栅信号延迟后 会对像素充电带来充电不足， 以及画面均匀性等不良影响。 因此 现有技术的大型面板均采用双边集成栅极驱动器的设计， 即在栅 极控制线两端集成完全相同的栅极驱动器， 如图 1所示，所述栅极 驱动器包括多个栅极驱动单元 1 ,所述栅极驱动单元 1的输入端分 别连接栅极时序信号线 Ckl、 Ck2、 Ck 3、 Ck4 , 输出端分别连接第 n-l、 n、 n+l、 n+2行栅极控制线， 其作用是分别用来驱动第 n-1、 n、 n+l、 n+2行栅极控制线。 然而， 此种设计会造成栅极驱动器占 用较大空间， 使得液晶面板的边框需要更多空间， 影响产品尺寸。 发明内容
本发明的实施例提供一种能够减少栅极驱动占用空间， 降低 产品尺寸的显示装置。
本发明的实施例提供的显示装置包括多行栅极控制线和多个 栅极驱动单元， 还包括多个补偿单元， 任一个补偿单元与两个所 述栅极驱动单元的输出端相连， 且连接一行栅极控制线。
优选地， 所述补偿单元包括第一薄膜晶体管和第二薄膜晶体 管； 所述第一薄膜晶体管的源极和第二薄膜晶体管的源极相连作 为补偿单元的栅极时序信号输入端； 所述第一薄膜晶体管的漏极 和第二薄膜晶体管的漏极相连作为补偿单元的驱动输出端； 所述 第一薄膜晶体管的栅极作为补偿单元的第一控制端； 所述第二薄 膜晶体管的栅极作为补偿单元的第二控制端。
优选地， 所述补偿单元的栅极时序信号输入端与一行栅极时 序信号线相连； 所述补偿单元的驱动输出端与一行栅极控制线相 连， 所述补偿单元的第一控制端与所述两个栅极驱动单元的其中 一个栅极驱动单元的输出端相连， 所述补偿单元的第二控制端与 所述两个栅极驱动单元的另一个栅极驱动单元的输出端相连。
优选地， 所述栅极驱动单元和补偿单元均集成在所述显示装 置的阵列基板上。
优选地， 所述显示装置为液晶显示器。
优选地， 所述多行栅极控制线的第一行栅极控制线和最后一 行栅极控制线两端均连接栅极驱动单元； 除第一行栅极控制线和 最后一行栅极控制线外， 其他各行栅极控制线的一端连接补偿单 元， 另一端连接栅极驱动单元， 且所述其他各行栅极控制线中的 相邻两行栅极控制线的同一端不同时为栅极驱动单元或补偿单 元。
优选地， 所述其他各行栅极控制线中任意一行栅极控制线一 端连接的补偿单元和与之相邻的前后两行栅极控制线连接的栅极 驱动单元的输出端相连， 所述补偿单元根据所述前后两行栅极控 制线连接的栅极驱动单元的输出， 驱动与其相连的栅极控制线。
优选地， 所述其他各行栅极控制线中， 奇数行栅极控制线左 端连接栅极驱动单元， 右端连接补偿单元， 偶数行栅极控制线左 端连接补偿单元， 右端连接栅极驱动单元。
优选地， 所述其他各行栅极控制线中， 奇数行栅极控制线右 端连接栅极驱动单元， 左端连接补偿单元， 偶数行栅极控制线右 端连接补偿单元， 左端连接栅极驱动单元。
本发明实施例的显示装置， 通过将传统的双边双栅极驱动单 元结构变为新的双边单栅极驱动单元加补偿单元的结构， 减少栅 极驱动的占用空间， 有效降低产品尺寸。 附图说明
图 1为现有技术的栅极驱动的结构示意图；
图 2为本发明实施例的显示装置的补偿单元的结构连接示意 图；
图 3为本发明实施例的显示装置的结构示意图；
图 4为本发明实施例的栅极时序信号线输出的栅极时序信号 波形图。 具体实施方式
下面结合附图及实施例对本发明进行详细说明如下。
需要说明的是， 在本发明实施例的描述中， "上" "下" "左" "右" 等指示的方位或位置关系为基于附图所示的方位或位置关 系， 仅是为了便于描述本发明实施例的筒化描述， 并非指示或暗 示所述的装置或元件必须有特定的方位， 因此不能理解为对本发 明的限制。
如图 2所示， Ck l、 Ck2、 Ck 3和 Ck4为显示装置的栅极时序信 号线， 1为栅极驱动单元。 本发明实施例提出的显示装置包括栅极 控制线和多个栅极驱动单元 1 , 还包括多个补偿单元 2 , 所述补偿 单元 2与两个所述栅极驱动单元 1的输出端相连， 且连接所述栅 极控制线。 所述补偿单元 2根据所述两个栅极驱动单元 1的输出 信号， 驱动与其相连的所述栅极控制线， 用以移位并传输栅信号 至所述栅极控制线。
所述补偿单元 2包括第一薄膜晶体管 T1和第二薄膜晶体管 T2 ; 所述第一薄膜晶体管 T1的源极和第二薄膜晶体管 T2的源极 相连作为补偿单元 2的栅极时序信号输入端； 所述第一薄膜晶体 管 T1的漏极和第二薄膜晶体管 T2的漏极相连作为补偿单元 2的 驱动输出端； 所述第一薄膜晶体管 T1的栅极作为补偿单元 2的第 一控制端； 所述第二薄膜晶体管 T2的栅极作为补偿单元 2的第二 控制端。 所述补偿单元 2的栅极时序信号输入端与栅极时序信号 线相连； 所述补偿单元 2的驱动输出端与所述栅极控制线相连， 所述补偿单元 2的第一控制端与所述两个栅极驱动单元 1的其中 一个栅极驱动单元 1的输出端相连， 所述补偿单元 2的第二控制 端与所述两个栅极驱动单元 1的另一个栅极驱动单元 1的输出端 相连。
应当说明的是， 由于这里采用的薄膜晶体管的源极、 漏极是 对称的， 所以其源极、 漏极是可以互换的。 在本发明实施例中， 为区分晶体管除栅极之外的两极， 将其中一极称为源极， 另一极 称为漏极。 若选取源极作为信号输入端、 则漏极作为信号输出端， 反之亦然。
一般情况下， 所述栅极驱动单元 1和补偿单元 2均集成在所 述显示装置的阵列基板上， 此种情况下同样可以有效减小阵列基 板的尺寸。
所述显示装置可以为液晶显示器或其他显示装置。
由于补偿单元 2需要连接两个栅极驱动单元 1才能工作， 因 此， 在实践中， 显示装置包括多行所述栅极控制线， 显示装置的 多行栅极控制线的第一行栅极控制线和最后一行栅极控制线两端 均连接栅极驱动单元 1 ; 除第一行栅极控制线和最后一行栅极控制 线外， 其他各行栅极控制线的一端连接补偿单元 2 , 另一端连接栅 极驱动单元 1 ,且所述其他各行栅极控制线中的相邻两行栅极控制 线的同一端不同时为栅极驱动单元 1或补偿单元 2 , 即所述其他各 行栅极控制线同一端中栅极驱动单元 1和补偿单元 2交替设置。 例如， 所述其他各行栅极控制线中， 奇数行栅极控制线左端连接 栅极驱动单元 1 , 右端连接补偿单元 2 , 偶数行栅极控制线左端连 接补偿单元 2 , 右端连接栅极驱动单元 1 ; 或者在所述其他各行栅 极控制线中， 奇数行栅极控制线右端连接栅极驱动单元 1 , 左端连 接补偿单元 2 , 偶数行栅极控制线右端连接补偿单元 2 , 左端连接 栅极驱动单元 1。 在上述技术方案中， 所述其他各行栅极控制线中 任意一行栅极控制线一端连接的补偿单元 2与前后两行栅极控制 线连接的栅极驱动单元 1的输出端相连， 所述补偿单元 2根据所 述前后两行栅极控制线连接的栅极驱动单元 1的输出， 驱动与其 相连的栅极控制线。
为了更好地理解本发明实施例， 下面进一步通过一个实施例 来说明本发明实施例的显示装置的具体结构及工作原理。
如图 3所示， 本实施例的显示装置包括 6行栅极控制线， 其 中 L1 -L6分别代表第 1行至第 6行栅极控制线， Ck l-Ck4分别代 表 4条栅极时序信号线， 栅极时序信号线 Ckl、 Ck2、 Ck 3、 Ck4 的栅极时序信号波形如图 4所示。 所述 6行栅极控制线的第 1行 栅极控制线和第 6行栅极控制线两端均连接栅极驱动单元 1 ; 除第 1行栅极控制线和第 6行栅极控制线外， 其他各行（即 L2-L5行） 栅极控制线的一端连接补偿单元 2 , 另一端连接栅极驱动单元 1 , 且所述其他各行（即 L2-L5行）栅极控制线中的相邻两行栅极控 制线的同一端不同时为栅极驱动单元 1或补偿单元 2。所述其他各 行（即 L2-L5行）栅极控制线中任意一行栅极控制线一端连接的 补偿单元 2与前后两行栅极控制线连接的栅极驱动单元 1的输出 端相连， 所述补偿单元 2根据所述前后两行栅极控制线连接的栅 极驱动单元 1的输出， 驱动与其相连的栅极控制线。
所述补偿单元 2包括第一薄膜晶体管 T1和第二薄膜晶体管
T2 ; 所述第一薄膜晶体管 T1的源极和第二薄膜晶体管 T2的源极 相连作为补偿单元 2的栅极时序信号输入端； 所述第一薄膜晶体 管 T1的漏极和第二薄膜晶体管 T2的漏极相连作为补偿单元 2的 驱动输出端； 所述第一薄膜晶体管 T1的栅极作为补偿单元 2的第 一控制端； 所述第二薄膜晶体管 T2的栅极作为补偿单元 2的第二 控制端。 所述补偿单元 2的栅极时序信号输入端与栅极时序信号 线相连； 所述补偿单元 2的驱动输出端与所述栅极控制线相连， 所述补偿单元 2的第一控制端与所述两个栅极驱动单元 1的其中 一个栅极驱动单元 1的输出端相连， 所述补偿单元 2的第二控制 端与所述两个栅极驱动单元 1的另一个栅极驱动单元 1的输出端 相连。
现以 L2行左端的补偿单元 2为例来说明补偿单元 2的工作原 理， 如图 3和图 4所示， 由于补偿单元 2的栅极时序信号输入端 连接第 2行的栅极时序信号线 Ck2 ,驱动输出端连接第 2行的栅极 控制线， 第一控制端连接第 1行左端的栅极驱动单元 1的输出端， 第二控制端连接第 3行左端的栅极驱动单元 1的输出端，所述第 1 行左端的栅极驱动单元 1和第 3行左端的栅极驱动单元 1可以交 替控制 T1和 T2的开通， 使得 Ck2与第 2行栅极控制线相连， 从 而驱动第 2行栅极控制线。
在上述实施方式中， 通过将传统的双边双栅极驱动单元 1结 构变为新的双边单栅极驱动单元 1加补偿单元 2的结构， 极大地 减少了栅极驱动的占用空间， 有效地降低了显示装置的产品尺寸。
以上实施方式仅用于说明本发明的实施例， 而并非对本发明 的限制， 有关技术领域的普通技术人员， 在不脱离本发明的精神 和范围的情况下， 还可以做出各种变化和变型， 因此所有等同的 技术方案也属于本发明的范畴， 本发明的专利保护范围应由权利 要求限定。

Claims

权 利 要 求 书
1、 一种显示装置， 包括多行栅极控制线和多个栅极驱动单元， 该显示装置还包括多个补偿单元，任一个补偿单元与两个栅极驱动单 元的输出端相连， 且连接一行栅极控制线。
2、 如权利要求 1所述的显示装置， 其中， 所述补偿单元包括第 一薄膜晶体管和第二薄膜晶体管；所述第一薄膜晶体管的源极和第二 薄膜晶体管的源极相连作为补偿单元的栅极时序信号输入端；所述第 一薄膜晶体管的漏极和第二薄膜晶体管的漏极相连作为补偿单元的 驱动输出端； 所述第一薄膜晶体管的栅极作为补偿单元的第一控制 端； 所述第二薄膜晶体管的栅极作为补偿单元的第二控制端。
3、 如权利要求 2所述的显示装置， 其中， 所述补偿单元的栅极 时序信号输入端与一行栅极时序信号线相连；所述补偿单元的驱动输 出端与一行栅极控制线相连，所述补偿单元的第一控制端与所述两个 栅极驱动单元的其中一个栅极驱动单元的输出端相连，所述补偿单元 的第二控制端与所述两个栅极驱动单元的另一个栅极驱动单元的输 出端相连。
4、 如权利要求 1-3任一项所述的显示装置， 其中， 所述栅极驱 动单元和补偿单元均集成在所述显示装置的阵列基板上。
5、 如权利要求 1-4任一项所述的显示装置， 其中， 所述显示装 置为液晶显示器。
6、 如权利要求 1-5任一权利要求所述的显示装置， 其中， 所述 多行栅极控制线的第一行栅极控制线和最后一行栅极控制线两端均 连接栅极驱动单元； 除第一行栅极控制线和最后一行栅极控制线外， 其他各行栅极控制线的一端连接补偿单元， 另一端连接栅极驱动单 元，且所述其他各行栅极控制线中的相邻两行栅极控制线的同一端不 同时为栅极驱动单元或补偿单元。
7、 如权利要求 6所述的显示装置， 其中， 所述其他各行栅极控 制线中任意一行栅极控制线一端连接的补偿单元和与之相邻的前后 两行栅极控制线连接的栅极驱动单元的输出端相连，所述补偿单元根 据所述前后两行栅极控制线连接的栅极驱动单元的输出，驱动与其相 连的栅极控制线。
8、 如权利要求 6-7任一项所述的显示装置， 其中， 所述其他各 行栅极控制线中， 奇数行栅极控制线左端连接栅极驱动单元， 右端连 接补偿单元， 偶数行栅极控制线左端连接补偿单元， 右端连接栅极驱 动单元。
9、 如权利要求 6-7任一项所述的显示装置， 其中， 所述其他各 行栅极控制线中， 奇数行栅极控制线右端连接栅极驱动单元， 左端连 接补偿单元， 偶数行栅极控制线右端连接补偿单元， 左端连接栅极驱 动单元。
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CN101727859A (zh) * 2008-10-15 2010-06-09 北京京东方光电科技有限公司 液晶显示器栅极驱动装置

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US9564454B2 (en) * 2013-10-07 2017-02-07 Shanghai Tianma Micro-electronics Co., Ltd. TFT array substrate, display panel and display device

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