WO2015010431A1 - 一种阵列基板及其制作方法、显示装置 - Google Patents

一种阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2015010431A1
WO2015010431A1 PCT/CN2013/089974 CN2013089974W WO2015010431A1 WO 2015010431 A1 WO2015010431 A1 WO 2015010431A1 CN 2013089974 W CN2013089974 W CN 2013089974W WO 2015010431 A1 WO2015010431 A1 WO 2015010431A1
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Prior art keywords
gate
partial region
metal layer
source
area
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PCT/CN2013/089974
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English (en)
French (fr)
Inventor
姜清华
李小和
刘永
邵贤杰
李红敏
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合肥京东方光电科技有限公司
京东方科技集团股份有限公司
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Priority to US14/361,883 priority Critical patent/US9219082B2/en
Publication of WO2015010431A1 publication Critical patent/WO2015010431A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • a Thin-Film Transistor Liquid Crystal Display includes a color filter substrate, an array substrate, and a liquid crystal layer between the color filter substrate and the array substrate.
  • the array substrate includes a transparent substrate, and a plurality of mutually parallel gate lines located inside the transparent substrate and a plurality of data lines vertically intersecting and electrically insulated from the gate lines, wherein the plurality of gate lines and the plurality of lines The data line defines a plurality of pixel units.
  • Each of the pixel units includes a pixel electrode, a storage capacitor (Cs), a liquid crystal capacitor (Clc), and a thin film transistor (TFT) as a switching device.
  • Cs and Ck are connected in parallel to the pixel electrode, and the pixel electrode is connected to the TFT.
  • the TFT 10 of the pixel unit includes a source 11 , a gate 12 , and a drain 13 .
  • the source 11 is electrically connected to the pixel electrode 20 , and the gate 12 and the gate line 30 .
  • the drain 13 is connected to the data line 40, the gate line 30 and the gate 12 are located in the first metal layer, the data line 40, the drain 13 and the source 11 are located in the second metal layer, and the source is II overlaps the gate 12.
  • the source overlaps the gate, thereby forming a parasitic capacitance (Cgs) between the source and the gate, wherein the size of Cgs is related to the overlap area of the source and the gate.
  • Cgs parasitic capacitance
  • a voltage jump variable Cgs_Cs + Ck - on the pixel electrode wherein A Vg is the difference between the turn-on voltage and the turn-off voltage applied on the gate.
  • a misalignment occurs, which causes a change in the overlap area between the source and the gate of the pixel unit. If the amount of misalignment between the first metal layer and the second metal layer of the adjacent pixel unit is different, the amount of change in the overlapping area between the source and the gate of the adjacent pixel unit is different, thereby causing adjacent pixels.
  • the amount of change in the parasitic capacitance Cgs of the cell is different, and the parasitic capacitance Cgs of the adjacent pixel unit is different after the misalignment occurs between the first metal layer and the second metal layer (the parasitic capacitance Cgs of the adjacent pixel unit is in the first metal)
  • the layer is identical to the second metal layer before the misalignment occurs. If the parasitic capacitance Cgs of the adjacent pixel units are different, the voltage jump variables on the pixel electrodes of the adjacent pixel units are different, so that the gray scales of the adjacent pixels are not uniform, thereby causing poor picture quality, for example, Flicker appears. ) and Mura (uneven grayscale of the screen).
  • the current TFT CD has a problem of poor picture quality when the amount of misalignment between the first metal layer and the second metal layer of the adjacent pixel unit is different.
  • the embodiment of the present invention provides an array substrate, a manufacturing method thereof, and a display device, which are used to solve the problem that the amount of misalignment between the first metal layer and the second metal layer of the adjacent pixel unit is different when the TFTXCD existing in the prior art is different. There will be problems with poor picture quality.
  • an array substrate including a thin film transistor TFT, the TFT includes a source, a gate, and a drain, the gate is located at a first metal layer, the source and The drain is located in the second metal layer, wherein
  • the shape of the source and the gate are satisfied: in a case where a misalignment occurs between the first metal layer and the second metal layer, an overlapping area of the source and the gate is constant.
  • the overlapping area of the source and the gate of the pixel unit is constant, and thus each The overlapping area of the source and the gate of each pixel unit is the same (the amount of change is 0), thereby ensuring the source of the adjacent pixel unit after the misalignment occurs between the first metal layer and the second metal layer.
  • the overlap area of the gate and the gate are the same, and the parasitic capacitance Cgs of the adjacent pixel unit is the same, thereby achieving a certain degree of uniformity of the gray level of the adjacent pixels, and avoiding or reducing the problem of poor picture quality.
  • the source includes an overlapping region with the gate and a direction parallel to the gate line a first partial region and a second partial region respectively located on both sides of the gate;
  • the increase/decrease bottom area of the first partial region is equal to the decrease/enhancement area of the second partial region.
  • the source and the gate are ensured.
  • the overlap area is constant.
  • the pattern of the first partial region, the second partial region, and the overlapping region with the gate includes a U-shaped pattern in which the opening faces in a direction parallel to the gate line and a closure with the " ⁇ -shaped pattern" Connected to the horizontally placed " ⁇ "-shaped pattern;
  • first partial region is located at a position where the one side of the "U” shape extends out of the gate, or at a position where the two sides of the "U” shape extend out of the gate
  • second partial region is located at a position where the "L"-shaped pattern extends out of the gate.
  • the pattern of the first partial region, the second partial region and the overlapping region with the gate is a pattern resembling a "shi" shape
  • first partial region is located at a position where the first side and/or the second side of the "shi"-shaped pattern extends out of the gate in a first direction parallel to the gate line;
  • the second partial region is located at a position where the first side and/or the second side of the "shi"-shaped pattern extends out of the gate in a second direction opposite to the first direction, the first side Parallel to the second side.
  • the specific structure of the source included in the TFT is provided, so that the technical solution of the present invention can be easily implemented by those skilled in the art. It should be noted that the specific source structures in the embodiments of the present invention are only used to explain the present invention, and are not intended to limit the present invention. Other structures that can be used to implement the technical solutions of the present invention are also within the protection scope of the present invention. Inside.
  • the array substrate further includes a data line connected to the drain, and a minimum distance value between the first partial area and the second partial area and the data line is not less than a set value, for example , 5 ⁇ - 10 ⁇ .
  • the gate includes a first partial region and a second partial region separated from each other, the source includes a third partial region overlapping the first partial region and overlapping with the second partial region Part IV area;
  • the increase/decrease bottom area of the third partial region is equal to the decrease/enhancement bottom area of the fourth partial region.
  • the source and the gate are ensured.
  • the overlap area of the poles is constant.
  • the pattern of the source is a T-like pattern composed of the third partial region, the fourth partial region, and a region between the first partial region and the second partial region;
  • the third partial region is located at a position where the inverted "T" shape overlaps the first partial region in a first direction parallel to the gate line, and the fourth partial region is located at the inverted "T"
  • the glyph is at a position overlapping the second partial region in a second direction opposite to the first direction.
  • a display device comprising the array substrate.
  • the display device since the array substrate included in the display device can ensure the gray level of adjacent pixels to a certain extent, the display device can avoid or reduce the occurrence of poor picture quality to some extent.
  • a method for fabricating the array substrate including:
  • An active layer and a source and a drain on the active layer are sequentially formed on the gate insulating layer, wherein the source and the drain are located in the second metal layer; Wherein, in a case where a misalignment occurs between the first metal layer and the second metal layer, an overlapping area of the source and the gate is constant.
  • the overlapping area of the source and the gate of the pixel unit is constant, and thus each pixel
  • the amount of change in the overlap area between the source and the gate of the cell is the same (the amount of change is 0), which can ensure that the gray level of adjacent pixels is uniform to a certain extent, and the problem of poor picture quality is avoided or reduced.
  • the solution of the embodiment of the present invention is such that when a misalignment occurs between the first metal layer and the second metal layer, even if the first metal layer and the second metal layer of the adjacent pixel unit
  • the amount of misalignment generated is different, and the overlapping area of the gate and the source of the adjacent pixel unit can be the same, so that the parasitic capacitance Cgs of the adjacent pixel unit is the same, thereby ensuring the voltage jump variable on the pixel electrode of the adjacent pixel unit.
  • the gray scale of adjacent pixels is uniform, and thus the problem of poor picture quality such as Flicker and Mura is avoided or reduced to some extent.
  • FIG. 1 is a schematic structural view of a pixel unit in the prior art
  • FIG. 2 is a schematic view showing a first structure of a pixel unit included in an array substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic view showing a second structure of a pixel unit included in an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a schematic view showing a third structure of a pixel unit included in the array substrate of the embodiment of the present invention.
  • FIG. 5 is a fourth structural diagram of a pixel unit included in an array substrate according to an embodiment of the present invention.
  • FIG. 6 is a fifth structural diagram of a pixel unit included in an array substrate according to an embodiment of the present invention.
  • a sixth structural diagram of a pixel unit included in the array substrate of the embodiment of the present invention is shown.
  • FIG. 8 is a schematic flow chart of a method for fabricating an array substrate according to the embodiment
  • 9A-9H are structural diagrams of pixel units included in an array substrate during fabrication of an array substrate according to an embodiment of the invention.
  • An array substrate includes a TFT, the TFT includes a source, a gate and a drain, the gate is located at the first metal layer, the source and the drain are located at the second metal layer, and the first metal layer and the first metal layer In the case where a misalignment occurs between the two metal layers, the overlap area of the source and the gate is constant.
  • the overlapping area of the source and the gate of the adjacent pixel unit is the same before the misalignment occurs between the first metal layer and the second metal layer, after the misalignment occurs between the first metal layer and the second metal layer, The amount of change in the overlapping area of the source and the gate of the adjacent pixel unit is different, and the overlapping area of the source and the gate of the adjacent pixel unit after the misalignment between the first metal layer and the second metal layer is recognized different.
  • the structure of the array substrate according to the embodiment of the present invention can ensure that the overlapping area of the source and the gate is constant in the case where a misalignment occurs between the first metal layer and the second metal layer, that is, according to the present invention
  • the array substrate of the embodiment can ensure that after the dislocation between the first metal layer and the second metal layer, the overlapping area of the source and the gate of the adjacent pixel unit is the same, so that the first metal layer and the second layer After the misalignment between the metal layers, the overlapping areas of the source and the gate of the adjacent pixel unit are the same, thereby ensuring that the gray level of the adjacent pixels is uniform to a certain extent, and the problem of poor picture quality is avoided or reduced.
  • An embodiment of the present invention provides an array substrate, including a TFT, the TFT includes a source, a gate, and a drain, the gate is located in the first metal layer, and the source and the drain are located in the second metal layer, where
  • the shape of the source and the gate are satisfied: in the case where a misalignment occurs between the first metal layer and the second metal layer, the overlapping area of the source and the gate is constant.
  • the array substrate includes a plurality of pixel units, each of the pixel units includes one TFT, and the implementation manner of the TFT in each pixel unit included in the array substrate provided by the embodiment of the present invention is described.
  • the embodiment of the present invention will be described below by taking an embodiment of a pixel unit included in the array substrate of the embodiment of the present invention as an example.
  • the pixel unit of the array substrate provided by the embodiment of the invention includes a TFT
  • the TFT includes a source, a gate and a drain
  • the gate is located in the first metal layer
  • the source and the drain are located in the second metal layer. among them,
  • the shape of the source and the gate are satisfied: in the case where a misalignment occurs between the first metal layer and the second metal layer, the overlapping area of the source and the gate is constant.
  • the gate is the bottom gate as an example.
  • the implementation of other types of gates eg., top gates, etc.
  • the implementation of the bottom gate is similar and will not be described here.
  • the amount of misalignment generated between the first metal layer and the second metal layer due to natural factors such as process instability is generally small, that is, within a preset misalignment amount ranging from ⁇ 2 ⁇ m to ⁇ 5 ⁇ m ⁇ .
  • the lower limit value of the preset misalignment amount range may be 0, that is, no misalignment occurs between the first metal layer and the second metal layer.
  • the source and/or the gate need to be improved.
  • the source and/or the gate need to be improved. The following will be introduced separately.
  • the overlap area of the source and the gate is constant when the source is misaligned between the first metal layer and the second metal layer.
  • the source (or the lateral cross-sectional pattern of the source) includes an overlap region with the gate (or a lateral cross-sectional pattern of the gate) and a gate at a direction parallel to the gate line (or , a transverse cross-sectional pattern of the gate) a first partial region and a second partial region on both sides;
  • the increased bottom area (or the reduced/increased area) of the first partial region and the reduced/increased bottom area of the second partial region is equal.
  • the source and drain of the thin film transistor (TFT) of the array substrate (pixel unit) of the embodiment of the present invention are the same, and the names can be interchanged; the drain connected to the data line can be connected to the pixel electrode. As the source; vice versa.
  • the array substrate (pixel unit) of the embodiment of the present invention further includes a gate line vertically connected to the gate, and a data line vertically connected to the drain, and a direction parallel to the gate line is a horizontal direction and a direction parallel to the data line. It is in the vertical direction.
  • the direction parallel to the gate line 30 is water.
  • the direction parallel to the data line 40 is a vertical direction.
  • the bottom area (or area) of the first partial region on the side of the gate (or the lateral cross-sectional pattern of the gate) according to the embodiment of the present invention is opposite to the gate (or the lateral cross-sectional pattern of the gate) The misalignment occurs between the first metal layer and the second metal layer.
  • the bottom portion area of the first partial region (opposite gate) on the gate side is A, between the first metal layer and the second metal layer.
  • the bottom area of the first partial region (relative to the gate) on the side of the gate changes to B.
  • the embodiment of the second partial region on the other side of the gate (or the lateral cross-sectional pattern of the gate) according to an embodiment of the present invention is similar to the embodiment of the first partial region according to the embodiment of the present invention, This will not be repeated here.
  • the first partial region and the second partial region are regions respectively located on opposite sides of the gate in a direction parallel to the gate line, and a misalignment occurs between the first metal layer and the second metal layer.
  • the increase/decrease bottom area of the first partial region is equal to the decrease/enhancement bottom area of the second partial region, thereby ensuring a constant area of the overlap region of the source and the gate, ensuring the source and the gate.
  • the overlap area is constant.
  • the area of the first portion region is increased (reduced), that is, the source and the gate
  • the parasitic capacitance Cgs between them is reduced (increased), and accordingly, the area of the second partial region is reduced (increased), that is, the parasitic capacitance Cgs between the source and the gate is increased (reduced). Since the increase/decrease area of the first partial region can be compensated by the reduced/increased area of the second partial region, the total parasitic capacitance Cgs between the source and the gate is ensured to be constant, avoiding the occurrence of Flkker and Miira.
  • the second metal layer is misaligned (ie, dislocated in the vertical direction) with respect to the first metal layer, due to the source (or the lateral cross-sectional pattern of the source) and the gate (or, the lateral direction of the gate)
  • the overlap between the overlap region of the cross-sectional pattern and the edge of the gate (or the lateral cross-sectional pattern of the gate) is relatively large, so that the overlap area of the source and the gate is not affected.
  • the offset of the angle may be decomposed into a misalignment in a direction parallel to the gate line and a misalignment in a direction perpendicular to the gate line, and parallel to the gate line.
  • Embodiments in which the misalignment in the direction and the misalignment in the direction perpendicular to the gate line are similar to the above-described embodiment in which the misalignment in the direction parallel to the gate line and the misalignment in the direction perpendicular to the gate line are This will not be repeated here.
  • the shape of the overlapping region of the source and the gate may be any shape that ensures the electrical properties of the TFT.
  • the shape of the overlapping region of the source and the gate may be designed as needed or empirically, for example, according to the shape of the source included in the TFT.
  • the shape of the first partial region and the second partial region may be any shape (for example, circular, rectangular or elliptical), and only needs to satisfy the case where a misalignment occurs between the first metal layer and the second metal layer.
  • the increase/decrease area of the first partial region is equal to the reduced/increased area of the second partial region.
  • the shape of the first partial region and the second partial region may be designed according to needs or experience. It should be noted that any overlap region including the gate (or the lateral cross-sectional pattern of the gate) and the two sides of the gate (or the lateral cross-sectional pattern of the gate) are respectively located in the direction parallel to the gate line.
  • the pixel unit includes a TFT 10, a pixel electrode 20, a gate line 30, and a data line 40.
  • the TFT I0 includes a source 11, a gate 12, and a drain 13, a source II and a pixel electrode. 20 is electrically connected to the via 50, the gate 12 is connected to the gate line 30, and the drain 13 is connected to the data line 40.
  • the gate 12 and the gate line 30 are located in the first metal layer, the source II and the drain. 13 and data line 40 are located in the second metal layer.
  • the source 11 (or the lateral cross-sectional pattern of the source 11) includes an overlap region lia with the gate electrode 12 (or a lateral cross-sectional pattern of the gate electrode 12), and is located at the gate electrode 12 in a direction parallel to the gate line, respectively. (Or, the transverse cross-sectional pattern of the gate electrode 12) the first partial region l ib and the second partial region iic on both sides.
  • a pattern of the first partial region I lb , the second partial region lie and the overlapping region lia with the gate electrode 12 (or the lateral cross-sectional pattern of the gate electrode 12), including the opening "U” in a direction parallel to the gate line A glyph pattern and an "L” shaped pattern that is connected to the closed edge of the "U” shape and placed laterally.
  • the first partial region lib is located at a position where one side of the "U" shape extends out of the gate 12 (or a lateral cross-sectional pattern of the gate 12), or on both sides of the "U" shape
  • the second partial region lie is located at the "L"-shaped extension of the gate 12 (or the lateral cross-sectional pattern of the gate 12) Location.
  • the U-shaped opening may face the drain or may face away from the drain.
  • the U-shaped opening faces the drain.
  • the first partial region l ib is located on a side of the "U" shape extending away from the through hole 50, or as shown in FIG. 5, located in the "U" shape away from the pass.
  • the two sides extending in the direction of the hole 50, the drain 13 (or the transverse cross-sectional pattern of the drain 13) are located between the two sides of the " ⁇ " shape, and the horizontally placed "L"-shaped pattern is rotated to the left.
  • the 45-degree "L" shape, the second partial region Uc is electrically connected to the pixel electrode 20 through the via 50.
  • the implementation manner of the source of the U-shaped opening facing away from the drain is similar to the implementation of the source of the U-shaped opening toward the drain, except that the glyph opening is back-drained.
  • the "L"-shaped pattern placed in the horizontal direction is a "L" shape rotated 45 degrees to the left and vertically inverted, and the drain (or the transverse cross-sectional pattern of the drain) is parallel to the horizontally placed "L"-shaped pattern. .
  • the "U"-shaped side and the closed side of the gate overlap, that is, the intersection with the gate (or the transverse cross-sectional pattern of the gate)
  • the shape of the side and the closed side of the stacking area can be designed according to needs or experience.
  • the closed side of the "U” shape is rectangular, as shown in FIG. 3, the "U"
  • the shape of the closed edge of the glyph is curved.
  • the shape of the first partial region and the second partial region may be a regular shape or an irregular shape.
  • the shape of the first partial area l ib is a rectangle
  • the shape of the second partial area lie is a horizontally placed "L" shape.
  • the shape of the second partial region may be deformed from the "L" shape to another shape as needed.
  • the rectangle is deformed to be perpendicular to the closed side of the "U" shape, i.e., the shape of the second partial region is "one".
  • the size requirements of the first partial regions may be the same or different, so as to achieve a misalignment between the first metal layer and the second metal layer, the first partial region
  • the increase/decrease area is equal to the decrease/enlargement area of the second partial area.
  • the first partial region lib is located on one side of the "U" shape (close to Gate! The upper edge of the upper and lower edges of 2, wherein the lower edge of the gate 12 is in contact with the gate line 30, the upper edge of the gate 12 is away from the gate line 30, and the upper edge of the gate 12 extends parallel to the lower edge of the gate 12)
  • the second partial region lie is located at a position where the "L"-shaped shape extends out of the cross-sectional pattern of the gate electrode i.
  • the shape of the second partial region 11c is The "L" shape placed horizontally.
  • the amounts of change of the lengths of the first partial region lib and the second partial region lie are equal, and thus, in order to realize the first metal layer and the second metal layer
  • the increase/decrease area of the first partial area lib is equal to the decrease/enlargement area of the second partial area lie
  • the width of the first partial area lib is required to be equal to the width of the rectangular area of the horizontal area of the second partial area lie.
  • the width value of the first partial region lib ranges from 5 ⁇ m to 10 ⁇ m.
  • the first partial region lib is located at one side of the "U" shape (near the lower edge in the upper and lower edges of the gate 12) and extends at a position of the cross-sectional pattern of the gate 12 and the first partial region
  • the shape of lib is a rectangle
  • the second partial region 11c is located at a position where the "L" shape extends out of the cross-sectional pattern of the gate 12 and the shape of the second partial region lie is a horizontally placed "L" shape.
  • the amounts of change of the lengths of the first partial region lib and the second partial region lie are equal, and thus, in order to realize the first metal layer and the second metal layer
  • the increase/decrease area of the first partial region lib is equal to the decrease/enlargement area of the second partial region lie
  • the width of the first partial region lib is required to be equal to the width of the rectangular region of the horizontal region of the second partial region 11c ( The embodiment of the widths of the first partial region lib and the second partial region 11c in FIGS. 2 and 4 is similar).
  • the first partial region lib is located at a position where the two sides of the "U" shape extend out of the cross-sectional pattern of the gate 12 and the shape of the first partial region lib is a rectangle, and the second partial region lie is located.
  • the "L" shape extends at a position of the cross-sectional pattern of the gate electrode 12 and the shape of the second partial portion 11c is a horizontally placed "L" shape.
  • the amounts of change of the lengths of the first partial region lib and the second partial region lie are equal, and thus, in order to realize the first metal layer and the second metal layer
  • the increase/decrease area of the first partial region lib is equal to the decrease/enlargement area of the second partial region lie, and is required to be respectively located on both sides of the "IT glyph”.
  • the sum of the width values of the first partial regions 1 ib at the position of the cross-sectional pattern of the gate electrode 12 is equal to the width of the rectangular portion of the horizontal region of the second partial region 11c.
  • the width of the rectangle of the horizontal area of the second partial region is in the range of 5 ⁇ . ⁇ .
  • the width of the first portion of the region can also be set as needed or empirically, e.g., based on pixel cell design experience.
  • the amount of misalignment between the first metal layer and the second metal layer due to natural factors such as process instability is within a predetermined amount of misalignment, and thus the first metal layer and the second metal layer are implemented.
  • the increase/decrease area of the first partial region is equal to the subtraction/increasing area of the second partial region, and the minimum distance between the source and the two edges of the gate (left and right edges)
  • the value is not less than the upper limit value of the preset misalignment amount range, and is described below by taking FIG. 2 as an example.
  • the shape of the first partial area l ib is a rectangle
  • the shape of the second partial area is a horizontally placed "L" shape.
  • the length value of the first partial region l ib (ie, the value of the first partial region l ib from the left edge of the gate 12) is a first distance value
  • the length of the rectangular portion of the horizontal region of the second partial region 1 ie is a second distance a value
  • the glyph being parallel to a side of the first partial region 1 ib and a value of a distance from a left edge of the gate 12, the closed edge of the "U" shaped being a distance from the right edge of the gate 12
  • the fourth distance value is not less than an upper limit value of the preset misalignment amount range.
  • the first distance value may be set according to needs or experience.
  • the first distance value ranges from ⁇ ⁇ - 5 ⁇ .
  • the larger the value of the first distance value, the second distance value, the third distance value, and the fourth distance value is, the larger the upper limit value of the preset misalignment amount range is, and the larger the preset misalignment amount range is. The lower the probability of occurrence of FUckeir and Mura.
  • the first distance value, the second distance value, the third distance value, and the fourth distance value are equal.
  • the first distance value, the second distance value, the third distance value, and the fourth distance value are equal, not only can the upper limit value of the preset misalignment amount range be large, but also the TFT can be ensured. Good electrical performance.
  • the minimum distance value between the first partial region and the second partial region and the data line (or the transverse cross-sectional pattern of the data line) is not less than a predetermined distance value threshold.
  • the distance The value threshold can be set as needed or empirically, for example, based on pixel unit design experience.
  • the distance value threshold has a value ranging from 5 ⁇ to 10 ⁇ .
  • the minimum distance between the first partial region and the second partial region and the data line (or the transverse cross-sectional pattern of the data line) is not less than the distance threshold, and the short circuit between the source and the data line can be prevented.
  • the minimum distance between the upper edge and the source of the gate is not less than the spacing threshold.
  • the spacing threshold can be set as needed or empirically.
  • the spacing threshold ranges from 3 ⁇ to 5 ⁇
  • the pattern of the first partial region 11b, the second partial region 11c, and the overlapping region l ia with the gate electrode 12 is similar to "s".
  • the pattern of the glyphs In order to achieve a misalignment between the first metal layer and the second metal layer, the overlapping area of the source and the gate is constant, and the first partial region and the second partial region are implemented in various forms.
  • the first partial region is located at a position where the first side and/or the second side of the "shi" shape extends in a first direction parallel to the gate line (or a lateral cross-sectional pattern of the gate) And the second partial region is located on the first side and/or the second side of the "shi" shape extending in a second direction opposite to the first direction (or a transverse cross-sectional pattern of the gate) At the position, the first side and the second side are parallel to each other.
  • the first partial region l ib is located on the first side of the "s" shape and extends out of the gate 12 in a first direction parallel to the gate line (or the lateral cross section of the gate 12 At a position of the pattern), the second partial region lie is located on the first side of the "shi" shape and extends out of the gate 12 in a second direction opposite to the first direction (or a transverse cross-sectional pattern of the gate 12) The location.
  • the width of the first partial region l ib is equal to the width of the second partial region lie.
  • the implementation of the width of the first partial area ib and the second partial area is similar to the implementation of the width of the first partial area ib in FIG. 2, and details are not described herein again.
  • the minimum distance between the source II and the two edges of the gate 12 (left and right edges)
  • the value is not less than the upper limit of the range of the preset misalignment.
  • the first partial region l ib has a rectangular shape
  • the second partial region l i e has a rectangular shape.
  • the length values of the first partial region 1 ib and the second partial region 11 c (ie, the value of the first partial region l ib from the left edge of the gate ! 2, and the second partial region 1 ie the value from the right edge of the gate 12) a first distance value, a value of a distance from a left edge of the gate 12 in the "shi" shape completely overlapping the cross-sectional pattern of the gate 12) is a second distance value, wherein the first distance value and The minimum value of the second distance values is not less than the upper limit value of the preset misalignment amount range.
  • the implementation manners of the first distance value and the second distance value are similar to the implementation manners of the first distance value and the second distance value in the first embodiment, and details are not described herein again.
  • the first partial region is located at a position where the second side of the "Shi" shape extends in a first direction parallel to the gate line and extends out of the gate (or a lateral cross-sectional pattern of the gate), and the second partial region A second side of the "shi" shape extends at a position of the gate (or a lateral cross-sectional pattern of the gate) in a second direction opposite to the first direction.
  • the first partial region is located at a position where the first side of the "shi" shape extends in a first direction parallel to the gate line (or a lateral cross-sectional pattern of the gate), and the second partial region A second side of the "shi" shape extends at a position of the gate (or a lateral cross-sectional pattern of the gate) in a second direction opposite to the first direction.
  • the first partial region is located at a position where the second side of the "shi" shape extends in a first direction parallel to the gate line (or a lateral cross-sectional pattern of the gate), and the second partial region A first side of the "shi" shape extends at a position of the gate (or a lateral cross-sectional pattern of the gate) in a second direction opposite to the first direction.
  • the embodiment of the second embodiment to the fourth embodiment is similar to the embodiment of the first embodiment, and details are not described herein again.
  • the first partial region is located at a position where the first side and the second side of the "shi" shape extend in a first direction parallel to the gate line (or a lateral cross-sectional pattern of the gate).
  • the second partial region is located at a position where the first side or the second side of the "shi" shape extends in a second direction opposite to the first direction (or a lateral cross-sectional pattern of the gate).
  • the sum of the widths of the first partial regions is equal to the width of the second partial regions.
  • the implementation manner of the widths of the first partial region and the second partial region is similar to the implementation of the widths of the first partial region 1 ib and the second partial region 11c in FIG. 5 , and details are not described herein again.
  • the minimum distance between the two edges (left and right edges) of the source and the gate is not less than the upper limit of the range of the preset misalignment.
  • Embodiment 1 of the embodiment of the present invention Implementation.
  • the first partial region is located at a position where the first side or the second side of the "Shi" shape extends in a first direction parallel to the gate line (or a lateral cross-sectional pattern of the gate)
  • the second partial region is located at a position where the first side and the second side of the "shi" shape extend in a second direction opposite to the first direction (or a lateral cross-sectional pattern of the gate).
  • the sum of the widths of the second partial regions is equal to the width of the first partial regions.
  • the implementation of the width of the first partial region and the second partial region is similar to the implementation of the widths of the first partial region ib and the second partial region ies in FIG. 5, and details are not described herein again.
  • the minimum distance between the two edges (left and right edges) of the source and the gate is not less than the upper limit of the range of the preset misalignment.
  • Embodiment 1 of the embodiment of the present invention Implementation.
  • the first partial region is located at a position where the first side and the second side of the "shi" shape extend in a first direction from a gate (or a lateral cross-sectional pattern of the gate), and the second partial region is located at a position The first side and the second side of the "shi" shape extend at a position of the gate (or a lateral cross-sectional pattern of the gate) in a second direction opposite to the first direction.
  • the sum of the widths of the second partial regions is equal to the sum of the widths of the first partial regions.
  • the implementation of the width of the first partial region and the second partial region is similar to the implementation of the width of the first partial region ib in FIG. 5, and details are not described herein again.
  • the first partial area and the second partial area are rectangular in shape, and the length values of the first partial area and the second partial area are first distance values, and the upper limit of the preset misalignment range is the first 5 Giant j3 ⁇ 4 '(i_.
  • the minimum distance value between the first partial region and the second partial region and the data line (or the transverse cross-sectional pattern of the data line) is not less than the distance value threshold.
  • the distance value threshold It can be set according to needs or experience, for example, based on pixel unit design experience.
  • the distance value threshold has a value ranging from 5 ⁇ to 10 ⁇ .
  • the minimum distance between the first partial region and the second partial region and the data line (or the transverse cross-sectional pattern of the data line) is not less than the distance threshold, and the short circuit between the source and the data line can be prevented.
  • the minimum distance between the upper edge and the source of the gate is not less than the spacing threshold.
  • the spacing threshold can be set as needed or empirically.
  • the spacing threshold ranges from 3 ⁇ to 5 ⁇
  • the above two embodiments are only two preferred embodiments of the improved source of the embodiment of the present invention, and the source structure in the embodiment of the present invention is simply deformed to make the source after the deformation.
  • the structure satisfies the case where the misalignment occurs between the first metal layer and the second metal layer, the overlapping area of the source and the gate is constant, or the other can satisfy the generation between the first metal layer and the second metal layer.
  • the source structure in which the overlap area of the source and the gate are constant is within the protection range of the embodiment of the present invention.
  • the gap between the source and the gate is constant when the gate is misaligned between the first metal layer and the second metal layer.
  • the gate (or the lateral cross-sectional pattern of the gate) includes a first partial region and a second partial region.
  • the amount of decrease/increase in the overlap area of the source (or the lateral cross-sectional pattern of the source) and the first partial region is equal to the source (or , the lateral cross-sectional pattern of the source) is increased/decreased by the overlap area of the second partial region.
  • any scheme for ensuring that the overlap area between the source and the gate is constant in the case where the gate structure is modified to ensure that a misalignment occurs between the first metal layer and the second metal layer is applicable to Embodiments of the invention.
  • the overlapping area of the source (or the lateral cross-sectional pattern of the source) and the first partial region may be increased (or reduced) by the source (or the lateral cross-sectional pattern of the source) and the second partial region.
  • the reduction (or increase) of the overlap area is compensated to ensure that the total parasitic capacitance Cgs between the source and the gate is constant, avoiding the occurrence of Flicker and Mura.
  • the overlapping area of the source and the gate is constant.
  • the gate (or the lateral cross-sectional pattern of the gate) includes a first partial region and a second partial region separated from each other, and the source (or the lateral cross-sectional pattern of the source) includes a portion overlapping the first partial region a three-part area and a fourth part area overlapping the second part area;
  • the increase/decrease area (or area) of the third partial region is equal to the decrease/enlargement area (or area) of the fourth partial region.
  • any increase or decrease in the bottom area (or area) of the third partial region is achieved by improving the source and the gate to ensure that a misalignment occurs between the first metal layer and the second metal layer.
  • the scheme in which the reduction/enhancement area (or area) of the fourth partial region is equal to ensure that the overlap area of the source and the gate is constant is applicable to the embodiment of the present invention.
  • the increase/decrease bottom area (or area) of the third partial region can be compensated by the reduced/increased bottom area (or area) of the fourth partial region, thereby ensuring the total between the source and the gate.
  • the parasitic capacitance Cgs is constant, avoiding the occurrence of Flicker and Mura.
  • the gate electrode 12 (or the lateral cross-sectional pattern of the gate electrode 12) includes a first partial region I 2a and a second partial region i2b separated from each other, and the source 11 (or source II)
  • the transverse cross-sectional pattern includes a third partial region i la overlapping the first partial region 12a and a fourth partial region I lb overlapping the second partial region 12b.
  • the source 11 (or the lateral cross-sectional pattern of the source) is a similar inverted shape composed of the first partial area I ia , the fourth partial area l ib , and the area ie between the first partial area I2a and the second partial area 12 b picture of.
  • the third partial region I la is located at a position where the inverted "T" shape overlaps the first partial region 12a in a first direction parallel to the gate line
  • the fourth partial region l ib is located at the inverted "T”
  • the glyph is at a position overlapping the second partial region 12b in a second direction opposite to the first direction.
  • the shapes of the third partial area i ia and the fourth partial area l ib may be set as needed or empirically, preferably, as shown in FIG. 7 , the third partial area i la and the fourth partial area l ib The shape is a rectangle.
  • the width of the third partial region 11a is equal to the width of the fourth partial region l ib .
  • the upper limit value of the predetermined misalignment amount range is a length value of the third partial region i la .
  • a display device includes the array substrate.
  • the display device can be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like, or any display product or component.
  • a method for fabricating an array substrate including:
  • Step 801 forming a gate on the base substrate, wherein the gate is located on the first metal layer; Step 802, forming a gate insulating layer covering the gate on the base substrate; Step 803, An active layer and a source and a drain on the active layer are sequentially formed on the gate insulating layer, wherein the source and the drain are located in the second metal layer.
  • an overlapping area of the source and the gate is constant.
  • step 801 forming a gate on the base substrate comprises:
  • the embodiment of the base substrate is similar to the embodiment of the base substrate in the prior art.
  • the base substrate is a glass substrate, a quartz substrate, or a flexible substrate.
  • the implementation of the gate metal layer is similar to the implementation of the gate metal layer of the prior art.
  • the gate metal layer is at least one film composed of a metal or alloy of Cr (chromium), Ti (titanium), Ta (barium), Mo (molybdenum), A1 (aluminum), and Cii (copper).
  • the thickness of the gate metal layer ranges from 50 ⁇ ⁇ to 400 ⁇ ⁇ .
  • the gate metal layer is etched, a different shape of the gate is etched away from the mask using different patterns.
  • the gate can be formed by a photolithography process including: coating a photoresist, exposing, developing, etching, and stripping the photoresist using a mask.
  • the gate metal layer may be etched as needed while forming a gate line.
  • FIG. 9A a plan view of forming a gate electrode and a gate line on a base substrate is shown in FIG. 9A, and - A cross-sectional view in FIG. 9A is shown in FIG. 9B. Shown.
  • a gate insulating layer covering the gate is formed on the base substrate, and the package is A gate insulating layer covering the gate is formed on the base substrate by a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • the gate insulating layer covers both the gate and the gate line.
  • the reaction gas corresponding to the gate insulating layer may be a mixed gas of SiH 4 (silane), NH 3 (ammonia gas) and 13 ⁇ 4, and the material of the gate insulating layer includes one of an oxide, a nitride and an oxygen-nitrogen compound.
  • the thickness of the gate insulating layer ranges from 1000A to 4000A.
  • an active layer and a source and a drain on the active layer are sequentially formed on the gate insulating layer, including: depositing an active layer on the gate insulating layer by a PECVD method And depositing a source/drain metal layer on the active layer by sputtering or thermal evaporation; and etching the active layer and the source/drain metal layer to form an active layer, and a source and a source on the active layer Drain.
  • the implementation of the active layer is similar to the implementation of the active layer in the prior art.
  • the thickness of the active layer ranges from 1000 ⁇ to 4000 ⁇ .
  • the active layer comprises a semiconductor layer and a cryptic semiconductor layer (ie, an ohmic contact layer) having a thickness ranging from 1000 ⁇ to 3,000 ⁇ , and a miscellaneous semiconductor layer having a thickness ranging from 300 ⁇ to 600 ⁇ .
  • the reactive gas corresponding to the active layer comprises a mixed gas of SiH 4 and 3 ⁇ 4, and a mixed gas of SiH 2 Cl 2 (dichlorosilane) and 3 ⁇ 4.
  • the embodiment of the source-drain metal layer is similar to the prior art source-drain metal layer.
  • the source/drain metal layer has a thickness in the range of 500A to 2500A.
  • the material of the source/drain metal layer comprises one of a metal or an alloy of Cr, W, Ti, Ta, Mo, Al and Cu.
  • the corresponding active layer region between the source and the drain is a corresponding region of the TFT channel pattern, and when the etching process is performed, the doped semiconductor layer of the corresponding region of the TFT channel pattern is completely better.
  • the source/drain metal layer is etched, different shapes of the source and the drain are etched by using masks of different patterns.
  • the source/drain metal layer may be etched as needed to form a data line.
  • a plan view of forming source, drain, and data lines on the active layer is shown in FIG. 9C, in which the drain is a linear electrode, the source The pole includes a U-shaped electrode and a linear electrode, a branch of the linear electrode and the U-shaped electrode extends beyond the gate edge, and a cross-sectional view taken along line B- in Fig. 9C is shown in Fig. 9D.
  • the method further includes:
  • Step 804 forming a passivation layer including a via hole on the second metal layer
  • Step 805 Form a pixel electrode electrically connected to the source through the via hole on the passivation layer.
  • step 804 forming a passivation layer including via holes on the second metal layer, comprising: depositing a passivation layer on the second metal layer by a PECVD method;
  • the passivation layer corresponding to the source is etched away to form a via that exposes the source.
  • the implementation of the passivation layer is similar to the implementation of the passivation layer of the prior art.
  • the thickness of the passivation layer ranges from 700A to 2000A.
  • the passivation layer corresponding to the reaction gas may be Si3 ⁇ 4, ⁇ ⁇ ⁇ ⁇ mixed gas, or a Si3 ⁇ 4Cl 2, ⁇ ⁇ ⁇ ⁇ 2 mixed gas, the material of the passivation layer comprises an oxide, nitride, or One of oxygen and nitrogen compounds.
  • FIG. 9A a plan view of forming a passivation layer including via holes on the second metal layer is as shown in FIG. 9A, wherein the source is electrically connected to the pixel electrode and the pixel electrode. Connected, and the cross section of CC ' in Figure 9 is shown in Figure 9F.
  • a pixel electrode electrically connected to the source via the via is formed on the passivation layer, including: depositing a transparent conductive layer on the passivation layer by sputtering or thermal evaporation; And etching the transparent conductive layer to form a pixel electrode electrically connected to the source through the via hole in the pixel region.
  • the embodiment of the transparent conductive layer is similar to the implementation of the transparent conductive layer in the prior art.
  • the thickness of the transparent conductive layer ranges from 300 ⁇ to 600 ⁇ .
  • the material of the transparent conductive layer comprises one or more of indium tin oxide, copper zinc oxide and aluminum zinc oxide.
  • FIG. 9G a plan view of a pixel electrode formed on the passivation layer and electrically connected to the source via the via is shown in FIG. 9G, and the D-D' direction in FIG. 9G The sectional view is shown in Figure 9 ⁇ .

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Abstract

一种阵列基板及其制作方法和显示装置。阵列基板包括TFT（10），TFT（10）包括源极（11）、栅极（12）和漏极（13），栅极（12）位于第一金属层，源极（11）和漏极（13）位于第二金属层；在第一金属层与第二金属层之间产生错位的情况下，源极（11）和栅极（12）的交叠面积恒定不变。解决了TFT-LCD在相邻像素单元的第一金属层与第二金属层之间的错位量不同时会存在画面品质不良的问题。

Description

基板及; 法、 显示
薄膜晶体管液晶显示器 ( Thin-Film Transistor Liquid Crystal Display, TFT-LCD) 包括彩膜基板、 阵列基板和位于所述彩膜基板与阵列基板之间的 液晶层。 所述阵列基板包括透明基板、 以及位于所述透明基板内侧的多条相 互平行的栅线和与所述栅线垂直交叉且电性绝缘的多条数据线， 其中， 多条 栅线和多条数据线限定出多个像素单元。
每个像素单元包括像素电极、 存储电容 （Cs)、 液晶电容 （Clc) 和作为 开关器件的薄膜晶体管（TFT)。 Cs和 Ck并行连接于像素电极， 且所述像素 电极与 TFT连接。 如图 1所示， 像素单元的 TFT 10包括源极 11、 栅极 12和 漏极 13 , 所述源极 11遥过通孔 50电连接于像素电极 20， 所述栅极 12与栅 线 30连接， 所述漏极 13与数据线 40连接， 所述栅线 30和栅极 12位于第一 金属层， 数据线 40、漏极 13和源极 11位于第二金属层， 且所述源极 II与所 述栅极 12交叠。所述源极与所述栅极交叠， 由此形成源极与栅极间的寄生电 容 （Cgs)， 其中 Cgs的大小和所述源极与栅极的交叠面积有关。
针对一个像素单元， 对与所述像素单元的 TFT的栅极连接的栅线上施加 开启电压时， 所述 TFT处于导通状态， 与所述 TFT的漏极连接的数据线上的 数据电压施加到像素电极上，对与并行连接于所述像素电极的 Cs和 Ck进行 充电。对与所述 TFT的栅极连接的栅线上施加关闭电压， 使所述 TFT处于关 闭状态， 施加到像素电极上的电压会由于寄生电容 Cgs的存在而发生跳变，
AVp ^ AYs
且所述像素电极上的电压跳变量 Cgs—Cs + Ck - , 其中， A Vg为栅极上 施加的开启电压与关闭电压之差。 在实际应用中， 由于工艺上的不稳定性， 第一金属层与第二金属层之间 会产生错位的情况，从而会导致像素单元的源极与栅极的交叠面积发生变化。 若相邻像素单元的第一金属层与第二金属层之间的错位量不同时， 则会造成 相邻像素单元的源极与栅极的交叠面积的变化量不同， 从而使得相邻像素单 元的寄生电容 Cgs的变化量不同， 以及相邻像素单元的寄生电容 Cgs在第一 金属层与第二金属层之间产生错位后不同（所述相邻像素单元的寄生电容 Cgs 在第一金属层与第二金属层之间产生错位前是相同的）。如果在相邻像素单元 的寄生电容 Cgs不同时， 相邻像素单元的像素电极上的电压跳变量不同， 使 得相邻像素的灰度不均匀， 从而引起画面品质不良， 例如， 出现 Flicker (画 面闪烁） 和 Mura (画面灰度不均匀） 等。
综上所述， 目前的 TFT CD在相邻像素单元的第一金属层与第二金属层 之间的错位量不同时会存在画面品质不良的问题。
本发明实施例提供了一种阵列基板及其制作方法、 显示装置， 用以解决 现有技术中存在的 TFTXCD 在相邻像素单元的第一金属层与第二金属层之 间的错位量不同时会存在画面品质不良的问题。
根据本发明实施例的第一个方面， 提供一种阵列基板， 包括薄膜晶体管 TFT, 所述 TFT包括源极、 栅极和漏极， 所述栅极位于第一金属层， 所述源 极和漏极位于第二金属层， 其中，
所述源极和栅极的形状满足： 在所述第一金属层与第二金属层之间产生 错位的情况下， 所述源极和栅极的交叠面积恒定不变。
在根据本发明的实施例中， 在所述阵列基板的第一金属层与第二金属层 之间产生错位的情况下， 像素单元的源极和栅极的交叠面积恒定不变， 因而 每个像素单元的源极和栅极的交叠面积的变化量均相同 （变化量为 0) , 从而 保证在第一金属层与第二金属层之间产生错位后， 相邻像素单元的源极和栅 极的交叠面积 ^然相同， 以及相邻像素单元的寄生电容 Cgs相同， 进而实现 在一定程度上保证相邻像素的灰度均匀， 避免或减少画面品质不良问题的发 牛
较佳地， 所述源极包括与栅极的交叠区域、 以及在与栅线平行的方向上 分别位于所述栅极两侧的第一部分区域和第二部分区域；
在所述第一金属层与第二金属层之间产生错位的情况下， 所述第一部分 区域的增 /减底面积与所述第二部分区域的减 /增底面积相等。
在根据本发明的实施例中， 通过改进 TFT所包括的源极的结构， 实现在 所述第一金属层与第二金属层之间产生错位的情况下， 保证所述源极和栅极 的交叠面积恒定不变。
较佳地， 所述第一部分区域、 第二部分区域和与栅极的交叠区域组成的 图案包括开口朝向与栅线平行的方向的" U"字形图案和与所述" ΙΓ字形图案 的封闭边连接 i横向放置的" υ '字形图案；
其中，所述第一部分区域位于所述" U"字形的一侧边延伸出所述栅极的位 置处， 或位于所述" U"字形的两个侧边延伸出所述栅极的位置处，所述第二部 分区域位于所述" L"字形图案延伸出所述栅极的位置处。
较佳地， 所述第一部分区域、 第二部分区域和与栅极的交叠区域组成的 图案为类似"士"字形的图案；
其中， 所述第一部分区域位于所述"士"字形图案的第一边和 /或第二边在 与栅线平行的第一方向上延伸出所述栅极的位置处； 以及
所述第二部分区域位于所述 "士"字形图案的第一边和 /或第二边在与第一 方向相反的第二方向上延伸出所述栅极的位置处， 所述第一边与第二边相互 平行。
在本发明实施例中， 提供了 TFT所包括的源极的具体结构， 以便本领域 技术人员可以很容易地实现本发明的技术方案。 需要说明的是， 本发明实施 例中的具体源极结构只用于解释本发明， 而并不 ^于限制本发明， 其它可以 用于实现本发明技术方案的结构也在本发明的保护范围之内。
较佳地， 所述阵列基板还包括与所述漏极连接的数据线， 所述第一部分 区域和第二部分区域与所述数据线之间的最小距离值不小于设定的阐值， 例 如， 5μιιι- 10μπι。
在本发明实施例中， 通过使第一部分区域和第二部分区域与数据线之间 的最小距离值不小于设定的阈值， 可以避免源极与数据线之间发生短路， 保 证 TFT具有较好的电性能。 较佳地， 所述栅极包括相互分开的第一部分区域和第二部分区域， 所述 源极包括与所述第一部分区域交叠的第三部分区域和与所述第二部分区域交 叠的第四部分区域；
在所述第一金属层与第二金属层之间产生错位的情况下， 所述第三部分 区域的增 /减底面积与所述第四部分区域的减 /增底面积相等。
在本发明实施例中， 通过改迸 TFT所包括的栅极和源极的结构， 实现在 所述第一金属层与第二金属层之间产生错位的情况下， 保证所述源极和栅极 的交叠面积恒定不变。
较佳地， 所述源极的图案为由所述第三部分区域、 第四部分区域和位于 所述第一部分区域和第二 .部分区域之间的区域组成的类似像 T字形的图案； 其中，所述第三部分区域位于所述倒" T"字形在与栅线平行的第一方向上 与所述第一部分区域交叠的位置处，所述第四部分区域位于所述倒" T"字形在 与所述第一方向相反的第二方向上与所述第二部分区域交叠的位置处。
在本发明实施例中， 提供了一种 TFT所包括的源极和栅极的具体结构， 以便本领域技术人员可以很容易地实现本发明的技术方案。 需要说明的是， 本发明实施例中的具体源极和栅极结构只 ^于解释本发明， 而并不用于限制 本发明， 其它可以用于实现本发明技术方案的结构也在本发明的保护范围之 内。
根据本发明实施例的第二个方面， 提供一种显示装置， 包括所述的阵列 基板。
在本发明实施例中， 由于所述显示装置包括的阵列基板能够在一定程度 上保证相邻像素的灰度均匀， 因而所述显示装置能够在一定程度上避免或减 少画面品质不良问题的发生。
根据本发明实施例的第三个方面， 提供一种所述阵列基板的制作方法， 包括：
在衬底基板上形成栅极， 其中所述栅极位于第一金属层；
在所述衬底基板上形成覆盖所述栅极的栅极绝缘层； 以及
在所述栅极绝缘层上依次形成有源层、 以及位于所述有源层上的源极和 漏极， 其中所述源极和漏极位于第二金属层； 其中， 在所述第一金属层与第二金属层之间产生错位的情况下， 所述源 极和栅极的交叠面积恒定不变。
在本发明实施例中， 在所述阵列基板的第一金属层与第二金属层之间产 生错位的情况下， 像素单元的源极和栅极的交叠面积恒定不变， 因而每个像 素单元的源极和栅极的交叠面积的变化量均相同 （变化量为 0)， 认而能够实 现在一定程度上保证相邻像素的灰度均匀， 避免或减少画面品质不良问题的 发生。
与现有技术相比， 采用本发明实施例的方案， 使得当第一金属层与第二 金属层之间产生错位的情况下， 即使相邻像素单元的第一金属层与第二金属 层之间产生的错位量不同， 相邻像素单元的栅极和源极的交叠面积也能够相 同， 使得相邻像素单元的寄生电容 Cgs相同， 从而保证相邻像素单元的像素 电极上的电压跳变量相同， 使得相邻像素的灰度均匀， 进而实现在一定程度 上避免或减少 Flicker和 Mura等画面品质不良问题的发生。
图 I为现 技术中像素单元的的结构示意图；
图 2 本发明实施例的阵列基板所包括的像素单元的第一种结构示 意图；
图 3 本发明实施例的阵列基板所包括的像素单元的第二种结构示 意图；
图 4 本发明实施例的阵列基板所包括的像素单元的第三种结构示 意图；
图 5 本发明实施例的阵列基板所包括的像素单元的第四种结构示 意图；
图 6 本发明实施例的阵列基板所包括的像素单元的第五种结构示 意图；
图 本发明实施例的阵列基板所包括的像素单元的第六种结构示 意图；
图 8为根据本 ^施例的用于制作阵列基板的方法的流程示意图； 图 9A〜图 9H为根据本发明实施例的阵列基板制作过程中阵列基板所包 括的像素单元的结构示意图。
根据本发明实施例的阵列基板包括 TFT， TFT包括源极、 栅极和漏极， 栅极位于第一金属层， 源极和漏极位于第二金属层； 在所述第一金属层与第 二金属层之间产生错位的情况下， 所述源极和栅极的交叠面积恒定不变。
由于在第一金属层与第二金属层之间产生错位之前'， 相邻像素单元的源 极和栅极的交叠面积相同， 在第一金属层与第二金属层之间产生错位之后， 相邻像素单元的源极和栅极的交叠面积的变化量不同， 认而造成第一金属层 与第二金属层之间产生错位后相邻像素单元的源极和栅极的交叠面积不同。
根据本发明实施例的阵列基板的结构能够保证在所述第一金属层与第二 金属层之间产生错位的情况下， 源极和栅极的交叠面积恒定不变， 即， 根据 本发明实施例的阵列基板能够保证在第一金属层与第二金属层之间产生错位 之后， 相邻像素单元的源极和栅极的交叠面积的变化量相同， 使得第一金属 层与第二金属层之间产生错位后相邻像素单元的源极和栅极的交叠面积相 同， 从而保证实现在一定程度上保证相邻像素的灰度均匀， 避免或减少画面 品质不良问题的发生。
下面结合说明书附图对本发明实施例作进一歩详细描述。
本发明实施例提供了一种阵列基板， 包括 TFT， TFT包括源极、 栅极和 漏极， 栅极位于第一金属层， 源极和漏极位于第二金属层， 其中，
所述源极和栅极的形状满足： 在第一金属层与第二金属层之间产生错位 的情况下， 源极和栅极的交叠面积恒定不变。
需要说明的是， 由于在本发明实施例中， 阵列基板包括多个像素单元， 每个像素单元包括一个 TFT, 且本发明实施例提供的阵列基板包括的每个像 素单元中的 TFT的实施方式类似， 下面将以本发明实施例的阵列基板包括的 一个像素单元的实施方式为例， 对本发明实施例的方案进行说明。
较佳地， 本发明实施例所提供的阵列基板的像素单元， 包括 TFT, TFT 包括源极、 栅极和漏极， 栅极位于第一金属层， 源极和漏极位于第二金属层， 其中，
所述源极和栅极的形状满足： 在第一金属层与第二金属层之间产生错位 的情况下， 源极和栅极的交叠面积恒定不变。
需要说明的是， 本发明实施例是以栅极是底栅为例进行的介绍， 具体实 施中， 其他类型的栅极 （例如， 顶栅等） 的实施方式与本发明实施例的栅极 (底栅） 的实施方式类似， 在此不再赘述。
具体实施中， 由于工艺不稳定等自然因素而造成的第一金属层与第二金 属层之间产生的错位量一般都比较小，即，在预设错位量范围如士 2μιπ〜士 5μιη 内。 优选地， 预设错位量范围的下限值可以为 0， 即， 第一金属层与第二金 属层之间未产生错位。
较佳地， 为了实现在第一金属层与第二金属层之间产生错位的情况下， 保证源极和栅极的交叠面积恒定不变， 需要对源极和 /或栅极进行改进， 下面 将分别进行介绍。
一、 本发明实施例通过改进源极实现在第一金属层与第二金属层之间产 生错位的情况下， 源极和栅极的交叠面积恒定不变。
较佳地， 源极 （或者， 源极的横向截面图案） 包括与栅极 （或者， 栅极 的橫向截面图案）的交叠区域、以及在与栅线平行的方向上分别位于栅极（或 者， 栅极的横向截面图案） 两侧的第一部分区域和第二部分区域；
在第一金属层与第二金属层之间产生错位的情况下， 第一部分区域的增 Ζ 减底面积 （或者， 减 /增面积） 与第二部分区域的减 /增底面积 （或者， 增 Ζ减 面积） 相等。
需要说明的是， 本发明实施例中括号内给出的是一种从源极和栅极的橫 向截面图案角度对本方案进行描述的方式。
当然， 本发明实施例的阵列基板 （像素单元） 的薄膜晶体管 （TFT) 的 源极和漏极制作工艺相同， 名称上可以互换； 可以将与数据线连接的作为漏 极， 与像素电极连接的作为源极； 反之亦然。
其中， 本发明实施例的阵列基板 （像素单元） 还包括与栅极垂直连接的 栅线， 与漏极垂直连接的数据线， 与栅线平行的方向为水平方向， 以及与数 据线平行的方向为垂直方向。 例如， 如图 2所示， 与栅线 30平行的方向为水 平方向， 与数据线 40平行的方向为垂直方向。 其中， 根据本发明实施例的位 于栅极（或者， 栅极的横向截面图案）一侧的第一部分区域相对栅极（或者， 栅极的横向截面图案） 的底面积 （或者， 面积） 会在第一金属层与第二金属 层之间产生错位后发生变化。 例如， 在第一金属层与第二金属层之间产生错 位前， 位于栅极一侧的第一部分区域 （相对栅极） 的底面积为 A， 在第一金 属层与第二金属层之间产生错位后， 位于栅极一侧的第一部分区域 （相对栅 极） 的底面积会变化为 B。
具体实施中， 根据本发明实施例的位于栅极 （或者， 栅极的横向截面图 案） 另一侧的第二部分区域的实施方式与根据本发明实施例的第一部分区域 的实施方式类似， 在此不再赘述。
具体实施中， 第一部分区域和第二部分区域为在与栅线平行的方向上分 别位于所述栅极两侧的区域， 在所述第一金属层与第二金属层之间产生错位 的情况下，第一部分区域的增 /减底面积与所述第二部分区域的减 /增底面积相 等， 从而确保了源极与栅极的交叠区域的面积恒定， 保证了源极和栅极的交 叠面积恒定不变。
当第二金属层相对第一金属层发生左 （右） 错位 （即， 在与栅线平行的 方向上的错位） 时， 第一部分区域的面积会增大（缩小）， 即源极与栅极间的 寄生电容 Cgs会缩小（增大），而相应地，第二部分区域的面积会缩小（增大）， 即源极与栅极间的寄生电容 Cgs会增大 （缩小）。 由于第一部分区域的增 /减 面积可以通过第二部分区域的减 /增面积来补偿， 从而确保了源极与栅极间的 总寄生电容 Cgs恒定不变， 避免 Flkker和 Miira的发生。
当第二金属层相对第一金属层发生上 （下） 错位 （即， 垂直方向上的错 位） 时， 由于源极 （或者， 源极的横向截面图案） 与栅极 （或者， 栅极的横 向截面图案） 的交叠区域与栅极 （或者， 栅极的横向截面图案） 的两边缘之 间的距离值比较大， 因而不会影响源极和栅极的交叠面积。
当第二金属层相对第一金属层发生一定角度的错位时， 一定角度的错位 可以分解为与栅线平行的方向上的错位和与栅线垂直的方向上的错位， 而与 栅线平行的方向上的错位和与栅线垂直的方向上的错位的实施方式与上述与 栅线平行的方向上的错位和与栅线垂直的方向上的错位的实施方式类似， 在 此不再赘述。
较佳地， 源极与栅极 （或者， 栅极的横向截面图案） 的交叠区域的形状 可以为能保证 TFT电性能的任何形状。
较佳地， 源极与栅极 （或者， 栅极的横向截面图案） 的交叠区域的形状 可以根据需要或经验设计， 例如， 根据 TFT包括的源极的形状设计。
较佳地， 第一部分区域和第二部分区域的形状可以为任何形状 （例如， 圆形、长方形或椭圆形）， 只需要满足在第一金属层与第二金属层之间产生错 位的情况下， 第一部分区域的增 /减面积与第二部分区域的减 /增面积相等即 较佳地，第一部分区域和第二部分区域的形状可以根据需要或经验设计。 需要说明的是， 任何包括与栅极 （或者， 栅极的横向截面图案） 的交叠 区域、 以及在与栅线平行的方向上分别位于栅极 （或者， 栅极的横向截面图 案）两侧的第一部分区域和第二部分区域的源极结构均适用于本发明实施例， 本发明实施例无法穷举所有的可能的源极结构， 下面将以两个较佳的实施例 对本发明实施例的源极结构进行详细介绍。 较佳地， 如图 2所示， 像素单元包括 TFT 10、 像素电极 20、 栅线 30和 数据线 40, TFT I 0包括源极 11、 栅极 12和漏极 13 , 源极 II与像素电极 20 遥过通孔 50进行电性连接， 栅极 12与栅线 30连接， 漏极 13与数据线 40连 接， 其中， 栅极 12和栅线 30位于第一金属层， 源极 I I、 漏极 13和数据线 40位于第二金属层。
源极 11 (或者， 源极 11 的横向截面图案） 包括与栅极 12 (或者， 栅极 12 的横向截面图案） 的交叠区域 lia、 以及在与栅线平行的方向上分别位于 栅极 12 (或者， 栅极 12的橫向截面图案） 两侧的第一部分区域 l ib和第二 部分区域 iic。 第一部分区域 I lb、 第二部分区域 l ie和与栅极 12 (或者， 栅 极 12的横向截面图案） 的交叠区域 lia组成的图案， 包括开口朝向与栅线平 行的方向的" U"字形图案和与所述" U"字形的封闭边连接且横向放置的" L"字 形图案。 其中， 第一部分区域 lib位于所述" U"字形的一侧边延伸出栅极 12 (或者， 栅极 12的横向截面图案） 的位置处， 或位于所述" U"字形的两个侧 边延伸出栅极 12 (或者， 栅极 12的横向截面图案） 的位置处， 第二部分区 域 lie位于所述" L"字形延伸出栅极 12 (或者， 栅极 12的横向截面图案） 的 位置处。
具体实施中，所述" U"字形开口可以朝向漏极，也可以背向漏极，较佳地, 所述" ΙΓ字形开口朝向漏极。 在所述 "U"字形开口朝向漏极时， 如图 2和图 4 所示，第一部分区域 l ib位于所述" U "字形向背离通孔 50方向延伸的一侧边, 或如图 5所示， 位于所述" U"字形向背离通孔 50方向延伸的两个侧边， 漏极 13 (或者， 漏极 13的横向截面图案） 位于所述" ΙΓ字形的两个侧边之间， 横 向放置的" L"字形图案为向左旋转 45度的" L"字形，第二部分区域 Uc通过通 孔 50与像素电极 20进行电性连接。
具体实施中， 所述" U"字形开口背向漏极时源极的实施方式与所述" U"字 形开口朝向漏极时源极的实施方式类似，只不过在所述 字形开口背向漏极 寸， 横向放置的" L"字形图案为向左旋转 45度且垂直翻转后的" L"字形， 且漏 极 （或者， 漏极的横向截面图案） 与横向放置的 "L"字形图案平行。
较佳地， 所述" U"字形与栅极（或者， 栅极的橫向截面图案）交叠的侧边 和封闭边， 即， 位于与栅极 （或者， 栅极的横向截面图案） 的交叠区域的侧 边和封闭边的形状可以根据需要或经验设计， 比如， 如图 2所示， 所述" U" 字形的封闭边的形状为长方形，如图 3所示，所述" U"字形的封闭边的形状为 弧形。
较佳地， 第一部分区域和第二部分区域的形状可以为规则形状， 也可以 为不规则形状。 例如， 如图 2所示， 第一部分区域 l ib的形状为长方形， 第 二部分区域 lie的形状为横向放置的 "L"字形。
具体实施中，第二部分区域的形状根据需要也可以由" L"字形变形为其他 形状。 例如， 变形为垂直于所述" U"字形的封闭边的长方形， 即， 第二部分区 域的形状为"一"字形。 较佳地， 当第一部分区域的位置不同时， 第一部分区 域的尺寸要求可能相同， 也可能不同， 以实现在第一金属层与第二金属层之 间产生错位的情况下，第一部分区域的增 /减面积与第二部分区域的减 /增面积 相等。
例如， 如图 2所示， 第一部分区域 lib位于所述" U"字形的一侧边（靠近 栅极！2的上下边缘中的上边缘， 其中栅极 12的下边缘与栅线 30接触， 栅极 12的上边缘远离栅线 30， 栅极 12的上边缘与栅极 12的下边缘相互平行）延 伸出栅极 12截面图案的位置处且第一部分区域 lib的形状为长方形，第二部 分区域 lie位于所述" L"字形延伸出栅极 12截面图案的位置处 i第二部分区 域 11c的形状为横向放置的 "L"字形。
由于在第一金属层与第二金属层之间产生错位的情况下， 第一部分区域 lib和第二部分区域 lie的长度的变化量相等，因而为了实现在第一金属层与 第二金属层之间产生错位的情况下， 第一部分区域 lib的增 /减面积与第二部 分区域 lie的减 /增面积相等， 要求第一部分区域 lib的宽度等于第二部分区 域 lie的水平区域的长方形的宽度。 较佳地， 第一部分区域 lib的宽度值的 取值范围为 5μιη- 10μπι。
例如， 如图 4所示， 第一部分区域 lib位于所述" U"字形的一侧边（靠近 栅极 12的上下边缘中的下边缘） 延伸出栅极 12截面图案的位置处且第一部 分区域 lib的形状为长方形， 第二部分区域 11c位于所述" L"字形延伸出栅极 12截面图案的位置处且第二部分区域 lie的形状为横向放置的 "L"字形。
由于在第一金属层与第二金属层之间产生错位的情况下， 第一部分区域 lib和第二部分区域 lie的长度的变化量相等，因而为了实现在第一金属层与 第二金属层之间产生错位的情况下， 第一部分区域 lib的增 /减面积与第二部 分区域 lie的减 /增面积相等， 要求第一部分区域 lib的宽度等于第二部分区 域 11c的水平区域的长方形的宽度 （图 2和图 4中的第一部分区域 lib和第 二部分区域 11c的宽度的实施方式类似）。
例如， 如图 5所示， 第一部分区域 lib位于所述" U"字形的两个侧边延伸 出栅极 12截面图案的位置处且第一部分区域 lib的形状为长方形，第二部分 区域 lie位于所述" L"字形延伸出栅极 12截面图案的位置处且第二部分区域 11c的形状为橫向放置的 "L"字形。
由于在第一金属层与第二金属层之间产生错位的情况下， 第一部分区域 lib和第二部分区域 lie的长度的变化量相等，因而为了实现在第一金属层与 第二金属层之间产生错位的情况下， 第一部分区域 lib的增 /减面积与第二部 分区域 lie 的减 /增面积相等， 要求分别位于所述" IT字形的两个侧边延伸出 栅极 12截面图案的位置处的第一部分区域 l ib的宽度值之和等于第二部分区 域 11c的水平区域的长方形的宽度。 较佳地， 第二部分区域 l ie的水平区域 的长方形的宽度值的取值范围为 5μ.Γη-10μηι。
较佳地， 第一部分区域的宽度值还可以根据需要或经验设定， 比如， 根 据像素单元设计经验确定。
较佳地， 由于工艺不稳定等自然因素而造成的第一金属层与第二金属层 之间产生的错位量在预设错位量范围内， 因而为了实现在第一金属层与第二 金属层之间产生错位的情况下， 第一部分区域的增 /减面积与所述第二部分区 域的减 /增面积相等， 源极与栅极的两边缘 （左、 右两边缘） 之间的最小距离 值不小于所述预设错位量范围的上限值， 下面以图 2为例迸行介绍。
例如， 如图 2所示， 第一部分区域 l ib的形状为长方形， 第二部分区域 l ie的形状为横向放置的 "L"字形。 第一部分区域 l ib的长度值 （即， 第一部 分区域 l ib距离栅极 12的左边缘的值） 为第一距离值， 第二部分区域 l ie的 水平区域的长方形的长度值为第二距离值，所述 字形平行于第一部分区域 l ib的一侧边距离栅极 12的左边缘的值为第 距离值， 所述" U"字型的封闭 边距离栅极 12的右边缘的值为第四距离值。 其中， 所述第一距离值、 第二距 离值、 第≡距离值和第四距离值中的最小值不小于所述预设错位量范围的上 限值。
具体实施中， 第一距离值可以根据需要或经验设定， 较佳地， 第一距离 值的取值范围为 Ι μιη- 5μηι。
具体实施中， 第一距离值、 第二距离值、 第三距离值和第四距离值的取 值越大， 预设错位量范围的上限值取值越大， 预设错位量范围越大， FUckeir 和 Mura发生的概率越小。
较佳地， 第一距离值、 第二距离值、 第≡距离值和第四距离值相等。 具 体实施中， 在第一距离值、 第二距离值、 第≡距离值和第四距离值相等时， 不仅可以保证预设错位量范围的上限值取值较大， 还可以保证 TFT具有较好 的电性能。
较佳地， 第一部分区域和第二部分区域与数据线 （或者， 数据线的横向 截面图案） 之间的最小距离值不小于预定的距离值阈值。 具体实施中， 距离 值阈值可以根据需要或经验设定， 例如， 根据像素单元设计经验确定。 较佳 地， 距离值阈值的取值范围为 5μηι- 10μϊη。
具体实施中， 第一部分区域和第二部分区域与数据线 （或者， 数据线的 横向截面图案） 之间的最小距离值不小于距离值阈值， 可以防止源极与数据 线间短路的情况发生。
较佳地， 栅极的上边缘与源极之间的最小距离值不小于间距阈值。 具体 实施中， 间距阈值可以根据需要或经验设定。 较佳地， 间距阈值的取值范围 为 3 ιη~5μηΐο
实施例二
较佳地， 如图 6所示， 第一部分区域 l l b、 第二部分区域 11c和与栅极 12 (或者， 栅极 12的横向截面图案） 的交叠区域 l ia组成的图案为类似"士" 字形的图案。 为了实现在第一金属层与第二金属层之间产生错位的情况下， 源极和栅极的交叠面积恒定不变， 第一部分区域和第二部分区域的实施方式 有多种。
较佳地， 第一部分区域位于所述"士"字形的第一边和 /或第二边在与栅线 平行的第一方向上延伸出栅极 （或者， 栅极的横向截面图案） 的位置处； 以 及第二部分区域位于所述"士"字形的第一边和 /或第二边在与第一方向相反的 第二方向上延伸出栅极 （或者， 栅极的横向截面图案） 的位置处， 所述第一 边与第二边相互平行。
下面将对第一部分区域和第二部分区域的多种实施方式分别进行介绍。 实施方式一， 如图 6所示， 第一部分区域 l ib位于所述"士"字形的第一 边在与栅线平行的第一方向上延伸出栅极 12 (或者， 栅极 12的横向截面图 案） 的位置处， 第二部分区域 l ie位于所述"士"字形的第一边在与第一方向 相反的第二方向上延伸出栅极 12 (或者， 栅极 12 的横向截面图案） 的位置 处。
较佳地， 第一部分区域 l ib的宽度等于第二部分区域 l ie的宽度。
具体实施中， 第一部分区域 l ib和第二部分区域 l ie的宽度的实施方式 与图 2中的第一部分区域 l ib的宽度的实施方式类似， 在此不再赘述。
较佳地， 源极 I I与栅极 12的两边缘 （左、 右两边缘） 之间的最小距离 值不小于所述预设错位量范围的上限值。
例如， 如图 6所示， 第一部分区域 l ib的形状为长方形， 第二部分区域 l i e的形状为长方形。
第一部分区域 l ib和第二部分区域 11 c的长度值（即， 第一部分区域 l ib 距离栅极！2的左边缘的值， 第二部分区域 l ie距离栅极 12的右边缘的值） 为第一距离值， 所述"士"字形中与栅极 12的截面图案完全交叠的一边距离栅 极 12的左边缘的值）为第二距离值， 其中， 所述第一距离值和第二距离值中 的最小值不小于所述预设错位量范围的上限值。
具体实施中， 第一距离值和第二距离值的实施方式与实施例一中的第一 距离值和第二距离值的实施方式类似， 在此不再赘述。
实施方式二， 第一部分区域位于所述"士"字形的第二边在与栅线平行的 第一方向上延伸出栅极 （或者， 栅极的横向截面图案） 的位置处， 第二部分 区域位于所述 "士"字形的第二边在与第一方向相反的第二方向上延伸出栅极 (或者， 栅极的横向截面图案） 的位置处。
实施方式三， 第一部分区域位于所述"士"字形的第一边在与栅线平行的 第一方向上延伸出栅极 （或者， 栅极的横向截面图案） 的位置处， 第二部分 区域位于所述 "士"字形的第二边在与第一方向相反的第二方向上延伸出栅极 (或者， 栅极的横向截面图案） 的位置处。
实施方式四， 第一部分区域位于所述"士"字形的第二边在与栅线平行的 第一方向上延伸出栅极 （或者， 栅极的横向截面图案） 的位置处， 第二部分 区域位于所述 "士"字形的第一边在与第一方向相反的第二方向上延伸出栅极 (或者， 栅极的横向截面图案） 的位置处。
具体实施中，实施方式二〜实施方式四的实施方式与实施方式一的实施方 式类似， 在此不再赘述。
实施方式五， 第一部分区域位于所述"士"字形的第一边和第二边在与栅 线平行的第一方向上延伸出栅极 （或者， 栅极的横向截面图案） 的位置处， 第二部分区域位于所述"士"字形的第一边或第二边在与第一方向相反的第二 方向上延伸出栅极 （或者， 栅极的横向截面图案） 的位置处。
较佳地， 第一部分区域的宽度之和等于第二部分区域的宽度。 具体实施中， 第一部分区域和第二部分区域的宽度的实施方式与图 5中 的第一部分区域 l ib和第二部分区域 11c的宽度的实施方式类似， 在此不再 赘述。
较佳地， 源极与栅极的两边缘 （左、 右两边缘） 之间的最小距离值不小 于所述预设错位量范围的上限值， 具体可参见本发明实施例的实施方式一的 实施。
实施方式六， 第一部分区域位于所述"士''字形的第一边或第二边在与栅 线平行的第一方向上延伸出栅极 （或者， 栅极的横向截面图案） 的位置处， 第二部分区域位于所述"士"字形的第一边和第二边在与第一方向相反的第二 方向上延伸出栅极 （或者， 栅极的横向截面图案） 的位置处。
较佳地， 第二部分区域的宽度之和等于第一部分区域的宽度。
具体实施中， 第一部分区域和第二部分区域的宽度的实施方式与图 5中 的第一部分区域 l ib和第二部分区域 l ie的宽度的实施方式类似， 在此不再 赘述。
较佳地， 源极与栅极的两边缘 （左、 右两边缘） 之间的最小距离值不小 于所述预设错位量范围的上限值， 具体可参见本发明实施例的实施方式一的 实施。
实施方式七， 第一部分区域位于所述"士"字形的第一边和第二边在第一 方向上延伸出栅极 （或者， 栅极的横向截面图案） 的位置处， 第二部分区域 位于所述"士"字形的第一边和第二边在与第一方向相反的第二方向上延伸出 栅极 （或者， 栅极的横向截面图案） 的位置处。
较佳地， 第二部分区域的宽度之和等于第一部分区域的宽度之和。
具体实施中， 第一部分区域和第二部分区域的宽度的实施方式与图 5中 的第一部分区域 l ib的宽度的实施方式类似， 在此不再赘述。
较佳地， 第一部分区域和第二部分区域的形状为长方形， 第一部分区域 和第二部分区域的长度值为第一距离值， 则所述预设错位量范围的上限值为 第一 5巨 j¾ '(i_。
较佳地， 第一部分区域和第二部分区域与数据线 （或者， 数据线的横向 截面图案） 之间的最小距离值不小于距离值阈值。 具体实施中， 距离值阈值 可以根据需要或经验设定， 例如， 根据像素单元设计经验确定。 较佳地， 距 离值阈值的取值范围为 5μηι-10μϊη。
具体实施中， 第一部分区域和第二部分区域与数据线 （或者， 数据线的 横向截面图案） 之间的最小距离值不小于距离值阈值， 可以防止源极与数据 线间短路的情况发生。
较佳地， 栅极的上边缘与源极之间的最小距离值不小于间距阈值。 具体 实施中， 间距阈值可以根据需要或经验设定。 较佳地， 间距阈值的取值范围 为 3 ιη~5μηΐο
需要说明的是， 上述两个实施例仅是本发明实施例的改进后的源极的两 种较佳实施方式， 对本发明实施例中的源极结构进行的简单变形以使变形后 的源极结构满足在第一金属层与第二金属层之间产生错位的情况下， 源极和 栅极的交叠面积恒定不变， 或其他能够满足在第一金属层与第二金属层之间 产生错位的情况下， 源极和栅极的交叠面积恒定不变的源极结构均在本发明 实施例的保护范围内。
二、 本发明实施例通过改进栅极实现在第一金属层与第二金属层之间产 生错位的情况下， 源极和栅极的交叠面积恒定不变。
较佳地， 栅极 （或者， 栅极的横向截面图案） 包括第一部分区域和第二 部分区域。 在第一金属层与第二金属层之间产生错位的情况下， 源极（或者， 源极的横向截面图案）与第一部分区域的交叠面积的减小量 /增加量等于源极 (或者，源极的横向截面图案）与第二部分区域的交叠面积的增加量 /减小量。
需要说明的是， 任何通过改迸栅极结构， 实现保证在第一金属层与第二 金属层之间产生错位的情况下， 源极与栅极的交叠面积恒定不变的方案均适 用于本发明实施例。
具体实施中， 源极 （或者， 源极的横向截面图案） 与第一部分区域增大 (或缩小） 的交叠面积可通过源极 （或者， 源极的横向截面图案） 与第二部 分区域的交叠面积的缩小 （或增大） 来补偿， 从而确保了源极与栅极间的总 寄生电容 Cgs恒定不变， 避免 Flicker和 Mura的发生。
三、 本发明实施例通过改进源极和栅极实现在第一金属层与第二金属层 之间产生错位的情况下， 源极和栅极的交叠面积恒定不变。 较佳地， 栅极 （或者， 栅极的横向截面图案） 包括相互分开的第一部分 区域和第二部分区域， 源极 （或者， 源极的横向截面图案） 包括与第一部分 区域交叠的第三部分区域和与第二部分区域交叠的第四部分区域；
在第一金属层与第二金属层之间产生错位的情况下， 第三部分区域的增 / 减底面积（或者， 面积）与第四部分区域的减 /增底面积（或者， 面积）相等。
需要说明的是， 任何通过改进源极和栅极， 实现保证在第一金属层与第 二金属层之间产生错位的情况下， 第三部分区域的增 /减底面积（或者， 面积） 与第四部分区域的减 /增底面积 （或者， 面积） 相等， 以保证源极和栅极的交 叠面积恒定不变的方案均适用于本发明实施例。
具体实施中， 第三部分区域的增 /减底面积 （或者， 面积） 可通过第四部 分区域的减 /增底面积 （或者， 面积） 来补偿， 从而确保了源极与栅极间的总 寄生电容 Cgs恒定不变， 避免 Flicker和 Mura的发生。
下面将以一个具体的实施例对遥过改进源极和栅极以实现源极和栅极的 交叠面积恒定不变的方案迸行介绍。
较佳地， 如图 7所示， 栅极 12 (或者， 栅极 12的横向截面图案） 包括 相互分开的第一部分区域 I 2a和第二部分区域 i2b， 源极 11 (或者， 源极 I I 的橫向截面图案） 包括与第一部分区域 12a交叠的第三部分区域 i la和与第 二部分区域 12b交叠的第四部分区域 I lb。 源极 11 (或者， 源极的橫向截面 图案） 为由第 部分区域 I ia、 第四部分区域 l ib和位于第一部分区域 I2a 和第二部分区域 12b之间的区域 l ie组成的类似倒 字形的图案。 其中， 第 三部分区域 I la位于所述倒" T"字形在与栅线平行的第一方向上与第一部分区 域 12a交叠的位置处，第四部分区域 l ib位于所述倒" T"字形在与所述第一方 向相反的第二方向上与第二部分区域 12b交叠的位置处。
具体实施中， 第三部分区域 i ia和第四部分区域 l ib的形状可以根据需 要或经验设 ， 较佳地， 如图 7所示， 第三部分区域 i la和第四部分区域 l ib 的形状为长方形。
较佳地， 第三部分区域 11a的宽度等于第四部分区域 l ib的宽度。
较佳地， 在第 部分区域 l ia的长度值和第四部分区域 l ib的长度值相 等时， 所述预设错位量范围的上限值为第三部分区域 i la的长度值。 具体实施中， 第三部分区域 11 a的长度值越大， 预设错位量范围的上限 值越大， 预设错位量范围越大， Flicker和 Mura发生的概率越小。
根据本发明实施例的显示装置， 包括所述的阵列基板。 所述显示装置可 以为： 液晶面板、 电子纸、 OLED面板、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品或部件。
根据本发明优选的实施例， 如图 8所示， 提供一种制作阵列基板的方法， 包括：
步骤 801、 在衬底基板上形成栅极， 其中所述栅极位于第一金属层； 步骤 802、 在所述衬底基板上形成覆盖所述栅极的栅极绝缘层； 步骤 803、 在所述栅极绝缘层上依次形成有源层、 以及位于所述有源层 上的源极和漏极， 其中所述源极和漏极位于第二金属层，
其中， 在所述第一金属层与第二金属层之间产生错位的情况下， 所述源 极和栅极的交叠面积恒定不变。
较佳地， 在步骤 801中， 在衬底基板上形成栅极， 包括：
采用溅射或热蒸发的方法， 在衬底基板上沉积一层栅金属层； 以及 对所述栅金属层进行刻蚀， 形成栅极。
具体实施中， 衬底基板的实施方式与现有技术中衬底基板的实施方式类 似， 较佳地， 衬底基板为玻璃基板、 石英基板、 或者柔性基板。
具体实施中， 栅金属层的实施方式与现有技术中栅金属层的实施方式类 似。 较佳地， 栅金属层为由 Cr (铬）、 Ti (钛）、 Ta (钽）、 Mo (钼）、 A1 (铝） 和 Cii (铜） 的金属或合金组成的至少一层薄膜。 较佳地， 栅金属层的厚度范 围为 50θΑ〜400θΑ。
较佳地， 在对栅金属层进行刻蚀时， 遥过采用不同图案的掩模板， 实现 刻蚀出不同形状的栅极。 例如， 可以通过光刻工艺形成栅极， 包括： 涂覆光 刻胶、 利用掩模板曝光、 显影、 刻蚀、 剥离光刻胶。
较佳地， 在形成栅极时， 可以根据需要对所述栅金属层进行刻蚀， 同时 形成栅线。 例如， 以形成图 2中的栅极和栅线为例， 在衬底基板上形成栅极 和栅线的平面图如图 9A所示， 并—且.图 9A中 A- 向剖面图如图 9B所示。
较佳地， 在歩骤 802中， 在衬底基板上形成覆盖栅极的栅极绝缘层， 包 括: 通过等离子体增强化学气相沉积 ( lasma enhanced chemical vapor deposition, PECVD) 方法， 在衬底基板上形成覆盖栅极的栅极绝缘层。
具体实施中， 在衬底基板上形成有栅线时， 所述栅极绝缘层同时覆盖栅 极和栅线。 较佳地， 栅绝缘层对应的反应气体可以为 SiH4 (硅烷）、 NH3 (氨 气）和1¾的混合气体， 栅绝缘层的材料包括氧化物、 氮化物和氧氮化合物中 的一种。 较佳地， 栅极绝缘层的厚度范围为 1000A〜4000 A。
较佳地， 在步骤 803中， 在栅极绝缘层上依次形成有源层、 以及位于有 源层上的源极和漏极， 包括： 通过 PECVD方法， 在栅极绝缘层上沉积有源 层， 以及通过溅射或热蒸发方法， 在有源层上沉积源漏金属层； 以及对有源 层和源漏金属层进行刻蚀， 形成有源层、 以及位于有源层上的源极和漏极。
具体实施中， 有源层的实施方式与现有技术中有源层的实施方式类似。 较佳地， 有源层的厚度范围为 1000 Α〜4000 Α。 较佳地， 有源层包括半 导体层和惨杂半导体层 （即， 欧姆接触层）， 半导体层的厚度范围为 1000 Α-3000 Α, 惨杂半导体层的厚度范围为 300 Α〜600 Α。 较佳地， 有源层对应 的反应气体包括 SiH4和 ¾的混合气体， 以及 SiH2Cl2 (二氯硅垸）和 ¾的混 合气体。
具体实施中， 源漏金属层的实施方式与现有技术中源漏金属层的实施方 式类似。 较佳地， 源漏金属层的厚度范围为 500A〜2500A。 较佳地， 源漏金 属层的材料包括 Cr、 W、 Ti、 Ta、 Mo、 Al和 Cu的金属或合金中的一种。
具体实施中， 源极和漏极之间对应的有源层区域为 TFT沟道图形对应区 域， 且在进行刻蚀工艺时， TFT沟道图形对应区域的掺杂半导体层被完全刻 较佳地， 在对源漏金属层进行刻蚀时， 通过采用不同图案的掩模板， 实 现刻蚀出不同形状的源极和漏极。
较佳地， 在形成源极和漏极时， 可以根据需要对所述源漏金属层进行刻 蚀， 同时形成数据线。 例如， 以形成图 2中的源极、 漏极和数据线为例， 在 有源层上形成源极、漏极和数据线的平面图如图 9C所示， 其中， 漏极为直线 状电极， 源极包括 U型电极和直线状电极， 直线状电极和 U型状电极的一分 支超出栅极边缘， 并且图 9C中 B- 向剖面图如图 9D所示。 较佳地， 在步骤 803之后， 还包括：
步骤 804、 在所述第二金属层上形成包括过孔的钝化层；
步骤 805、 在所述钝化层上形成通过所述过孔与所述源极进行电性连接 的像素电极。
较佳地， 在步骤 804中， 在第二金属层上形成包括过孔的钝化层， 包括: 通过 PECVD方法， 在第二金属层上沉积钝化层； 以及
刻蚀掉源极对应位置的钝化层， 以形成暴露出源极的过孔。
具体实施中， 钝化层的实施方式与现有技术中钝化层的实施方式类似。 较佳地， 钝化层的厚度范围为 700A〜2000A。 较佳地， 钝化层对应的反 应气体可以为 Si¾、 ΝΗ^Π Ν2的混合气体， 或者为 Si¾Cl2、 ΝΗ^Π Ν2的混 合气体， 钝化层的材料包括氧化物、 氮化物或者氧氮化合物中的一种。
例如， 以形成图 2中的过孔为例， 在第二金属层上形成包括过孔的钝化 层的平面图如图 9Ε所示， 其中， 源极遥过过孔与像素电极迸行电性连接， 并 且图 9Ε中 C C ' 向剖面图如图 9F所示。
较佳地， 在歩骤 805中， 在钝化层上形成通过过孔与源极进行电性连接 的像素电极， 包括： 通过溅射或热蒸发方法， 在钝化层上沉积透明导电层； 以及对透明导电层迸行刻蚀， 在像素区域形成通过过孔与源极进行电性连接 的像素电极。
具体实施中， 透明导电层的实施方式与现有技术中透明导电层的实施方 式类似。
较佳地， 透明导电层的厚度范围为 300Α〜600Α。 较佳地， 透明导电层的 材料包括氧化铟锡、 氧化铜锌和氧化铝锌中的一种或多种。
例如， 以形成图 2中的像素电极为例， 在钝化层上形成遥过过孔与源极 进行电性连接的像素电极的平面图如图 9G所示， 并且图 9G中 D- D' 向剖面 图如图 9Η所示。
尽管已描述了本发明的优选实施例， 但本领域内的技术人员一旦得知了 基本创造性概念， 则可对这些实施例作出另外的变更和修改。 所以， 所^权 利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然， 本领域的技术人员可以对本发明进行各种改动和变型而不脱离本 发明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。

Claims

1. 一种阵列基板， 包括薄膜晶体管， 所述薄膜晶体管包括源极、栅极和漏 极，所述栅极位于第一金属层，所述源极和漏极位于第二金属层，其特征在于， 所述源极和栅极的形状满足： 在所述第一金属层与第二金属层之间产生错 位的情况下， 所述源极和栅极的交叠面积恒定不变。
2. 如权利要求 1所述的阵列基板，其特征在于，所述源极包括与栅极的交 叠区域、 以及在与栅线平行的方向上分别位于所述栅极两侧的第一部分区域和 第二部分区域；
在所述第一金属层与第二金属层之间产生错位的情况下，所述第一部分区 域的增 /减底面积与所述第二部分区域的减 /增底面积相等。
3. 如权利要求 2所述的阵列基板， 其特征在于， 所述第一部分区域、 第二 部分区域和与栅极的交叠区域组成的图案包括开口朝向与栅线平行的方向的
"U"字形图案和与所述 "U"字形图案的封闭边连接 i横向放置的 "L"字形 图案；
其中， 所述第一部分区域位于所述 "U"字形的一侧边延伸出所述栅极的 位置处， 或位于所述 " U"字形的两个侧边延伸出所述栅极的位置处， 所述第 二部分区域位于所述 "L"字形延伸出所述栅极的位置处。
4. 如权利要求 2所述的阵列基板， 其特征在于， 所述第一部分区域、第二 部分区域和源极与栅极的交叠区域组成的图案为类似 "士" 字形的图案；
其中， 所述第一部分区域位于所述 "士"字形的第一边和 /或第二边在与栅 线平行的第一方向上延伸出所述栅极的位置处； 以及
所述第二部分区域位于所述 "士 "字形的第一边和 /或第二边在与第一方向 相反的第二方向上延伸出所述栅极的位置处， 所述第一边与第二边相互平行。
5. 如权利要求 2〜4任一所述的阵列基板，其特征在于，还包括与所述漏极 连接的数据线，所述第一部分区域和第二部分区域与所述数据线之间的最小距 离值不小于设定的阐值， 所述设定的阈值在 5μηι- 1 Ομηι范围内。
6. 如权利要求 1所述的阵列基板，其特征在于，所述栅极包括相互分开的 第一部分区域和第二部分区域， 所述源极包括与所述第一部分区域交叠的第三 部分区域和与所述第二部分区域交叠的第四部分区域； 在所述第一金属层与第二金属层之间产生错位的情况下，所述第三部分区 域的增 /减底面积与所述第四部分区域的减 /增底面积相等。
7. 如权利要求 6所述的阵列基板，其特征在于，所述源极的图案为由所述 第三部分区域、第四部分区域和位于所述第一部分区域和第二部分区域之间的 区域组成的类似倒 "T"字形的图案；
其中， 所述第三部分区域位于所述懷 "T"字形在与栅线平行的第一方向 上与所述第一部分区域交叠的位置处， 所述第四部分区域位于所述倒 "T "字 形在与所述第一方向相反的第二方向上与所述第二部分区域交叠的位置处。
8. 一种显示装置，其特征在于，包括如权利要求 1〜7任一项所述的阵列基 板。
9. 一种如权利要求 1 -7 中任一项所述的阵列基板的制作方法， 其特征在 于， 该方法包括：
在衬底基板上形成栅极， 其中所述栅极位于第一金属层；
在所述衬底基板上形成覆盖所述栅极的栅极绝缘层； 以及
在所述栅极绝缘层上依次形成有源层、 以及位于所述有源层上的源极和漏 极， 其中所述源极和漏极位于第二金属层，
其中， 在所述第一金属层与第二金属层之间产生错位的情况下， 所述源极 和栅极的交叠面积恒定不变。
PCT/CN2013/089974 2013-07-23 2013-12-19 一种阵列基板及其制作方法、显示装置 WO2015010431A1 (zh)

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