WO2015000248A1 - 芯片的邦定方法及芯片邦定结构 - Google Patents

芯片的邦定方法及芯片邦定结构 Download PDF

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Publication number
WO2015000248A1
WO2015000248A1 PCT/CN2013/087438 CN2013087438W WO2015000248A1 WO 2015000248 A1 WO2015000248 A1 WO 2015000248A1 CN 2013087438 W CN2013087438 W CN 2013087438W WO 2015000248 A1 WO2015000248 A1 WO 2015000248A1
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Prior art keywords
substrate
chip
reserved area
absorbing structure
energy
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English (en)
French (fr)
Inventor
权宁万
姜太声
李�瑞
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Beijing BOE Optoelectronics Technology Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/692—Ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07332—Compression bonding, e.g. thermocompression bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/074—Connecting or disconnecting of anisotropic conductive adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/381—Auxiliary members
    • H10W72/387—Flow barriers

Definitions

  • Embodiments of the present invention relate to a bonding method of a chip and a chip bonding structure. Background technique
  • the current small-size liquid crystal display product basically uses a chip bonding process for fixing a chip (Chip On Glass, COG) on a substrate to drive the liquid crystal display panel, for example, forming a bump on the chip. After that, it is directly connected to the lead of the liquid crystal display on the substrate.
  • a chip bonding process for fixing a chip (Chip On Glass, COG) on a substrate to drive the liquid crystal display panel, for example, forming a bump on the chip. After that, it is directly connected to the lead of the liquid crystal display on the substrate.
  • COG Chip On Glass
  • the high temperature indenter first contacts the chip, and the heat is conducted to the anisotropic conductive paste and the substrate through the chip. At this time, the temperature difference between the chip and the substrate is large, causing a difference in the expansion size between the two.
  • the anisotropic conductive paste is cured, the relative position between the chip and the substrate is fixed.
  • the chip and the substrate are cooled down, and the chip shrinks to a larger size than the substrate, so that the opposite ends of the chip generate a larger pair of substrates.
  • the stress causes the chip and substrate to warp.
  • the warpage of the chip and the substrate may cause chip peeling, chip breakage, and display effects such as uneven brightness.
  • Embodiments of the present invention provide a chip bonding method and a chip bonding structure capable of preventing warpage of a chip and a substrate.
  • An aspect of the invention provides a bonding method for a chip, comprising: providing an energy absorbing structure on a substrate, the energy absorbing structure being located beside a reserved area of the substrate, wherein the reserved area is for placing a chip; The chip is bonded within the reserved area on the substrate.
  • the energy absorbing structure may be symmetrically located on both sides of the reserved area.
  • the energy absorbing structure may include a groove or a through hole.
  • the providing an energy absorbing structure on the substrate may include: The substrate is etched, and an energy absorbing structure is disposed on the substrate.
  • the method before the chip is bonded in the reserved area on the substrate, the method further includes: coating an anisotropic conductive paste on the reserved area.
  • a chip bonding structure comprising: a substrate and a chip disposed on the substrate, the two sides of the substrate are provided with an energy absorbing structure, the energy absorbing structure is located outside the reserved area of the substrate, The chip is disposed on the reserved area.
  • the energy absorbing structure may be symmetrically located on both sides of the reserved area.
  • the energy absorbing structure may be a groove or a through hole provided on the substrate.
  • an anisotropic conductive paste is coated on the reserved area, and the chip is disposed on the anisotropic conductive paste, and the chip and the reserved area are set by the anisotropic conductive adhesive.
  • the metal wire is turned on.
  • FIG. 1 is a schematic flow chart of a bonding method of a chip according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of a substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a substrate in an embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a substrate in an embodiment of the present invention.
  • FIG. 5 is a schematic structural view of a substrate according to an embodiment of the present invention.
  • One embodiment of the present invention provides a bonding method for a chip. As shown in FIG. 1, the bonding method for a chip can be performed as follows.
  • Step S101 An energy absorbing structure is disposed on the substrate, the energy absorbing structure is located beside a reserved area of the substrate, and the reserved area is used for placing a chip.
  • an energy absorbing structure 2 is disposed on the substrate 1.
  • the energy absorbing structure 2 can be placed next to the reserved area 3 reserved for the placement of the chip by the substrate 1, with a predetermined distance d therebetween.
  • the predetermined distance d can be determined as needed.
  • the size of the energy absorbing structure 2 can be determined according to the bonding temperature, the thickness of the substrate 1, and the combined IC size to obtain a better effect.
  • Step S102 Bond the chip in the reserved area on the substrate.
  • the reserved area of the substrate 1 is located on two adjacent edge sides of the substrate 1, and the width of the coated anisotropic conductive paste 5 and the edges of the anisotropic conductive paste 5 and the substrate 1 are different according to the model of the different substrate 1. The distance between them is different. For example, for a rectangular substrate 1 of about 64 inches, the width of the anisotropic conductive paste 5 is 1.0 mm, which is 0.5 mm from the edge of the substrate 1; the thickness of the coated anisotropic conductive paste 5 may be about 0.3 mm to 0.5. Mm.
  • the anisotropic conductive paste 5 mainly comprises two parts of a resin adhesive and conductive particles.
  • the resin adhesive is mainly used to bond the chip 4 on the substrate 1, fix the relative position of the electrode between the chip 4 and the substrate 1, and provide a pressing force to maintain the electrode.
  • Contact area with conductive particles may be metal particles or resin particles whose surface is coated with, for example, carbon.
  • the high temperature indenter 6 first contacts the chip 4, and the heat is transmitted to the anisotropic conductive paste 5 and the substrate through the chip 4. 1.
  • the ductility of the substrate 1 is not as good as that of the chip 4, resulting in a difference in the expansion size between the substrate 1 and the chip 4.
  • the anisotropic conductive paste 5 is cured, the relative position between the chip 4 and the substrate 1 is fixed.
  • the chip 4 and the substrate 1 are cooled down, and the chip 4 is shrunk to a larger size than the substrate 1, so that the chip 4 is Both ends generate a large stress on the substrate 1.
  • the energy absorbing structure 2 on the substrate 1 can absorb the stress generated by the chip 4 on the substrate 1 to prevent the chip 4 and the substrate 1 from warping, thereby preventing the chip 4 from being peeled off, the chip 4 being broken, and the display effect being uneven. The occurrence of adverse consequences.
  • a bonding method of a chip is provided.
  • the energy absorbing structure can absorb the chip on the substrate during the cooling process by providing an energy absorbing structure on the substrate beside the reserved area where the chip is placed.
  • the generated stress causes the chip and the substrate to be flat after the cooling is completed, thereby preventing warpage of the chip and the substrate, thereby preventing the occurrence of adverse effects such as chip peeling, chip breakage, and display unevenness.
  • the stress of the chip 4 on the substrate 1 is located at opposite ends of the chip 4, in order to enable the energy absorbing structure 2 to better absorb the stress of the chip 4 on the substrate 1, preferably, as shown in FIG. 1 or 2.
  • the energy absorbing structure 2 is symmetrically located on both sides of the reserved area 3.
  • the energy absorbing structure 2 can be disposed as a groove in the surface of the substrate 1 on which the chip is disposed, for example, a groove having a trapezoidal cross section, and the cross section of the groove can also be set as a rectangle, a semicircle, or the like.
  • the size, shape, and the like of the groove can be set according to actual conditions.
  • the planar pattern of the energy absorbing structure 2, which is set as a groove for example, may be rectangular or other shapes such as a triangle, an ellipse, a wave, an irregular figure or the like.
  • the energy absorbing structure 2 may also be a through hole or other structure, such as a circular or rectangular through hole, which is not limited in the embodiment of the present invention.
  • the energy absorbing structure 2 is a groove or a through hole
  • a suitable energy absorbing structure 2 can be disposed on the substrate 1 by etching the substrate 1.
  • the energy absorbing structure 2 is a groove formed on the same side of the substrate 1 as the chip 4, or may be formed on the opposite side of the substrate 1 from the chip 4.
  • the substrate 1 may be a glass substrate, a quartz substrate or the like.
  • the embodiment of the present invention further provides a chip bonding structure, comprising a substrate 1 and a chip 4 disposed on the substrate 1.
  • the substrate 1 is provided with an energy absorbing structure 2 on both sides thereof, and the energy absorbing structure 2 is located on the substrate.
  • the chip 4 is disposed on the outside of the reserved area 3.
  • the energy absorbing structure 2 is symmetrically located on both sides of the reserved area 3, for example.
  • the energy absorbing structure 2 is, for example, a groove or a through hole provided on the substrate 1.
  • the anisotropic conductive paste 5 is coated on the reserved area 3, and the chip 4 is disposed on the anisotropic conductive paste 5, and the metal disposed on the chip 4 and the reserved area 3 is passed through the anisotropic conductive adhesive 5. The line is turned on.

Landscapes

  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

一种芯片的邦定方法以及芯片邦定结构。该邦定方法包括在基板（1）上设置吸能结构（2），吸能结构（2）位于基板（1）的预留区域（3）旁，预留区域（3）用于设置芯片（4）；将芯片（4）邦定在基板（1）上的预留区域（3）内。该邦定结构包括基板（1）及设置于基板（1）上的芯片（4），基板（1）的两侧设置有吸能结构（2），吸能结构（2）位于基板（1）的预留区域（1）外侧，预留区域（1）上设置芯片（4）。

Description

芯片的邦定方法及芯片邦定结构 技术领域
本发明的实施例涉及一种芯片的邦定方法及芯片邦定（bonding )结构。 背景技术
为了更好的降低成本， 目前小尺寸液晶显示产品基本采用将芯片 （Chip On Glass, COG )固定于基板上的芯片邦定工艺方法对液晶显示面板进行驱 动， 例如为在棵芯片上形成凸点后， 在基板上直接与液晶显示屏的引线相连 接。
在 COG邦定工艺过程中， 当对 IC进行热压（主压）时， 高温的压头先 接触到芯片， 通过芯片将热量传导到各向异性导电胶和基板。 此时， 芯片与 基板的温度差异较大， 造成两者之间膨胀尺寸有差异。 各向异性导电胶固化 后， 芯片与基板之间的相对位置就固定下来， 主压结束后， 芯片和基板冷却 下来， 芯片收缩的尺寸比基板大，使得芯片的两端产生较大的对基板的应力， 这样就导致芯片和基板产生翘曲。 而芯片和基板产生翘曲会导致芯片剥离、 芯片断裂、 显示效果明暗不均等不良后果。
目前解决芯片和基板翘曲的问题主要采用低温各向异性导电胶（ ACF ) 产品， 但是目前该产品价格昂贵， 而且技术不成熟。 发明内容
本发明的实施例提供了一种芯片的邦定方法及芯片邦定结构， 能够防止 芯片和基板发生翘曲。
本发明的一个方面提供了一种芯片的邦定方法， 包括： 在基板上设置吸 能结构， 所述吸能结构位于所述基板的预留区域旁， 所述预留区域用于放置 芯片； 将所述芯片邦定在所述基板上的所述预留区域内。
例如， 在该方法中， 所述吸能结构可以对称位于所述预留区域两侧。 例如， 在该方法中， 所述吸能结构可以包括凹槽或通孔。
例如， 在该方法中， 所述在基板上设置吸能结构可以包括： 通过对所述 基板进行刻蚀， 在所述基板上设置吸能结构。
例如， 在该方法中， 将所述芯片邦定在所述基板上的所述预留区域内之 前， 还可以包括： 在所述预留区域上涂布各向异性导电胶。
本发明的另一个方面还提供一种芯片邦定结构， 包括基板及设置于基板 上的芯片， 该基板的两侧设置有吸能结构， 该吸能结构位于所述基板的预留 区域外侧， 所述预留区域上设置该芯片。
例如， 该芯片邦定结构中， 所述吸能结构可以对称位于所述预留区域两 侧。 所述吸能结构可以为在基板上设置的凹槽或通孔。
例如， 该芯片邦定结构中， 在所述预留区域上涂布有各向异性导电胶， 该芯片设置于各向异性导电胶上， 通过各向异性导电胶使得芯片和预留区域 上设置的金属线导通。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例中的芯片的邦定方法流程示意图；
图 2为本发明实施例中的一种基板结构示意图；
图 3为本发明实施例中的一种基板结构示意；
图 4为本发明实施例中的一种基板结构示意；
图 5为本发明实施例中的一种基板结构示意。
附图标记说明：
1一基板； 2—吸能结构； 3—预留区域；
4一芯片； 5—各向异性导电胶； 6—压头。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。 本发明的一个实施例提供一种芯片的邦定方法， 如图 1所示， 该用于芯 片的邦定方法可以如下进行。
步骤 S101、在基板上设置吸能结构， 所述吸能结构位于所述基板的预留 区域旁， 所述预留区域用于放置芯片。
如图 2所示， 基板 1上设置有吸能结构 2。 为了使得吸能结构 2能够充 分吸收芯片的两端对基板 1的应力， 吸能结构 2可以放置在基板 1为了放置 芯片而预留出来的预留区域 3旁， 二者间隔预定距离 d。 该预定距离 d可以 根据需要确定。 吸能结构 2的尺寸可以根据邦定的温度、 基板 1的厚度和结 合的 IC尺寸确定以获得更好的效果。
步骤 S102、 将所述芯片邦定在所述基板上的所述预留区域内。
在将所述芯片 4邦定在所述基板 1上的所述预留区域 3之前， 还需要在 所述预留区域 3上涂布各向异性导电胶 5。
通常， 基板 1的预留区域位于基板 1相邻的两个边缘侧， 根据不同基板 1的型号，涂覆的各向异性导电胶 5的宽度、以及各向异性导电胶 5与基板 1 边缘之间的距离都有所不同。 例如， 对于约 64寸的矩形的基板 1 , 各向异性 导电胶 5的宽度为 1.0mm, 距离基板 1边缘为 0.5mm; 涂覆的各向异性导电 胶 5的厚度可以约为 0.3mm~0.5mm。
各向异性导电胶 5主要包括树脂黏着剂、 导电粒子两大部分。 树脂黏着 剂的功能除了防湿气、 黏着、 耐热及绝缘功能外， 主要用于将芯片 4邦定在 基板 1上， 固定芯片 4与基板 1间电极的相对位置， 并提供压迫力量以维持 电极与导电粒子间的接触面积。 例如， 导电粒子可以是金属颗粒或表面包覆 例如碳的树脂颗粒。
之后， 在邦定芯片 4到基板 1的预留区域 3的过程中， 进行主压时， 高 温的压头 6先接触到芯片 4, 通过芯片 4将热量传导到各向异性导电胶 5和 基板 1。 此时， 受到材料限制， 基板 1的延展性没有芯片 4好， 造成基板 1 和芯片 4之间膨胀尺寸有差异。 各向异性导电胶 5固化后， 芯片 4与基板 1 之间的相对位置就固定下来， 主压结束后， 芯片 4和基板 1冷却下来， 芯片 4收缩的尺寸比基板 1大， 使得芯片 4的两端产生较大的对基板 1的应力。 基板 1上的吸能结构 2能够吸收芯片 4对基板 1产生的应力， 防止芯片 4和 基板 1产生翘曲， 进而防止芯片 4剥离、 芯片 4断裂、 显示效果明暗不均等 不良后果的产生。
在本实施例的技术方案中， 提供了一种芯片的邦定方法， 通过在基板上 设置位于放置芯片的预留区域旁的吸能结构， 吸能结构能够吸收芯片在冷却 过程中对基板所产生的应力， 使得冷却结束后芯片和基板都较为平整， 防止 芯片和基板产生翘曲， 进而防止芯片剥离、 芯片断裂、 显示效果明暗不均等 不良后果的产生。
进一步的， 通常芯片 4对基板 1的应力位于芯片 4的彼此相对的两端， 为了使得吸能结构 2能够更好地吸收芯片 4对基板 1的应力， 优选的， 如图 1或 2所示， 吸能结构 2对称位于所述预留区域 3两侧。
如图 3或 4所示， 吸能结构 2可设置为在基板 1设置芯片的表面中的凹 槽， 例如截面为梯形的凹槽， 凹槽的截面也可设置为矩形、 半圓形等， 所述 凹槽的尺寸、 形状等都可根据实际情况设置。 如图 2所示， 例如设置为凹槽 的吸能结构 2的平面图形可以为矩形， 也可以其他形状， 例如三角形、 橢圓 形、 波浪形、 不规则图形等。
另外， 如图 5所示， 吸能结构 2也可以为通孔或其他结构， 例如圓形或 矩形的通孔， 本发明实施例对此不进行限制。
当吸能结构 2为凹槽或通孔时， 可以通过对所述基板 1进行刻蚀， 在所 述基板 1上设置合适的吸能结构 2。 如图 4所示， 吸能结构 2为凹槽， 该凹 槽形成在基板 1与芯片 4相同一侧，也可以形成在基板 1与芯片 4相反一侧。
在本发明的实施例中， 基板 1可为玻璃基板、 石英基板等。
本发明的实施例还提供一种芯片邦定结构， 包括基板 1及设置于基板 1 上的芯片 4,该基板 1的两侧设置有吸能结构 2,该吸能结构 2位于所述基板 的预留区域 3外侧， 所述预留区域 3上设置该芯片 4。
进一步的， 所述吸能结构 2例如对称地位于所述预留区域 3两侧。 所述 吸能结构 2例如为在基板 1上设置的凹槽或通孔。 在所述预留区域 3上涂布 有各向异性导电胶 5 , 该芯片 4设置于各向异性导电胶 5上， 通过各向异性 导电胶 5使得芯片 4和预留区域 3上设置的金属线导通。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种芯片的邦定方法， 包括：
在基板上设置吸能结构， 所述吸能结构位于所述基板的预留区域旁， 所 述预留区域用于设置芯片；
将所述芯片邦定在所述基板上的所述预留区域内。
2、 ^据权利要求 1所述的芯片的邦定方法， 其中， 所述吸能结构位于所 述基板的预留区域旁包括：
所述吸能结构对称位于所述预留区域两侧。
3、 根据权利要求 1或 2所述的芯片的邦定方法， 其中，
所述吸能结构为 槽或通孔。
4、根据权利要求 3所述的芯片的邦定方法， 其中， 所述在基板上设置吸 能结构包括：
通过对所述基板进行刻蚀， 在所述基板上设置吸能结构。
5、 根据权利要求 1-4任一所述的芯片的邦定方法， 其中， 所述将所述芯 片邦定在所述基板上的所述预留区域内之前， 还包括：
在所述预留区域上涂布各向异性导电胶。
6、一种芯片邦定结构， 包括基板及设置于基板上的芯片， 该基板的两侧 设置有吸能结构， 该吸能结构位于所述基板的预留区域外侧， 所述预留区域 上设置该芯片。
7、根据权利要求 6所述的芯片邦定结构， 其中， 所述吸能结构对称位于 所述预留区域两侧。
8、根据权利要求 6或 7所述的芯片邦定结构， 其中， 所述吸能结构为在 基板上设置的凹槽或通孔。
9、 根据权利要求 6-8任一所述的芯片邦定结构， 其中， 在所述预留区域 上涂布有各向异性导电胶， 所述芯片设置于各向异性导电胶上， 通过各向异 性导电胶使得芯片和预留区域上设置的金属线导通。
PCT/CN2013/087438 2013-07-04 2013-11-19 芯片的邦定方法及芯片邦定结构 Ceased WO2015000248A1 (zh)

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