WO2014207793A1 - Dispositif à semi-conducteurs et son procédé de fabrication - Google Patents

Dispositif à semi-conducteurs et son procédé de fabrication Download PDF

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WO2014207793A1
WO2014207793A1 PCT/JP2013/067176 JP2013067176W WO2014207793A1 WO 2014207793 A1 WO2014207793 A1 WO 2014207793A1 JP 2013067176 W JP2013067176 W JP 2013067176W WO 2014207793 A1 WO2014207793 A1 WO 2014207793A1
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silicon carbide
region
carbide region
semiconductor device
gate electrode
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PCT/JP2013/067176
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English (en)
Japanese (ja)
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三江子 松村
大輔 松元
悠佳 清水
浩孝 濱村
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株式会社日立製作所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, for example, a semiconductor device provided with a trench gate type field effect transistor (Metal Oxide Semiconductor Field Effect Transistor: hereinafter abbreviated as MOSFET) on a silicon carbide (SiC) substrate and a manufacturing method thereof. It is related to effective technology.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • SiC-MOSFETs MOSFETs using SiC substrates
  • SiC has a higher dielectric breakdown strength than silicon (Si)
  • SiC-MOSFET SiC-MOSFETs are also being applied to high-voltage semiconductor devices that could not withstand using a Si substrate.
  • vertical power MOSFET structures include a planar structure called a DMOSFET (Double Diffusion MOSFET) and a trench structure called a UMOSFET (U-shape MOSFET).
  • DMOSFET Double Diffusion MOSFET
  • UMOSFET U-shape MOSFET
  • the trench structure has the advantage that the device arrangement can be increased in density and the on-resistance can be reduced because there is no resistance due to a parasitic junction field effect transistor (JFET) that occurs when the trench structure is not used.
  • JFET parasitic junction field effect transistor
  • avalanche breakdown is likely to occur near the gate insulating film, and gate dielectric breakdown is likely to occur. Therefore, as a countermeasure against gate dielectric breakdown, a second body region having a deeper impurity concentration than the drift layer and deeper than the bottom of the trench gate is disposed in the center between the plurality of trench gates, thereby allowing avalanche breakdown to occur at the trench gate.
  • a method of keeping away from see, for example, Patent Document 1.
  • Patent Document 1 the on-state current path is narrowed due to the influence of the second body region, and the on-resistance becomes high.
  • a method has been proposed in which a high concentration region having a higher impurity concentration than the drift layer is partially disposed in a region sandwiched between the trench gate and the second body region (for example, Patent Documents). 2).
  • the above-described high concentration region is useful for widening the current path and lowering the on-resistance, but when applied to a high voltage semiconductor device, the high concentration region induces channel punch-through when the element is in an off state.
  • the present inventor found for the first time that there is a problem.
  • An object of the present invention is to provide a technique capable of suppressing or preventing channel punch-through in a semiconductor device in which a trench gate type field effect transistor is provided on a silicon carbide substrate.
  • a semiconductor device penetrates through a second conductivity type second silicon carbide region provided on a first conductivity type first silicon carbide region on a first conductivity type silicon carbide substrate.
  • a trench gate type field effect transistor having a gate electrode provided through a gate insulating film in a trench having a depth terminating in the first silicon carbide region, wherein the second carbonization is provided at a position spaced from the gate electrode;
  • a fifth conductivity type fifth silicon carbide region extending from the bottom end of the silicon region toward the silicon carbide substrate and terminating at a position deeper than the bottom of the gate electrode in the first silicon carbide region;
  • the first silicon carbide region between the side surface of the gate electrode and the side end portion of the fifth silicon carbide region on the opposite side thereof and between the bottom of the gate electrode and the silicon carbide substrate.
  • the first silicon carbide provided A sixth silicon carbide region of the first conductivity type, which is set to a higher impurity concentration than pass, those with a.
  • a method for manufacturing a semiconductor device comprising: a second conductivity type second silicon carbide provided on a first conductivity type first silicon carbide region on a first conductivity type silicon carbide substrate; A trench gate type field effect transistor having a gate electrode provided through a gate insulating film in a trench having a depth penetrating the region and terminating at the first silicon carbide region, at a position spaced from the gate electrode A second conductivity type fifth element extending from the bottom end of the second silicon carbide region toward the silicon carbide substrate and terminating at a position deeper than the bottom of the gate electrode in the first silicon carbide region.
  • the first silicon carbide region of Provided, those having the steps of forming a sixth silicon carbide region of the first conductivity type is set to a higher impurity concentration than the first silicon carbide region.
  • channel punch-through can be suppressed or prevented in a semiconductor device in which a trench gate type field effect transistor is provided on a silicon carbide substrate.
  • FIG. 2 is a cross-sectional view taken along line II of the semiconductor device of FIG. 1.
  • FIG. 3 is a graph showing calculated values of impurity concentration profiles along the line II-II in FIG. 2.
  • FIG. 3 is a graph showing calculated values of an impurity concentration profile along the line III-III in FIG. 2. It is principal part sectional drawing of a semiconductor device when there is no 2nd body area
  • FIG. 3 is an enlarged cross-sectional view of a main part of the semiconductor device of FIG. 2. It is a graph which shows the x dependence of the electric field value Eox added to the gate insulating film of the bottom corner
  • region The value obtained by subtracting the potential at the boundary between the first body region and the drift layer in the off state when there is no high concentration region from the potential at the boundary between the first body region and the drift layer in the off state when the high concentration region exists.
  • FIG. 3 is an enlarged cross-sectional view of a main part of the semiconductor device of FIG. 2.
  • FIG. 3 is an enlarged cross-sectional view of a main part of the semiconductor device of FIG. 2.
  • It is a graph which shows the relationship between the impurity concentration of a high concentration area
  • It is a graph which shows the relationship between the impurity concentration of a high concentration area
  • FIG. 25 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 24;
  • FIG. 26 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 25;
  • FIG. 27 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 26;
  • FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27;
  • FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28;
  • FIG. 30 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 29;
  • FIG. 31 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 30; It is principal part sectional drawing of the unit element area
  • FIG. 1 is a plan view of a unit element region of the semiconductor device according to the first embodiment
  • FIG. 2 is a cross-sectional view taken along line II of the semiconductor device of FIG.
  • the power MOSFET which is the semiconductor device of the first embodiment, is a trench gate type SiC-MOSFET designed to handle a large amount of power, and is used, for example, for power conversion and control of power equipment.
  • the present invention is applied to an n-channel MOSFET in which n-type and p-type are interchanged.
  • the n-type (first conductivity type) SiC region contains, for example, nitrogen (N) or phosphorus (P)
  • the p-type (second conductivity type) SiC region includes Contains, for example, boron (B) or aluminum (Al).
  • the substrate (first conductivity type silicon carbide substrate) 1 is made of, for example, n + -type SiC, and has a first surface (upper surface in FIG. 1) and a second surface on the back side (lower surface in FIG. 1). And have.
  • An epitaxial layer EP is provided on the first surface of the substrate 1.
  • the epitaxial layer EP is made of, for example, n-type SiC.
  • a drift layer (first silicon carbide region) 2 is provided in contact with the substrate 1 in the lowermost layer of the epitaxial layer EP (on the first surface of the substrate 1).
  • the drift layer 2 is made of, for example, n-type SiC, and its impurity concentration is set lower than that of the substrate 1.
  • the withstand voltage against the high voltage of the power MOSFET is set to be high.
  • a first body region (second silicon carbide region) 3 a is provided on the drift layer 2 in contact with the drift layer 2.
  • the first body region 3a is made of p-type SiC, for example.
  • a groove 4 is formed on the epitaxial layer EP.
  • the grooves 4 are formed in a lattice shape, for example.
  • the planar shape of the groove 4 is not limited to a lattice shape, and can be variously changed.
  • a stripe shape may be used.
  • channel 4 was a square shape was illustrated, it is not limited to this, A various change is possible, for example, a hexagon shape may be sufficient.
  • the trench 4 extends from the upper surface of the epitaxial layer EP through the first body region 3 a and extends to a middle position in the depth direction of the drift layer 2 and terminates.
  • the cross-sectional shape of the groove 4 is rectangular is illustrated, but the present invention is not limited to this, and various modifications are possible, and it may be U-shaped or V-shaped.
  • a gate electrode 6G is formed inside the groove 4 with a gate insulating film 5 interposed therebetween.
  • the gate insulating film 5 is made of, for example, silicon oxide (SiO 2 ) and is formed so as to cover the inner surface (side surface and bottom surface) of the groove 4.
  • the thickness of the gate insulating film 5 is, for example, 10 to 100 nm.
  • the gate electrode 6G is made of, for example, low resistance polysilicon doped with P.
  • Each region surrounded by the groove 4 is a unit element region.
  • p + type body contact region (third silicon carbide region) 3b and n + type source region (fourth silicon carbide region) 7S are adjacent to first body region 3a. Is provided.
  • the body contact region 3b is formed of, for example, p + type SiC. As shown in FIG. 1, the body contact region 3 b is provided substantially at the center of the unit element region so as to be separated from the groove 4. As shown in FIG. 2, the body contact region 3b is provided in contact with the upper portion of the first body region 3a and is electrically connected to the first body region 3a.
  • the source region 7S is made of, for example, n + type SiC. As shown in FIG. 1, the source region 7 ⁇ / b> S surrounds the body contact region 3 b and is formed in a frame shape so that the outer periphery thereof is in contact with the groove 4. Further, as shown in FIG. 2, the source region 7S is provided in contact with the upper portion of the first body region 3a.
  • a p + -type second body region (fifth silicon carbide region) 3c is provided in a state of being electrically connected to the first body region 3a immediately below the body contact region 3b. ing.
  • the second body region 3c is provided substantially at the center of the unit element region.
  • the planar dimension of the second body region 3c is formed to be larger than the planar dimension of the body contact region 3b.
  • the second body region 3 c extends from the lower portion of the first body region 3 a toward the substrate 1 to a position deeper than the bottom of the groove 4, and does not reach the substrate 1. 2 is formed so as to terminate at an intermediate position in the depth direction.
  • a high concentration region (sixth silicon carbide region) 8 is provided in drift layer 2 on the lower side of second body region 3c.
  • the high concentration region 8 is formed of, for example, n + -type SiC, and is between the side surface of the gate electrode 6G and the side portion of the second body region 3c opposite to the gate electrode 6G, and the bottom end portion of the gate electrode 6G And in the state where it is in contact with the second body region 3 c in the drift layer 2 between the substrate 1 and the substrate 1.
  • the high concentration region 8 at the above position, it is possible to suppress or prevent punch-through from occurring in the channel of the SiCMOSFET even when a high voltage is applied between the source and the drain when the SiCMOSFET is in the OFF state. be able to.
  • An interlayer insulating film 9 is deposited on the upper surface of the epitaxial layer EP via the gate insulating film 5 as shown in FIG.
  • the interlayer insulating film 9 is formed of, for example, silicon oxide (SiO 2 ), and the surface of the gate electrode 6G outside the trench 4 is covered with the interlayer insulating film 9.
  • a source body contact common electrode (hereinafter simply referred to as a common electrode) 10 is formed on the interlayer insulating film 9.
  • the common electrode 10 is formed of a metal such as nickel (Ni), for example, and is electrically connected to both the body contact region 3b and the source region 7S through contact holes formed in the interlayer insulating film 9 and the gate insulating film 5. It is connected.
  • a surface protective film 12 is deposited on the interlayer insulating film 9 so as to cover the common electrode 10.
  • the surface protective film 12 is formed of, for example, a single film of silicon oxide (SiO 2 ) or a laminated film of silicon oxide and silicon nitride.
  • the drain contact electrode 14 is electrically connected to the second surface side of the substrate 1.
  • a power MOSFET when a positive voltage is applied to the gate electrode 6G with a voltage applied between the source region 7S and the substrate 1, the gate on the side surface of the gate electrode 6G in the first body region 3a. A portion adjacent to the insulating film 5 is inverted, and a drain current flows from the source region 7 ⁇ / b> S toward the substrate 1.
  • the drain region of the power MOSFET is composed of the substrate 1, the drift layer 2, and the high concentration region 8.
  • FIG. 3 and FIG. 4 show calculated values of impurity concentration profiles on the II-II line and the III-III line of FIG. 2, respectively.
  • the horizontal axis Dep indicates the depth
  • the vertical axis Con indicates the impurity concentration.
  • 3 and 4 indicate the total impurity concentration profile.
  • 3 and 4 indicate the high concentration region 8 and the alternate long and short dash line indicates the impurity concentration profile of the drift layer 2, respectively.
  • the two-dot chain line in FIG. 4 shows the impurity concentration profile of the second body region 3c.
  • the impurity concentration (broken line) in the high concentration region 8 is set higher than the impurity concentration (dashed line) in the drift layer 2.
  • the impurity concentration (broken line) in the high concentration region 8 is set to be lower than the impurity concentration (two-dot chain line) in the second body region 3c. . Thereby, even if the high concentration region 8 overlaps the second body region 3c, the second body region 3c is left.
  • the impurity concentration profile of the first body region 3a As shown in FIG. 4, the impurity concentration (two-dot chain line) of the second body region 3c is set higher than the impurity concentration (dotted line) of the first body region 3a.
  • the thin solid line in FIG. 3 shows the impurity concentration profile of the source region 7S.
  • the impurity concentration of the source region 7S and the body contact region 3b is set higher than the impurity concentration of the first body region 3a.
  • FIG. 5 is a cross-sectional view of the main part of the semiconductor device when there is no second body region
  • FIG. 6 is a cross-sectional view of the semiconductor device when there is a second body region.
  • 5 and 6 are cross-sectional views, but some hatchings are omitted for easy understanding of the drawings.
  • the arrows in FIGS. 5 and 6 schematically show the electric field.
  • the electric field is dispersed in the second body region 3c even when a high voltage is applied between the source and the drain.
  • the concentration in the vicinity of the bottom of the groove 4 can be suppressed or prevented. For this reason, damage and destruction of the gate insulating film 5 can be suppressed or prevented.
  • FIGS. 7 and 8 are cross-sectional views, but some hatchings are omitted for easy understanding of the drawings.
  • the arrows in FIGS. 7 and 8 schematically show the current distribution.
  • the extension of the depletion layer from the side of the second body region 3c toward the channel is suppressed, The current that has passed through the channel flows so as to spread toward the high concentration region 8. For this reason, since the on-resistance of the SiC-MOSFET can be reduced, the drain current can be increased.
  • FIG. 9 is an enlarged cross-sectional view of a main part of the semiconductor device of FIG. Although FIG. 9 is a cross-sectional view, some hatching is omitted for easy understanding of the drawing.
  • the symbol x is the distance from the side surface of the gate electrode 6G to the side edge of the high concentration region 8
  • the symbol y is the distance from the bottom surface of the gate electrode 6G to the upper end of the high concentration region 8.
  • the end portions (the side end portion, the upper end portion, and the like) of the high concentration region 8 are positions where the impurity concentration value in the high concentration region 8 is 1 ⁇ 2 of the impurity concentration peak value in the high concentration region 8. .
  • 10 to 12 show the x dependence of transistor characteristics obtained by device simulation.
  • the calculation of the on-state was performed, for example, under the condition that the drain-source voltage was 0.05V and the gate-source voltage was 20V.
  • the calculation of the off-state was performed under the condition that, for example, the drain-source voltage was 100V and the gate-source voltage was 0V.
  • FIG. 10 shows the x dependence of the electric field value Eox applied to the gate insulating film at the bottom corner of the groove in the off state.
  • the electric field value Eox was normalized by the electric field value Eox0 when there was no high concentration region 8.
  • Eox / Eox0 shows a high value of 1 or more in a state where x ⁇ 0 ⁇ m, that is, the side end portion of the high concentration region 8 extends below the gate electrode 6G, but x> 0 ⁇ m, that is, the high concentration region 8 In the state where the side end portion of the gate electrode is separated from the side surface of the gate electrode 6G, a low value of 1 or less is shown. Therefore, by separating the side edge of the high concentration region 8 from the side surface of the gate electrode 6G, the electric field locally applied to the gate insulating film 5 can be reduced, so that gate breakdown can be suppressed or prevented. .
  • FIG. 11 shows the x dependency of the drain current Id.
  • a broken line LL indicates a lower limit value of the drain current Id.
  • the drain current Id exceeds the lower limit regardless of the distance x.
  • x ⁇ 0.3 ⁇ m, that is, in the state where the side edge of the high concentration region 8 enters below the gate electrode 6G, the drain current Id is It shows a low value. Therefore, it can be seen that it is better to separate the side end portion of the high concentration region 8 from the side surface of the gate electrode 6G from the viewpoint of drain current.
  • FIG. 12 shows the x dependency of the punch-through index.
  • the punch-through index indicates that the first body region and the drift layer in the off state when there is no high concentration region from the potential Pot at the boundary between the first body region and the drift layer in the off state when the high concentration region exists.
  • the value obtained by subtracting the potential Pot0 at the boundary (Pot-Pot0).
  • An increase in Pot-Pot0 in the positive direction indicates an increase in the channel potential and means that punch-through is easy.
  • a broken line UL indicates an upper limit value of the punch-through index.
  • FIGS. 13 to 15 show the y dependency of transistor characteristics obtained by device simulation.
  • the on-state and off-state calculation conditions are the same as described with reference to FIGS.
  • FIG. 13 shows the y dependency of the electric field value Eox applied to the gate insulating film at the bottom corner of the trench in the off state.
  • Eox / Eox0 shows a value higher than 1 when y ⁇ 0 ⁇ m, ie, the high concentration region 8 is above the bottom surface of the gate electrode 6G, but y> 0 ⁇ m, ie, the high concentration region 8 is the bottom surface of the gate electrode 6G.
  • the value is lower than 1 in a state where the distance from the center of the second body region 3c is approaching the bottom end. Therefore, by providing the high concentration region 8 so that the upper end portion of the high concentration region 8 is located below the bottom surface of the gate electrode 6G, the electric field Eox locally applied to the gate insulating film 5 can be reduced. In addition, gate breakdown can be suppressed or prevented.
  • FIG. 14 shows the y dependency of the value Ron / Ron0 obtained by normalizing the on-resistance Ron when there is a high concentration region with the on-resistance Ron0 when there is no high concentration region.
  • the value of Ron / Ron0 becomes smaller than 1 at y ⁇ 0.5 ⁇ m. Therefore, by providing the high concentration region 8 so that the upper end portion of the high concentration region 8 is located above the bottom end portion of the second body region 3c, the on-resistance can be reduced.
  • FIG. 15 shows the potential at the boundary between the first body region and the drift layer in the off state when there is no high concentration region from the potential Pot at the boundary between the first body region and the drift layer in the off state when there is a high concentration region. It shows the y dependency of a value obtained by subtracting Pot0 (Pot-Pot0).
  • An increase in Pot-Pot0 in the positive direction indicates an increase in the channel potential and means that punch-through is easy.
  • Pot-Pot0 increases rapidly when y ⁇ 0 ⁇ m, but is 0 or less when y> 0 ⁇ m. Therefore, by providing the high concentration region 8 so that the upper end of the high concentration region 8 is located below the bottom surface of the gate electrode 6G, punch-through can be suppressed or prevented.
  • FIGS. 16 and 17 are cross-sectional views, but some hatchings are omitted for easy viewing of the drawings. Further, the arrows in FIGS. 16 and 17 schematically show the electric field.
  • the electric field from the lateral direction from the high concentration region 8 toward the gate electrode 6G Concentrates on the bottom corners of the gate electrode 6G, causing gate breakdown. Further, the electric field from the high concentration region 8 toward the gate electrode 6G increases the potential of the drift layer 2 portion and the channel portion between the side end portion of the high concentration region 8 and the side surface of the gate electrode 6G. It tends to occur.
  • the upper end portion of the high concentration region 8 is located below the bottom surface of the gate electrode 6G (the bottom end portion side of the second body region 3c).
  • the electric field from the high concentration region 8 toward the gate electrode 6G is dispersed on the side surface and the bottom surface of the gate electrode 6G.
  • the electric field concentration on the bottom corner of the gate electrode 6G is alleviated, gate dielectric breakdown can be suppressed or prevented.
  • punch-through can be suppressed or prevented.
  • FIGS. 18 and 19 are enlarged cross-sectional views of the main part of the semiconductor device of FIG. 18 and 19 are cross-sectional views, but some hatchings are omitted for easy viewing of the drawings.
  • the high concentration region 8 is a region surrounded by a broken line A, that is, between the side surface of the gate electrode 6G and the side end portion of the second body region 3c opposite to the gate electrode 6G. It is preferably provided in a region between the bottom surface of the electrode 6G and the bottom end portion of the second body region 3c.
  • the side end in the radial direction of the high concentration region 8 is preferably located on the second body region 3c side from the position separated by XA / 2 from the side surface of the gate electrode 6G in order to obtain the above effect.
  • the position of the upper end portion of the high concentration region 8 is the gate electrode.
  • FIG. 20 shows the relationship between the impurity concentration Con8 (horizontal axis) of the high-concentration region 8 and the electric field value Eox (vertical axis) applied to the gate insulating film.
  • the calculation of the off-state was performed, for example, under the condition that the drain-source voltage was 100V and the gate-source voltage was 0V.
  • a broken line CEP indicates the impurity concentration of the epitaxial layer EP (that is, the drift layer 2), and a broken line CB2 indicates the impurity concentration of the second body region 3c.
  • the gate concentration is increased by setting the impurity concentration of the high concentration region 8 to twice or more of the impurity concentration of the drift layer 2 and reducing the impurity concentration of the high concentration region 8 to half or less of the impurity concentration of the second body region 3c. This is preferable for reducing the electric field Eox applied to the film 5.
  • FIG. 21 shows the relationship between the impurity concentration Con8 (horizontal axis) and the drain current Id (vertical axis) in the high concentration region.
  • the calculation of the on-state was performed, for example, under the condition that the drain-source voltage was 0.05V and the gate-source voltage was 20V.
  • the drain current Id can be increased by making the impurity concentration of the high concentration region 8 higher than the impurity concentration of the epitaxial layer EP (that is, the drift layer 2).
  • the drain current can be increased by setting the impurity concentration of the high concentration region 8 to at least twice the impurity concentration of the drift layer 2.
  • FIG. 22 shows the relationship between the impurity concentration Con8 (horizontal axis) in the high-concentration region and the potential Pot-Pot0 (vertical axis).
  • the impurity concentration of the high concentration region 8 As shown in FIG. 22, by making the impurity concentration of the high concentration region 8 higher than the impurity concentration of the epitaxial layer EP (that is, the drift layer 2) and lower than the impurity concentration of the second body region 3c, Since the potential Pot can be reduced, punch-through can be suppressed or prevented. In particular, it is preferable to suppress or prevent punch-through by setting the impurity concentration of the high concentration region 8 to be not less than twice the impurity concentration of the drift layer 2 and not more than half the impurity concentration of the second body region 3c. .
  • FIG. 23 is a cross-sectional view of a main part of the outermost semiconductor device in the element arrangement region in which a group of a plurality of unit element regions is arranged.
  • the second body region 3c and the high concentration region 8 are provided in the same manner as described above outside the outermost groove 4 in the element arrangement region of the power MOSFET. Thereby, damage and destruction of the gate insulating film 5 in the groove 4 at the outermost periphery of the element arrangement region can be suppressed or prevented.
  • the second body region 3c and the high concentration region 8 outside the outermost peripheral groove 4 of the element arrangement region are formed simultaneously with the formation processes of the second body region 3c and the high concentration region 8 in the element arrangement region. .
  • a gate extraction electrode 10G is formed on the interlayer insulating film 9.
  • the gate lead electrode 10G is electrically connected to the gate electrode 6G in the outermost groove 4 through a contact hole formed in the interlayer insulating film 9.
  • the gate extraction electrode 10 ⁇ / b> G is formed of the same material as that of the common electrode 10 at the same time, and is covered with the surface protective film 12 similarly to the common electrode 10.
  • FIGS. 24 to 31 are fragmentary cross-sectional views of the semiconductor device of the present embodiment during the manufacturing process.
  • an epitaxial wafer EPW shown in FIG. 24 is prepared.
  • the substrate 1 constituting the epitaxial wafer EPW is formed of, for example, an n + type 4H—SiC wafer having an offset of 8 °, 4 °, 2 °, 0.5 °, or the like.
  • the impurity concentration of the substrate 1 is, for example, 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 .
  • an epitaxial layer EP made of n-type SiC is formed by an epitaxial growth method.
  • the impurity concentration of the epitaxial layer EP is, for example, 1 ⁇ 10 14 to 1 ⁇ 10 18 cm ⁇ 3 , and here, for example, 2 ⁇ 10 16 cm ⁇ 3 .
  • a mask (not shown) for forming the first body region is formed on the epitaxial layer EP by photolithography (hereinafter simply referred to as lithography).
  • lithography photolithography
  • the planar shape of the mask is formed such that the first body region is exposed and the other regions are covered.
  • the lithography method is a method of forming a photoresist pattern by a series of processes such as application of a photoresist film, exposure and development.
  • Al ions are implanted into the upper portion of the epitaxial layer EP exposed from the mask.
  • the implantation conditions are, for example, 30 keV, 7 ⁇ 10 11 cm ⁇ 2 , 80 keV, 1.5 ⁇ 10 12 cm ⁇ 2 , 150 keV, 2 ⁇ 10 12 cm ⁇ 2 and 250 keV, 3.5 ⁇ 10 12 cm ⁇ 2.
  • the p-type first body region 3a is formed on the epitaxial layer EP, and n formed between the first body region 3a and the substrate 1 by the epitaxial layer EP.
  • a type drift layer 2 is formed.
  • the depth from the upper surface of the epitaxial layer EP in the first body region 3a is, for example, 0.4 ⁇ m.
  • the impurity concentration of the first body region 3a is, for example, 1 ⁇ 10 16 to 1 ⁇ 10 18 cm ⁇ 3 .
  • the first body region 3a may be formed of B ions instead of Al ions.
  • the first body region 3a may be formed by an epitaxial method instead of the ion implantation method. That is, the first body region 3a may be formed by depositing p-type SiC on the n-type epitaxial layer EP by an epitaxial method.
  • a mask M1 for forming a second body region is formed on the epitaxial layer EP by lithography as shown in FIG.
  • the planar shape of the mask M1 is formed such that the second body region is exposed and the other regions are covered.
  • the mask M1 as an ion implantation mask, for example, Al ions are implanted into the epitaxial layer EP exposed from the mask M1.
  • the implantation conditions are, for example, 600 keV, 1.5 ⁇ 10 13 cm ⁇ 2 , 800 keV, 2.5 ⁇ 10 13 cm ⁇ 2 and 1000 keV, 3 ⁇ 10 13 cm ⁇ 2 .
  • the p-type second body region 3c is formed in the epitaxial layer EP.
  • the second body region 3c is electrically connected to the first body region 3a.
  • the second body region 3 c extends from the bottom of the first body region 3 a toward the substrate 1, and is formed so as to terminate at a midway position in the depth direction of the drift layer 2 without reaching the substrate 1.
  • the depth from the upper surface of the epitaxial layer EP is, for example, 1.2 ⁇ m.
  • the peak concentration value of the impurity concentration of the second body region 3c is, for example, 1 ⁇ 10 18 cm ⁇ 3 .
  • the p-type second body region 3c may be formed of B ions.
  • Al ions are implanted into the upper portion of the epitaxial layer EP exposed from the mask M1.
  • the implantation conditions for example, to 15keV, 1 ⁇ 10 14 cm -2 and 30keV, 1 ⁇ 10 14 cm -2 .
  • a p-type body contact region 3b is formed above the first body region 3a.
  • the body contact region 3b is electrically connected to the first body region 3a.
  • the body contact region 3b is formed so as to extend from the upper surface of the epitaxial layer EP to an intermediate position in the depth direction of the first body region 3a.
  • the impurity concentration of the body contact region 3b is, for example, 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the body contact region 3b may be formed of B ions.
  • the covering region of the mask M1 is retracted by a dry etching method to widen the opening of the mask M1.
  • N ions are implanted into the epitaxial layer EP exposed from the opening region of the mask M1 using the mask M1.
  • the implantation conditions are, for example, 700 keV, 5 ⁇ 10 12 cm ⁇ 2 and 900 keV, 7 ⁇ 10 12 cm ⁇ 2 .
  • the n + -type high concentration region 8 is formed so as to be in contact with the lower end portion of the second body region 3c.
  • the mask M1 is shared when forming the body contact region 3b, the second body region 3c, and the high concentration region 8, a series of processes of the lithography method can be reduced, so that the semiconductor Device manufacturing time can be reduced.
  • the amount of material used can be reduced, the cost of the semiconductor device can be reduced.
  • the body contact region 3b, the second body region 3c, and the high concentration region 8 can be formed in a self-aligned manner. Therefore, each unit element region can be miniaturized and the element integration density can be improved.
  • the electrical characteristics and reliability of the power MOSFET can be improved.
  • the depth from the upper surface of the epitaxial layer EP to the upper end portion of the high-concentration region 8 is, for example, 0.7 ⁇ m, below the depth of a groove to be described later, and at the bottom end portion of the second body region 3c. It was set above the depth (for example, 1.2 ⁇ m). Moreover, it provided so that the side edge part of the high concentration area
  • the peak concentration value of the impurity concentration in the high concentration region 8 was set higher than the impurity concentration in the drift layer 2 and lower than the peak value of the impurity concentration in the second body region 3c. That is, in the present embodiment, a part of the high concentration region 8 is ion-implanted so as to overlap the second body region 3c, but the net impurity concentration of the second body region 3c is higher than that of the high concentration region 8.
  • the injection conditions were adjusted to be ⁇ 10 18 cm ⁇ 3 . Thereby, the second body region 3c is left without being erased by the high concentration region 8.
  • a mask (not shown) in which the source region 7S is exposed and the others are covered is formed in the epitaxial layer EP by lithography.
  • N ions are implanted into the upper portion of the first body region 3a.
  • the implantation conditions for example, to 15keV, 3 ⁇ 10 14 cm -2 and 30keV, 3 ⁇ 10 14 cm -2 .
  • an n + -type source region 7S is formed on the first body region 3a so as to be adjacent to the body contact region 3b.
  • the source region 7S is formed so as to extend from the upper surface of the epitaxial layer EP to a middle position in the depth direction of the first body region 3a.
  • the impurity concentration of the source region 7S is, for example, 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the ions implanted into the source region 7S may be P ions.
  • a carbon film (not shown) is deposited on the epitaxial layer EP as a cap material by a CVD (Chemical Vapor Deposition) method or the like, and then annealed to perform doping. Activate the impurities. Thereafter, the carbon film is removed by an oxygen plasma ashing method or the like.
  • an etching process is performed using the mask as an etching mask.
  • the grooves 4 are formed in the epitaxial layer EP.
  • the trench 4 is formed to extend downward from the upper surface of the epitaxial layer EP through the source region 7S and the first body region 3a, and terminates at a position in the middle of the depth of the drift layer 2.
  • a gate insulating film 5 is formed by a CVD method or the like so as to cover the upper surface of the epitaxial layer EP and the inner surface (side surface and bottom surface) of the trench 4.
  • the gate insulating film 5 is made of, for example, silicon oxide (SiO 2 ) having a thickness of about 10 to 100 nm. Note that the gate insulating film 5 may be formed by, for example, a dry oxidation method or another method.
  • a P-doped polysilicon film having a thickness of about 100 to 300 nm is deposited on the epitaxial layer EP so as to fill the trench 4 by a CVD method or the like and then patterned by a lithography method and a dry etching method. Then, a gate electrode 6G is formed as shown in FIG.
  • the gate electrode 6G and the epitaxial layer EP are insulated by the gate insulating film 5 between them.
  • an interlayer insulating film 9 is deposited on the epitaxial layer EP so as to cover the gate electrode 6G by a CVD method or the like, and then contact holes are formed in the interlayer insulating film 9 by a lithography method and a dry etching method. To do. Both the source region 7S and the body contact region 3b are exposed from the contact hole.
  • the common film 10 is formed by patterning the metal film by lithography or dry etching. At this time, the gate extraction electrode 10G shown in FIG. 23 may be formed simultaneously.
  • a metal film such as Ni is deposited on the second surface side of the substrate 1 by sputtering or the like, and the drain electrode 14 is similarly formed.
  • a surface protective film 12 for device protection is deposited above the upper surface of the epitaxial layer EP, and wiring to the gate electrode 6G, the common electrode 10 and the drain electrode 14 is performed.
  • a semiconductor device is completed by cutting a SiC chip from the wafer EPW.
  • FIG. 32 is a fragmentary cross-sectional view of a unit element region in the semiconductor device of the second embodiment.
  • the high concentration region 8 is separated from the side end portion of the second body region 3c without contacting the side end portion of the second body region 3c in the region surrounded by the broken line A described in FIG. At the same position, it is formed in a planar frame shape so as to surround the periphery of the second body region 3c.
  • the on-resistance when the power MOSFET is in the on state, the on-resistance can be reduced by expanding the current path, and when the power MOSFET is in the off state, gate dielectric breakdown and channel punch-through can be suppressed or prevented.

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Abstract

　L'invention porte sur un dispositif à semi-conducteurs dans lequel un substrat au carbure de silicium (SiC) comporte un MOSFET de type à grille dans une tranchée dans lequel une électrode de grille (6G) est intégrée dans une tranchée (4) avec un film d'isolation de grille (5) interposé entre celles-ci, le dispositif à semi-conducteurs comprenant une seconde région de corps de type p (3c) s'étendant vers le substrat (1) depuis une partie d'extrémité inférieure d'une première région de corps de type p (3a) entre la source et le drain, et se terminant au niveau d'un emplacement à mi-chemin dans la direction de profondeur d'une couche de dérive de type n (2). Une région à concentration élevée de type n+ (8) ayant une concentration d'impuretés supérieure à celle de la couche de dérive (2) est disposée au niveau de chaque emplacement dans la couche de dérive (2) entre une surface latérale de l'électrode de grille (6G) dans la tranchée (4) et une partie d'extrémité latérale de la seconde région de corps (3c) tournée vers la surface latérale de l'électrode de grille (6G) et entre la surface inférieure de l'électrode de grille (6G) dans la tranchée (4) et le substrat (1). Il est ainsi possible, en raison de la fourniture de la région à concentration élevée, de supprimer ou d'empêcher le problème de perçage se produisant dans un canal de MOSFET de puissance lorsque le MOSFET de puissance est dans un état éteint.
PCT/JP2013/067176 2013-06-24 2013-06-24 Dispositif à semi-conducteurs et son procédé de fabrication WO2014207793A1 (fr)

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CN104882367A (zh) * 2015-05-05 2015-09-02 刘莉 一种改善SiC MOSFET器件沟道迁移率的方法
JPWO2015104949A1 (ja) * 2014-01-10 2017-03-23 三菱電機株式会社 炭化珪素半導体装置
WO2017187670A1 (fr) * 2016-04-27 2017-11-02 三菱電機株式会社 Composant à semi-conducteur et composant de conversion de puissance
CN109065626A (zh) * 2018-08-21 2018-12-21 电子科技大学 一种具有介质阻挡层的槽栅dmos器件
CN111627987A (zh) * 2020-05-29 2020-09-04 东莞南方半导体科技有限公司 一种Fin沟道结构SiC场效应晶体管器件
CN113066866A (zh) * 2021-03-15 2021-07-02 无锡新洁能股份有限公司 碳化硅mosfet器件及其工艺方法
TWI812995B (zh) * 2020-08-13 2023-08-21 大陸商杭州芯邁半導體技術有限公司 SiC MOSFET器件的製造方法

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JPWO2015104949A1 (ja) * 2014-01-10 2017-03-23 三菱電機株式会社 炭化珪素半導体装置
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CN109065626B (zh) * 2018-08-21 2021-03-30 电子科技大学 一种具有介质阻挡层的槽栅dmos器件
CN111627987A (zh) * 2020-05-29 2020-09-04 东莞南方半导体科技有限公司 一种Fin沟道结构SiC场效应晶体管器件
TWI812995B (zh) * 2020-08-13 2023-08-21 大陸商杭州芯邁半導體技術有限公司 SiC MOSFET器件的製造方法
CN113066866A (zh) * 2021-03-15 2021-07-02 无锡新洁能股份有限公司 碳化硅mosfet器件及其工艺方法
CN113066866B (zh) * 2021-03-15 2022-07-26 无锡新洁能股份有限公司 碳化硅mosfet器件及其工艺方法

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