WO2014206117A1 - 降低二维晶体材料接触电阻的方法和设置 - Google Patents

降低二维晶体材料接触电阻的方法和设置 Download PDF

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WO2014206117A1
WO2014206117A1 PCT/CN2014/073586 CN2014073586W WO2014206117A1 WO 2014206117 A1 WO2014206117 A1 WO 2014206117A1 CN 2014073586 W CN2014073586 W CN 2014073586W WO 2014206117 A1 WO2014206117 A1 WO 2014206117A1
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material layer
layer
contact material
dimensional crystalline
crystalline material
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French (fr)
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贾昆鹏
粟雅娟
朱慧珑
赵超
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/881—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being a two-dimensional material
    • H10D62/882—Graphene
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    • H10D64/00—Electrodes of devices having potential barriers
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0114—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors to diamond, semiconducting diamond-like carbon or graphene
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/418—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials the conductive layers comprising transition metals
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H10P30/2044—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors into semiconducting carbon, e.g. diamond or semiconducting diamond-like carbon
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering

Definitions

  • the present disclosure relates generally to the field of semiconductor fabrication and, more particularly, to a method and arrangement for reducing the contact resistance of a two-dimensional crystal material. Background technique
  • Two-dimensional crystal materials have received extensive attention since their inception.
  • Existing two-dimensional crystal materials such as graphene, transition metal disulfides, and terpenes have excellent electrical properties and are mainly used in the manufacture of FETs. Micromechanical sensors, etc.
  • the purpose of the present disclosure is to address at least one of the above technical drawbacks, and to provide a method and arrangement for reducing the contact resistance between a two-dimensional crystalline material and other materials.
  • a method comprising: forming a contact material layer on a two-dimensional crystalline material layer; performing ion implantation; and performing thermal annealing.
  • an arrangement comprising: a two-dimensional layer of crystalline material and a layer of contact material formed thereon. At the interface between the two-dimensional crystalline material layer and the contact material layer, a low resistance state is formed by vacancies, contact materials, and implanted ions in the two-dimensional crystalline material (eg, bonding).
  • ion implantation is performed via the contact material layer, and an annealing process is applied, effectively reducing the contact resistance between the two-dimensional crystal material and the contact material.
  • FIG. 1 shows a flow chart of a method of reducing contact resistance between a two-dimensional crystalline material and a contact material in accordance with an embodiment of the present disclosure
  • ion implantation may be performed.
  • the ions bombard the two-dimensional layer of crystalline material and can create vacancies therein.
  • thermal annealing can be performed.
  • the temperature of the thermal annealing may be about 350 ° C to 500 ° C, and the annealing time may be about 1 to 30 minutes.
  • Thermal annealing effectively interacts with the material of the contact material layer and the implanted ions to form a low resistance state.
  • the vacancies and the material of the contact material layer and the implanted ions can interact to form a bond, and the formed chemical bond can modify the contact interface to reduce the contact resistance.
  • Ion implantation can be performed via a layer of contact material. Since ion implantation is performed via the contact material layer, bombardment of the implanted ions to the two-dimensional crystal material can be adjusted by controlling one or more of the material type, thickness, and ion type, energy, and dose of the contact material layer. Effect, and The implanted ion density staying at the interface can be adjusted to effectively control the contact resistance between the contact material layer and the two-dimensional crystalline material layer.
  • the bombardment effect of the implanted ions on the two-dimensional crystal material can be adjusted by controlling one or more of the implanted ion type, energy and dose, and the implanted ion density staying at the interface can be adjusted to effectively control the contact material layer.
  • a two-dimensional crystalline material layer can be disposed on the substrate.
  • a two-dimensional crystalline material layer may be provided on a semiconductor substrate to fabricate a semiconductor device.
  • the substrate may include various forms of conductors or insulator substrates. A particular type of substrate can be selected depending on the device to be fabricated.
  • the contact material layer may be patterned, for example, patterned into a contact pattern. Such patterning can be achieved, for example, by photolithographic techniques.
  • ion implantation may be limited to the region where the patterned contact material layer is located to avoid affecting the two-dimensional crystalline material layer of other regions. This localized ion implantation can be achieved, for example, by a mask layer (e.g., masking the area where implantation is not required).
  • the patterning of the above contact material layer and localized ion implantation can be achieved in combination.
  • a patterned mask layer can be formed on the two-dimensional crystalline material layer.
  • the pattern of the mask layer may correspond to the contact pattern.
  • the mask layer may shield a region of the two-dimensional crystalline material layer that does not need to form a contact material layer, and an opening in the mask layer may expose the two-dimensional crystalline material layer to be formed. The area in contact with the material layer.
  • a preliminary contact material layer may be formed on the two-dimensional crystalline material layer on which the mask layer is formed.
  • the portion of the preliminary contact material layer at the top of the mask layer can be removed later; and the portion of the preliminary contact material layer in the mask layer opening covers the two-dimensional crystalline material layer, and thus the contact material layer can be formed.
  • ion implantation can be performed via the preliminary contact material layer in the presence of the mask layer. Due to the presence of the mask layer, ion implantation may not substantially affect the area covered by the mask layer.
  • the mask layer can be removed and the portion of the preliminary contact material layer thereon removed.
  • the portion of the preliminary contact material layer remaining i.e., the portion located above the opening of the mask layer
  • the mask layer can include a photoresist.
  • the mask layer and the portion of the preliminary contact material layer thereon may be removed together by a lift-off process or the like.
  • the mask layer may comprise a hard mask.
  • the mask layer can be etched by wet etching, and thus the portion of the preliminary contact material layer thereon is removed.
  • the method may further include performing thermal annealing. This annealing can clean the surface of the two-dimensional crystalline material layer.
  • a substrate 200 may be provided having a two-dimensional crystalline material layer 202 thereon, as shown in FIG.
  • the substrate 200 may include any substrate that needs to transfer a two-dimensional crystal material such as graphene and serve as a metal contact, or other substrate, such as single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon germanium, silicon carbide, germanium An alloy semiconductor such as indium, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide or other compound semiconductor.
  • Substrate 200 may also include a stacked semiconductor structure such as Si/SiGe, silicon-on-insulator (SOI) or silicon-on-insulator (SGOI).
  • the two-dimensional crystalline material layer includes a two-dimensional crystalline material, that is, a material of a monoatomic layer or a molecular layer, such as graphene, a disulfide of a transition metal, and a terpene.
  • the two-dimensional crystalline material layer may include graphene.
  • the single or multi-layered graphene material can be formed by chemical vapor deposition (CVD), thermal decomposition, micro-mechanical lift-off, and their bond transfer methods or other suitable methods.
  • a patterned mask layer 204 can be formed on the two-dimensional crystalline material layer 202, as shown in FIG.
  • the mask layer 204 may include a hard mask, such as a hard mask of silicon nitride, aluminum oxide or silicon dioxide.
  • the mask layer 204 can be formed by depositing a layer of mask material and then patterning. For example, a photoresist may be formed on the deposited mask material layer, and the photoresist may be patterned by exposure, development, or the like. Thereafter, the patterned photoresist layer may be etched by using the patterned photoresist as a mask to form a mask layer 204. After the hard mask is formed, a thermal annealing process may also be performed to clean the surface of the two-dimensional crystalline material layer 202.
  • the mask layer 204 can include a photoresist.
  • the patterned photoresist mask layer can be formed by steps of gluing, pre-baking, exposure, development, and the like.
  • a contact material layer may be formed on the two-dimensional crystalline material layer 202 formed with the mask layer 204, the contact material layer may include a portion 206-1 located at the top of the mask layer 204 and located at the mask layer The portion 206-2 of the opening 204 is as shown in FIG.
  • the contact material layer portion 206-2 can be in contact with the two-dimensional crystalline material layer 202, for example to control voltage, derive current, and the like.
  • the layer of contact material (206-1, 206-2) may comprise a conductor material.
  • the contact material layer may include a metal material such as Ti, Pd, Ni, Cr, Pt, W, Cu, or the like.
  • the contact material layer can be formed by evaporation, sputtering or other suitable method, the thickness of which is determined by the later device process requirements.
  • ion implantation can be performed as shown in Figure 5.
  • Ion implantation can be performed by selecting appropriate ions and injection methods according to specific needs.
  • the implanted ions may include a daunting ion, and the implantation dose may be 4el5, and the implantation energy may be determined by the material and thickness of the contact material layer.
  • the implanted ions and the implant dose are not limited to this, and the appropriate ion type and implant dose can be selected according to requirements.
  • the mask layer 204 and the contact material layer portion 206-1 thereon can be removed, as shown in FIG.
  • the mask layer when the mask layer includes a hard mask such as silicon dioxide, the hard mask can be removed by wet etching such as hydrofluoric acid (HF) solution, thereby removing the contact material layer thereon.
  • wet etching such as hydrofluoric acid (HF) solution
  • the mask layer 204 and the contact material layer portion 206-1 thereon may be removed by a lift-off process.
  • a stripping solvent photoresist mask layer 204 is dissolved by using a solvent such as acetone, and the contact material layer portion 206-1 thereon is also peeled off together, thereby removing the mask layer 204 and the portion of the contact material layer thereon. 206-1.
  • thermal annealing can be performed.
  • thermal annealing may also be performed.
  • the temperature of the thermal annealing may be about 350 ° C - 500 ° C, and the thermal annealing time may be It is about 30 minutes. Thermal annealing can effectively interact the contact vacancies with the contact material and the implanted ions (e.g., bond) to reduce contact resistance.
  • the arrangement can include a two-dimensional crystalline material layer 202 and a contact material layer 206-2 formed thereon.
  • the contact material layer 206-2 can be patterned, for example, to form a contact to the two-dimensional crystalline material layer 202.
  • the vacancies in the two-dimensional crystalline material layer, the material of the contact material layer, and the implanted ions may interact to form a low resistance state.
  • vacancies, materials for contact material layers, and implants The sub-links may be bonded, which may reduce the contact resistance between the two-dimensional crystalline material layer 202 and the contact material layer 206-2.
  • the subsequent device processing process can be performed according to the actual needs of the device, for example, further patterning the two-dimensional crystalline material layer 202, as shown in FIG.
  • ion implantation is performed via the contact material layer after the formation of the contact material layer.
  • ion implantation may be performed first to form a contact material layer.
  • ion implantation may be performed after the mask layer 204 is formed as shown in Fig. 3; and a contact material layer is formed as shown in Figs. 4-7 (the ion implantation shown in Fig. 5 is omitted).

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

提供了一种降低二维晶体材料接触电阻的方法和设置。一示例方法可以包括：在二维晶体材料层上形成接触材料层；进行离子注入；以及进行热退火。

Description

降低二维晶体材料接触电阻的方法和设置 本申请要求了 2013年 6月 25日提交的、 申请号为 201310254601.0、名称 为 "降低二维晶体材料接触电阻的方法" 的中国专利申请的优先权， 其全部内 容通过引用结合在本申请中。 技术领域
本公开一般地涉及半导体制造领域， 更具体地， 涉及一种降低二维晶体材 料接触电阻的方法和设置。 背景技术
集成电路及微机械技术高速发展， 近年来新材料、新工艺和新器件不断的 涌现， 尤其是新型材料得到了更加广泛的关注。二维晶体材料自从问世就得到 了广泛的关注，现有的二维晶体材料例如石墨烯、过渡金属的二硫化物以及锗 烯等，其具有优良的电学特性，主要应用于制造场效应管以及微机械传感器等。
然而，在这些二维晶体材料在应用时， 都不可避免的会遇到与其他材料之 间的接触电阻的问题， 而降低接触电阻正是更好的发挥其优良电学特性的关 键。 例如， 对于石墨烯材料， 由于其在室温下具有超高的载流子迁移率， 而被 用于沟道材料制作晶体管， 然而石墨烯与其他材料的接触电阻不能被有效降 低， 接触电阻在长沟道器件时可以有比较高的容忍度， 但是对于短沟道器件， 接触电阻的大小与沟道电阻大小相当时则会极大的影响器件的性能。石墨烯与 其他材料的接触电阻已经成为石墨烯器件缩小尺寸、提高性能的一个主要限制 因素。 发明内容
本公开的目的旨在至少解决上述技术缺陷之一，提供一种利于降低二维晶 体材料与其他材料之间接触电阻的方法及设置。
根据本公开的一个方面， 提供了一种方法， 包括： 在二维晶体材料层上形 成接触材料层； 进行离子注入； 以及进行热退火。 根据本公开的另一方面， 提供了一种设置， 包括： 二维晶体材料层及在其 上形成的接触材料层。在二维晶体材料层与接触材料层之间的界面处， 由二维 晶体材料中的空位、 接触材料和注入离子相互作用 （例如， 成键）而形成低阻 态。
根据本公开的实施例， 经由接触材料层， 进行离子注入， 并且施加退火工 艺， 有效降低了二维晶体材料与接触材料之间的接触电阻。
附图说明
本公开技术上述的和 /或附加的方面和优点从下面结合附图对实施例的描 述中将变得明显和容易理解， 其中：
图 1 示出了根据本公开实施例的降低二维晶体材料与接触材料之间的接 触电阻的方法的流程图；
图 2-图 7示出了根据本公开实施例的设置的多个形成阶段的截面示意图。 具体实施方式
下面详细描述本公开的实施例， 所述实施例的示例在附图中示出， 其中自 始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元 件。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本公开， 而不能 解释为对本公开的限制。
根据本公开的实施例，为了降低二维晶体材料层与接触材料层之间的接触 电阻，可以进行离子注入。 离子轰击二维晶体材料层，并可以在其中产生空位。 之后， 可以进行热退火。 例如， 热退火的温度可以为约 350 °C -500 °C , 热退火 的时间可以为约 1-30分钟。 热退火有效地使注入后的空位与接触材料层的材 料以及注入离子相互作用而形成低阻态。例如， 空位与接触材料层的材料以及 注入离子可以相互作用而成键， 形成的化学键可以对接触界面进行修饰，从而 降低接触电阻。
离子注入可以经由接触材料层进行。 由于经由接触材料层来进行离子注 入， 所以可以通过控制接触材料层的材料种类、厚度以及注入的离子类型、 能 量和剂量中的一项或多项， 来调节注入离子对二维晶体材料的轰击效果， 并且 可以调节停留在界面处的注入离子密度，进而有效控制接触材料层与二维晶体 材料层之间的接触电阻。
也可以先进行离子注入， 再形成接触材料层。可以通过控制注入的离子类 型、能量和剂量中的一项或多项，来调节注入离子对二维晶体材料的轰击效果， 并且可以调节停留在界面处的注入离子密度，进而有效控制接触材料层与二维 晶体材料层之间的接触电阻。
二维晶体材料层可以设于衬底上。例如，二维晶体材料层可以设于半导体 衬底上， 以制造半导体器件。 当然， 本公开不限于此， 衬底可以包括各种形式 的导体或绝缘体衬底。 可以根据所需制造的器件， 来选择特定类型的衬底。
根据本公开的实施例， 可以对接触材料层进行构图， 例如， 构图为接触部 图案。这种构图例如可以通过光刻技术来实现。在接触材料层被构图的情况下， 离子注入可以局限于构图的接触材料层所在的区域，以避免对其他区域的二维 晶体材料层造成影响。这种局域化的离子注入例如可以通过掩膜层来实现 (例 如， 通过掩膜层遮蔽不需要进行注入的区域）。
为了简化工艺，特别是避免额外增加掩膜版和刻蚀工艺， 上述接触材料层 的构图和局域化离子注入可以结合实现。例如， 可以在二维晶体材料层上形成 构图的掩膜层。掩膜层的图案可以对应于接触部图案， 例如， 掩膜层可以遮蔽 二维晶体材料层上无需形成接触材料层的区域，而掩膜层中的开口可以露出二 维晶体材料层上需要形成接触材料层的区域。可以在其上形成有掩膜层的二维 晶体材料层上形成预备接触材料层。预备接触材料层位于掩膜层顶部的部分在 之后可以去除； 而预备接触材料层在掩膜层开口中的部分覆盖二维晶体材料 层， 并由此可以构成接触材料层。 在这种情况下， 可以在存在掩膜层的情况下 经由预备接触材料层进行离子注入。 由于掩膜层的存在， 离子注入可以基本上 不影响掩膜层覆盖的区域。 随后， 可以去除掩膜层， 并一同去除其上的预备接 触材料层部分。 留下的预备接触材料层部分（即， 上述位于掩膜层开口中的部 分）可以形成构图的接触材料层。
掩膜层可以包括光刻胶。 此时， 可以釆用剥离工艺等， 一起去除掩膜层及 其上的预备接触材料层部分。 或者， 掩膜层可以包括硬掩膜。 此时， 可以釆用 湿法刻蚀腐蚀掩膜层， 并因此去除其上的预备接触材料层部分。 在二维晶体材料层上形成图案化的掩膜层之后，且在掩膜层及二维晶体材 料层上形成接触材料层之前， 该方法还可以包括进行热退火。这种退火可以清 洁二维晶体材料层的表面。
本公开的技术可以多种形式呈现。以下将结合图 1和 2对一具体示例进行 详细的描述。
在 S01 , 可以提供衬底 200, 所述衬底 200上具有二维晶体材料层 202 , 如图 2所示。
衬底 200 可以包括任意需要转移如石墨烯等二维晶体材料并作为金属接 触的衬底， 或其他衬底， 例如单晶硅、 多晶硅、 非晶硅、 锗， 硅锗、 碳化硅、 锑化铟、 碲化铅、 砷化铟、 磷化铟、 砷化镓或锑化镓等合金半导体或其他化合 物半导体。 衬底 200还可以包括叠层半导体结构， 例如 Si/SiGe、 绝缘体上硅 ( SOI )或绝缘体上硅锗 ( SGOI )。
二维晶体材料层包括二维晶体材料， 即为单原子层或分子层的材料， 例如 石墨烯、 过渡金属的二硫化物以及锗烯等。
在本实施例中，二维晶体材料层可以包括石墨烯。 可以利用化学气相淀积 ( CVD )、 热分解法、 微机械剥离法， 以及他们的键合转移法或其他合适的方 法来形成单层或多层的石墨烯材料。
在 S02 , 可以在二维晶体材料层 202上形成图案化的掩膜层 204, 如图 3 所示。
在本实施例中， 掩膜层 204可以包括硬掩膜， 例如氮化硅、 三氧化二铝或 二氧化硅等的硬掩膜。 可以通过淀积掩膜材料层而后图案化来形成该掩膜层 204。 例如， 可以在淀积的掩膜材料层上形成光刻胶， 并通过曝光、 显影等对 光刻胶构图。 之后， 可以该构图的光刻胶为掩模， 对掩膜材料层进行刻蚀如， 从而形成掩膜层 204。 在形成硬掩膜后， 还可以进行热退火工艺， 以清洁二维 晶体材料层 202的表面。
在另一实施例中， 该掩膜层 204可以包括光刻胶。 例如， 可以通过涂胶、 前烘、 曝光、 显影等步骤形成图案化的光刻胶掩膜层。
在 S03 , 可以在形成有掩膜层 204的二维晶体材料层 202上形成接触材料 层，该接触材料层可以包括位于掩膜层 204顶部的部分 206-1以及位于掩膜层 204开口中的部分 206-2, 如图 4所示。
接触材料层部分 206-2可以与二维晶体材料层 202相接触，例如以控制电 压、 导出电流等等。 通常， 接触材料层 （206-1 , 206-2 )可以包括导体材料。 在本实施例中， 接触材料层可以包括金属材料， 例如 Ti、 Pd、 Ni、 Cr、 Pt、 W、 Cu等。 可以通过蒸发、 溅射或其他合适的方法来形成接触材料层， 其厚度范 围由后期器件工艺要求决定。
在 S04, 可以进行离子注入， 如图 5所示。
可以根据具体的需要选择合适的离子和注入方式进行离子注入。
在本实施例中， 注入离子可以包括碑离子， 注入剂量可以为 4el5 , 注入 能量可以由接触材料层的材料和厚度决定。但是， 注入离子和注入剂量不局限 于此， 可以 4艮据需求选取合适的离子类型和注入剂量。
在 S05 , 可以去除掩膜层 204及其上的接触材料层部分 206-1 , 如图 6所 示。
在本实施例中，在掩膜层包括硬掩膜如二氧化硅时， 可以通过湿法刻蚀如 氢氟酸（HF )溶液腐蚀去除硬掩膜， 进而去除其上的接触材料层。
在另一实施例中，掩膜层包括光刻胶时， 可以通过剥离工艺一并去除掩膜 层 204及其上的接触材料层部分 206-1。 具体的， 例如利用丙酮等剥离溶剂光 刻胶掩膜层 204溶解， 其上的接触材料层部分 206-1也随其一同剥离， 从而一 起去除了掩膜层 204及其上的接触材料层部分 206-1。
在 S06, 可以进行热热退火。
在离子注入和剥离掩膜层及其上的接触材料层部分后， 还可以进行热退 火， 在本实施例中， 热退火的温度可以为约 350 °C-500°C , 热退火的时间可以 为约 30分钟。 热退火可以有效的使注入后的空位与接触材料和注入离子相互 作用 （例如， 成键）进而降低接触电阻。
于是， 得到了这样一种设置。 如图 6所示， 该设置可以包括二维晶体材料 层 202及在其上形成的接触材料层 206-2。 接触材料层 206-2可以是构图的， 例如形成对二维晶体材料层 202的接触部。在二维晶体材料层 202与接触材料 层 206-2之间的界面处， 二维晶体材料层中的空位、 接触材料层的材料和注入 离子可以相互作用从而形成低阻态。 例如， 空位、接触材料层的材料和注入离 子可以成键，这种键可以降低二维晶体材料层 202与接触材料层 206-2之间的 接触电阻。
在如上所述完成接触后， 可以根据器件实际需求进行后续器件加工工艺， 例如进一步对二维晶体材料层 202进行图形化， 参考图 7所示。
在以上的实施例中，尽管在形成接触材料层之后经由接触材料层来进行离 子注入。 但是， 本公开不限于此。 例如， 可以先进行离子注入， 再形成接触材 料层。 具体地， 可以在如图 3所示形成掩膜层 204之后， 进行离子注入； 再如 图 4-7所示形成接触材料层（省略图 5中所示的离子注入）。
以上所述，仅是本公开的实施例而已 ,并非对本公开作任何形式上的限制。 虽然本公开已以实施例披露如上， 然而并非用以限定本公开。任何熟悉本 领域的技术人员， 在不脱离本公开技术方案范围情况下， 都可利用上述揭示的 方法和技术内容对本公开技术方案作出许多可能的变动和修饰 ,或修改为等同 变化的等效实施例。 因此， 凡是未脱离本公开技术方案的内容， 依据本公开的 技术实质对以上实施例所做的任何简单修改、等同变化及修饰， 均仍属于本公 开技术方案保护的范围内。

Claims

权 利 要 求 书
1. 一种方法， 包括：
在二维晶体材料层上形成接触材料层；
进行离子注入； 以及
2. 根据权利要求 1所述的方法， 其中， 离子注入经由接触材料层进行。
3. 根据权利要求 1所述的方法， 其中， 在进行离子注入之后再形成接触 材料层。
4. 根据权利要求 1所述的方法， 其中， 所述二维晶体材料层设于衬底上。
5. 根据权利要求 1所述的方法， 还包括： 对所述接触材料层构图。
6. 根据权利要求 5所述的方法， 其中， 构图包括：
在二维晶体材料层上形成构图的掩膜层；
在其上形成有掩膜层的二维晶体材料层上形成预备接触材料层， 其中，在 存在掩膜层的情况下经由预备接触材料层进行离子注入； 以及
去除掩膜层及其上的预备接触材料层部分，留下的预备接触材料层部分形 成构图的接触材料层。
7. 根据权利要求 6所述的方法， 其中， 所述掩膜层包括光刻胶； 釆用剥 离工艺去除掩膜层上的预备接触材料层部分。
8. 根据权利要求 6所述的方法， 其中， 所述掩膜层包括硬掩膜； 釆用湿 法刻蚀腐蚀掩膜层， 继而去除其上的预备接触材料层部分。
9. 根据权利要求 8所述的方法， 其中， 在所述二维晶体材料层上形成图 案化的掩膜层之后，且在掩膜层及二维晶体材料层上形成接触材料层之前， 该 方法还包括： 进行热退火。
10. 根据权利要求 1所述的方法，其中，所述二维晶体材料层包括石墨烯、 过渡金属的二石克化物以及锗烯中的一项或多项。
11. 根据权利要求 1所述的方法， 其中， 热退火的温度为约 350°C-500°C , 热退火的时间为约 1-30分钟。
12. 一种设置， 包括： 二维晶体材料层及在其上形成的接触材料层，
其中，在二维晶体材料层与接触材料层之间的界面处，二维晶体材料层中 的空位、 接触材料层的材料和注入离子相互作用形成低阻态。
13. 根据权利要求 12所述的设置， 其中， 空位、 接触材料层的材料和注 入离子成键。
PCT/CN2014/073586 2013-06-25 2014-03-18 降低二维晶体材料接触电阻的方法和设置 Ceased WO2014206117A1 (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114203541A (zh) * 2021-11-26 2022-03-18 华中科技大学 一种将金属电极转移至二维材料上的方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106328501B (zh) * 2015-06-23 2019-01-01 中国科学院微电子研究所 半导体器件的制造方法
CN107146815A (zh) * 2017-03-21 2017-09-08 广东工业大学 一种肖特基栅场效应晶体管及其制备方法与应用
CN115863176B (zh) * 2022-12-23 2025-11-25 武汉大学 一种利用低能离子注入掺杂构建二维横向p-n同质结的方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6014476A (ja) * 1983-07-04 1985-01-25 Nec Corp 半導体装置の製造方法
JPH02303158A (ja) * 1989-05-18 1990-12-17 Sanyo Electric Co Ltd 半導体集積回路の製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5832415A (ja) * 1981-08-20 1983-02-25 Sanyo Electric Co Ltd コンタクト抵抗低減方法
JPH09106958A (ja) * 1995-06-23 1997-04-22 De Beers Ind Diamond Div Ltd 結晶基体のドーピング
US7064021B2 (en) * 2003-07-02 2006-06-20 Au Optronics Corp. Method for fomring a self-aligned LTPS TFT
US7169660B2 (en) * 2003-10-06 2007-01-30 Atmel Corporation Lithography-independent fabrication of small openings for forming vertical mos transistor
US8808810B2 (en) * 2009-12-15 2014-08-19 Guardian Industries Corp. Large area deposition of graphene on substrates, and products including the same
US8895417B2 (en) * 2011-11-29 2014-11-25 International Business Machines Corporation Reducing contact resistance for field-effect transistor devices
CN102623310A (zh) * 2012-03-31 2012-08-01 中国科学院微电子研究所 一种制备金属与石墨烯欧姆接触的方法
CN105027294B (zh) * 2013-02-22 2019-03-05 Hrl实验室有限责任公司 石墨烯异质结构场效应晶体管

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6014476A (ja) * 1983-07-04 1985-01-25 Nec Corp 半導体装置の製造方法
JPH02303158A (ja) * 1989-05-18 1990-12-17 Sanyo Electric Co Ltd 半導体集積回路の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114203541A (zh) * 2021-11-26 2022-03-18 华中科技大学 一种将金属电极转移至二维材料上的方法

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