WO2014205935A1 - 一种测试基板及采用该测试基板制造的探针卡 - Google Patents

一种测试基板及采用该测试基板制造的探针卡 Download PDF

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Publication number
WO2014205935A1
WO2014205935A1 PCT/CN2013/084152 CN2013084152W WO2014205935A1 WO 2014205935 A1 WO2014205935 A1 WO 2014205935A1 CN 2013084152 W CN2013084152 W CN 2013084152W WO 2014205935 A1 WO2014205935 A1 WO 2014205935A1
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Prior art keywords
test
substrate
wafer
tested
test substrate
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PCT/CN2013/084152
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English (en)
French (fr)
Inventor
蒋力
徐强
李慧云
徐国卿
苏少博
张晓龙
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中国科学院深圳先进技术研究院
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Publication of WO2014205935A1 publication Critical patent/WO2014205935A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
    • G01R1/07378—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate adapter, e.g. space transformers

Definitions

  • the present invention relates to a test substrate and a probe card manufactured using the test substrate, and more particularly to a semiconductor manufacturing industry for detecting a chip.
  • a test substrate and a probe card manufactured using the test substrate belong to the technical field of electronic testing.
  • BACKGROUND OF THE INVENTION With the continuous advancement of the chip manufacturing process, the size of the chip is continuously reduced while the operation speed is continuously increased. However, as the semiconductor fabrication process enters deep nanoscale, the performance of the chip has not been able to continue to improve as it has been, mainly due to the following factors: (1) The delay on the chip interconnect has replaced the delay of the device itself, and has become improved.
  • the three-dimensional chip refers to stacking the unpackaged wafers 10 in a vertical direction and packaging them into a complete chip. These stacked wafers 10 pass signals to each other through a technique called "Through Si l icon Via" (TSV).
  • FIG. 1a is a perspective view of two layers of wafers 10 stacked together.
  • the substrate 20 of the first layer of wafer 10 is thinned to allow the contacts 7 to be tested to be through-silicon vias in the three-dimensional chip.
  • the substrate 20 of the first layer of wafer 10 is penetrated.
  • the via vias are coupled to the wafer routing layer 11 of the second wafer 10 to function to transfer signals (including data/power/ground/clock signals) at the wafer device layer 12.
  • a cross-sectional view of three wafers 10 bonded together by an adhesive layer 22 is shown in Figure 1b.
  • each wafer 10 passes through the contact 7 to be tested, i.e., through-silicon vias and adjacent
  • the wafer 10 establishes a signal connection.
  • the integration density of the devices in the chip is increased, the signal delay is reduced, the power consumption of the chip is reduced, and more importantly, the chips of different processes can be integrated by stacking, thereby reducing The cost and risk of multi-process chip manufacturing.
  • various defects introduced in the manufacturing process of the three-dimensional chip lead to a low yield of the three-dimensional chip.
  • the wafer 10 is not inspected before stacking, and the process of forming through-silicon vias on the wafer 10 is very complicated, and it is easy to cause defects in the wafer 10 when the through-silicon via is formed, resulting in the wafer not being used normally.
  • any one of the wafers 10 fails, which will result in the entire three-dimensional chip being unusable, which results in a low yield of the three-dimensional chip.
  • the industry and academia have proposed a method that can effectively improve the yield of three-dimensional chips, that is, pre-stack testing.
  • the basic principle is to test the wafer 10 before stacking and packaging, and discard the faulty wafer 10 to ensure that the stacked wafers 10 are fault-free wafers, and improve the yield of the three-dimensional chip.
  • the wafer 10 is only a bare wafer prior to stacking, which does not have any pins that can be externally connected to the test tool, so how to input test signals into the devices on the wafer 10 and how to pass test signals from the devices on the wafer 10. Leading out becomes a problem.
  • the existing pre-stack test schemes are mainly divided into two categories:
  • Front detection as shown in Fig. 2a, that is, the test probe 13 does not directly contact the contact 7 to be tested, that is, the through-silicon via, but transmits the test signal by touching the specially designed test pad 19 on the front side of the wafer 10.
  • the advantage of the front side detection is that the wafer 10 is not ground, but the disadvantage is that the test pad 19 has a relatively large area, occupies more on-chip area, increases test time and cost, and the other end of the through-silicon via is buried in the wafer substrate 20. It is not possible to test the TSV directly.
  • some researchers have designed a built-in self-test (bui lt in self test) structure to test through-silicon vias, such as M. Cho, C.
  • the test probe 13 directly contacts the contact to be tested 7 on the back side of the wafer 10, i.e., through the through silicon via, and transmits the test signal via the through silicon via.
  • the backside detection does not have the shortcomings of the frontal detection method, it also has many shortcomings.
  • the size of the test probe 13 can only be as small as 35 micrometers, but the size of the through-silicon via is currently less than 4.4 micrometers. Obviously, this huge gap makes it impossible to accurately detect the TSV with the test probe 13, as shown in Fig. 3, due to the large size difference between the test probe 13 and the through-silicon via, a test probe 13 is simultaneously covered.
  • the wafer 10 must be thinned to a thickness of about 50 microns, and on the other hand, the wafer 10 must be applied. Sufficient pressure is required to allow the test probe 13 to be in full contact with the through-silicon via. Under this pressure, the wafer 10 of this thickness is very susceptible to damage. Moreover, the thinned wafer 10 is easily bent and the surface is not flat, which makes it impossible for some of the test probes 13 to sufficiently contact the through-silicon vias, which greatly affects the quality of the test signal.
  • each test probe 13 contacts a plurality of vias, such as B. No ia and K. Ghakrabarty, Proc. I Etern I nternat i ona l Test Conference, pp. 1 -10 (Prot. Prob i ng of TSVs in 3D) Stacked I Cs ", discloses that each test probe 13 contacts a plurality of contacts 7 to be tested, that is, a through-silicon via, as shown in FIG. 4, a plurality of through-silicon vias detected by the same test probe 13 One end is shorted together to form a TSV g roup .
  • test flip-flop 23 with a switch is connected, and all of the test flip-flops 23 with the switch are finally connected to the test scan.
  • Chains by controlling the corresponding trigger switches, they can control the test signal to pass only a selected through-silicon via in the network, and determine the resistance/capacitance value by measuring the time of charge and discharge of the silicon via to determine whether it is defective. .
  • this method indirectly solves the problem of over-silicon via detection, it has many limitations. First, because of the use of the test scan chain, this method can only be modularized, that is, only digital circuits can be tested.
  • Patent No. CN 1 02478950 A entitled “Direct Probe Test Probe Test Device” discloses a probe test device including a space transformer, and a vertical probe set at the bottom, The device under test is in contact with the upper space converter and the probe interface board. Although the probe set includes a plurality of vertical probes, the size is significantly reduced compared to the conventional probe card. Existing fabrication process probes are not compatible with over-silicon vias (over-silicon vias up to 4.4 microns, and test probes can only be as small as 35 microns).
  • the space converter provides an interface for converting the wiring space from a small pitch to a large pitch
  • the space converter is fabricated on the size of the board, the vertical probe and the space converter are used. It is impossible to perform micro-level over-silicon vias at the same time, and it is not suitable for pre-stack testing of wafers of three-dimensional chips and 2.5-dimensional chips.
  • the technical problem to be solved by the present invention is that the size of the chip testing device in the prior art is too large, and the size of the through-silicon vias on the wafers forming the three-dimensional chip is small and the arrangement density is large, and the through-silicon vias cannot be detected one by one at the same time.
  • test substrate capable of simultaneously detecting each via via, suitable for inspection before wafer package of a three-dimensional chip, and using the test substrate Manufactured probe card.
  • the present invention relates to a test substrate for performing pre-stack testing on a wafer, comprising: a plurality of test end micro bumps, according to the bottom of the wafer
  • the same layout of the contacts to be tested is arranged in a top surface of the base of the test substrate, and each of the test end microprotrusions matches a size of the contact to be tested; a plurality of through substrate perforations, the top of which passes through the top layer wiring and the test end micro
  • the protrusions are connected and electrically connected in a one-to-one manner; a plurality of detecting protrusions are arranged on a bottom surface of the base of the test substrate, and each of the detecting protrusions is electrically connected to a bottom of each of the through-substrate perforations, And each of the detecting protrusions matches the size of each test probe.
  • the test end microbumps are formed on the top surface of the pedestal of the test substrate by an etching technique.
  • the through substrate vias are arranged in the same layout as the detecting protrusions.
  • the bottom of the base of the test substrate is provided with an underlying wiring, and the through-substrate vias are connected and electrically connected in one-to-one correspondence with the detecting protrusions through the underlying wiring.
  • the detecting protrusions are disposed on a bottom surface of the base of the test substrate in the same layout as the test probe.
  • the top surface of the base of the test substrate is covered with an elastic adhesive layer, and the elastic adhesive layer and the test-end micro-protrusion are electrically connected to the portion corresponding to the contact to be tested, and the remaining portion is insulated.
  • the elastic adhesive layer is an anisotropic conductive adhesive.
  • the base of the test substrate is made of an insulating silicon material or a glass material.
  • the through substrate via includes a through hole penetrating through the base of the test substrate, an insulating material plated on the inner surface of the through hole, and a metal material poured in the through hole.
  • the contact to be tested is a through-silicon via or a micro-bump to be tested; the micro-bump to be tested is formed at the bottom of the wafer by an etching technique.
  • a probe card manufactured using the test substrate by removing the detecting protrusion, and in the measuring
  • the bottom layer of the base of the test substrate is increased in wiring, and the test signal is transmitted through the newly added wiring to each test end microprotrusion on the top surface of the base of the test substrate, and the microbump is protruded through the test end. Passing to each of the contacts to be tested at the bottom of the wafer, and outputting the tested signal to detect the wafer; the contact to be tested is a through-silicon via or a micro-bump to be tested; The microbump to be measured is formed at the bottom of the wafer by an etching technique.
  • the test substrate of the present invention includes a plurality of test end micro bumps arranged on a top surface of the base of the test substrate, in a position corresponding to the contact to be tested at the bottom of the wafer to be tested.
  • the size of the through-substrate vias can be made very large, such as 100 ⁇ m. This large size design allows the substrate to be perforated. The manufacturing defect rate is almost zero, and the pitch of the through-substrate is much larger than the contact to be tested, such as the pitch of the through-silicon via. With this layout, the smaller pitch between the contacts to be tested can be converted into a larger pitch between the vias of the substrate, because the defect rate of the test substrate is almost zero, so that the test substrate can be simultaneously measured by the test substrate. Point (such as through silicon via) is tested.
  • the test probe is in one-to-one contact with the detecting protrusion, and the test signal is transmitted to the through substrate through the detecting protrusion, and the through substrate is perforated through the top layer wiring and the test end micro bump. Passing the test signal to the contact to be tested of the wafer to be tested, such as over the TSV, and transmitting the test signal through the wiring on the wafer to be tested, detecting the entire wafer to be tested, screening out the failed wafer, because all passes The tested wafers are all qualified wafers, thereby improving the yield of the three-dimensional chip or the 2.5-dimensional chip.
  • the contact to be tested (such as a through-silicon via) has a one-to-one correspondence with the micro-protrusion of the test end
  • the test-end micro-protrusion has a one-to-one correspondence with the through-substrate perforation, and the over-substrate perforation and detection
  • the protrusions are in one-to-one correspondence, and the size of the detecting protrusions matches the size of the test probe, so that the test probes are indirectly equivalent to simultaneously detecting each of the contacts to be tested (such as over-silicon vias). Reduced inspection time and reduced measurement error.
  • test substrate of the present invention can be made as long as the test substrate is large enough
  • the signal enters all of the contacts to be tested simultaneously (such as over-silicon vias), greatly increasing the test bandwidth.
  • the present invention since all the contacts to be tested (such as over-silicon vias) can be detected at the same time, the present invention can be tested without adding any intrusive structure to the wafer. It saves wiring resources, reduces mutual interference between lines, and reduces measurement errors.
  • the test substrate of the present invention transmits test signals to all devices on the wafer to be tested through the contacts to be tested and the wiring on the wafer to be tested, and the wafers to be tested are detected by all the inputs and outputs of the wafer to be tested. Functional testing is performed, so digital circuits, analog circuits, RF circuits, etc. can be tested to expand the testable range.
  • FIG. 1 a is a three-dimensional structure diagram of a three-dimensional chip
  • FIG. Figure 2a is a schematic view of the front side detection in the background art
  • Figure 2b is a schematic view of the back side detection in the background art
  • Figure 3 is a schematic view showing the comparison between the test probe and the through-silicon vias
  • Figure 4 is a through-silicon via in the background art.
  • FIG. 5 is a schematic perspective view of a test substrate according to an embodiment of the present invention
  • FIG. 6 is a schematic cross-sectional view of a test substrate according to an embodiment of the present invention
  • 7 is a schematic diagram of the top layer wiring of the test substrate of the present invention
  • FIG. 8 is a schematic diagram of the underlying wiring of the test substrate of the present invention
  • FIG. 5 is a schematic perspective view of a test substrate according to an embodiment of the present invention
  • FIG. 6 is a schematic cross-sectional view of a test substrate according to an embodiment of the present invention
  • 7 is a schematic
  • FIG. 9a is a schematic view of the test substrate for testing each wafer on the wafer;
  • FIG. A schematic diagram of testing each of the multiple wafers on the wafer;
  • Figure 10 is a perspective view of the test substrate when testing the wafer.
  • the reference numerals in the figure are indicated as: 1 - pedestal, 2- test end microprotrusion, 3-pass substrate perforation, 4-probing projection, 5-contact pad, 6-elastic layer, 7 - to be touched Point, 8-top wiring, 9-underlay, 1 0-wafer, 1 1 - wafer wiring layer, 1 2-chip device layer, 1 3-test probe, 14-top wiring horizontal wiring layer, 1 5-top Wiring vertical wire, 1 6-underlying vertical wire, 1 7-underlying horizontal wire layer, 1 8-wafer, 19-test pad, 20-substrate, 21-tray, 22-adhesive layer, 23- Test trigger with switch.
  • Embodiment 1 The test substrate of the present invention is used for pre-stacking testing of the wafer 10, as shown in FIG. 5 and FIG. 6, comprising: a plurality of test end micro bumps 2, according to the bottom of the wafer 10
  • the same layout of the contacts to be tested 7 is arranged on the top surface of the base 1 of the test substrate, and each of the test end microprotrusions 2 matches the size of the contact to be tested 7.
  • the contact to be tested 7 is a through-silicon via, and the manufacturing process of the through-silicon via is a prior art, which is not described in detail; the test-end micro-bump 2 is formed by etching technology.
  • the top surface of the susceptor 1 of the test substrate has been etched to a level of 20 nanometers. Therefore, the microprojection 2 of the test end can be made small enough, for example, 5-1 0 micrometers, so the test end is slightly convex.
  • the size of the 2 can be made to match the size of the micro-silicon vias, and because the plurality of test-end micro-bumps 2 are arranged in the same layout as the over-silicon vias at the bottom of the wafer 10.
  • the top surface of the base 1 of the substrate therefore, when testing the wafer 10, the test end microbump 2 There is a one-to-one correspondence with the vias located at the bottom of the wafer 10.
  • a plurality of through-substrate vias 3 are connected to the top of the test-side micro-protrusions through the top-level wiring 8 and electrically connected.
  • the top layer wiring 8 has two layers. The first layer is on the top surface of the base 1 of the test substrate, and is covered with a test end microbump 2 for contacting the contact 7 to be tested, for example.
  • the through-silicon vias are connected one-to-one to fully contact and form a conductive path.
  • the test terminal micro bumps 2 are connected to the metal wires in the second layer top wiring horizontal wire layer 14 through the top wiring vertical wires 15.
  • the metal wires connect the top wiring vertical wires 15 connected from each of the test terminal micro bumps 2 to their corresponding via substrate vias 3. In this way, all of the test end microprotrusions 2 are connected to the respective corresponding substrate vias 3 and electrically conducted.
  • the second horizontal wire layer in order to make the top-level vertical wire 15 correspond to the through-substrate perforation, we need to use some routing algorithms. For details, see Application No. 6150729, entitled "Routing Desnity Ehancement for Semi U.S. Patent Application for the BGA Package And Printed Wiring Boards.
  • the through-substrate through hole 3 is formed by drilling a hole in the base 1 of the test substrate, then plating an inner surface of the through hole with an insulating material, and then pouring a metal (copper or other metal material). Since the poured metal material flows from the holes to the surface of the susceptor 1, it is necessary to corrode the excess metal on the surface. Up to this point, the through-substrate perforations 3 are substantially formed.
  • the top and bottom of the substrate via 3 etch the metal lines so that they are connected to the metal lines in the wiring layer and electrically conducted.
  • the through substrate via 3 includes a through hole penetrating through the base 1 of the test substrate, an insulating material plated on the inner surface of the through hole, and a metal material poured in the through hole.
  • the size of the through-substrate via 3 can be made very large, such as 100 micrometers. With the current process, the yield of large-sized through-substrate perforations has been very high and can be considered to be almost zero defect. It can be seen that the size of the through-substrate perforations is much larger than the size of the through-silicon perforations.
  • a plurality of detecting protrusions 4 are arranged on the bottom surface of the base 1 of the test substrate. As an optional embodiment, the detecting protrusion 4 can be selected as a C4 (Controlled Col lapse Chip).
  • each of the detecting protrusions 4 is electrically connected to a bottom of each of the through substrate vias 3, and each of the detecting protrusions 4 matches the size of each test probe 13
  • Each of the test probes 13 can be in close contact with each of the detecting protrusions 4 and through the through substrate through holes 3 corresponding to the detecting protrusions 4, the top layer wiring 8 and the test end micro protrusions 2, and the corresponding touches to be tested are established. point The signal connection of 7 realizes that one test probe 13 corresponds to only one contact 7 to be tested and transmits a test signal for detection.
  • the through substrate vias 3 are arranged in the same layout as the detecting protrusions 4 without increasing the underlying wiring 9, thereby establishing the test probe 13 and the detecting protrusions. 4, through the substrate perforation 3, the top layer wiring 8, the test end micro bumps 2, the contact to be tested 7 such as the signal contact between the through silicon vias.
  • the bottom of the base 1 of the test substrate is provided with an underlying wiring 9 through which the through-substrate vias 3 are connected in one-to-one correspondence with the detecting protrusions 4 and Electrically conductive. As shown in Fig.
  • the underlying wiring 9 has two layers: The first layer is on the bottom surface of the susceptor 1 of the test substrate, and is covered with a detecting protrusion 4 for detecting the test probe 13. All of the detecting bumps 4 are connected to the metal lines in the second layer of the underlying wiring horizontal wiring layer 17 through the underlying wiring vertical wires 16. In the second layer of the underlying wiring horizontal wiring layer 17, the metal wires respectively connect the underlying wiring vertical wires 16 respectively connected from the detecting bumps 4 to the bottoms of the corresponding via substrate vias 3. In this way, all the detecting protrusions 4 are connected and electrically connected to the corresponding corresponding substrate through holes 3. The underlying wiring 9 also needs to use some routing algorithms.
  • the bottom of the base 1 of the test substrate is provided with a contact pad 5 corresponding to the detecting protrusion 4 for making the detecting protrusion 4 better with the test probe 13 and
  • the substrate is perforated 3 to improve signal transmission quality.
  • the contact pad 5 can be connected to the detecting protrusion 4 by soldering, and the contact pad 5 directly conducts the via hole 3 and the detecting protrusion 4 without increasing the underlying wiring 9.
  • the through substrate vias 3 are arranged in the same layout as the detecting protrusions 4, because the contact pads 5 are one-to-one correspondingly soldered to the detecting protrusions 4,
  • the layout of the through-substrate vias 3 is also consistent with the layout of the contact pads 5, and the contact pads 5 can directly electrically conduct the corresponding via-substrate vias 3 and the detecting bumps 4.
  • the bottom of the base 1 of the test substrate is provided with a contact pad 5 corresponding to the detecting protrusions 4, and the contact pad 5 can be soldered.
  • the detecting bumps 4 are connected, and the contact pads 5 electrically conduct the via substrate vias 3 and the detecting bumps 4 through the underlying wiring 9.
  • the detecting protrusions 4 are disposed on the bottom surface of the base 1 of the test substrate in the same layout as the test probes 13. In this way, the test probe 13 can be in one-to-one contact with all the detecting protrusions 4, which is equivalent to detecting all the contacts 7 to be tested, such as through-silicon vias, and greatly shortening the detection of the wafer 10 . At the same time, direct detection of the contact 7 to be tested can be achieved without adding any intrusive structure to the wafer 10.
  • the top surface of the base 1 of the test substrate is covered with an elastic rubber layer 6 , and the elastic rubber layer 6 and the test end micro protrusion 2 vertically correspond to the contact to be tested 7 .
  • the elastic adhesive layer 6 can electrically conduct the test end microbump 2 and the contact to be tested 7 vertically.
  • the elastic adhesive layer 6 may be an anisotropic conductive adhesive.
  • the basic component of the anisotropic conductive adhesive is a semi-solidified adhesive, which contains particles. At a certain temperature, the particles will be broken after being squeezed. After the particles are broken, the conductive particles will be released to form a conductive path, so that the ends of the particles are formed into conductive paths.
  • a layer of anisotropic conductive adhesive is applied on the top surface of the base 1 of the test substrate and heated appropriately to allow the anisotropic conductive adhesive to adhere to the test substrate.
  • the separator of the anisotropic conductive adhesive surface layer is peeled off, and the wafer to be tested is placed on the anisotropic conductive adhesive by using a carrier device, and the test contact 7 at the bottom of the wafer 10 and the test end on the test substrate are placed.
  • the microprotrusions 2 are aligned.
  • the wafer 10 is pressed down and the temperature is raised to sufficiently bond the wafer 10 and the test substrate.
  • the particles between the contact to be tested 7 and the test tip microprotrusions 2 are crushed and then ruptured, releasing conductive particles, forming a conductive path between the contact to be tested 7 and the test end microprotrusions 2.
  • the wafer 10 is relatively easily peeled off; since the anisotropic conductive paste has good plasticity, after the extrusion, the contact 7 to be tested and the test end are slightly raised. 2 Full contact ensures good signal quality.
  • the base 1 of the test substrate is made of an insulating silicon material or a glass material.
  • the contact to be tested 7 passes through the through silicon via, and the test signal can be transmitted to all the devices on the wafer 10 through the wafer wiring layer 11 on the wafer 10.
  • the detection of all the input and output signals of the wafer 10 performs functional tests on the wafer 10, so that digital circuits, analog circuits, radio frequency circuits, and the like can be tested.
  • the smaller pitch between the contacts 7 to be tested such as the through-silicon vias
  • the test probe 13 is in one-to-one contact with the detecting protrusion 4, and the test signal is transmitted through the detecting protrusion 4 to the through-substrate through hole 3,
  • the substrate via 3 transmits a test signal to the contact 7 to be tested of the wafer 10 through the top wiring 8 and the test terminal micro bump 2, such as over the via, and passes through the wafer wiring layer 1 on the wafer 10.
  • Embodiment 2 Since the wafer 10 in the 2.5-dimensional chip has no through-silicon via, the following modifications can be made on the basis of Embodiment 1: In order to perform pre-stack test on the wafer 10 constituting the 2.5-dimensional chip, as a, the micro-bump to be tested is formed as an input/output port of the test signal by etching at the bottom of the wafer 10. At present, the etching technology has reached the level of 20 nanometers, therefore, the The microtips can be made small enough, such as 5-1 0 micrometers, to establish a signal connection with the various devices on the wafer 10 through the wafer wiring layer 11.
  • test end microbumps 2 on the top surface of the substrate 1 of the test substrate are arranged in the same layout as the contacts 7 to be tested at the bottom of the wafer 10, that is, the microbumps to be tested.
  • a one-to-one correspondence may be established between the micro-protrusion of the end to be tested and the micro-protrusion 2 of the test end, and the micro-protrusion of the end to be tested may pass through the test end micro-protrusion 2, the top-level wiring 8, and the over-substrate
  • the perforation 3, the detecting protrusion 4, and the like establish a signal connection corresponding to each of the test probes.
  • Each test probe 13 can indirectly transmit the test signal to each of the micro-bumps corresponding to the test end, and input and output a test signal through the micro-bump to be tested, because the test end is slightly raised.
  • the signal connection is established by the wafer wiring layer 1 1 and the respective devices on the wafer 10, so that the functions of the micro-bumps to be measured and the entire wafer 10 can be detected, and the defective wafer can be eliminated. In this way, the packaged wafers can all be qualified wafers, thereby improving the yield of the 2.5-dimensional chip.
  • Embodiment 3 The test substrate described in Embodiment 1, Embodiment 2 can also be used to manufacture a probe card without indirectly transmitting a test signal to the contact 7 to be tested on the wafer 10 without using the test probe 13 indirectly.
  • the embodiment is as follows: For the test substrate not containing the contact pad 5, only the detecting protrusion 4 located on the bottom surface of the susceptor 1 of the test substrate is removed, and wiring is added at the bottom layer of the susceptor 1 of the test substrate. And directly transmitting the test signal from the automatic test machine to each test end microbump 2 on the top surface of the base 1 of the test substrate by adding wiring, and passing the test end microbump 2, It is transferred to each of the contacts 7 to be tested located at the bottom of the wafer 10, and the test signal is output to an automatic test machine by adding wiring, and the wafer 10 is detected to reject the defective wafer.
  • the detecting protrusion 4 and the contact pad 5 need to be removed, and wiring is added to the bottom layer of the base 1 of the test substrate, and the new The additional wiring directly transmits the test signal from the automatic test machine to each test end microprotrusion 2 located on the top surface of the base 1 of the test substrate, and passes through the test end microbump 2 to the location On each of the contacts 7 to be tested at the bottom of the wafer 10, the test signal is output to an automatic test machine by adding wiring, and the wafer 10 is detected to reject the defective wafer.
  • the contact to be tested 7 is a through-silicon via or a micro-bump to be tested; the micro-bump to be tested is formed at the bottom of the wafer 10 by an etching technique.
  • Embodiment 4 This solution can be used for pre-stack testing of a plurality of wafers 10, such as wafers 18, in addition to being used for pre-stack testing of a wafer 10. As shown in FIG. 9a, the test substrate adheres to the wafer 10 on a wafer 18 each time. During the test, the test end microbumps 2 on the test substrate and the to-be-tested contacts 7 of the wafer 10 on the bonded wafer 18 are tested.
  • the detecting protrusions 4 on the test substrate are connected to each test probe 13 in a corresponding manner, and the test probe 13 introduces a test signal from the automatic test machine. Since the test end micro bumps 2 on the test substrate are arranged in accordance with the layout of the contacts 7 to be tested on the wafer 10 of the wafer 18, it is equivalent to indirectly establishing each test probe. 13 is in signal communication with each of the contacts 7 to be tested on the wafer 18 in a one-to-one correspondence, so that all the wafers 10 on the wafer 18 can be sequentially inspected, and the defective wafers are removed, thereby improving the production. The yield of the wafer. As shown in FIG.
  • a larger test substrate can also be fabricated so that a plurality of wafers 10 on the wafer 18 can be simultaneously bonded, and the plurality of wafers 10 are simultaneously detected by the test probe 13 to improve the detection speed.
  • the test substrate is large enough, we can place enough test-end micro-protrusions 2 on it, through the substrate vias 3 and the detection bumps 4, so that all the detection contacts 7, such as silicon Both the perforation or the microprojection on the end to be tested can be simultaneously detected by the test probe 13.

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Abstract

提供一种测试基板及采用该测试基板制造的探针卡，所述测试基板顶部表面上的测试端微凸起（2）按照待测晶片（10）底部待测触点（7）的布局进行排列，通过顶层布线（8）与过基板穿孔（3）对应连接并电导通，过基板穿孔（3）与测试基板底部表面的探测凸起（4）对应连接并电导通，探测凸起（4）与测试探针（13）的尺寸相匹配，建立了测试探针（13）与测试端微凸起（2）和待测触点（7）间一一对应的信号关系，解决了现有技术中因测试探针（13）尺寸过大而待测触点（7）尺寸过小，无法通过测试探针（13）直接对每一待测触点（7）进行检测的问题。通过在测试基板顶部表面铺上异方性导电胶，使得测试端微凸起（2）与待测触点（7）无需接触即可电导通，避免了对晶片（10）的损伤且提高了信号传输性质。

Description

一种测试基板及采用该测试基板制造的探针卡 技术领域 本发明涉及一种测试基板及采用该测试基板制造的探针卡，具体是一种 在半导体制造业，用来对芯片进行检测的一种测试基板及采用该测试基板制 造的探针卡， 属于电子测试技术领域。 背景技术 随着芯片制造工艺的不断进步， 芯片的体积不断减小同时运算速度不断 提高。 然而， 随着半导体制成工艺进入深纳米级， 芯片的性能己经无法像原 来那样继续提高， 主要受以下因素影响： （1) 芯片互连上的延迟己经取代器 件本身的延迟，成为提高芯片速率的最大障碍；（2)随着集成度的不断提高， 芯片中集成了更多数量的不同工艺的器件， 如数字逻辑器件、 模拟器件和射 频器件等， 芯片中器件数量的增加导致芯片的面积增大， 同时不同器件间的 连线也随之增加， 同时使芯片制造工艺的复杂度也不断增加， 严重影响进一 步提高芯片的集成度和运行速度。 为了延续摩尔定律， 产生了三维芯片的技 术思路。 三维芯片是指将未封装的晶片 10在垂直方向上进行堆叠， 并封装成一 颗完整的芯片。这些堆叠在一起的晶片 10通过一种叫做 "过硅穿孔" (Through Si l icon Via, 简称 TSV) 的技术来互相传递信号。 图 1a为两层晶片 10堆叠 在一起的立体图， 如图 1a所示， 第一层晶片 10的衬底 20被削薄后就可以 让待测触点 7， 在三维芯片中即为过硅穿孔穿透第一层晶片 10的衬底 20。 过硅穿孔与第二层晶片 10的晶片布线层 11连在一起， 起到了在晶片器件层 12传递信号（包括数据 /电源 /接地 /时钟信号）的作用。 图 1b中显示了三个 晶片 10， 通过粘合层 22粘结堆叠在一起的剖面图， 如图 1b所示， 每一层晶 片 10都通过待测触点 7， 即过硅穿孔和相邻晶片 10建立了信号联系。 通过 三维芯片的方式， 增大了芯片中器件的集成密度， 减少信号延迟， 降低芯片 功耗， 更重要的是， 不同工艺的芯片可以通过堆叠方式集成在一起， 减少了 多工艺芯片制造的成本和风险。 但是三维芯片在制造过程中引入的各种缺陷 导致三维芯片的良品率过低。 其中很重要的一个原因是晶片 10在堆叠封装 前没有进行检测， 而在晶片 10上形成过硅穿孔的工艺非常复杂， 很容易在 形成过硅穿孔时给晶片 10 带来缺陷导致晶片无法正常使用， 而将未经检测 的多片晶片 10进行堆叠封装后， 任何一个晶片 10发生故障， 都将导致整个 三维芯片无法使用， 这就导致了三维芯片的良品率过低。 为了解决这一难题， 业界和学术界提出了一种可以有效提高三维芯片良 品率的方法， 即堆叠前测试。 其基本原理就是在堆叠封装前先对晶片 10进 行测试， 把有故障的晶片 10丢弃， 以保障进行堆叠封装的晶片 10都是无故 障的晶片， 提高三维芯片的良品率。 但是， 晶片 10在堆叠封装前只是一片 裸晶片， 其不具有任何可以外接测试工具的管脚， 因此如何将测试信号输入 到晶片 10上的器件中以及如何将测试信号从晶片 10上的器件中引出成为一 个难题。 现有的堆叠前测试方案主要分为两类：
(1) 正面探测， 如图 2a所示， 即测试探针 13不直接接触待测触点 7， 即过硅穿孔， 而是通过触碰晶片 10正面专门设计的测试衬垫 19来传递测试 信号。 正面探测的优点是不用磨薄晶片 10， 但缺点就是测试衬垫 19面积比 较大， 占用较多的片上面积， 增加了测试时间和成本， 而且过硅穿孔的另一 端埋在晶片衬底 20中，无法直接对过硅穿孔进行测试。为了解决这一问题， 有研宄人员设计出内建自检 （bui lt in self test) 结构对过硅穿孔进行测 试， 如 M. Cho， C. Liu, D. Kim, S. Lim, 和 S. Mukhopadhyay, 在 IEEE/ACM Int, Conf. (美国计算机学会 /电子和电气工程师协会国际学术会议） 以及 Computer- Aided Design, pp. 694-697， 2010. (2010 年计算机辅助设计 694 到 697 页） 发表的论文 "Design Method and Test Structure to Character i ze and Repair TSV Defect Induced Signal Degradation in 3D System" 就介绍了这样一种方案， 但这类方法需要为每个过硅穿孔设计对 应的自检结构电路。 目前三维芯片中往往有上千个过硅穿孔， 密度也在 10000/mm2上下， 因此这类方法会占用大量的芯片面积和布线资源。而且自检 结构电路往往有很多模拟器件， 在数字器件中加入模拟器件， 不但极大的增 加了制造成本， 而且这些模拟器件非常容易受到周围数字电路的干扰， 导致 较大的测试误差， 另外， 上述方法只提供了对过硅穿孔的测试， 而无法通过 过硅穿孔测试晶片 10上的电路。
(2) 背面探测， 如图 2b所示， 既测试探针 13直接接触晶片 10背面的 待测触点 7， 即过硅穿孔， 并经由过硅穿孔来传递测试信号。 背面探测虽然 没有正面探测方法所具有的那些缺点， 但它同样有很多不足。 首先测试探针 13的尺寸最小只能达到 35微米， 但目前过硅穿孔的尺寸最小己经达到 4. 4 微米以下。 显然， 这种巨大的差距造成了无法用测试探针 13准确探测过硅 穿孔， 如图 3所示， 由于测试探针 13和过硅穿孔之间巨大的尺寸差距， 一 个测试探针 13 同时覆盖多个过硅穿孔， 无法做到对单个过硅穿孔的直接探 测； 其次为了能够让过硅穿孔裸露， 晶片 10必须被削薄到 50微米左右的厚 度， 而另一方面， 必须给晶片 10施加足够的压力才能让测试探针 13和过硅 穿孔充分接触。 在这种压力下， 这个厚度的晶片 10 非常容易损坏。 而且削 薄后的晶片 10很容易弯曲及表面不平整， 这就使得某些测试探针 13无法与 过硅穿孔充分接触， 大大影响了测试信号的质量。 考虑到过硅穿孔和测试探针 13之间有如此大的尺寸差距， 现有技术又 提出一种允许每个测试探针 13接触多个过硅穿孔的方法， 如 B. No i a 和 K. Ghakrabarty于 201 1年在 Proc. I EEE I nternat i ona l Test Conference, pp. 1 -10 (美国电气电子工程师协会期刊第 1 -10 页） 发表的论文 " Pre-bond Prob i ng of TSVs i n 3D stacked I Cs "， 就公开了每个测试探针 13接触多 个待测触点 7， 即过硅穿孔的方案， 如图 4所示， 多个被同一个测试探针 13 探测的过硅穿孔有一端被短路在一起，形成一个过硅穿孔网络（TSV g roup)。 为了能够区别地测试每个过硅穿孔， 在过硅穿孔的另一端， 连接一个带开关 的测试触发器 23 (Gated Scan F l i p f l op ) , 所有这些带开关的测试触发器 23最终连成测试扫描链， 通过控制对应的触发器开关， 他们可以控制让测试 信号只通过网络中的某个选定的过硅穿孔， 通过测量过硅穿孔充放电的时间 估计其电阻 /电容值来确定是否有缺陷。 这一方法虽然间接地解决了对过硅 穿孔探测的难题， 但也有很多局限性， 首先， 由于使用了测试扫描链， 使这 种方法只能进行模块化测试， 即只能测试数字电路， 这一局限对于三维芯片 尤为致命， 因为三维芯片的一大优势就是在一个芯片中集成多种不同工艺的 晶片 1 0 (包括模拟电路、 RF视频电路、 存储器等）。 这些非数字电路的晶片 1 0都无法使用上面提出的方法； 其次， 这种测试手段不可避免的需要改变原 始晶片内部的电路， 这种侵入式的设计方法在实际的生产中有很大的局限性; 最后， 同一个网络中的过硅穿孔是无法同时并行测试的， 比如， 如果每个测 试探针 1 3接触五个过硅穿孔， 那么就需要五个时钟周期来完成对所有的过 硅穿孔的测试。 所以， 实际上， 这个方法用了以时间换取空间的策略， 测试 完所有的过硅穿孔的话消耗的时间太长， 测试效率太低。 公开号为 CN 1 02478950 A， 发明名称为 "直接针测式的探针测试装置" 的专利文献， 公开了一种包括空间转换器的探针测试装置， 最下方为垂直式 探针组， 与待测装置接触， 上方连接空间转换器以及探针接口板等组件， 虽 然所述探针组包括多个垂直式探针， 相较于传统的探针卡， 尺寸有了明显的 缩小， 但采用现有的制作工艺探针无法做到与过硅穿孔的尺寸相匹配（过硅 穿孔可达 4. 4微米以下， 而测试探针最小也只能达到 35微米）。 并且虽然通 过空间转换器提供了使布线空间从较小间距转换成较大间距的接口， 但因空 间转换器是在电路板的尺寸量级上制作的， 因此通过垂直式探针和空间转换 器无法对微米级的过硅穿孔同时进行逐个检测， 不适于对三维芯片、 2. 5维 芯片的晶片进行堆叠前测试。 发明内容 本发明所要解决的技术问题是现有技术中芯片测试装置尺寸过大，而构 成三维芯片中的晶片上的过硅穿孔尺寸小且排列密度大，无法同时对过硅穿 孔逐个进行检测， 因而不适用于对三维芯片的晶片进行封装前的检测，从而 提供一种能够同时对每个过硅穿孔进行检测，适用于三维芯片的晶片封装前 的检测的一种测试基板及采用该测试基板制造的探针卡。 为解决上述技术问题， 本发明是通过以下技术方案实现的： 本发明涉及一种测试基板， 用于对晶片进行堆叠前测试， 包括： 多个测试端微凸起， 按照与所述晶片底部的待测触点相同的布局排列于 所述测试基板的基座的顶部表面， 且每一所述测试端微凸起与所述待测触点 的尺寸相匹配； 多个过基板穿孔， 其顶部通过顶层布线与所述测试端微凸起一一对应连 接并电导通； 多个探测凸起， 排列于所述测试基板的基座的底部表面， 每一所述探测 凸起与每一所述过基板穿孔的底部对应电连接， 且每一所述探测凸起与每一 测试探针的尺寸相匹配。 所述测试端微凸起通过刻蚀技术在所述测试基板的基座的顶部表面形 成。 作为一种可选的实施方式， 所述过基板穿孔按照与所述探测凸起相同的 布局进行排列。 作为另一种可选的实施方式， 所述测试基板的基座的底部设置有底层布 线， 所述过基板穿孔通过所述底层布线与所述探测凸起一一对应连接并电导 通。 所述探测凸起按照与测试探针相同的布局设置于所述测试基板的基座 的底部表面。 所述测试基板的基座的顶部表面覆盖一层弹性胶层， 所述弹性胶层与所 述测试端微凸起与所述待测触点垂直对应的部分电导通， 其余部分绝缘。 所述弹性胶层为异方性导电胶。 所述测试基板的基座由绝缘的硅材料或玻璃材料制成。 所述过基板穿孔包括贯穿所述测试基板的基座的通孔， 镀于所述通孔内 表面的绝缘材质及所述通孔内灌注的金属材料。 所述待测触点为过硅穿孔或待测端微凸起； 所述待测端微凸起是通过刻蚀技术在所述晶片的底部形成。 一种采用所述测试基板制造的探针卡， 通过去除探测凸起， 并在所述测 试基板的基座的底层增加布线， 将测试信号通过新增的布线传递到位于所述 测试基板的基座的顶部表面的每个测试端微凸起， 并通过所述测试端微凸起， 传递到位于所述晶片底部的每个待测触点上， 并将测试后的信号输出， 对所 述晶片进行检测； 所述待测触点为过硅穿孔或待测端微凸起； 所述待测端微 凸起是通过刻蚀技术在所述晶片的底部形成。 本发明的上述技术方案相比现有技术具有以下优点：
( 1 ) 本发明所述的测试基板， 包括多个测试端微凸起， 排列于所述测 试基板的基座的顶部表面， 按照与待测晶片底部的待测触点一一对应的位置 进行布局； 多个过基板穿孔， 其顶部通过顶层布线与所述测试端微凸起一一 对应连接并电导通， 其底部与位于所述测试基板的基座的底部表面的探测凸 起对应相连并电导通， 所述探测凸起与每一测试探针的尺寸相匹配， 从而建 立起位于待测晶片底部的待测触点与测试探针间的一一对应的信号联系。 因 为待测触点， 比如过硅穿孔的间距很密， 密度在 10000/mm2上下， 过基板穿 孔的尺寸可以做的很大， 比如 1 00微米， 这种大尺寸的设计可以使过基板穿 孔的制造缺陷率几乎为零， 且过基板穿孔的间距也要远大于待测触点， 比如 过硅穿孔的间距。 通过这种布局， 可以将待测触点间较小的间距转换为过基 板穿孔间的较大的间距， 因为测试基板的缺陷率几乎为零， 因此， 可以通过 这种测试基板同时对待测触点 （比如过硅穿孔） 进行测试， 测试时， 测试探 针与探测凸起一一对应接触， 将测试信号通过探测凸起传送到过基板穿孔， 过基板穿孔通过顶层布线和测试端微凸起将测试信号传送到待测晶片的待 测触点， 比如过硅穿孔上， 并通过待测晶片上的布线传递测试信号， 对整个 待测晶片进行检测， 筛除不合格的晶片， 因为所有经过检测的晶片均为合格 晶片， 从而提高了三维芯片或者 2. 5维芯片的良品率。 且因为所述待测触点 (比如过硅穿孔） 与测试端微凸起为一一对应关系， 所述测试端微凸起与过 基板穿孔为一一对应， 而所述过基板穿孔与探测凸起一一对应， 且所述探测 凸起的尺寸与测试探针尺寸相匹配， 因而所述测试探针就间接的相当于同时 对每一待测触点 （比如过硅穿孔） 进行检测， 缩短了检测时间， 减少了测量 误差。
( 2 ) 本发明所述的测试基板， 只要测试基板足够大， 就可以让所有的 信号同时进入所有的待测触点 （比如过硅穿孔）， 大大提高了测试带宽。
( 3 ) 本发明所述的测试基板， 由于所有的待测触点 （比如过硅穿孔）， 都可以同时被探测到， 因此本发明不需要在晶片内加入任何侵入式的结构即 可进行测试，节省了布线资源，减少了线路间的相互干扰，减小了测量误差。
( 4) 本发明所述的测试基板， 通过待测触点和待测晶片上的布线将测 试信号传送到待测晶片上的所有器件， 通过对待测晶片的所有输入输出的检 测， 对待测晶片进行功能性测试， 因此， 可以对数字电路、 模拟电路、 射频 电路等进行测试， 扩大了可测试范围。
( 5 ) 利用本发明所述的测试基板制作的探针卡， 通过去除探测凸起， 并在所述测试基板的基座的底层增加布线， 将测试信号通过新增的布线传递 到位于所述测试基板的基座的顶部表面的每个测试端微凸起， 并通过所述测 试端微凸起， 传递到位于所述晶片底部的每个待测触点上， 并将测试后的信 号输出， 对所述晶片进行检测。 无需引入第三方测试探针即可对晶片进行检 测， 简化了测试设备。 附图说明 为了使本发明的内容更容易被清楚的理解， 下面结合附图， 对本发明 作进一步详细的说明， 其中， 图 1 a是三维芯片的立体结构示意图； 图 1 b是三维芯片的剖面图； 图 2a是背景技术中正面探测的示意图； 图 2b是背景技术中背面探测的示意图； 图 3是测试探针和过硅穿孔间尺寸比较的示意图； 图 4是背景技术中对过硅穿孔网络进行检测的示意图； 图 5是本发明所述测试基板的立体结构示意图； 图 6是本发明一实施方式所述测试基板的剖面示意图； 图 7是本发明所述测试基板顶层布线示意图; 图 8是本发明所述测试基板底层布线示意图； 图 9a是测试基板每次粘连晶圆上的一块晶片进行测试的示意图； 图％是测试基板每次粘连晶圆上的多块晶片进行测试的示意图； 图 1 0是测试基板测试晶圆时的立体图。 图中附图标记表示为： 1 -基座， 2- 测试端微凸起， 3-过基板穿孔 ， 4-探测凸起 ， 5-接触衬垫， 6- 弹性胶层， 7-待测触点， 8-顶层布线， 9-底 层布线， 1 0-晶片， 1 1 -晶片布线层， 1 2-晶片器件层， 1 3-测试探针， 14-顶 层布线水平导线层， 1 5-顶层布线垂直导线， 1 6-底层布线垂直导线， 1 7-底 层布线水平导线层， 1 8-晶圆， 19-测试衬垫， 20-衬底， 21 -托盘， 22-粘合 层， 23-带开关的测试触发器。 具体实施方式 下面将对本发明的实施方式进行详细说明。 实施例 1 本发明所述的测试基板， 用于对晶片 1 0进行堆叠前测试， 如图 5、 图 6 所示， 包括： 多个测试端微凸起 2，按照与所述晶片 1 0底部的待测触点 7相同的布局 排列于所述测试基板的基座 1的顶部表面， 且每一所述测试端微凸起 2与所 述待测触点 7的尺寸相匹配。 对于三维芯片来说， 所述待测触点 7为过硅穿孔， 过硅穿孔的制造工艺 为现有技术， 此不赘述； 所述测试端微凸起 2是通过刻蚀技术形成于所述测 试基板的基座 1 的顶部表面， 目前， 刻蚀技术己经达到 20纳米级， 因此， 所述测试端微凸起 2可以做到足够小， 比如 5-1 0微米， 因此测试端微凸起 2 的尺寸可以做成与微米级的过硅穿孔的尺寸相匹配， 又因为多个测试端微凸 起 2是按照与所述晶片 1 0底部的过硅穿孔相同的布局排列于所述测试基板 的基座 1 的顶部表面， 因此， 对晶片 1 0进行测试时， 所述测试端微凸起 2 与位于所述晶片 10底部的过硅穿孔是一一对应连接的。 多个过基板穿孔 3， 其顶部通过顶层布线 8与所述测试端微凸起 2—一 对应连接并电导通。 如图 7所示， 所述顶层布线 8有两层， 第一层在测试基 板的基座 1 的顶部表面， 上面布满了测试端微凸起 2， 用以与待测触点 7， 比如过硅穿孔一一对应连接， 充分接触并形成导电通路。 所述测试端微凸起 2通过顶层布线垂直导线 15连接到第二层顶层布线水平导线层 14中的金属 线。在第二层顶层布线水平导线层 14中， 金属线会将从每个测试端微凸起 2 连下来的顶层布线垂直导线 15连接到其对应的过基板穿孔 3 。 如此一来， 所有的测试端微凸起 2都会和各自对应的过基板穿孔 3相连并电导通。 在第 二层水平导线层中， 要使顶层布线垂直导线 15与过基板穿孔 3—一对应， 我们需要用到一些布线算法， 具体可参看申请号为 6150729， 发明名称为 " Routing Desnity Ehancement for Semi conductor BGA Package And Printed Wiring Boards"的美国专利申请。 但这些布线算法是公开的技术， 不属于本发明范畴， 此不赘述。 所述过基板穿孔 3， 是通过在测试基板的基座 1 中钻孔， 然后在该通孔 内表面镀上绝缘材质， 之后灌入金属 （铜或者其他金属材质） 形成。 由于灌 入的金属材质会从孔中流至基座 1 的表面， 因此需要腐蚀表面多余的金属。 到此为止， 过基板穿孔 3就基本成型了。 过基板穿孔 3的顶部和底部会刻蚀 金属线， 使它们与布线层中的金属线相连并电导通。 因此， 所述过基板穿孔 3包括贯穿所述测试基板的基座 1 的通孔， 镀于所述通孔内表面的绝缘材质 及所述通孔内灌注的金属材料。 所述过基板穿孔 3的尺寸可以做的很大， 比 如 100微米， 以目前的工艺， 大尺寸的过基板穿孔的良率己经非常高， 几乎 可以认为是零缺陷。 可见， 过基板穿孔的尺寸要比过硅穿孔的尺寸大很多。 多个探测凸起 4， 排列于所述测试基板的基座 1 的底部表面， 做为可选 的实施方式， 所述探测凸起 4 可以选用 C4 (Control led Col lapse Chip
Connection) 凸起， 每一所述探测凸起 4与每一所述过基板穿孔 3的底部对 应电连接， 且每一所述探测凸起 4与每一测试探针 13的尺寸相匹配， 因此 每一测试探针 13可以与每一探测凸起 4紧密接触并通过与该探测凸起 4对 应的过基板穿孔 3、 顶层布线 8、 测试端微凸起 2， 建立起与对应的待测触点 7的信号联系，既实现了一个测试探针 13只对应一个待测触点 7并对其发送 测试信号进行检测 。 克服了现有技术的不足， 缩短了检测时间， 减少了测
作为一种可选的实施方式， 在不增加底层布线 9的情况下， 所述过基板 穿孔 3按照与所述探测凸起 4相同的布局进行排列，从而建立起测试探针 13、 探测凸起 4、 过基板穿孔 3、 顶层布线 8、 测试端微凸起 2、 待测触点 7比如 过硅穿孔间的信号联系。 作为另一种可选的实施方式， 所述测试基板的基座 1 的底部设置有底层 布线 9， 所述过基板穿孔 3通过所述底层布线 9与所述探测凸起 4一一对应 连接并电导通。 如图 8所示， 底层布线 9有两层： 第一层在测试基板的基座 1 的底部表面， 上面布满了探测凸起 4， 用于让测试探针 13探测。 所有的探 测凸起 4通过底层布线垂直导线 16连接到第二层底层布线水平导线层 17中 的金属线。 在第二层底层布线水平导线层 17 中， 金属线分别会将各自从探 测凸起 4连上来的底层布线垂直导线 16连接到对应的过基板穿孔 3的底部。 如此一来，所有的探测凸起 4都会和各自对应的过基板穿孔 3连接并电导通。 底层布线 9也需要用到一些布线算法， 具体可参照对顶层布线 8的描述， 此 不赘述。 作为一种改进， 所述测试基板的基座 1 的底部设置有与所述探测凸起 4 一一对应的接触衬垫 5，用于使探测凸起 4更好的与测试探针 13和过基板穿 孔 3接触， 提高信号传输质量。 所述接触衬垫 5可以通过焊接的方式与探测 凸起 4连接且在不增加底层布线 9的情况下， 所述接触衬垫 5直接将所述过 基板穿孔 3与所述探测凸起 4电导通， 此时所述过基板穿孔 3要按照与所述 探测凸起 4相同的布局进行排列， 因为所述接触衬垫 5是一一对应焊接于所 述探测凸起 4上的， 因此所述过基板穿孔 3的布局也与所述接触衬垫 5的布 局一致， 所述接触衬垫 5就可以直接将对应的所述过基板穿孔 3与所述探测 凸起 4电导通。 作为一种可选的实施方式， 所述测试基板的基座 1 的底部设置有与所述 探测凸起 4一一对应的接触衬垫 5， 所述接触衬垫 5可以通过焊接的方式与 探测凸起 4连接， 且所述接触衬垫 5通过底层布线 9将所述过基板穿孔 3与 所述探测凸起 4电导通。 作为一种优选的实施方式， 所述探测凸起 4按照与测试探针 1 3相同的 布局设置于所述测试基板的基座 1 的底部表面。 这样， 测试探针 1 3就可以 与所有的探测凸起 4一一对应接触， 就相当于可以同时对所有的待测触点 7 比如过硅穿孔进行检测， 大大缩短了对晶片 1 0 的检测时间， 也无需在晶片 1 0内加入任何侵入式的结构即可实现对待测触点 7的直接探测。 作为一种改进，所述测试基板的基座 1的顶部表面覆盖一层弹性胶层 6， 所述弹性胶层 6与所述测试端微凸起 2与所述待测触点 7垂直对应的部分电 导通， 其余部分绝缘， 如图 6所示， 所述弹性胶层 6可以垂直电导通所述测 试端微凸起 2与所述待测触点 7。 所述弹性胶层 6可以选用异方性导电胶， 异方性导电胶的基本组成部分 为半凝固态的的黏性胶， 内含有微粒。 在一定温度下， 这些微粒受到挤压后 便会破裂， 多个微粒破裂后， 会释放导电粒子， 形成一个导电通道， 使挤压 这些微粒的两端形成导电通路。 具体使用时， 先在测试基板的基座 1的顶部 表面铺上一层异方性导电胶并适当加热， 使异方性导电胶能粘连在测试基板 上。 然后剥去异方性导电胶表层的隔膜， 利用载体设备将待测晶片置于该异 方性导电胶上， 并将所述晶片 1 0底部的待测触点 7与测试基板上的测试端 微凸起 2对齐。 最后， 向下挤压所述晶片 1 0并升高温度使所述晶片 1 0和测 试基板充分粘合。待测触点 7和测试端微凸起 2之间的微粒受到挤压后破裂， 释放出导电粒子， 在待测触点 7和测试端微凸起 2之间形成一个导电通道。 因为所述晶片 1 0表面和测试基板表面只有待测触点 7和测试端微凸起 2是 凸起的， 既只有待测触点 7和测试端微凸起 2间的微粒会受到挤压破裂并释 放导电粒子， 而其它部分的异方性导电胶中的微粒仍然保持完整和游离状态， 不会释放导电粒子。 因此， 相邻待测触点 7间以及相邻测试端微凸起 2间不 会形成短路。 通过此种方式， 待测触点 7和测试端微凸起 2间无需直接接触即可形成 电导通， 不会损伤所述晶片 1 0; 测试完成后， 加热融化异方性导电胶， 即可 实现测试基板和所述晶片 1 0的分离， 比较容易剥离所述晶片 1 0; 由于异方 性导电胶具有良好的可塑性， 经过挤压之后， 可以使待测触点 7和测试端微 凸起 2充分接触， 保证了良好的信号质量。 作为可选的实施方式， 所述测试基板的基座 1 由绝缘的硅材料或玻璃材 料制成。 本实施例中， 所述待测触点 7， 既过硅穿孔， 可以通过所述晶片 1 0上的 晶片布线层 1 1将测试信号传送到所述晶片 1 0上的所有器件， 通过对所述晶 片 1 0的所有输入输出信号的检测， 对所述晶片 1 0进行功能性测试， 因此， 可以对数字电路、 模拟电路、 射频电路等进行测试。 本方案， 可以将待测触点 7， 比如过硅穿孔间较小的间距转换为过基板 穿孔 3间的较大的间距， 因为测试基板的缺陷率几乎为零， 因此， 可以通过 这种测试基板同时对待测触点 7 (比如过硅穿孔） 进行测试， 测试时， 测试 探针 1 3与探测凸起 4一一对应接触， 将测试信号通过探测凸起 4传送到过 基板穿孔 3， 过基板穿孔 3通过顶层布线 8和测试端微凸起 2将测试信号传 送到所述晶片 1 0的待测触点 7， 比如过硅穿孔上， 并通过所述晶片 1 0上的 晶片布线层 1 1传递测试信号，对整个晶片 1 0进行检测，筛除不合格的晶片， 因为所有经过检测的晶片均为合格晶片， 从而提高了三维芯片的良品率。 且 因为所述待测触点 （比如过硅穿孔） 与测试端微凸起 2为一一对应关系， 所 述测试端微凸起 2与过基板穿孔 3为一一对应， 而所述过基板穿孔 3与探测 凸起 4一一对应， 且所述探测凸起的尺寸与测试探针 1 3尺寸相匹配， 因而 所述测试探针 1 3就间接的相当于同时对每一待测触点 7 (比如过硅穿孔）进 行检测， 缩短了检测时间， 减少了测量误差。 实施例 2 因为 2. 5维芯片中的晶片 1 0无过硅穿孔， 在实施例 1 的基础上可以做 如下改动： 为了对构成 2. 5维芯片的晶片 1 0进行堆叠前测试， 作为一种可选的实 施方式， 可以在所述晶片 1 0底部通过刻蚀技术形成待测端微凸起作为测试 信号的输入输出端口。 目前， 刻蚀技术己经达到 20纳米级， 因此， 所述待 测端微凸起可以做到足够小， 比如 5-1 0微米， 通过晶片布线层 1 1与晶片 1 0 上的各个器件建立信号联系。 因为位于所述测试基板的基底 1的顶部表面的测试端微凸起 2是按照与 所述晶片 1 0底部的待测触点 7， 即待测端微凸起的相同的布局进行排列， 因 此所述待测端微凸起与测试端微凸起 2之间可以建立一一对应的信号联系， 则所述待测端微凸起可以通过测试端微凸起 2、 顶层布线 8、 过基板穿孔 3、 探测凸起 4等， 建立与每一测试探针 1 3—一对应的信号联系 。 既每一测试 探针 1 3可以间接将测试信号传入与之对应的每一待测端微凸起， 通过待测 端微凸起输入、 输出测试信号， 因所述待测端微凸起通过晶片布线层 1 1 与 晶片 1 0上的各个器件建立了信号联系， 因此可以对待测端微凸起和整个晶 片 1 0 的功能进行检测， 剔除有缺陷的晶片。 通过此种方式， 可以使被封装 的晶片都为合格晶片， 从而提高了 2. 5维芯片的良品率。 实施例 3 实施例 1、 实施例 2所述测试基板也可用于制造探针卡， 无需额外使用 测试探针 1 3间接传输测试信号给所述晶片 1 0上的待测触点 7 。实施方式如 下： 对于不含有接触衬垫 5的测试基板， 只需拆除位于所述测试基板的基座 1 的底部表面的探测凸起 4， 并在所述测试基板的基座 1 的底层增加布线， 并通过新增布线直接将来自自动测试机上的测试信号传递到位于所述测试 基板的基座 1 的顶部表面的每个测试端微凸起 2， 并通过所述测试端微凸起 2， 传递到位于所述晶片 1 0底部的每个待测触点 7上， 并通过新增布线将测 试后的信号输出至自动测试机， 对所述晶片 1 0进行检测， 剔除不良晶片。 对于既含有接触衬垫 5， 又含有探测凸起 4的测试基板， 需要拆除所述 探测凸起 4及接触衬垫 5， 并在所述测试基板的基座 1 的底层增加布线， 并 通过新增布线直接将来自自动测试机上的测试信号传递到位于所述测试基 板的基座 1的顶部表面的每个测试端微凸起 2，并通过所述测试端微凸起 2， 传递到位于所述晶片 1 0底部的每个待测触点 7上， 并通过新增布线将测试 后的信号输出至自动测试机， 对所述晶片 1 0进行检测， 剔除不良晶片。 所述待测触点 7为过硅穿孔或待测端微凸起； 所述待测端微凸起是通过 刻蚀技术在所述晶片 10的底部形成。 实施例 4 本方案除了可以用于一片晶片 10的堆叠前测试，也可以对多片晶片 10， 比如晶圆 18进行堆叠前测试。 如图 9a所示， 测试基板每次粘连一块晶圆 18上的晶片 10， 测试时， 测 试基板上的测试端微凸起 2与粘连的晶圆 18上的晶片 10的待测触点 7—一 对应相接， 测试基板上的探测凸起 4与每一测试探针 13—一对应相接， 所 述测试探针 13从自动测试机引入测试信号。 因为所述测试基板上的测试端 微凸起 2是按照与位于所述晶圆 18的晶片 10上的待测触点 7的布局进行排 列的， 所以， 相当于间接建立了每一测试探针 13与晶圆 18上的晶片 10的 每一待测触点 7间一一对应的信号联系， 从而可以逐次对晶圆 18上的所有 晶片 10进行检测， 将不良的晶片剔除， 提高生产出来的晶片的良品率。 如图％所示， 也可以制作更大的测试基板， 使其可以同时粘连多个位 于晶圆 18上的晶片 10， 利用测试探针 13对多个晶片 10同时进行检测， 提 高检测速度。 如图 10所示， 只要测试基板足够大， 我们就可以在其上设置足够多的 测试端微凸起 2， 过基板穿孔 3和探测凸起 4， 使所有的探测触点 7， 比如过 硅穿孔或者待测端微凸起都能被测试探针 13同时探测。 显然， 上述实施例仅仅是为清楚地说明所作的举例， 而并非对实施方式 的限定。 对于所属领域的普通技术人员来说， 在上述说明的基础上还可以做 出其它不同形式的变化或变动。 这里无需也无法对所有的实施方式予以穷举。 而由此所引伸出的显而易见的变化或变动仍处于本发明创造的保护范围之 中。

Claims

权 利 要 求 书
1 . 一种测试基板， 用于对晶片 （10) 进行堆叠前测试， 其特征 在于， 包括： 多个测试端微凸起（2)， 按照与所述晶片（10)底部的待测触点 (7)相同的布局排列于所述测试基板的基座（1 ) 的顶部表面， 且每 一所述测试端微凸起 （2) 与所述待测触点 （7) 的尺寸相匹配； 多个过基板穿孔 （3)， 其顶部通过顶层布线 （8) 与所述测试端 微凸起 （2) —一对应连接并电导通； 多个探测凸起 （4)， 排列于所述测试基板的基座 （1 ) 的底部表 面， 每一所述探测凸起（4)与每一所述过基板穿孔（3) 的底部对应 电连接， 且每一所述探测凸起 （4) 与每一测试探针 （13) 的尺寸相 匹配。
2. 根据权利要求 1所述的测试基板， 其特征在于： 所述测试端微凸起（2)通过刻蚀技术在所述测试基板的基座（1 ) 的顶部表面形成。
3. 根据权利要求 1或 2所述的测试基板， 其特征在于： 所述过基板穿孔（3)按照与所述探测凸起（4)相同的布局进行 排列。
4. 根据权利要求 1或 2所述的测试基板， 其特征在于： 所述测试基板的基座 （1 ) 的底部设置有底层布线 （9)， 所述过 基板穿孔 （3) 通过所述底层布线 （9) 与所述探测凸起 （4) 一一对 应连接并电导通。
5. 根据权利要求 1 -4任一所述的测试基板， 其特征在于： 所述探测凸起 （4) 按照与测试探针 （13) 相同的布局设置于所 述测试基板的基座 （1 ) 的底部表面。
6. 根据权利要求 1 -5任一所述的测试基板， 其特征在于： 所述测试基板的基座 （1 ) 的顶部表面覆盖一层弹性胶层 （6)， 所述弹性胶层 （6) 与所述测试端微凸起 （2) 与所述待测触点 （7) 垂直对应的部分电导通， 其余部分绝缘。
7. 根据权利要求 6所述的测试基板， 其特征在于： 所述弹性胶层 （6) 为异方性导电胶。
8. 根据权利要求 1 -7任一所述的测试基板， 其特征在于： 所述测试基板的基座 （1 ) 由绝缘的硅材料或玻璃材料制成。
9. 根据权利要求 1 -8任一所述的测试基板， 其特征在于： 所述过基板穿孔（3)包括贯穿所述测试基板的基座（1 )的通孔， 镀于所述通孔内表面的绝缘材质及所述通孔内灌注的金属材料。
10. 根据权利要求 1 -9任一所述的测试基板， 其特征在于： 所述待测触点 （7) 为过硅穿孔或待测端微凸起； 所述待测端微凸起是通过刻蚀技术在所述晶片（10 )的底部形成。
1 1 . 一种采用权利要求 1 -10任一所述测试基板制造的探针卡， 其特征在于： 所述探针卡通过去除探测凸起 (4)，并在所述测试基板的基座（1 ) 的底层增加布线，将测试信号通过新增的布线传递到位于所述测试基 板的基座 （1 ) 的顶部表面的每个测试端微凸起 （2)， 并通过所述测 试端微凸起（2)，传递到位于所述晶片（10)底部的每个待测触点（7) 上， 并将测试后的信号输出， 对所述晶片 （10 )进行检测； 所述待测 触点 （7) 为过硅穿孔或待测端微凸起； 所述待测端微凸起是通过刻 蚀技术在所述晶片 （10) 的底部形成。
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