WO2014205695A1 - 发光元件及其制造方法 - Google Patents

发光元件及其制造方法 Download PDF

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Publication number
WO2014205695A1
WO2014205695A1 PCT/CN2013/078051 CN2013078051W WO2014205695A1 WO 2014205695 A1 WO2014205695 A1 WO 2014205695A1 CN 2013078051 W CN2013078051 W CN 2013078051W WO 2014205695 A1 WO2014205695 A1 WO 2014205695A1
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WIPO (PCT)
Prior art keywords
semiconductor
semiconductor stacked
light
substrate
block
Prior art date
Application number
PCT/CN2013/078051
Other languages
English (en)
French (fr)
Inventor
黄建富
吕志强
林俊宇
邱新智
Original Assignee
晶元光电股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR1020187009115A priority Critical patent/KR20180036798A/ko
Priority to DE112013007192.4T priority patent/DE112013007192B4/de
Priority to PCT/CN2013/078051 priority patent/WO2014205695A1/zh
Priority to KR1020177021582A priority patent/KR20170091793A/ko
Priority to CN201380077836.5A priority patent/CN105453276B/zh
Priority to CN201910498576.8A priority patent/CN110277379B/zh
Priority to KR1020167002062A priority patent/KR101766704B1/ko
Priority to US14/901,415 priority patent/US9705029B2/en
Application filed by 晶元光电股份有限公司 filed Critical 晶元光电股份有限公司
Publication of WO2014205695A1 publication Critical patent/WO2014205695A1/zh
Priority to US15/609,795 priority patent/US20170271548A1/en
Priority to US15/944,459 priority patent/US10319877B2/en
Priority to US16/436,544 priority patent/US10680133B2/en
Priority to US16/883,742 priority patent/US11088298B2/en
Priority to US17/397,388 priority patent/US11901480B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H01L33/501—Wavelength conversion elements characterised by the materials, e.g. binder
    • H01L33/502—Wavelength conversion materials
    • H01L33/504—Elements with two or more wavelength conversion materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes

Definitions

  • the present invention relates to a light-emitting element and a method of manufacturing the same; and more particularly to a light-emitting element having a plurality of semiconductor stacked blocks and a method of manufacturing the same.
  • Light-Emitting Diode has good characteristics such as low energy consumption, low heat generation, long operating life, shock resistance, small size, and fast response. It is suitable for various lighting and display applications.
  • components of multi-cell light-emitting diodes that is, components composed of a plurality of light-emitting diodes, such as array type light-emitting diodes, have become increasingly popular in the market.
  • HV LED high voltage LED
  • the existing array type light emitting diode element 1 includes a substrate 10 and a plurality of light emitting diode units 12 arranged on the substrate 10 in two dimensions, as shown in FIG. 7A and FIG. 7B.
  • Each of the light emitting diode units 12 includes a light emitting stack.
  • the layer includes a p-type semiconductor layer 121, a light-emitting layer 122, and an n-type semiconductor layer 123.
  • the light-emitting diode units 12 apply an etching process to the light-emitting stack on the substrate 10 to form the trenches 14 to divide the plurality of light-emitting diode units 12.
  • the trenches 14 formed between the plurality of LED units 12 can insulate the LED units 12 from each other, and further pass through the partially-individed LED unit 12 to the n-type semiconductor layer 123, respectively.
  • a first electrode 18 and a second electrode 16 are formed on the exposed region of the semiconductor layer 123 and the p-type semiconductor layer 121.
  • the first electrode 18 and the second electrode 16 of the plurality of light emitting diode units 12 are selectively connected through the conductive wiring structure 19 such that a series or parallel circuit is formed between the plurality of light emitting diode units 12. For example, if a circuit in series is formed, it is a DC high voltage LED (HV LED).
  • HV LED DC high voltage LED
  • the components formed by such a manufacturing process often cause the overall luminance of the components to decrease due to the light emitted by the respective LED units 12 from each other.
  • the plurality of LED units 12 apply an etching process to the light-emitting layer of a region of the same substrate to form the trench 14 and divide the plurality of LED units.
  • the components and the components are formed from different regions of the substrate, and there is a difference in optical characteristics or electrical uniformity between the components.
  • An object of the present invention is to provide a method for fabricating a light emitting device, comprising: providing a first substrate; providing a semiconductor layer on the first substrate, wherein the semiconductor layer stack comprises a first electrical semiconductor layer, The light emitting layer is located above the first electrical semiconductor layer, and a second electrical semiconductor layer is located above the light emitting layer, and the semiconductor stack is patterned to form a plurality of semiconductor stacked blocks separated from each other, wherein the above The plurality of semiconductor stacked blocks include a first semiconductor stacked block and a second semiconductor stacked block; performing a separating step to separate the first semiconductor stacked block from the first substrate, and the first substrate retains the above a second semiconductor stacked block; providing a permanent substrate having a first surface, a second surface, and a third semiconductor stacked block on the first surface; and bonding the first semiconductor stacked block and the second One of the semiconductor stacked blocks is on the second surface.
  • FIG. 1 is a top plan view showing a substrate used in an embodiment of a method of manufacturing a light-emitting element of the present invention
  • 2A to 2E show an embodiment of a separation method used in the method of manufacturing a light-emitting element of the present invention
  • FIGS. 3A to 3E are diagrams showing a first embodiment of a method of manufacturing a light-emitting element of the present invention.
  • FIG. 3F is a view showing a fourth embodiment of a method of manufacturing a light-emitting element of the present invention.
  • Figure 4 is a view showing a fifth embodiment of the method of manufacturing a light-emitting element of the present invention.
  • Figure 5 is a view showing a sixth embodiment of the method of manufacturing a light-emitting element of the present invention.
  • FIG. 6(a) and 6(b) show the actual measurement and distribution of a substrate used in an embodiment of the method for manufacturing a light-emitting device of the present invention, and the portion of FIG. 6(a) illustrates a luminous intensity. Distinguishing between the first region and the second region, the portion of FIG. 6(b) exemplifies that the first region and the second region are distinguished by the dominant wavelength;
  • Metal wire 301' permanent substrate
  • 501a, 501b, 501c and 501d semiconductor stacked block
  • FIG. 1 is a top view of a substrate used in an embodiment of a method of fabricating a light-emitting device of the present invention, the substrate 101 having a plurality of semiconductor stacked blocks, such as semiconductor stacked blocks 131, 132, 133, 134 and 135, which are fabricated by a semiconductor.
  • the laminate (not shown) is formed by patterning, wherein the patterning generally refers to a fabrication process in which the photoresist is covered and exposed to light after exposure and development.
  • a plurality of partitions 104v, 104h are formed by patterning, and the semiconductor stack is divided into a plurality of the above-described semiconductor stack blocks by the partitions 104v, 104h.
  • the method of patterning is not limited thereto, and other methods such as direct cutting of the semiconductor laminate by laser are also an embodiment.
  • the semiconductor stack may be grown on the substrate 101, that is, the substrate 101 is a growth substrate of the semiconductor laminate; or the semiconductor laminate may be formed on another growth substrate, and the semiconductor laminate is transferred to the substrate by a transfer technique.
  • a semiconductor layer (or a semiconductor stacked block) and a substrate 101 may further include a bonding layer (not shown).
  • the transfer technology is known to those skilled in the art and will not be described here.
  • the plurality of semiconductor stacked blocks are optically or electrically different, so that an optical characteristic value of each semiconductor stacked block can be measured by performing a measuring step.
  • an electrical characteristic value and the semiconductor stacked blocks can be divided into a first region and a second region on the substrate 101 according to a predetermined difference between an optical characteristic value or an electrical characteristic value.
  • the optical characteristic value is, for example, an emission intensity or a wavelength, and the wavelength may be a dominant wave length or a peak wave length, and the electrical characteristic value is, for example, a forward voltage.
  • the semiconductor laminates are laminated according to a predetermined difference in luminous intensity.
  • the block is divided into a first area and a second area on the substrate 101.
  • the predetermined difference in luminous intensity difference is greater than or equal to 3%, thereby distinguishing a first region from a substantially circular shape, as shown by a circular region covered by a circular boundary line 103 in the figure, and The two regions are substantially a ring shape surrounding the first region, as shown by the ring shape around the circular boundary line 103 in the figure.
  • the light-emission intensity distributions of the semiconductor stacked blocks located in the first region are similar to each other, and the light-emission intensity distributions of the semiconductor stacked blocks located in the second region are close to each other.
  • the average light-emitting intensity of the semiconductor stacked blocks (for example, the semiconductor stacked blocks 131, 132, and 133) located in the first region is 4400 mcd
  • the standard deviation of the luminous intensity of the semiconductor stacked block in this region is The value is about 0.5 to 1.5 mcd
  • the average luminous intensity of the semiconductor stacked blocks (for example, the semiconductor stacked blocks 134 and 135) in the second region is 4000 mcd
  • the standard deviation of the luminous intensity of the semiconductor stacked block in this region is The value is about 0.5 to 1.5 mcd
  • the difference in optical characteristics between the first region and the second region may be that the difference between the peak light wavelength or the main light wavelength is greater than or equal to 1 nm, and the electrical differences may include The difference in forward voltage is greater than or equal to 2%.
  • Fig. 6(a) and Fig. 6(b) are distribution diagrams of actual measurement results, and part of Fig. 6(a) illustrates a measurement result of luminous intensity (Iv), and according to a luminous intensity The difference predetermined value distinguishes the first region from the second region, and the difference in the difference in luminous intensity in this embodiment is greater than or equal to 3%. As shown in the section of (Fig.
  • the illuminance intensity measured by each semiconductor stacked block is indicated by a color (gray scale in the figure), and the illuminance intensity value represented by each color (gray scale in the figure) can be referred to
  • the indication of the relationship between the lower luminous intensity value and the color (the gray scale in the figure), as shown by the dotted line in the figure, can be seen that the first region distinguished is mainly composed of red light with a light intensity of 130mcd ( In the figure, the gray scale) is composed of orange (the gray scale in the figure) indicating the luminous intensity of 129mcd, and only a few semiconductor laminated blocks (the gray scale in the figure) representing the luminous intensity of 124mcd.
  • a region is substantially circular, having an average luminous intensity of about 129 mcd, and the second region is substantially an annular shape surrounding the first region, mainly by a green (grey gray) semiconductor laminate representing a luminous intensity of 124 mcd.
  • the block is composed of only a few red (in the figure) gray with a light intensity of 130mcd and an orange color (a gray scale in the figure) with a substitute intensity of 129mcd.
  • the average luminous intensity of the second region is about 124mcd, which is the first
  • the part of (b) is exemplified by a measurement result of a dominant wavelength (WLD), and a predetermined value according to a difference of a dominant wavelength (WLD).
  • the predetermined value of the main wavelength difference is greater than or equal to 1 nm, and the distinction is made.
  • the first region and the second region are distinguished, the first region (shown by a broken line in the figure) is substantially circular, the average dominant wavelength is about 685 nm, and the second region is substantially surrounding the first region. a ring shape having an average dominant wavelength of about 683 nm, wherein the average wavelength of the main wavelength of the semiconductor stacked block of the first region is larger than the average value of the dominant wavelength of the semiconductor stacked block of the second region, and the difference is 2 nm, which is greater than the difference of the dominant wavelength.
  • the predetermined value is 1 nm.
  • a substrate 201 includes a semiconductor laminate 202 thereon, the semiconductor laminate 202 includes a first electrical semiconductor layer 202a; and the light emitting layer 202b is located at the first electrical property. Above the semiconductor layer 202a; and a second electrically conductive semiconductor layer 202c is located over the luminescent layer 202b.
  • the first electrical semiconductor layer 202a and the second electrical semiconductor layer 202c are electrically different, for example, the first electrical semiconductor layer 202a is an n-type semiconductor layer, and the second electrical semiconductor layer 202c is a p-type semiconductor layer.
  • the first electrical semiconductor layer 202a, the light emitting layer 202b, and the second electrical semiconductor layer 202c are formed of a ⁇ -V material, such as an aluminum gallium indium phosphide (AlGalnP) series material or aluminum gallium indium nitride (AlGalnN). Series of materials.
  • AlGalnP aluminum gallium indium phosphide
  • AlGalnN aluminum gallium indium nitride
  • FIG. 2B after performing the foregoing patterning step, a spacer 212 having a width d is formed to divide the semiconductor laminate 202 into a plurality of semiconductor stacked blocks 231, 232, 233, 234 and 235, respectively corresponding to FIG.
  • the semiconductor stacked blocks 131, 132, 133, 134 and 135 respectively have light-emitting intensities as described in FIG.
  • a first sacrificial layer 211 is formed on the semiconductor stacked block to be removed to facilitate the separation step.
  • the semiconductor stacked blocks to be removed are the semiconductor stacked blocks 232 and 234.
  • the first sacrificial layer 211 may be formed by first forming a layer of the first sacrificial layer 211 on the entire substrate 201, and then selectively removing the semiconductor stacked block 232 by a yellow light and etching process.
  • the first sacrificial layer 211 is formed on the 234. It should be noted that those skilled in the art also understand that, in the manufacturing process sequence, the first sacrificial layer 211 may be formed at the position of the semiconductor stacked blocks 232 and 234 to be removed. Another yellow light and etching process is performed to complete the steps of patterning the semiconductor stack 202 into a plurality of semiconductor stacked blocks 231, 232, 233, 234, and 235. In FIG.
  • the separating step is performed, including: providing a first temporary substrate 221 to bond the first sacrificial layer 211 with the first temporary substrate 221; and then, as shown in FIG. 2D, the semiconductor stacked block to be removed 232 and 234 are separated from the substrate 201.
  • a laser 241 photo may be applied to the interface between the semiconductor stacked blocks 232 and 234 to be removed and the substrate 201.
  • the shots are used to assist in the separation of the semiconductor stacked blocks 232 and 234 from the substrate 201.
  • the semiconductor stack 202 may also be transferred to the substrate 201 by a transfer technique after another growth substrate is formed. In this case, the semiconductor stack 202 may also be selectively transferred to the substrate 201.
  • a sacrificial layer (not shown) is formed between the substrate 201 and the substrate 201.
  • the sacrificial layer itself is weak in material or weakly bonded to the substrate 201.
  • FIG. 3E shows that after the separation step is performed, the semiconductor stacked blocks 232 and 234 are separated from the substrate 201, and the substrate 201 retains the semiconductor stacked blocks 231, 233 and 235.
  • the first temporary substrate 221 and the semiconductor stacked blocks 232 and 234 thereon, or the substrate 201 and the semiconductor stacked blocks 231, 233 thereon are shown in FIGS. 3A to 3E for the manufacture of the light-emitting element of the present invention.
  • a permanent substrate 301 is provided.
  • the permanent substrate 301 has at least a first surface 301P1 and a second surface 301P2.
  • the permanent substrate 301 further has a third surface 301P3.
  • the first surface 301P1 and the second surface 301P2 are not coplanar.
  • the non-coplanar surface forms the non-coplanar first surface 301P1 and the second surface 301P2 by applying a yellow light and an etching process to a permanent substrate having a planar surface.
  • the material of the permanent substrate 301 is, for example, glass, sapphire (A1 2 0 3 ), or a silicon (Si) substrate.
  • the semiconductor stacked block 234 of FIG. 2E is bonded to the first surface 301P1 of the permanent substrate 301.
  • the semiconductor laminate block 234 can be directly bonded to the permanent by appropriate warming and pressing, for example, a temperature of about 300 ° C to 420 ° C and a pressure of about 11,000 Kgf to 14000 Kgf.
  • Substrate 301; this bonding may also be selectively performed by a bonding layer 312B1.
  • silicon dioxide may be selected as the bonding layer 312B1.
  • the semiconductor stacked block 234 is separated from the first temporary substrate 221; and when this step is performed, a laser irradiation (not shown) is applied to the interface between the semiconductor stacked block 234 and the first sacrificial layer 211 to assist the semiconductor.
  • a laser irradiation (not shown) is applied to the interface between the semiconductor stacked block 234 and the first sacrificial layer 211 to assist the semiconductor. The separation of the stacked block 234 from the first sacrificial layer 211.
  • the semiconductor stacked block 232 is bonded to the second surface 301P2 of the permanent substrate 301.
  • This bonding is substantially similar to the bonding of the above-described semiconductor stacked block 234, and therefore will not be described again.
  • the semiconductor stacked blocks 231, 232, 233, 234, and 235 correspond to the semiconductor stacked blocks 131, 132, 133, 134, and 135 of FIG.
  • the average luminous intensity is 4400 mcd
  • the semiconductor stacked blocks 234 and 235 are located in the second region of FIG. 1 above and the average luminous intensity is 4000 mcd
  • the semiconductor stacked blocks 231, 232 and 233 and the semiconductor stacked blocks 234 and 235 The difference is greater than 3% in terms of luminous intensity.
  • a plurality of semiconductor stacked blocks which are originally located in two regions which are optically or electrically differently are reassigned and combined.
  • the semiconductor stacked blocks 132 and 133 may be combined into one element in a subsequent fabrication process due to their close proximity and substantially in the same area (see FIGS. 1 and 2B).
  • the semiconductor stacked blocks 134 and 135 are combined into another element B in a subsequent fabrication process because they are located close to each other and are substantially in the same area (see FIGS. 1 and 2B).
  • component A will comprise two semiconductor stacked blocks having an average luminous intensity of 4400 mcd
  • component B will comprise two semiconductor stacked blocks having an average luminous intensity of 4000 mcd
  • the two elements have poor uniformity of luminous intensity.
  • the first surface 301P1 has a semiconductor stacked block 234 which is originally located in the second region having an average luminous intensity of 4000 mcd in FIG. 1
  • the second surface 301P2 has a semiconductor stacked block 232 which is originally in the first region of the average luminous intensity of 4400 mcd in Fig. 1.
  • a plurality of semiconductor stacked blocks which are originally located in optical characteristics (e.g., luminous intensity of the present embodiment) or two regions having large differences in electrical properties have been redistributed and combined.
  • optical characteristics e.g., luminous intensity of the present embodiment
  • two regions having large differences in electrical properties have been redistributed and combined.
  • a semiconductor stacked block 233 of a first region having an intensity of 4400 mcd Therefore, the above two elements have a better performance in terms of uniformity of luminous intensity between elements.
  • the semiconductor stacked blocks 234 and 232 are respectively bonded to the permanent substrate 301 and are respectively located on the non-coplanar first surface 301P1 and the second surface 301P2, thereby reducing the mutual absorption of light between the respective semiconductor stacked blocks. In this case, the overall brightness of the component is better.
  • Another semiconductor stacked block 23X may be bonded on the third surface 301P3 of the permanent substrate 301 via the bonding method as described above, as shown in FIG. 3D.
  • the semiconductor laminate block 23X herein is not particularly limited, and those skilled in the art will understand how the optical characteristics between the elements of the components which are produced by reallocating and combining the semiconductor laminate blocks as disclosed above. Upper or electrical uniformity has a better performance.
  • each semiconductor stacked block is partially etched by a yellow light and etching process to expose the respective semiconductor stacked blocks to the first electrical semiconductor layer 202a, and a dielectric layer 320 is formed on each of the semiconductor stacks.
  • a metal wire forming step is performed to form a metal line 330 between the semiconductor stacked blocks to electrically connect the semiconductor stacked blocks, and the electrical connection relationship thereof is In series or in parallel.
  • the metal lines 330 as shown in FIG. 3E electrically connect the respective semiconductor stacked blocks to form a series relationship.
  • the present embodiment exemplifies that the two semiconductor stacked blocks bonded to the permanent substrate 301 are the semiconductor stacked blocks separated from the substrate 201 in FIG. 2E, those skilled in the art are not limited thereto, for example, in FIG. 2E.
  • the semiconductor stacked blocks 231, 233, and 235 are left on the substrate 201.
  • the semiconductor stacked blocks remaining on the substrate 201 may be bonded to the permanent substrate 301.
  • the situation is substantially as shown in FIGS. 3B to 3E, and only the first temporary substrate 221 and the semiconductor stacked block thereon are correspondingly changed to the substrate 201 and the semiconductor stacked blocks 231, 233, and 235 thereon, so The illustration is repeated.
  • the bonding step is to align the substrate 201 with the permanent substrate 301 to bond the semiconductor stacked blocks 231, 233, or 235 to the surface to be bonded; and the board 201 is away from the permanent substrate 301, The bonded semiconductor stacked blocks are separated from the substrate 201.
  • the semiconductor stacked blocks 231, 233, and 235 remaining on the substrate 201 may be separated from the substrate 201 and then bonded to the permanent substrate 301 as in the first embodiment, in which case
  • the bonding step is bonded to bond the semiconductor stacked blocks 231, 233, or 235 to a second temporary substrate and separate the semiconductor stacked blocks 231, 233, or 235 from the substrate 201; and then the second temporary substrate and the permanent substrate Bonding 301 to bond the semiconductor stacked blocks 231, 233, or 235 to the surface to be bonded; and moving the second temporary substrate away from the permanent substrate 301, and bonding the bonded semiconductor stacked block to the second temporary substrate Separation.
  • the first embodiment illustrates the semiconductor stacked block (ie, the semiconductor stacked block 234) on the first surface 301P1 of the permanent substrate 301 and the semiconductor stacked block on the second surface 301P2 (ie, the semiconductor stacked block) 232) from the same semiconductor stack 202, but is not limited thereto, that is, in other embodiments, the semiconductor stacked block on the first surface 301P1 and the semiconductor stacked block on the second surface 301P2 may be derived from different The semiconductor stack, for example, the semiconductor stacked block on the first surface 301P1 is the semiconductor stacked block 234, and the semiconductor stacked block on the second surface 301P2 can be derived from the semiconductor stack of another different substrate.
  • the semiconductor laminate may be bonded to the permanent substrate 301 via the first temporary substrate 221 or the substrate 201 or the second temporary substrate as described above.
  • Fig. 3F shows a fourth embodiment of the present invention, which is substantially the same as the first embodiment, but the permanent substrate 301 in the first embodiment is changed to the permanent substrate 301 in this embodiment.
  • the first surface 301P1, the second surface 301P2, and the third surface 301P3 having a non-coplanar surface with respect to the permanent substrate 301, the first surface 301, the P1, the second surface 301, P2 of the permanent substrate 301 of the present embodiment, and
  • the third surface 301, P3 is coplanar, but when each semiconductor laminate is bonded to the permanent substrate 301, it is passed through a bonding layer of different thickness. The effect of making each semiconductor stacked block not coplanar.
  • the semiconductor stacked block 234 is bonded to the first surface 301, P1 via a first bonding layer 312'B1
  • the semiconductor stacked block 232 is bonded to the second surface 301, P2 via a second bonding layer 312?
  • the first bonding layer 312'B1 and the second bonding layer 312, B2 are different in thickness, so that the semiconductor stacked block 234 and the semiconductor stacked block 232 are not coplanar.
  • FIG. 4 shows a fifth embodiment of the present invention.
  • This embodiment shows that the semiconductor stacked blocks are not optically or electrically different from each other as shown in FIG. 1 on the substrate, but for a plurality of regions on the same substrate.
  • the semiconductor stacked block can still be classified into a general specification area, a low specification area, and a plurality of semiconductor stacked blocks according to the measurement results of an optical characteristic value or an electrical characteristic value.
  • the optical characteristic value or the electrical characteristic value is higher than the general specification area, and the general specification area is larger than the low specification area.
  • FIG. 4 as a result of measuring the luminous intensity of a plurality of semiconductor stacked blocks on a substrate, the position and luminous intensity of each of the semiconductor stacked blocks on the substrate can be stored in the machine after measurement.
  • the horizontal axis is the luminous intensity
  • the vertical axis is the number of semiconductor laminated blocks corresponding to the respective luminous intensities.
  • the a result area is a low specification area, and the average luminous intensity is approximately 700mcd; b the result area is a general specification area, and the average luminous intensity is approximately 900mcd; and the c result area is a high specification area, which emits light.
  • the average intensity is approximately 1200 mcd.
  • the result of the redistribution can select five semiconductor stacked block joints belonging to the general specification area (the average luminous intensity is approximately 900mcd).
  • the element C is formed; and the other element D can select three semiconductor laminated blocks belonging to the low-standard area (the average luminous intensity is approximately 700 mcd) to be bonded to the permanent substrate as shown in FIG. 3A.
  • two semiconductor stacked blocks belonging to a high-standard area are bonded to the same permanent substrate 301 to form an element D.
  • the semiconductor stacked blocks in the regions at different positions of the production substrate may have large differences in optical characteristics or electrical properties, for example, in the embodiment, the light-emitting intensity is high, and the value may be as high as 1200 mcd in the high-standard area. The lower the luminous intensity, the value can be as low as 700mcd in the low specification area.
  • the redistribution of the semiconductor laminated block in this embodiment the uniformity of the components produced will be improved and controlled, and the component C and The luminous intensity of the element D was approximately 4500 mcd.
  • the semiconductor stacked blocks are bonded to the permanent substrate 301 by respective positions On different surfaces of the non-coplanar plane, the light emitted from each other by the respective semiconductor stacked blocks can be reduced, and the overall brightness of the elements can be better.
  • the optical characteristic value or the electrical characteristic value may be obtained by performing measurement on the semiconductor stacked block of each substrate in whole or in a sampling manner before the separating step;
  • these optical characteristic values or electrical characteristic values can also be obtained through a certain number of statistics to obtain a predetermined statistical value.
  • a certain number of statistics can determine the boundary position of the first region and the second region, that is, obtain a predetermined value of the radius of the first region, and corresponding two
  • the optical characteristic value or the electrical characteristic value of the region is not necessarily measured in the manufacturing process for each of the produced substrates.
  • the semiconductor stacked blocks bonded on the permanent substrate 301 may be derived from different semiconductor laminates, such as the semiconductor stacked blocks on the first surface 301P1 and the second surface 301P2.
  • the semiconductor stacked blocks can be derived from semiconductor stacks of different substrates.
  • Such an application can be further applied to enhance the color rendering of the light-emitting element, i.e., to increase the CRI value of the light-emitting element, which is applied to the sixth embodiment of the present invention as shown in FIG.
  • FIG. 5A two semiconductor stacked blocks 501a and 501b are respectively bonded to the permanent substrate 501, and the bonding method is substantially the same as that of the first embodiment of FIG.
  • the two semiconductor stacked blocks 501a and 501b are separated from each other.
  • the semiconductor stack of the substrate for example, the semiconductor stacked block 501a is separated from a semiconductor stack having an emission dominant wavelength of about 620 nm to 645 nm, and the semiconductor stacked block 501b is separated from a semiconductor stack having an emission dominant wavelength of about 595 nm to 620 nm. That is, the two semiconductor stacked blocks 501a and 501b are separated from different substrates, and the semiconductor stacked block 501a can emit light of a dominant red wavelength, and the semiconductor stacked block 501b can emit light of an orange dominant wavelength.
  • the two semiconductor stacked blocks when they are bonded to the permanent substrate 501, they can be a light-emitting element 500a, which is used to replace the red or orange color of the general warm white light source with only a single semiconductor stack;
  • the light-emitting element 500a can be used in combination with blue and YAG phosphors.
  • the warm white light source is formed by having different main wavelengths of light of the two semiconductor stacked blocks 501a and 501b, and more than a single semiconductor stacked chip.
  • the formed warm white light source has better color rendering properties.
  • the semiconductor stacked block 502c for providing the blue light source is also directly bonded to the permanent substrate 501.
  • the light-emitting element 500b thus directly forms a warm white light source, wherein the three semiconductor stacked blocks 501a, 501b and 501c are separated from the semiconductor stack of different substrates, for example, the semiconductor stacked block 501a is separated from a main wavelength of about 620 nm.
  • semiconductor stacked block 501b is separated from a semiconductor stack having an illuminating dominant wavelength of about 595 nm to 620 nm
  • the semiconductor stacked block 501c is separated from a semiconductor stack having an illuminating dominant wavelength of about 440 nm to 460 nm; that is, three semiconductor stacked blocks 501a, 501b And 501c are separated from different substrates, and the semiconductor stacked block 501a can emit light of a dominant red wavelength, the semiconductor stacked block 501b can emit light of an orange dominant wavelength, and the semiconductor stacked block 501c can emit light of a dominant wavelength of blue. .
  • a fourth semiconductor stacked block 503d is bonded on the permanent substrate 501.
  • the four semiconductor stacked blocks 501a, 501b, 501c and 501d are separated from the semiconductor stack of different substrates, and the colors and wavelengths of the semiconductor stacked blocks 501a, 501b and 501c are as described in FIG. 5B, and the semiconductor stacked block 503d It has a dominant wavelength of light of about 510 nm to 530 nm and emits light of a green dominant wavelength.
  • the warm white light source formed by the light-emitting element 500c has a higher CRI value than the light-emitting element 500b shown in Fig. 5B, and the color rendering property is better.

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Abstract

一种发光元件的制造方法，包括：提供第一基板（201）；提供一半导体叠层（202）在第一基板上，其中半导体叠层包括从下至上依次层叠的第一电性半导体层（202a）、发光层（202b）和第二电性半导体层（202c），将半导体叠层经图形化形成彼此分割的多个半导体叠层块（231，232，233，234，235），多个半导体叠层块包括第一半导体叠层块和第二半导体叠层块；实施一分离步骤，将第一半导体叠层块和第二半导体叠层块分离，使第一基板上保留有第二半导体叠层块；提供一永久基板（301）具有第一表面（301P1）、和第二表面（301P2），且第三半导体叠层块位于第一表面上；以及结合第一半导体叠层块和第二半导体叠层块中的一个到第二表面。

Description

发光元件及其制造方法 技术领域
本发明涉及一种发光元件及其制造方法； 特别是涉及一种具多个半导体叠层 块的发光元件及其制造方法。 背景技术
发光二极管 (Light-Emitting Diode, LED)具有耗能低、 低发热、 操作寿命长、 防震、 体积小、 以及反应速度快等良好特性， 因此适用于各种照明及显示用途。 随着其应用技术的发展， 多元 (multi-cell)发光二极管的元件， 即由多个发光二极 管组成的元件， 例如阵列式发光二极管的元件， 在市场上的应用渐为广泛。 例如， 光学显示装置、 交通号志、 以及照明装置等， 其中高压发光二极管 (High Voltage LED , HV LED)的照明元件即为一例。
现有的阵列式发光二极管元件 1 , 如图 7A与图 7B所示， 包含一基板 10、 多 个发光二极管单元 12以二维方式排列于基板 10上， 每一个发光二极管单元 12 包含一发光叠层， 包含一 p型半导体层 121、一发光层 122、 以及一 n型半导体层 123。这些发光二极管单元 12对基板 10上的发光叠层施以蚀刻制作工艺，形成沟 槽 14而分割出此多个发光二极管单元 12。 由于基板 10不导电， 因此于多个发光 二极管单元 12间形成的沟槽 14可使各发光二极管单元 12彼此绝缘，另外再通过 部分独刻发光二极管单元 12至 n型半导体层 123,分别于 n型半导体层 123的暴 露区域以及 p型半导体层 121上形成一第一电极 18以及一第二电极 16。 再通过 导电配线结构 19选择性连接多个发光二极管单元 12的第一电极 18及第二电极 16,使得多个发光二极管单元 12之间形成串联或并联的电路。 例如， 若形成串联 的电路， 即为直流的高压发光二极管 (High Voltage LED, HV LED)。
然而， 此种制作工艺所形成的元件， 常常会因各个发光二极管单元 12 间彼此互相吸收所发出的光， 而造成元件整体亮度降低。 此外， 此种制 作工艺所形成的元件， 其多个发光二极管单元 12对同一基板的一区域的 发光叠层施以蚀刻制作工艺，以形成上述沟槽 14而分割出多个发光二 极管单元， 故元件与元件间可能因形成自基板不同区域， 而有元件间在光学特 性上或电性上均匀性不佳的问题。 发明内容
本发明公开的目的在于提供一种发光元件的制造方法， 包括： 提供一第一基 板； 提供一半导体叠层于上述第一基板上， 其中上述半导体叠层包括一第一电性 半导体层、 一发光层位于上述第一电性半导体层之上、 以及一第二电性半导体层 位于上述发光层之上， 且上述半导体叠层经图形化而形成彼此分隔的多个半导体 叠层块， 其中上述多个半导体叠层块包括一第一半导体叠层块及一第二半导体叠 层块； 实行一分离步骤将上述第一半导体叠层块与上述第一基板分离， 且上述第 一基板保留有上述第二半导体叠层块； 提供一永久基板具有一第一表面、 一第二 表面、 以及一第三半导体叠层块于上述第一表面上； 以及接合上述第一半导体叠 层块及上述第二半导体叠层块的其中之一于上述第二表面上。 附图说明
图 1 所示为本发明发光元件的制造方法的一实施例所使用的一基板的上视 图；
图 2A至图 2E所示为本发明的发光元件的制造方法所使用的分离方法的实施 例；
图 3A至图 3E所示为本发明的发光元件的制造方法的第一实施例； 图 3F所示为本发明的发光元件的制造方法的第四实施例；
图 4所示为本发明的发光元件的制造方法的第五实施例；
图 5所示为本发明的发光元件的制造方法的第六实施例；
图 6(a)、 图 6(b)所示为本发明发光元件的制造方法的一实施例所使用的一基 板的实际量测及分布情形， 图 6(a)的部分例示一以发光强度区分出第一区域及第 二区域， 图 6(b)的部分则例示一以主波长区分出第一区域及第二区域；
图 7A及图 7B所示为现有的阵列式发光二极管元件。 主要元件符号说明
1: 现有的阵列式发光二极管元件
10: 基板
101:基板 103: 区分界线
104v， 104h: 分隔道
12: 发光二极管单元
121: p型半导体层
122: 发光层
123: n型半导体层
131, 132, 133, 134及 135: 半导体叠层块
14: 沟槽
16: 第二电极
18: 第一电极
19: 导电配线结构
201 :基板
202: 半导体叠层
202a: 第一电性半导体层
202b: 发光层
202c: 第二电性半导体层
d: 分隔道宽度
211 : 第一牺牲层
212: 分隔道
221: 第一暂时基板
231, 232, 233, 234及 235: 半导体叠层块
23X: 半导体叠层块
241: 激光
301 : 永久基板
301P1: 第一表面
301P2: 第二表面
301P3: 第三表面
312B1，312B2及 312B3:接合层
320: 介电层
330: 金属线 301': 永久基板
301 1: 第一表面
301 2: 第二表面
301 3: 第三表面
312'Bl: 第一接合层
312Έ2Ρ2: 第二接合层
312Έ3: 第三接合层
500a, 500b及 500c: 发光元件
501: 永久基板
501a,501b, 501c及 501d: 半导体叠层块 具体实施方式
图 1为本发明发光元件的制造方法的一实施例所使用的基板的上视图， 基板 101上具有多个半导体叠层块， 例如半导体叠层块 131,132,133,134及 135 , 这些 半导体叠层块由一半导体叠层 (图未示)经图形化所形成， 其中图形化一般是指经 覆盖光致抗蚀剂并曝光显影后加以蚀刻的制作工艺。 经图形化后形成多个的分隔 道 104v, 104h, 而半导体叠层被分隔道 104v, 104h分隔成上述的多个的半导体叠 层块。 但图形化的方法并不限于此， 其他方法， 例如以激光直接切割半导体叠层 也为一实施例。 此外， 上述半导体叠层可能在基板 101上成长， 即基板 101是半 导体叠层的成长基板； 也可能是半导体叠层形成在另一成长基板后， 经移转技术 将半导体叠层移转至此基板 101上， 于此情形时， 半导体叠层 (或半导体叠层块) 与基板 101 间可能还包括一粘结层 (图未示)。 移转技术为熟悉此技术领域的人士 所现有， 在此不予赘述。
值得注意的是， 在本实施例中， 上述的多个的半导体叠层块在光学特性上或 电性上不同， 故可经由实行一量测步骤测得各半导体叠层块的一光学特征值或一 电性特征值， 并且可依一光学特征值或电性特征值的差异预定值将这些半导体叠 层块在基板 101上分成一第一区域及一第二区域。 其中光学特征值例如为发光强 度或波长， 且波长可以是主波长 (dominant wave length)或峰波长 (peak wave length), 而电性特征值例如为正向电压 (forward voltage)。 在本实施例中， 于量测 各半导体叠层块的发光强度后， 依一发光强度的差异预定值， 将这些半导体叠层 块在基板 101上分成一第一区域及一第二区域。 在此实施例中发光强度差异预定 值为差异大于或等于 3%, 依此区分出一第一区域大致为圓形， 如图中圓形的区 分界线 103内所涵盖的圓形区域， 而第二区域则大致为环绕上述第一区域的一环 状， 如图中圓形的区分界线 103外围的环状所涵盖的区域。 其中位于第一区域的 半导体叠层块的发光强度分布彼此相近， 而位于第二区域的半导体叠层块的发光 强度分布彼此相近。 于本实施例中，位于第一区域的半导体叠层块 (例如半导体叠 层块 131, 132,及 133)的平均发光强度为 4400 mcd, 此区域内的半导体叠层块的 发光强度的标准差值约在 0.5~1.5mcd,而位于第二区域的半导体叠层块 (例如半导 体叠层块 134及 135)的平均发光强度为 4000 mcd,此区域内的半导体叠层块的发 光强度的标准差值约在 0.5~1.5mcd; 第一区域与第二区域内的半导体叠层块的发 光强度差异约为 10%((4400-4000)/4000=10%), 亦即大于或等于 3%。
除了发光强度外， 在其他实施例中， 用以区分出第一区域及第二区域的光学 特性不同则可能为峰光波长或主光波长的差异大于或等于 lnm, 而电性不同则可 能包括正向电压 (forward voltage)的差异大于或等于 2%。 图 6(a)、 图 6(b)所示为一 实际量测结果的分布图， 图 6 (a)的部分例示一以发光强度 (Iv)的量测结果区分， 且依一发光强度的差异预定值区分出第一区域及第二区域， 在此实施例发光强度 差异的差异预定值为大于或等于 3%。如 (图 6a)的部分所示，各半导体叠层块所测 得的发光强度以颜色 (图中为灰阶)标示，各颜色 (图中为灰阶)所代表的发光强度值 可参照其下方的发光强度值与颜色 (图中为灰阶)对照关系的标示， 如图中虚线所 圏示的区域， 可看出所区分出的第一区域主要是由代^ ^光强度 130mcd的红色 (图中为灰阶)与代表示发光强度 129mcd的橘色（图中为灰阶)所构成， 而仅包含少 数代表发光强度 124mcd的绿色 (图中为灰阶)的半导体叠层块，此第一区域大致为 圓形，平均发光强度约 129mcd,而第二区域则大致为环绕上述第一区域的一环状， 主要系由代表发光强度 124mcd的绿色 (图中为灰阶)的半导体叠层块所构成，仅包 含少数代 光强度 130mcd的红色（图中为灰阶)与代 光强度 129mcd的橘色 (图中为灰阶)， 此第二区域的平均发光强度约 124mcd, 亦即第一区域的半导体叠 层块的发光强度平均值较位于第二区域的半导体叠层块的发光强度平均值大， 其 差异约为 4%((129-124)/124=4%), 大于或等于 3%。 （b)的部分则例示一以主波长 (WLD)的量测结果区分， 且依一主波长 (WLD)的差异预定值， 在此实施例为主波 长差异预定值大于或等于 lnm, 而区分出第一区域及第二区域， 如图 6 (b)的部分 所示， 所区分出第一区域及第二区域， 第一区域 (如图中虚线所圏示)大致为圓形， 平均主波长约 685nm, 而第二区域则大致为环绕上述第一区域的一环状， 平均主 波长约 683nm, 其中第一区域的半导体叠层块的主波长平均值较位于第二区域的 半导体叠层块的主波长平均值大， 其差异为 2nm, 大于主波长差异预定值 lnm。
图 2A至图 2E显示为本发明的发光元件的制造方法所使用的分离方法的实施 例。 如上述图 1中所述， 在图 2A中， 一基板 201包含一半导体叠层 202于其上， 此半导体叠层 202包括一第一电性半导体层 202a; —发光层 202b位于第一电性 半导体层 202a之上； 以及一第二电性半导体层 202c位于发光层 202b之上。第一 电性半导体层 202a和第二电性半导体层 202c电性相异， 例如第一电性半导体层 202a是 n型半导体层， 而第二电性半导体层 202c是 p型半导体层。 第一电性半 导体层 202a、发光层 202b、及第二电性半导体层 202c为 ΙΠ-V族材料所形成， 例 如为磷化铝镓铟（ AlGalnP)系列材料或氮化铝镓铟（ AlGalnN)系列材料。 在图 2B中， 实施前述的图形化步骤后， 形成宽度为 d的分隔道 212将半导体叠 层 202分隔为多个的半导体叠层块 231, 232, 233, 234及 235 , 分别对应于图 1中 的半导体叠层块 131, 132, 133, 134及 135 , 而且分别具有如图 1中所述的发光强 度及分别位于上述的第一区域及第二区域； 亦即半导体叠层块 231, 232, 及 233 位于上述图 1中的第一区域且发光强度为 4400 mcd, 而半导体叠层块 234及 235 位于上述图 1中的第二区域且的发光强度为 4000 mcd,半导体叠层块 231, 232, 及 233与半导体叠层块 234及 235就发光强度而言差异大于 3%。 接着， 在欲移离 的半导体叠层块上形成一第一牺牲层 211以利实行分离步骤， 在本实施例中， 欲 移离的半导体叠层块为半导体叠层块 232及 234。 此第一牺牲层 211的形成可以 是先在整个基板 201上形成一整层第一牺牲层 211的材料后， 再以黄光及蚀刻制 作工艺选择性地在欲移离的半导体叠层块 232及 234上形成此第一牺牲层 211。 值得注意的是， 熟悉此技术领域的人士也了解， 在制作工艺顺序上， 也可以是先 在欲移离的半导体叠层块 232及 234的位置上形成此第一牺牲层 211后， 再以另 一黄光及蚀刻制作工艺以完成前述的半导体叠层 202的图形化成多个的半导体叠 层块 231, 232, 233, 234, 及 235的步骤。 在图 2C中， 实行分离步骤， 包括： 提供 一第一暂时基板 221 , 使第一牺牲层 211与第一暂时基板 221接合； 之后， 如图 2D所示，将欲移离的半导体叠层块 232及 234与基板 201分离。在实施上述步骤 时， 可在欲移离的半导体叠层块 232及 234与基板 201的界面施以一激光 241照 射， 以辅助半导体叠层块 232及 234与基板 201的分离。 再者， 半导体叠层 202 也可能在另一成长基板形成后， 再经移转技术移转至基板 201上， 于此情形时， 也可在半导体叠层 202移转至基板 201时，选择性地在欲移离的半导体叠层块 232 及 234的位置上， 先形成与基板 201间的一牺牲层 (图未示)， 此牺牲层本身材料 较脆弱或与基板 201的接合较弱， 如此可在欲移离的半导体叠层块 232及 234与 基板 201分离时， 使欲移离的半导体叠层块 232及 234与基板 201较易分离。
图 2E显示实行分离步骤后， 半导体叠层块 232及 234与基板 201分离， 而 基板 201保留有半导体叠层块 231 , 233及 235。值得注意的是，第一暂时基板 221 及其上的半导体叠层块 232及 234, 或基板 201及其上的半导体叠层块 231 , 233 图 3A至图 3E显示为本发明的发光元件的制造方法的第一实施例。 首先， 如 图 3A所示， 提供一永久基板 301 , 此永久基板 301至少具有一第一表面 301P1、 一第二表面 301P2, 在本实施例中， 永久基板 301还具有一第三表面 301P3。 其 中， 如图所绘示， 第一表面 301P1与第二表面 301P2非共平面。 在一实施例中， 此非共平面经由对一原本具有一平面表面的永久基板施以黄光及蚀刻制作工艺而 形成此非共平面的第一表面 301P1及第二表面 301P2。 永久基板 301的材料例如 为玻璃， 蓝宝石（A1203), 或硅 (Si)基板。
接着， 如图 3B所示， 接合图 2E中的半导体叠层块 234于永久基板 301的第 一表面 301P1上。 例如当永久基板 301的材料为蓝宝石基板时， 经过适当的加温 加压， 例如温度约为 300°C~420°C , 压力约为 11000Kgf~14000Kgf , 可使半导体 叠层块 234直接接合于永久基板 301 ;此接合也可为选择性地通过一接合层 312B1 进行接合， 例如当永久基板 301的材料为蓝宝石基板时， 可选择二氧化硅为接合 层 312B1。 然后将半导体叠层块 234与第一暂时基板 221分离； 而在实施此步骤 时， 在半导体叠层块 234与第一牺牲层 211的界面施以一激光照射 (图未示)， 以 辅助半导体叠层块 234与第一牺牲层 211的分离。
接着，如图 3C所示，接合半导体叠层块 232于永久基板 301的第二表面 301P2 上。 此接合大致与上述半导体叠层块 234的接合类似， 故不再赘述。
如同在前面图 2A中所述，在一实施例中，半导体叠层块 231, 232, 233, 234,及 235对应于图 1中的半导体叠层块 131, 132, 133, 134, 及 135而分别具有如图 1中 所述的发光强度，亦即半导体叠层块 231, 232, 及 233位于上述图 1中的第一区域 且平均发光强度为 4400 mcd,而半导体叠层块 234及 235位于上述图 1中的第二 区域且平均发光强度为 4000 mcd,半导体叠层块 231, 232及 233与半导体叠层块 234及 235就发光强度而言差异大于 3%。经由上述实施例制造方法的所产生的发 光元件， 让原本位于光学特性上或电性上有较大差异性的两区域的多个半导体叠 层块得以重新分配组合。 例如若以先前技术中所述的方法， 半导体叠层块 132与 133可能因位置相近且大致位于同一区域 (请参图 1及图 2B)而于后续制作工艺中 组合成为一元件 。 同样地， 半导体叠层块 134与 135因位置相近且大致位于同 一区域 (请参图 1及图 2B)而于后续制作工艺中组合成为另一元件 B。 如此， 元件 A将包含两个平均发光强度为 4400 mcd的半导体叠层块， 而元件 B将包含两个 平均发光强度为 4000 mcd的半导体叠层块， 两元件发光强度均匀性不佳。 依 经由上述实施例制造方法的所产生的发光元件， 例如图 3C 中， 第一表面 301P1 上有原本在位于图 1 中平均发光强度为 4000 mcd 的第二区域的半导体叠层块 234; 而第二表面 301P2上有原本在位于图 1中平均发光强度为 4400 mcd的第一 区域的半导体叠层块 232。故原本位于光学特性上 (如本实施例的发光强度)或电性 上有较大差异性的两区域的多个半导体叠层块已重新分配组合。 同样地， 通过上 述实施例的制造方法， 也可以得到另一元件包含有原本在位于图 1中平均发光强 度为 4000 mcd的第二区域的半导体叠层块 235及原本在位于图 1中平均发光强度 为 4400 mcd的第一区域的半导体叠层块 233。 因而上述两元件在元件间发光强度 均匀性有较佳的表现。
此外， 半导体叠层块 234及 232经由接合至永久基板 301 , 而分别位于非共 平面的第一表面 301P1与第二表面 301P2上，因此可降低各个半导体叠层块间彼 此互相吸收所发出光的情形， 而使元件整体亮度有较佳表现。
经由如同前述的接合方法， 可在永久基板 301的第三表面 301P3上接合另一 半导体叠层块 23X,如图 3D所示。此处的半导体叠层块 23X并没有特别的限定， 熟悉此技术领域的人士当了解其重点在于如何如同上述的揭示使半导体叠层块重 新分配组合而达到产出的各元件的元件间光学特性上或电性上均匀性有较佳 的表现。 接着， 如图 3E所示， 以黄光及蚀刻制作工艺将各半导体叠层块部分 蚀刻以暴露各半导体叠层块至其第一电性半导体层 202a, 并形成介电层 320于 各半导体叠层块的侧壁， 最后实施一金属线形成步骤以形成一金属线 330 于各半导体叠层块间， 以使各半导体叠层块电连接， 其电连接关系可 为串联或并联。 如图 3E所示金属线 330 电连接各半导体叠层块形成一 串联关系。
虽然本实施例例示接合至永久基板 301的两半导体叠层块均为图 2E中与 基板 201分离的半导体叠层块， 但熟悉此技术领域的人士当明了不限于此， 例 如在图 2E中， 在基板 201上保留有半导体叠层块 231, 233, 及 235 , 在一第二实 施例中， 也可以这些存留在基板 201上的半导体叠层块接合至永久基板 301。 其 情形大致如同图 3B至 3E中所示，仅图中第一暂时基板 221及其上的半导体叠层 块对应改为基板 201及其上的半导体叠层块 231, 233,及 235,故不再重复绘示其 图示。 因此在此情形下， 其接合步骤为将基板 201与永久基板 301对位接合， 以 使半导体叠层块 231, 233, 或 235接合至欲接合的表面上；以及 板 201与永久 基板 301远离， 并使接合的半导体叠层块与基板 201分离。 又或者在第三实施例 中，这些存留在基板 201上的半导体叠层块 231, 233, 及 235可以如同第一实施例 先被自基板 201分离后再接合至永久基板 301 , 在此情形下， 其接合步骤接合为 将半导体叠层块 231, 233, 或 235接合于一第二暂时基板并使半导体叠层块 231, 233, 或 235与基板 201分离； 再将第二暂时基板与永久基板 301对位接合， 以使 半导体叠层块 231, 233, 或 235接合至欲接合的表面上；以及使第二暂时基板与永 久基板 301远离， 并使接合的半导体叠层块与第二暂时基板分离。
值得注意的是， 虽然第一实施例例示永久基板 301的第一表面 301P1上的半 导体叠层块 (即半导体叠层块 234)与第二表面 301P2上的半导体叠层块 (即半导体 叠层块 232)源自同一的半导体叠层 202, 但并不限于此， 亦即在其他实施例， 第 一表面 301P1上的半导体叠层块与第二表面 301P2上的半导体叠层块可源自不同 的半导体叠层， 例如第一表面 301P1上的半导体叠层块为半导体叠层块 234, 而 第二表面 301P2上的半导体叠层块可源自另一不同的基板的半导体叠层。 又或虽 源自同一的半导体叠层， 但可分别如同上述通过第一暂时基板 221或基板 201或 第二暂时基板而被接合至永久基板 301上。
图 3F显示本发明的第四实施例， 此实施例大致与第一实施例相同， 但第一 实施例中的永久基板 301在本实施例改为永久基板 301，。 相对于永久基板 301具 有非共平面的第一表面 301P1、 第二表面 301P2, 及第三表面 301P3, 本实施例的 永久基板 301，的第一表面 301，P1、 第二表面 301，P2, 及第三表面 301，P3则为共 平面， 但在各半导体叠层块接合至永久基板 301，时， 则通过不同厚度的接合层达 到使各半导体叠层块不共平面的效果。 亦即， 例如半导体叠层块 234经由一第一 接合层 312'Bl接合于第一表面 301，P1上， 半导体叠层块 232经由一第二接合层 312Έ2接合于第二表面 301，P2上， 而第一接合层 312'Bl与第二接合层 312，B2 厚度不同， 以使半导体叠层块 234与半导体叠层块 232非共平面。
值得注意的是， 虽然在第一实施例说明可使用如图 1因光学特征值或电性特 征值不同而在基板上区分出多个区域的多个半导体叠层块进行接合， 但本发明并 不限于此。 图 4显示本发明的第五实施例， 此实施例显示半导体叠层块在光学特 性或电性上并非如同图 1在基板上即可区分出不同区域， 但对于位于同一基板上 的多个的半导体叠层块， 仍可对其依据一光学特征值或电性特征值的量测结果， 将此多个的半导体叠层块区分别归类于一一般规格区， 一低规格区， 及一高规格 区， 其中光学特征值或电性特征值为高规格区大于一般规格区， 且一般规格区大 于低规格区。 以图 4为例， 对于一基板上的多个的半导体叠层块进行发光强度量 测的结果， 各半导体叠层块于基板上的位置及发光强度可于量测后存于机台中。 图中水平轴为发光强度， 垂直轴则为对应各发光强度的半导体叠层块的数量。 如 图所示， a结果区为低规格区， 其发光强度平均值大致为 700mcd; b结果区为一 般规格区， 其发光强度平均值大致为 900mcd; 而 c结果区为高规格区， 其发光强 度平均值大致为 1200mcd。 而利用如图 2的分离方法及如图 3的接合方法， 可根 据存于机台中的各半导体叠层块的位置及发光强度的数据， 挑选适当的半导体叠 层块接合于如图 3A的永久基板 301上，而达到半导体叠层块的重新分配。如图 4 右方所示， 若一元件上设计有 5个半导体叠层块， 则重新分配的结果， 可挑选 5 个属于一般规格区 (发光强度平均值大致为 900mcd)的半导体叠层块接合于如图 3A的永久基板 301上，形成元件 C;而另一元件 D则可挑选 3个属于低规格区 (发 光强度平均值大致为 700mcd) 的半导体叠层块接合于如图 3A的永久基板 301上， 并挑选 2个属于高规格区 (发光强度平均值大致为 1200mcd) 的半导体叠层块接合 于同一永久基板 301上， 以形成元件 D。 如此， 虽然于生产基板不同位置的区域 的半导体叠层块在光学特性或电性上会有较大的差异， 例如本实施例中发光强度 高者， 其值可高到高规格区的 1200mcd, 而发光强度低者， 其值可低到低规格区 的 700mcd, 但经本实施例对半导体叠层块的重新分配， 产出的各元件其元件间 均匀性将获得改善及控制， 元件 C与元件 D的发光强度均大致为 4500mcd。 此外， 如第一实施例所提及， 半导体叠层块经由接合至永久基板 301 , 而分别位 于非共平面的不同表面， 可降低各个半导体叠层块间彼此互相吸收所发出光 的情形， 而使元件整体亮度有较佳表现。
值得注意的是， 在以上各实施例中， 光学特征值或电性特征值可在分离步骤 前， 实际针对各基板的半导体叠层块全部或采样性地实行量测而取得； 而在制作 工艺稳定的情况下， 这些光学特征值或电性特征值也可经由一定数量的统计后得 到一事先决定的统计值。 例如针对图 1的情形， 在制作工艺稳定的情况下， 一定 数量的统计后即可确定第一区域与第二区域的边界位置， 即得到第一区域的半径 的一预定值， 及对应两个区域的光学特征值或电性特征值， 而不必在制造过程中 在对各产出的基板一一进行量测。
如第一实施例图 3E的叙述中所提及， 永久基板 301上接合的半导体叠层块 可源自不同的半导体叠层， 例如第一表面 301P1 上的半导体叠层块与第二表面 301P2上的半导体叠层块可源自不同的基板的半导体叠层。 而这样的应用更可进 一步应用以增进发光元件的演色性， 亦即提高发光元件的 CRI值， 其应用如图 5 所显示的本发明的第六实施例。 如图 5A所示， 永久基板 501上分别接合了两个 半导体叠层块 501a及 501b, 其接合方法大致如同图 3第一实施例所示， 但两个 半导体叠层块 501a及 501b分离自不同的基板的半导体叠层， 例如半导体叠层块 501a分离自一具有发光主波长约 620nm至 645nm的半导体叠层， 而半导体叠层 块 501b分离自一具有发光主波长约 595nm至 620nm的半导体叠层； 亦即两个半 导体叠层块 501a及 501b分离自不同的基板，且半导体叠层块 501a可发出红色主 波长之光， 而半导体叠层块 501b可发出橘色主波长之光。如此， 当此两半导体叠 层块被接合至永久基板 501时， 可成为一发光元件 500a, 用以取代一般的暖白光 源中的红色或橘色的仅具单一半导体叠层的芯片； 亦即，此发光元件 500a可用于 与蓝色及 YAG荧光粉组合， 所形成的暖白光源因具有两个半导体叠层块 501a及 501b的不同主波长之光，较仅具单一半导体叠层的芯片所形成的暖白光源有较佳 的演色性。
或者， 可以如图 5B所示， 永久基板 501上除了如同上述分别接合了两个半 导体叠层块 502a及 502b, 还直接将用以提供蓝色光源的半导体叠层块 502c也接 合于永久基板 501上，发光元件 500b因而直接形成一暖白光源，其中三个半导体 叠层块 501a,501b及 501c分离自不同的基板的半导体叠层， 例如半导体叠层块 501a分离自一具有发光主波长约 620nm至 645nm的半导体叠层， 半导体叠层块 501b分离自一具有发光主波长约 595nm至 620nm的半导体叠层， 而半导体叠层 块 501c分离自一具有发光主波长约 440nm至 460nm的半导体叠层； 亦即三个半 导体叠层块 501a,501b及 501c分离自不同的基板， 且半导体叠层块 501a可发出 红色主波长之光， 半导体叠层块 501b 可发出橘色主波长之光， 而半导体叠层块 501c可发出蓝色主波长之光。
或者更进一步地， 可以如图 5C所示， 永久基板 501上除了如同上述分别接 合了三个半导体叠层块 503a,503b及 503c夕卜， 更多加接合一第四的半导体叠层块 503d。其中， 四个半导体叠层块 501a,501b,501c及 501d分离自不同的基板的半导 体叠层， 半导体叠层块 501a,501b及 501c的颜色及波长如同图 5B所述， 而半导 体叠层块 503d具有发光主波长约 510nm至 530nm, 可发出绿色主波长之光。 由 于多加了此绿色主波长光的半导体叠层 503d, 发光元件 500c所形成的暖白光源 的 CRI值较图 5B所示的发光元件 500b更高， 演色性更佳。
上述实施例仅为例示性说明本发明的原理及其功效， 而非用于限制本发明。 任何本发明所属技术领域中具有通常知识者均可在不违背本发明的技术原理及精 神的情况下， 对上述实施例进行修改及变化。 因此本发明的权利保护范围如后述 的权利要求所列。

Claims

权利要求书
1、 一种发光元件的制造方法， 包括：
提供一第一基板；
提供一半导体叠层于该第一基板上， 其中该半导体叠层包括一第一电性半导 体层、 一发光层位于该第一电性半导体层之上、 以及一第二电性半导体层位于该 发光层之上， 且该半导体叠层经图形化而形成彼此分隔的多个半导体叠层块， 其 中该多个半导体叠层块包括一第一半导体叠层块及一第二半导体叠层块；
实行一分离步骤将该第一半导体叠层块与该第一基板分离， 且该第一基板保 留有该第二半导体叠层块；
提供一永久基板具有一第一表面、 一第二表面、 以及一第三半导体叠层块于 该第一表面上； 以及
接合该第一半导体叠层块及该第二半导体叠层块的其中之一于该第二表面 上。
2、如权利要求 1所述的发光元件的制造方法，其中被接合的该第一半导体叠 层块及该第二半导体叠层块的其中之一与该第三半导体叠层块的主波长差异大于 或等于 lnm。
3、如权利要求 1所述的发光元件的制造方法，其中被接合的该第一半导体叠 层块及该第二半导体叠层块的其中之一与该第三半导体叠层块的正向电压
(forward voltage)差异大于或等于 2%„
4、如权利要求 1所述的发光元件的制造方法，其中被接合的该第一半导体叠 层块及该第二半导体叠层块的其中之一与该第三半导体叠层块的发光强度差异大 于或等于 3%。
5、 如权利要求 1所述的发光元件的制造方法， 其中该分离步骤包括： 形成一第一牺牲层于在该第一半导体叠层块上；
提供一暂时基板；
接合该暂时基板与该第一牺牲层； 以及
自该第一基板分离该第一半导体叠层块。
6、如权利要求 1所述的发光元件的制造方法，其中包括接合该第二半导体叠 层块于该永久基板， 该接合步骤包括：
对位接合该第一基板与该永久基板， 以使该第二半导体叠层块接合于该第二 表面上； 以及
自该第一基板分离该第二半导体叠层块。
7、如权利要求 1所述的发光元件的制造方法，其中包括接合该第二半导体叠 层块于该永久基板， 该接合步骤包括：
提供一暂时基板；
接合该第二半导体叠层块于该暂时基板；
自该第一基板分离该第二半导体叠层块；
对位接合该暂时基板与该永久基板， 以使该第二半导体叠层块接合于该第二 表面上； 以及
自该暂时基板分离该第二半导体叠层块。
8、如权利要求第 1项所述的发光元件的制造方法，其中该第二表面及该第一 表面不在同一水平面。
9、如权利要求 1所述的发光元件的制造方法，还包括对该永久基板施以一黄 光及独刻制作工艺以使该第二表面及该第一表面不在同一水平面。
10、 如权利要求 1所述的发光元件的制造方法， 其中该第三半导体叠层块经 由一第一接合层接合于该第一表面上， 被接合的该第一半导体叠层块及该第二半 导体叠层块的其中之一经由一第二接合层接合于该第二表面上， 且该第一接合层 与该第二接合层的厚度不同。
11、 如权利要求 1所述的发光元件的制造方法， 其中该多个半导体叠层块被 区分成一第一区域及一第二区域， 其中该第一区域大致为圓形， 而该第二区域大 致为环绕该第一区域的一环状。
12、如权利要求 11所述的发光元件的制造方法，其中被接合的该第一半导体 叠层块及该第二半导体叠层块的其中之一位于该第一区域， 该第三半导体叠层块 分离自该第二区域而接合于该永久基板上。
13、如权利要求 11所述的发光元件的制造方法，还包含在该分离步骤前， 实 行一量测步骤以测得各该多个半导体叠层块的一光学特征值或一电性特征值， 并 依一该光学特征值或该电性特征值的差异预定值决定该第一区域及该第二区域。
14、如权利要求 11所述的发光元件的制造方法，还包括经由统计后得到该第 一区域的一半径的一预定值。
15、 如权利要求 1所述的发光元件的制造方法， 还包括形成一金属线电连接 被接合的该第一半导体叠层块及该第二半导体叠层块的其中之一与该第三半导体 叠层块。
16、如权利要求 15所述的发光元件的制造方法，其中被接合的该第一半导体 叠层块及该第二半导体叠层块的其中之一与该第三半导体叠层块为串联或并联。
17、 如权利要求 1所述的发光元件的制造方法， 其中该第三半导体叠层块分 离自一第三基板而接合于该永久基板上。
18、如权利要求 17所述的发光元件的制造方法，其中被接合的该第一半导体 叠层块及该第二半导体叠层块的其中之一发出主波长约 595nm至 620nm之光， 而该第三半导体叠层块发出主波长约 620nm至 645nm之光。
19、 如权利要求 1所述的发光元件的制造方法， 还包括： 依据各该多个的半 导体叠层块的一光学特征值或一电性特征值将该多个的半导体叠层块区分为一般 规格区， 低规格区， 及高规格区， 且位于该高规格区的半导体叠层块的该光学特 征值或该电性特征值大于位于该一般规格区的半导体叠层块的该光学特征值或该 电性特征值， 而位于该一般规格区的半导体叠层块的该光学特征值或该电性特征 值大于位于该低规格区的半导体叠层块的该光学特征值或该电性特征值。
20、如权利要求 19所述的发光元件的制造方法，其中该第三半导体叠层块分 离自该第一基板， 且皮接合的该第一半导体叠层块及该第二半导体叠层块的其中 之一选自于该低规格区与高规格区中之一， 而该第三半导体叠层块选自于另一。
21、如权利要求 19所述的发光元件的制造方法，其中该第三半导体叠层块分 离自该第一基板， 且被接合的该第一半导体叠层块及该第二半导体叠层块的其中 之一与该第三半导体叠层块均选自于该一般规格区。
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Publication number Priority date Publication date Assignee Title
CN110148655A (zh) * 2019-05-21 2019-08-20 北京易美新创科技有限公司 微型led芯片巨量转移方法
DE112013007281B4 (de) * 2013-07-29 2021-07-01 Epistar Corporation Verfahren zum selektiven Transferieren von Halbleitervorrichtungen

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105870265A (zh) * 2016-04-19 2016-08-17 京东方科技集团股份有限公司 发光二极管基板及其制备方法、显示装置
JP6142070B1 (ja) * 2016-12-27 2017-06-07 Ｌｕｍｉｏｔｅｃ株式会社 有機エレクトロルミネッセント素子および照明装置
FR3062953A1 (fr) * 2017-02-15 2018-08-17 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif comportant une pluralite de diodes
US20190044023A1 (en) * 2017-08-01 2019-02-07 Innolux Corporation Methods for manufacturing semiconductor device
DE102021108397A1 (de) 2021-04-01 2022-10-06 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Transferverfahren für optoelektronisches halbleiterbauelement

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080081400A1 (en) * 2003-03-06 2008-04-03 Sony Corporation Device transfer method and display apparatus
CN102479896A (zh) * 2010-11-26 2012-05-30 大连美明外延片科技有限公司 一种发光二极管芯片
CN102509731A (zh) * 2011-12-28 2012-06-20 厦门市三安光电科技有限公司 交流式垂直发光元件及其制作方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2790237B2 (ja) 1993-06-28 1998-08-27 日亜化学工業株式会社 多色発光素子
US6215244B1 (en) * 1997-06-16 2001-04-10 Canon Kabushiki Kaisha Stacked organic light emitting device with specific electrode arrangement
US6872635B2 (en) * 2001-04-11 2005-03-29 Sony Corporation Device transferring method, and device arraying method and image display unit fabricating method using the same
JP3940596B2 (ja) 2001-05-24 2007-07-04 松下電器産業株式会社 照明光源
US7005679B2 (en) 2003-05-01 2006-02-28 Cree, Inc. Multiple component solid state white light
DE112005002889B4 (de) * 2004-12-14 2015-07-23 Seoul Viosys Co., Ltd. Licht emittierendes Bauelement mit einer Mehrzahl Licht emittierender Zellen und Baugruppen-Montage desselben
US7474681B2 (en) * 2005-05-13 2009-01-06 Industrial Technology Research Institute Alternating current light-emitting device
CN103925521A (zh) * 2005-12-21 2014-07-16 科锐公司 照明装置
JP2006135367A (ja) * 2006-02-20 2006-05-25 Rohm Co Ltd 半導体発光装置
JP2007329463A (ja) * 2006-05-09 2007-12-20 Mitsubishi Chemicals Corp 半導体発光素子
JP4808550B2 (ja) * 2006-06-05 2011-11-02 株式会社フジクラ 発光ダイオード光源装置、照明装置、表示装置及び交通信号機
JP2008084908A (ja) * 2006-09-26 2008-04-10 Toshiba Lighting & Technology Corp 発光装置
CN101072464A (zh) * 2006-10-06 2007-11-14 范朝阳 带有集成保护功能的交直流发光二极管
KR20090002284A (ko) * 2007-06-26 2009-01-09 엘지이노텍 주식회사 발광 장치
JP5175121B2 (ja) * 2008-02-29 2013-04-03 晶元光電股▲ふん▼有限公司 半導体素子
TW200951359A (en) * 2008-06-06 2009-12-16 Taiwan Solutions Systems Corp LED lamp module and its fabricating method
JP5132524B2 (ja) * 2008-11-04 2013-01-30 キヤノン株式会社 窒化ガリウム系化合物半導体層の移設方法、及び窒化ガリウム系化合物半導体層が接合された基板
US20100237379A1 (en) * 2009-03-19 2010-09-23 Wu-Cheng Kuo Light emitting device
JP2010251360A (ja) * 2009-04-10 2010-11-04 Sony Corp 表示装置の製造方法および表示装置
EP2430652B1 (en) * 2009-05-12 2019-11-20 The Board of Trustees of the University of Illionis Printed assemblies of ultrathin, microscale inorganic light emitting diodes for deformable and semitransparent displays
WO2010151600A1 (en) * 2009-06-27 2010-12-29 Michael Tischler High efficiency leds and led lamps
JP2011124311A (ja) * 2009-12-09 2011-06-23 Toshiba Corp 半導体発光素子の製造方法および積層構造体
TWI557875B (zh) 2010-07-19 2016-11-11 晶元光電股份有限公司 多維度發光裝置
TWI557934B (zh) * 2010-09-06 2016-11-11 晶元光電股份有限公司 半導體光電元件
TWI521690B (zh) 2011-07-25 2016-02-11 財團法人工業技術研究院 發光元件的轉移方法以及發光元件陣列
CN102903804B (zh) * 2011-07-25 2015-12-16 财团法人工业技术研究院 发光元件的转移方法以及发光元件阵列
TW201324843A (zh) 2011-12-09 2013-06-16 Chi Mei Lighting Tech Corp 發光二極體之製作方法
US9231178B2 (en) * 2012-06-07 2016-01-05 Cooledge Lighting, Inc. Wafer-level flip chip device packages and related methods

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080081400A1 (en) * 2003-03-06 2008-04-03 Sony Corporation Device transfer method and display apparatus
CN102479896A (zh) * 2010-11-26 2012-05-30 大连美明外延片科技有限公司 一种发光二极管芯片
CN102509731A (zh) * 2011-12-28 2012-06-20 厦门市三安光电科技有限公司 交流式垂直发光元件及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112013007281B4 (de) * 2013-07-29 2021-07-01 Epistar Corporation Verfahren zum selektiven Transferieren von Halbleitervorrichtungen
CN110148655A (zh) * 2019-05-21 2019-08-20 北京易美新创科技有限公司 微型led芯片巨量转移方法

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