WO2014201822A1 - 阵列基板、显示装置及阵列基板的修复方法 - Google Patents

阵列基板、显示装置及阵列基板的修复方法 Download PDF

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Publication number
WO2014201822A1
WO2014201822A1 PCT/CN2013/089450 CN2013089450W WO2014201822A1 WO 2014201822 A1 WO2014201822 A1 WO 2014201822A1 CN 2013089450 W CN2013089450 W CN 2013089450W WO 2014201822 A1 WO2014201822 A1 WO 2014201822A1
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WIPO (PCT)
Prior art keywords
repair
line
array substrate
common
peripheral circuit
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Ceased
Application number
PCT/CN2013/089450
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English (en)
French (fr)
Inventor
贾丕健
尹雄宣
郝昭慧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Beijing BOE Display Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US14/355,327 priority Critical patent/US9335596B2/en
Publication of WO2014201822A1 publication Critical patent/WO2014201822A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • Embodiments of the present invention relate to an array substrate, a display device, and a method of repairing an array substrate. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the display panel is a main component of the TFT-LCD.
  • the array substrate and the color film substrate are assembled and filled with liquid crystal.
  • the array substrate includes a plurality of gate lines and a plurality of data lines, and the switch is provided by the gate lines.
  • the signal, the data scan signal is provided by the data line, and the gate line and the data line are usually connected to the leads of the peripheral circuit.
  • the leads in the peripheral circuit may be disconnected, thereby causing the gate line or the data line to be ineffective to input signals, and may even cause the entire display panel to be scrapped.
  • the array substrate completed based on the existing production process cannot quickly and effectively repair the leads in the disconnected peripheral circuit, thereby affecting production efficiency and waste of resources. Summary of the invention
  • Embodiments of the present invention provide an array substrate, a display device, and a method for repairing an array substrate. After the lead wires of the peripheral circuit are damaged in the production process of the array substrate, the leads can be quickly and effectively repaired, thereby improving production efficiency and avoiding waste of resources.
  • an embodiment of the present invention provides an array substrate, including: a display area; a peripheral area, wherein a peripheral circuit is disposed, and the peripheral circuit includes a plurality of leads, and the peripheral area includes: an insulating layer disposed on Above the layer on which the peripheral circuit is located; and a wire repair layer disposed on the insulating layer, wherein the wire repair layer includes at least two common repair lines extending along a direction of the lead arrangement of the peripheral circuit, and A plurality of repair lines electrically connected to the two common repair lines are disposed between the two adjacent public repair lines.
  • an embodiment of the present invention provides a display device including the array substrate as described above And a counter substrate opposite to the array substrate.
  • an embodiment of the present invention provides a method for repairing the above array substrate, comprising the steps of: S21: when a lead in the peripheral circuit is broken, disconnecting a lead of the broken peripheral circuit from a break point Fusing the ends of the disconnected portion and the common repair line to form a first splice point and a second splice point for electrically connecting the lead of the broken peripheral circuit to the common repair line; S22, selecting a repair line connecting the first fusion point to the second fusion point, wherein the intersection of the repair line and the common repair line where the first fusion point is located is a first contact and The intersection of the common repair line where the two fusion splices are located is a second joint, forming a connecting line from the first splice point, the first joint, the second joint to the second splice point, and connecting the connecting line The common repair line is disconnected, and the connecting line is used as a lead of the broken peripheral circuit.
  • FIG. 1 is a partial structural schematic view of an array substrate according to an embodiment of the invention.
  • FIG. 2 is a partial schematic view of an array reversed of a peripheral circuit lead according to an embodiment of the present invention
  • FIG. 3 is a partial schematic view of an array substrate after lead repair of the peripheral circuit according to an embodiment of the present invention
  • FIG. 4 is a schematic view of the connecting line in accordance with an embodiment of the present invention. detailed description
  • Embodiment 1 of the present invention provides an array substrate, as shown in FIG. 1, comprising: a display area; a peripheral area in which a peripheral circuit is disposed, and the peripheral circuit includes a plurality of leads 1 spaced apart from each other, and
  • the peripheral region includes: an insulating layer disposed on a layer of a lead of the peripheral circuit (not shown in the figure); provided on the insulating layer, including at least two leads along the peripheral circuit
  • a lead repair layer of the common repair line 2 extending in the direction of alignment (not shown in the figure), and a plurality of repair lines 3 electrically connected thereto are disposed between the adjacent two common repair lines 2.
  • the lead 1 of the peripheral circuit shown in Fig. 1 of the present embodiment is a zigzag line. In practical applications, the lead 1 may be in various forms.
  • a via 5 for electrically connecting the common repair line 2 and the common electrode 4 is also provided in the insulating layer.
  • the via 5 may be plural and distributed at different locations, wherein the via 5 is filled with a conductive material for electrically connecting the common repair line 2 to the common electrode 4, which may also be regarded as electrically connecting the lead repair layer to the common electrode layer. This prevents electrostatic breakdown of the lead repair layer due to static buildup during production.
  • At least two of the common repair lines 2 are respectively disposed in a set area adjacent to the lead wires 1 of the peripheral circuit, and the set area can be set according to the actual wiring or the damage probability of the lead 1.
  • the number of repair lines 3 may correspond one-to-one with the number and position of the leads 1 of the peripheral circuit; however, we should consider that the repair line 3 is too dense to interfere with the normal operation of the array substrate, and the over-dense repair line 3 will also use more materials. Therefore: the number of repair lines 3 can be less than the number of leads 1 of the peripheral circuit, and the lead wires 1 of at least two peripheral circuits are included between adjacent two repair lines 3.
  • the repair line is perpendicular to the common repair line; or, the repair line is parallel to the direction of a portion of the line segment of the lead of the peripheral circuit.
  • the common repair line and the repair line are made of Cr, W, Cu, Ti, Ta, Mo or ITO.
  • the insulating layer is one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or a composite structure of at least two of the above films.
  • a lead repair layer including a common repair line and a repair line is disposed on a layer where the peripheral circuit of the peripheral region is located, and when the lead is broken, an appropriate repair line and a part of the common are selected according to the position of the broken lead.
  • the repairing wires form a connecting wire, and the broken wires are replaced by the connecting wires, which can quickly and effectively repair the breakage of the leads of the peripheral circuits of the array substrate, thereby improving production efficiency and saving resources.
  • Embodiment 2 of the present invention provides a display device including the array substrate as described above. And a counter substrate opposite to the array substrate.
  • a third embodiment of the present invention provides a method for fabricating an array substrate, comprising the following steps: Step S11, forming a gate line, a data line, a common electrode in a display area on a substrate, and forming a peripheral circuit in the peripheral area, the periphery
  • the circuit includes a plurality of leads spaced apart from each other and electrically connected to the gate lines and the data lines.
  • Step S12 forming an insulating layer over the layer where the peripheral circuit of the substrate of the step S11 is completed, wherein the insulating layer has a via hole therein, and the insulating layer may be one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Or a composite structure of at least two kinds of films described above, wherein the via holes are filled with a conductive material.
  • Step S13 forming a wire repair layer on the peripheral region of the substrate in which the step S12 is completed, the lead repair layer being disposed on the insulating layer, the lead repair layer may be made of metal Cr, W, Cu, Ti, Ta, Mo or ITO It can be made of other metal materials which can achieve the object of the embodiments of the present invention, and is not limited thereto.
  • the lead repair layer includes at least two common repair lines extending along the direction of the lead arrangement of the peripheral circuit, and the adjacent two common repair lines respectively correspond to the two ends of the lead of the peripheral circuit, and each of the common repair lines corresponds to the lead of the peripheral circuit.
  • One end, and two adjacent repair lines are disposed between the two common repair lines; the common repair line is electrically connected to the common electrode through the hole; of course, the through holes may be multiple and distributed in different positions.
  • the purpose is to have the common repair line fully electrically connect the common repair line to the common electrode in the event that the subsequent repair of the peripheral circuit leads is affected.
  • the common repair line After the common repair line is electrically connected to the common electrode, it can also be regarded as a wire repair layer electrically connected to the common electrode layer, which can prevent electrostatic breakdown caused by static electricity accumulation of the lead repair layer in the production process.
  • the number of repair lines may correspond to the number and position of the leads of the peripheral circuits; it may also be set as follows: The number of repair lines is smaller than the number of leads of the peripheral circuit, and the corresponding areas, adjacent two repairs Leads between the lines including at least two peripheral circuits.
  • the repair line is perpendicular to the common repair line; or, the repair line is parallel to the direction of a portion of the line segment of the lead of the peripheral circuit.
  • a lead repair layer including a common repair line and a repair line is disposed, and when the lead is broken, according to the position of the broken lead , select a suitable repair line and a part of the public repair line to form a new connection line, and replace the broken lead with the connection line, which can quickly and effectively repair the array substrate
  • the breakage of the leads of the peripheral circuits improves production efficiency and saves resources.
  • Embodiment 4 of the present invention provides a method for repairing the above array substrate, comprising the following steps:
  • the common repair line that is welded in step S21 is the two common repair lines that are closest to the two ends that are disconnected at the break point.
  • the beneficial effects of the embodiments of the present invention are as follows: Based on the lead repair layer including the common repair line and the repair line disposed on the array substrate, when the lead of the peripheral circuit of the array substrate is broken, according to the position of the broken lead, a suitable repair line and a part are selected.
  • the common repair line constitutes a new connecting line, and the broken lead is replaced by the connecting line, which can quickly and effectively repair the breakage of the lead wires of the peripheral circuit of the array substrate, thereby improving production efficiency and saving resources.
  • the method for repairing an array substrate according to an embodiment of the present invention is exemplarily described below with reference to the accompanying drawings, wherein the array substrate to be modified is as shown in FIG. 1 , and the schematic diagram of the lead wires of the peripheral circuit is broken as shown in FIG. 2 . The break 6 of the lead 1 is included.
  • the end of the lead 1 of the broken peripheral circuit of the array substrate shown in FIG. 2 is welded to the intersection of the common repair line 2, and the overlap is the common repair line 2 provided on the lead 1 adjacent to the peripheral circuit. When it is in the set area of the end, it overlaps with the lead 1. As shown in Fig. 3, after the above steps, the first splice point 7 and the second splice point 8 which electrically connect the lead 1 of the broken peripheral circuit to the common repair line 2 are formed.
  • a repair line 3 and a part of the common repair line 2 are selected between the first fusion joint 7 and the second fusion joint 8, so that a connection line as shown in FIG. 4 is formed from the first fusion joint 7 to the second fusion joint 8 10;
  • a repair line 3 having the shortest distance connecting the first welding point 7 to the second welding point 8 may be selected.
  • the repair line 3 at another location can be selected.
  • the common repair line 2 is cut according to the shape of the connecting wire 10 as shown in FIG. 4, of course, considering the cut Problems such as cutting accuracy, erroneous damage, etc., generally do not choose to cut completely in accordance with the shape of the connecting line 10.
  • cutting is performed on the common repairing line 2 constituting the first welding point 7, the second welding point 8 and a part of the common repairing line 2 of the connecting line 10, as shown in the figure. 3 shows the cut-off portion 9, and the four cut-off portions 9 are located outside the connecting line 10.
  • the cut wire 10 is used as the lead 1 of the peripheral circuit to achieve a quick and effective repair of the lead 1 of the broken peripheral circuit.
  • the cutting of the setting of the connecting line 10 can be carried out according to actual conditions.
  • the cutting of the common repair line 2 is performed, so that the cut-off portion 9 is on the common repair line 2, and in addition to this, the cut-off portion 9 may also be on the repair line 3, or a part of the cut-off portion 9 at the common repair line 2 Upper part of the cut-off point 9 is on the repair line 3.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

本发明公开了一种阵列基板、显示装置及阵列基板的修复方法，该阵列基板包括：显示区域；外围区域，其中设置有外围电路，且外围电路包括多条引线（1），且所述外围区域包括：绝缘层，设置于所述外围电路所在层之上；以及引线修复层，设置于所述绝缘层之上；其中所述引线修复层至少两条沿所述外围电路的引线（1）排列方向延伸的公共修复线（2），且相邻的两条所述公共修复线之间设置有若干条与之电连接的修复线（3）。

Description

阵列基板、 显示装置及阵列基板的修复方法 技术领域
本发明的实施例涉及一种阵列基板、 显示装置及阵列基板的修复方法。 背景技术
在液晶显示器技术领域中， 薄膜晶体管液晶显示器 TFT-LCD ( Thin Film Transistor Liquid Crystal Display )以其大尺寸、 高度集成、 功能强大、 工艺灵 活、 低成本等优势而广泛应用于电视机、 电脑、 手机等产品领域。
显示面板是 TFT-LCD 的主要部件， 一般由制作完成的阵列基板和彩膜 基板对盒组装并灌注液晶而成， 其中阵列基板包括多条栅线和多条数据线， 由栅线提供开关扫描信号， 由数据线提供数据扫描信号， 栅线和数据线通常 与外围电路的引线连接。 在阵列基板的生产过程中， 由于生产工序复杂， 可 能使外围电路中的引线发生断开， 从而造成栅线或数据线不能有效的输入信 号， 甚至可能导致整个显示面板报废。 目前， 基于现有生产工序所完成的阵 列基板， 不能快速有效的修复断开的外围电路中的引线， 从而影响生产效率 和造成资源浪费。 发明内容
本发明的实施例提供一种阵列基板、 显示装置及阵列基板的修复方法， 在阵列基板的生产过程中外围电路的引线损坏后，能够快速有效的修复引线, 从而提高生产效率和避免资源浪费。
一方面， 本发明的实施例提供一种阵列基板， 包括： 显示区域； 外围区 域， 其中设置有外围电路， 且所述外围电路包括多条引线， 且所述外围区域 包括： 绝缘层， 设置于所述外围电路所在层之上； 以及引线修复层， 设置于 所述绝缘层之上， 其中所述引线修复层包括至少两条沿所述外围电路的引线 排列方向延伸的公共修复线， 且相邻的两条所述公共修复线之间设置有多条 与两条所述公共修复线电连接的修复线。
另一方面， 本发明的实施例提供一种显示装置， 包括如上述的阵列基板 以及与所述阵列基板对盒的对置基板。
再一方面， 本发明的实施例提供一种上述阵列基板的修复方法， 包括如 下步骤： S21、 当所述外围电路中的引线发生断裂时， 将断裂的所述外围电 路的引线从断裂点处断开的两端与所述公共修复线的交叠处进行熔接， 形成 使所述断裂的外围电路的引线与所述公共修复线电连接的第一熔接点和第二 熔接点； S22、 选择一条连接所述第一熔接点至所述第二熔接点距离最短的 所述修复线， 所述修复线与所述第一熔接点所在的公共修复线的交点是第一 接点且与所述第二熔接点所在的公共修复线的交点是第二接点， 形成从所述 第一熔接点、 第一接点、 第二接点至所述第二熔接点的连接线， 并将所述连 接线与所述公共修复线断开，用所述连接线作为所述断裂的外围电路的引线。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为根据本发明实施例的阵列基板的局部结构示意图；
图 2为根据本发明实施例的外围电路引线断裂的阵列 反的局部示意图； 图 3为根据本发明实施例的所述外围电路的引线修复后的阵列基板的局 部示意图； 以及
图 4为根据本发明实施例的所述连接线的示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明的实施例一提供了一种阵列基板， 如图 1所示， 包括： 显示区域； 外围区域， 其中设置有外围电路， 且所述外围电路包括彼此间隔设置的多条 引线 1 , 且所述外围区域包括： 设置于外围电路的引线所在层之上的绝缘层 (未在图中标出） ； 设置于绝缘层之上的、 包括至少两条沿外围电路的引线
1排列方向延伸的公共修复线 2的引线修复层（未在图中标出） ， 相邻的两 条公共修复线 2之间设置有若干条与之电连接的修复线 3。
需要注意的是， 为了便于描述， 在本实施例附图 1中所示出的外围电路 的引线 1为 Z字型折线， 实际应用中， 引线 1可以为多种形式。
示例性地， 绝缘层中还设置有用于电连接公共修复线 2与公共电极 4的 过孔 5。 过孔 5可以为多个且分布于不同位置， 其中过孔 5中填充有导电材 料用于将公共修复线 2与公共电极 4电连接， 这样也可以视为引线修复层与 公共电极层电连接， 这可以防止生产过程中， 引线修复层由于静电积累所引 起的静电击穿。
示例性地， 公共修复线 2中的至少两条， 分别设置于邻近外围电路的引 线 1两端的设定区域内， 该设定区域可以根据实际布线或者引线 1的损坏机 率情况进行设置。
示例性地， 修复线 3的数量与外围电路的引线 1的数量和位置可以一一 对应； 但是我们应该考虑到， 修复线 3过于密集有可能干扰阵列基板的正常 运行， 而且过密集的修复线 3也将使用更多的材料。 因此： 修复线 3的数量 可以少于外围电路的引线 1的数量， 相邻两条修复线 3之间包括至少两条外 围电路的引线 1。
示例性地， 修复线与公共修复线垂直； 或者， 修复线与外围电路的引线 的一部分线段的方向平行。
示例性地， 公共修复线和修复线由 Cr、 W、 Cu、 Ti、 Ta、 Mo或 ITO制 成。
示例性地， 绝缘层为氧化硅薄膜、 氮化硅薄膜和氮氧化硅薄膜的其中一 种， 或是上述至少两种薄膜的复合结构。
本发明实施例有益效果如下： 在外围区域的外围电路所在层之上设置包 括公共修复线和修复线的引线修复层， 当引线断裂时，根据断裂引线的位置， 选择合适的修复线和一部分公共修复线组成一条连接线， 以该连接线代替断 裂的引线， 可以快速、 有效修复阵列基板的外围电路的引线的断裂， 提高生 产效率， 节省资源。
此外， 本发明的实施例二提供了一种显示装置， 包括如上述的阵列基板 以及与该阵列基板对盒的对置基板。
本发明的实施例三提供了一种阵列基板的制作方法， 包括如下步骤： 步骤 Sll、 在基板上的显示区域中形成栅线、 数据线、 公共电极以及在 外围区域中形成外围电路， 该外围电路包括若干彼此间隔设置且电连接到栅 线和数据线的引线。
步骤 S12、在完成步骤 S11的基板的外围电路的所在层之上形成绝缘层， 其中绝缘层中具有过孔， 该绝缘层可以为氧化硅薄膜、 氮化硅薄膜和氮氧化 硅薄膜的其中一种， 或是上述至少两种薄膜的复合结构， 其中过孔中填充有 导电材料。
步骤 S13、 在完成步骤 S12的基板的外围区域中形成引线修复层， 该引 线修复层设置在该绝缘层之上， 该引线修复层可以由金属 Cr、 W、 Cu、 Ti、 Ta、 Mo或 ITO制成， 当然也可以为其他可以实现本发明实施例目的的金属 材料， 在此不——限定。
引线修复层包括至少两条沿外围电路的引线排列方向延伸的公共修复 线， 相邻的两条公共修复线分别对应外围电路的引线的两端， 每条公共修复 线各对应外围电路的引线的一端， 且相邻的两条公共修复线之间设置有若干 条与之电连接的修复线； 公共修复线经过孔与公共电极电连接， 当然， 过孔 可以为多个且分布于不同位置， 其目的是使公共修复线在影响后续修复外围 电路引线的情况下， 将公共修复线与公共电极充分电连接。 将公共修复线与 公共电极电连接后， 也可以视为引线修复层与公共电极层电连接， 这可以防 止生产过程中引线修复层的静电积累所引起的静电击穿。
示例性地,修复线的数量与外围电路的引线的数量和位置可以一一对应； 也可以如下设置： 修复线的数量小于外围电路的引线的数量， 且相对应的区 域， 相邻两条修复线之间的包括至少两条外围电路的引线。
示例性地， 修复线与公共修复线垂直； 或者， 修复线与外围电路的引线 的一部分线段的方向平行。
本发明实施例有益效果如下： 在形成有栅线、 数据线、 外围电路和公共 电极的阵列基板上， 设置包括公共修复线和修复线的引线修复层， 当引线断 裂时， 根据断裂引线的位置， 选择合适的修复线和一部分公共修复线组成一 条新的连接线， 以该连接线代替断裂的引线， 可以快速、 有效修复阵列基板 的外围电路的引线的断裂， 提高生产效率， 节省资源。
本发明的实施例四提供一种上述阵列基板的修复方法， 包括如下步骤：
521、 当外围电路的引线发生断裂时， 将断裂的外围电路的引线从断裂 点处断开的两端与公共修复线的交叠处进行熔接， 形成使断裂的外围电路的 引线与公共修复线电连接的第一熔接点和第二熔接点；
522、 选择一条连接第一熔接点至第二熔接点距离最短的修复线， 形成 第一熔接点至第二熔接点的连接线， 并将连接线与公共修复线断开， 用连接 线作为断裂的外围电路的引线。
示例性地， 步骤 S21中进行熔接的公共修复线， 为与断裂点处断开的两 端距离最近的两条公共修复线。
本发明实施例有益效果如下： 基于阵列基板上设置的包括公共修复线和 修复线的引线修复层， 当阵列基板的外围电路的引线断裂时， 根据断裂引线 的位置， 选择合适的修复线和一部分公共修复线组成一条新的连接线， 以该 连接线代替断裂的引线， 可以快速、 有效修复阵列基板的外围电路的引线的 断裂， 提高生产效率， 节省资源。
示例性地， 以下参照附图对本发明实施例提供阵列基板的修复方法进行 示例性说明， 其中待修改的阵列基板如图 1所示， 其外围电路的引线断裂后 的示意图如图 2所示， 包括引线 1的断裂处 6。
将如图 2所示的阵列基板的断裂的外围电路的引线 1的两端与公共修复 线 2的交叠处进行熔接， 该交叠处为公共修复线 2设置于邻近外围电路的引 线 1两端的设定区域内时， 与引线 1的交叠位置。 如图 3所示， 上述步骤之 后， 形成使断裂的外围电路的引线 1与公共修复线 2电连接的第一熔接点 7 和第二熔接点 8。
在第一熔接点 7和第二熔接点 8之间选择一条修复线 3、 以及一部分公 共修线 2, 从而由第一熔接点 7至第二熔接点 8形成如图 4所示的一条连接 线 10; 示例性地， 为了减小连接线 10的电阻， 可选择一条连接第一熔接点 7 至第二熔接点 8距离最短的修复线 3。 当然基于不同的目的 （例如为了使连 接线 10与未断裂的外围电路的引线 1 的电阻匹配） ， 可以选择另外位置的 修复线 3。
根据如图 4所示的连接线 10的形状切断公共修复线 2, 当然， 考虑到切 割精度、误损伤等问题， 通常不会选择完全按该连接线 10的形状切割。通常 情况下， 根据该连接线 10的形状， 在组成该连接线 10的第一熔接点 7、 第 二熔接点 8和一部分公共修复线 2的外侧的公共修复线 2上进行切割， 如在 图 3示出的切断处 9, 4个切断处 9均位于连接线 10的外侧。 使切割后的连 接线 10作为外围电路的引线 1 , 实现对断裂的外围电路的引线 1的快速、 有 效的修复。
需要注意的是， 对于连接线 10的设定的切割， 可以根据实际情况实施。 本实施例中对公共修复线 2的切割， 因此切断处 9在公共修复线 2上， 除此 情况之外， 切断处 9还可以在修复线 3上， 或者一部分切断处 9在公共修复 线 2上， 一部分切断处 9在修复线 3上。 上述情况根据本发明实施例均可以 得到， 在此不——举例。 发明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。

Claims

权利要求书
1、 一种阵列基板， 包括：
显示区域；
外围区域， 其中设置有外围电路， 且所述外围电路包括彼此间隔设置的 多条引线， 且所述外围区域包括：
绝缘层， 设置于所述外围电路所在层之上； 以及
引线修复层， 设置于所述绝缘层之上，
其中所述引线修复层包括至少两条沿所述外围电路的引线排列方向延伸 的公共修复线， 且相邻的两条所述公共修复线之间设置有多条与两条所述公 共修复线电连接的修复线。
2、如权利要求 1所述的阵列基板，其中所述绝缘层中还设置有用于电连 接所述公共修复线与公共电极的过孔。
3、如权利要求 2所述的阵列基板， 其中所述过孔中填充有导电材料， 用 于电连接所述公共修复线和所述公共电极。
4、如权利要求 1-3中任一项所述的阵列基板， 其中所述公共修复线中的 至少两条， 分别设置于邻近所述外围电路的引线两端的设定区域内。
5、如权利要求 1-4中任一项所述的阵列基板， 其中所述修复线的数量与 所述外围电路的引线的数量和位置——对应。
6、如权利要求 1-4中任一项所述的阵列基板， 其中所述修复线的数量少 于所述外围电路的所述引线的数量， 相邻两条所述修复线之间包括至少两条 外围电路的引线。
7、如权利要求 1-6中任一项所述的阵列基板， 其中所述修复线与所述公 共修复线垂直； 或者， 所述修复线与所述外围电路的引线的一部分线段的方 向平行。
8、如权利要求 1所述的阵列基板，其中所述公共修复线和所述修复线由 Cr、 W、 Cu、 Ti、 Ta、 Mo或 ITO制成。
9、如权利要求 1所述的阵列基板， 其中所述绝缘层为氧化硅薄膜、 氮化 硅薄膜和氮氧化硅薄膜的中的一种， 或是上述至少两种薄膜的复合结构。
10、如权利要求 1-9中任一项所述的阵列基板，其中所述引线为 Z字形。
11、 一种显示装置， 包括：
阵列基板， 如权利要求 1-10中任一项所述； 以及
对置基板， 与所述阵列基板对盒。
12、一种如权利要求 1-10中任一项所述的阵列基板的修复方法， 包括如 下步骤：
S21、 当所述外围电路中的引线发生断裂时， 将断裂的所述外围电路的 引线从断裂点处断开的两端与所述公共修复线的交叠处进行熔接， 形成使所 述断裂的外围电路的引线与所述公共修复线电连接的第一熔接点和第二熔接 点；
S22、 选择一条连接所述第一熔接点至所述第二熔接点距离最短的所述 修复线， 形成所述第一熔接点至所述第二熔接点的连接线， 并将所述连接线 与所述公共修复线断开， 用所述连接线作为所述断裂的外围电路的引线。
13、 如权利要求 12所述的修复方法， 其中所述步骤 S21 中进行熔接的 所述公共修复线， 为与断裂点处断开的两端距离最近的两条公共修复线。
14、 如权利要求 12或 13所述的修复方法， 其中将所述连接线与所述公 共修复线断开的切断处在所述公共修复线上， 或者在所述修复线上， 或者一 部分在所述公共修复线上而另一部分在所述修复线上。
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